CY7C1352G-250AXI - Cypress Semiconductor

PRELIMINARY

4-Mbit (256Kx18) Pipelined SRAM

with NoBL™ Architecture

CY7C1352G

Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600

Document #: 38-05514 Rev. *A Revised November 10, 2004

Features

• Pin compatible and functionally equivalent to ZBT™

devices

• Internally self-timed output buffer control to eliminate

the need to use OE

• Byte Write capability

• 256K x 18 common I/O architecture

• Single 3.3V power supply

• 2.5V / 3.3V I/O Operation

• Fast clock-to-output times

• 2.6 ns (for 250-MHz device)

• 2.8 ns (for 200-MHz device)

• 3.5 ns (for 166-MHz device)

• 4.0 ns (for 133-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Asynchronous output enable (OE)

• Pb-Free 100 TQFP package

• Burst Capability—linear or interleaved burst order

• ZZ” Sleep Mode Option and Stop Clock option

Functional Description[1]

The CY7C1352G is a 3.3V, 256K x 18 synchronous-pipelined

Burst SRAM designed specifically to support unlimited true

back-to-back Read/Write operations without the insertion of

wait states. The CY7C1352G is equipped wi th the advanced

No Bus Latency™ (NoBL™) logic required to enable consec-

utive Read/Write operations with data being transferred on

every clock cycle. This feature dramatically improves the

throughput of the SRAM, especially in systems that require

frequent Write/Read transitions.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN) signal,

which, when deasserted, suspends operation and extends the

previous clock cycle. Maximum access delay from the clock

rise is 2.6 ns (250-MHz device).

Write operations are controlled by the two Byte Write Select

(BW[A:B]) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

Notes:

1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

A0, A1, A

MODE

CE1

CE2

CE3

READ LOGIC

DQs

DQP

MEMORY

ARRAY

INPUT

ADDRESS

WRITE ADDRESS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

BURST

LOGIC A0'

A1'

D0 Q1

ADV/LD

INPUT

CLK

WRITE

DRIVERS

Sleep

Control

Logic Block Diagram

PRELIMINARY CY7C1352G

Document #: 38-05514 Rev. *A Page 2 of 13

Selection Guide

250 MHz 200 MHz 166 MHz 133 MHz Unit

Maximum Access T i me 2.6 2.8 3.5 4.0 ns

Maximum Operating Current 325 265 240 225 mA

Maximum CMOS Standby Current 40 40 40 40 mA

Shaded area cont ains advance information. Please contact your local Cypress sales representative for availability of these p arts.

Pin Configuration

DDQ

DQP

DDQ

DQP

DDQ

CLK

CEN

100

ADV/LD

MODE

CY7C1352G

100-Pin TQFP

BYTE A

BYTE B

PRELIMINARY CY7C1352G

Document #: 38-05514 Rev. *A Page 3 of 13

Pin Definitions

Name I/O Description

A0, A1, A Input-

Synchronous Address Inputs used to select one of the 256K address locations. Sampled at the rising

edge of the CLK. A[1:0] are fed to the two-bit burst counter.

BW[A:B] Input-

Synchronous Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled

on the rising edge of CLK.

WE Input-

Synchronous Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW.

This signal must be asserted LOW to initiate a write sequence.

ADV/LD Input-

Synchronous Advance/Load Input. Used to advance the on-chip address counter or load a new address.

When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW ,

a new address can be loaded into the device for an access. After being deselected, ADV/LD

should be driven LOW in order to load a new address.

CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.

CLK is only recognized if CEN is active LOW.

CE1Input-

Synchronous Chip Enable 1 Input, acti ve LOW. Sampled on the rising edge of CLK. Used in conjunction

with CE2 and CE3 to select/deselect the device.

CE2Input-

Synchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction

with CE1 and CE3 to select/deselect the device.

CE3Input-

Synchronous Chip Enable 3 Input, acti ve LOW. Sampled on the rising edge of CLK. Used in conjunction

with CE1 and CE2 to select/deselect the device.

OE Input-

Asynchronous Output Enable, asynchronous input, active LOW. Combined with the synchronous logic

block inside the device to control the direction of the I/O pi ns. When LOW, the DQ pins are

allowed to behave as outputs. When deasserted HIGH, DQ pins are tri-stated, and act as input

data pins. OE is masked during the data portion of a write sequence, during the first clock when

emerging from a deselected state, when the device has been deselected.

CEN Input-

Synchronous Clock Enable Input, active LOW . When asserted LOW the Clock signal is recognized by the

SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not

deselect the device, CEN can be used to extend the previous cycle when required.

ZZ Input-

Asynchronous ZZ “sleep” Input. This active HIGH input places the device in a non-time-critical “sleep”

condition with data integrity preserved. For normal operation, this pin has to be LOW or left

floating. ZZ pin has an internal pull-down.

DQs I/O-

Synchronous Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered

by the rising edge of CLK. As outputs, they deliver the data contained in the memory location

specified by the address during the clock rise of the read cycle. The direction of the pins is

controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave

as outputs. When HIGH, DQs and DQP[A:B] are placed in a tri-state condition. The outputs are

automatically tri-stated during the data portion of a write sequence, during the first clock when

emerging from a deselected state, and when the device is deselected, regardless of the state

of OE.

DQP[A:B] I/O-

Synchronous Bidirectional Dat a Parity I/ O Lines . Functionally, these signals are identical to DQs. During

write sequences, DQP[A:B] is controlled by BW[A:B] correspondingly.

MODE Input Strap Pin Mode Input. Selects the burst order of the device.

When tied to Gnd selects linear burst sequence. When tie d to VDD or left floating selects

interleaved burst sequence .

VDD Power Supply Power supply inputs to the core of the device.

VDDQ I/O Power Supply Power supply for the I/O circuitry.

VSS Ground Ground for the device.

NC No Connects. Not internally connected to the die.

PRELIMINARY CY7C1352G

Document #: 38-05514 Rev. *A Page 4 of 13

Functional Overview

The CY7C1352G is a synchronous-pipelined Burst SRAM

designed specifically to eliminate wait states during

Write/Read transitions. All synchronous inputs pass through

input registers controlled by the rising edge of the clock. The

clock signal is qualified with the Clock Enable input signal

(CEN). If CEN is HIGH, the clock signal is not recognized and

all internal states are maintained. All synchronous op erations

are qualified with CEN. All data outputs pass through output

registers controlled by the rising edge of the clock. Maximu m

access delay from the clock rise (tCO) is 2.6 ns (250-MHz

device).

Accesses can be initiated by asserting all three Chip Enables

(CE1, CE2, CE3) active at the rising edge of the clock. If Clock

Enable (CEN) is active LOW and ADV/LD is asserted LOW,

the address presented to the device will be latched. The

access can either be a read or write operation, dep ending on

the status of the Write Enable (WE). BW[A:B] can be used to

conduct byte write operations.

Write operations are qualified by the Write Enable (WE). All

writes are simplified with on-chip synchronous self-timed write

circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an

asynchronous Output Enab le (OE) simplify depth expansion.

All operations (Reads, Writes, and Deselects) are pipelined.

ADV/LD should be driven LOW once the device has been

deselected in order to load a new address for the next

operation.

Single Read Accesses

A read access is initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW , (2) CE1, CE2,

and CE3 are ALL asserted active, (3) the Write Enable input

signal WE is deasserted HIGH, and (4) ADV/LD is asserted

LOW. The address presented to the address inputs is latched

into the Address Regi ster and presented to the memory core

and control logic. The control logic determines that a read

access is in progress and allows the requested data to

propagate to the input of the output register. At the rising edge

of the next clock the requested data is allowed to propagate

through the output register and onto the data bus, provided OE

is active LOW. After the first clock of the read access the output

buffers are controlled by OE and the internal control logic. OE

must be driven LOW in order for the device to drive out the

requested data. During the second clock, a subsequent

operation (Read/Write/Deselect) can be initia ted. Deselecting

the device is also pipelined. Therefore, when the SRAM is

deselected at clock rise by one of the chip enable signa ls, its

output will tri-state following the next clock rise.

Burst Read Accesses

The CY7C1352G has an on-chip burst counter that allows the

user the ability to supply a si ngle address and conduct up to

four Reads without reasserting the address inputs. ADV/LD

must be driven LOW in order to load a new address in to the

SRAM, as described in the Single Read Access section above.

The sequence of the burst counter is determined by the MODE

input signal. A LOW input on MODE selects a linear burst

mode, a HIGH selects an interleaved burst sequence. Both

burst counters use A0 and A1 in the burst seque nce, and will

wrap-around when incremente d sufficiently. A HIGH input on

ADV/LD will increment the internal burst counter regardless of

the state of chip enables inputs or WE. WE is latched at the

beginning of a burst cycle. Therefore, the type of access (Read

or Write) is maintained throughout the burst sequence.

Single Write Accesses

Write accesses are initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW , (2) CE1, CE2,

and CE3 are ALL asserted active, and (3) the write signal WE

is asserted LOW. The address presented to the address inputs

is loaded into the Address Register. The write signals are

latched into the Control Logi c block.

On the subsequent clock rise the data lines are automatically

tri-stated regardless of the state of the OE input signal. This

allows the external logic to present the data on DQs and

DQP[A:B]. In addition, the address for the subsequent access

(Read/Write/Deselect) is latched into the Address Register

(provided the appropriate control signals are asserted).

On the next clock rise the data presented to DQs and

DQP[A:B] (or a subset for byte write operations, see Write

Cycle Description table for details) inputs is latched into the

device and the write is complete.

The data written during the Write operation is controlled by

BW[A:B] signals. The CY7C1352G provides byte write

capability that is described in the Write Cycle Description table.

Asserting the Write Enable input (WE) with the selected Byte

Write Select (BW[A:B]) input will selectively write to only the

desired bytes. Bytes not selected during a byte write operation

will remain unaltered. A synchronous self-timed write

mechanism has been provided to simplify the write operations.

Byte write capability has been included in order to greatly

simplify Read/Modify/Write sequences, which can be reduced

to simple byte write operations.

Because the CY7C1352G is a common I/O device, data

should not be driven into the device while the outputs are

active. The Output Enable (OE) can be deasserted HIGH

before presenting data to the DQs and DQP[A:B] input s. Doing

so will tri-state the output drivers. As a safety precaution, DQs

and DQP[A:B] are automatically tri-stated during the data

portion of a write cycle, regardless of the state of OE.

Burst Write Accesses

The CY7C1352G has an on-chip burst counter that allows the

user the ability to supply a singl e address and conduct up to

four Write operations without reasserting the address inpu ts.

ADV/LD must be driven LOW in order to load the initial

address, as described in the Single Write Access section

above. When ADV/LD is driven HIGH on the subsequent clock

rise, the chip enables (CE1, CE2, and CE3) and WE inputs are

ignored and the burst counter is incremented. The correct

BW[A:B] inputs must be driven in each cycle of the burst write

in order to write the correct bytes of data.

PRELIMINARY CY7C1352G

Document #: 38-05514 Rev. *A Page 5 of 13

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the “sleep” mode are not

considered valid nor is the completion of the operation

guaranteed. The d evice must be deselecte d prior to entering

the “sleep” mode. CE1, CE2, and CE3, must remain inactive for

the duration of tZZREC after the ZZ input returns LOW.

Interleaved Burst Address Table

(MODE = Floating or VDD)

First

Address

A1, A0

Second

Address

A1, A0

Third

Address

A1, A0

Fourth

Address

A1, A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Linear Burst Address Table (MODE = GND)

First

Address

A1, A0

Second

Address

A1, A0

Third

Address

A1, A0

Fourth

Address

A1, A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

Truth Table [2, 3, 4, 5, 6, 7, 8]

Operation Address

Used CE ZZ ADV/LD WE BWxOE CEN CLK DQ

Deselect Cycle None H L L X X X L L-H tri-state

Continue Deselect Cycle None X L H X X X L L-H tri-state

Read Cycle (Begin Burst) External L L L H X L L L-H Data Out (Q)

Read Cycle (Continue Burst) Next X L H X X L L L-H Data Out (Q)

NOP/Dummy Read (Begin Burst) External L L L H X H L L-H tri-state

Dummy Read (Continue Burst) Next X L H X X H L L-H tri-state

Write Cycle (Begin Burst) External L L L L L X L L-H Data In (D)

Write Cycle (Continue Burst) Next X L H X L X L L-H Data In (D)

NOP/WRITE ABORT (Begin Burst) None L L L L H X L L-H tri-state

WRITE ABORT (Continue Burst) Next X L H X H X L L-H tri-state

IGNORE CLOCK EDGE (Stall) Current X L X X X X H L-H –

SNOOZE MODE None X H X X X X X X tri-state

Notes:

2. X=”Don't Care.” H= Logic HIGH, L =Logic LOW. CE stands for ALL Chip Enables act ive. BWX = L signifies at least one Byte W rite S elect is active, BWX = Valid

signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.

3. Write is defined by BW[A:B], and WE. See Write Cycle Descriptions table.

4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.

5. The DQ and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

6. CEN = H, inserts wait states.

7. Device will power-up deselected and the I/Os in a tri-st ate condition, regardless of OE.

8. OE is asynchronous and is not sampled with the clock rise. It is masked internally duri ng write cycles. During a read cycle DQs and DQP[A:B] = tri-state when OE

is inactive or when the device is deselected, and DQs and DQP[A:B] = data when OE is active.

PRELIMINARY CY7C1352G

Document #: 38-05514 Rev. *A Page 6 of 13

Truth Table for Read/Write [ 2, 3]

Function WE BWBBWA

Read H X X

Write − No bytes written L H H

Write Byte A − (DQA and DQPA)LHL

Write Byte B − (DQB and DQPB)LLH

Write All Bytes L L L

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit

IDDZZ Snooze mode standby current ZZ > VDD − 0.2V 40 mA

tZZS Device operation to ZZ ZZ > VDD − 0.2V 2tCYC ns

tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns

tZZI ZZ active to snooze current This parameter is sampled 2tCYC ns

tRZZI ZZ inactive to exit snooze current This parameter is sampled 0 ns

PRELIMINARY CY7C1352G

Document #: 38-05514 Rev. *A Page 7 of 13

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature ..................................... −65°C to +150°C

Ambient Temperature with

Power Applied.................................................. −55°C to +125°C

Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V

DC Voltage Applied to Outputs

in tri-state..................................................−0.5V to VDDQ + 0.5V

DC Input V oltage ...................................... −0.5V to VDD + 0.5V

Current into Outputs (LOW).........................................20 mA

Static Discharge V o ltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current............... ... ... ............................... > 200 mA

Operating Range

Range Ambient

Temperature (TA)V

DD VDDQ

Com’l 0°C to +70°C 3.3V – 5%/+10 % 2.5V –5%

to VDD

Ind’l –40°C to +85°C

Electrical Characteristics Over the Operating Range [9, 10]

Parameter Descr iption Test Conditions Min. Max. Unit

VDD Power Supply Voltage 3.135 3.6 V

VDDQ I/O Supply Voltage 2.375 VDD V

VOH Output HIGH Voltage VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA 2.4 V

VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA 2.0 V

VOL Output LOW Voltage VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA 0.4 V

VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA 0.4 V

VIH Input HIGH Voltage[9] VDDQ = 3.3V 2.0 VDD + 0.3V V

VDDQ = 2.5V 1.7 VDD + 0.3V V

VIL Input LOW Voltage[9] VDDQ = 3.3V –0.3 0.8 V

VDDQ = 2.5V –0.3 0 .7 V

IXInput Load Current except ZZ

and MODE GND ≤ VI ≤ VDDQ −55µA

Input Current of MODE Input = VSS −30 µA

Input = VDD 5µA

Input Current of ZZ Input = VSS −5µA

Input = VDD 30 µA

IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled −55µA

IDD VDD Operating Supply

Current VDD = Max., IOUT = 0 mA,

f = fMAX = 1/tCYC 4-ns cycle, 250 MHz 325 mA

5-ns cycle, 200 MHz 265 mA

6-ns cycle, 166 MHz 240 mA

7.5-ns cycle, 133

MHz 225 mA

ISB1 Automatic CE

Power-Down

Current—TTL Inputs

VDD = Max, Device Deselected,

VIN ≥ VIH or VIN ≤ VIL

f = fMAX = 1/tCYC

4-ns cycle, 250 MHz 120 mA

5-ns cycle, 200 MHz 110 mA

6-ns cycle, 166 MHz 100 mA

7.5-ns cycle, 133

MHz 90 mA

ISB2 Automatic CE

Power-down

Current—CMOS Inputs

VDD = Max, Device Deselected,

VIN ≤ 0.3V or VIN > VDDQ –

0.3V, f = 0

All speeds 40 mA

Shaded areas conta in advance information.

Notes:

9. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> -2V (Pulse width less than tCYC/2).

10.TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 20 0ms. During this time VIH < VDD and VDDQ < VDD.

PRELIMINARY CY7C1352G

Document #: 38-05514 Rev. *A Page 8 of 13

ISB3 Automatic CE

Power-down

Current—CMOS Inputs

VDD = Max, Device Deselected,

or VIN ≤ 0.3V or VIN > VDDQ –

0.3V

f = fMAX = 1/tCYC

4-ns cycle, 250 MHz 105 mA

5-ns cycle, 200 MHz 95 mA

6-ns cycle, 166 MHz 85 mA

7.5-ns cycle, 133

MHz 75 mA

ISB4 Automatic CE

Power-down

Current—TTL Inputs

VDD = Max, Device Deselected,

VIN ≥ VIH or VIN ≤ VIL, f = 0 All speeds 45 mA

Thermal Resistance[11]

Parameter Description Test Conditions TQFP Package Unit

ΘJA Thermal Resistance

(Junction to Ambient) Test conditions follow standard test methods and

procedures for measuring thermal impedance, per

EIA / JESD51.

TBD °C/W

ΘJC Thermal Resistance

(Junction to Case) TBD °C/W

Capacitance[11]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VDD = 3.3V,

VDDQ = 3.3V

5pF

CCLK Clock Input Capacitance 5 pF

CI/O Input/Output Capacitance 5 pF

AC Test Loads and Waveforms

Note:

11.Tested initially and af ter any design or process changes that may affect these parameters.

Electrical Characteristics Over the Operating Range [9, 10] (continued)

Parameter Descr iption Test Conditions Min. Max. Unit

1ns

OUTPUT

R = 317Ω

R = 351Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL= 50Ω

Z0= 50Ω

= 1.5V

3.3V ALL INPUT PULSES

VDDQ

GND

90%

10% 90%

10%

≤1 ns ≤1 ns

(c)

OUTPUT

R = 1667Ω

R =1538Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL= 50Ω

Z0= 50Ω

VT= 1.25V

2.5V ALL INPUT PULSES

VDDQ

GND

90%

10% 90%

10%

≤1 ns ≤1 ns

(c)

3.3V I/O Test Load

2.5V I/O Test Load

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Document #: 38-05514 Rev. *A Page 9 of 13

Switching Characteristics Over the Operating Range [16, 17]

Parameter Description 250 MHz 200 MHz 166 MHz 133 MHz Unit

Min. Max Min. Max Min. Max Min. Max

tPOWER VDD (typical) to the first Access[12] 1 1 1 1 ms

Clock

tCYC Clock Cycle Time 4.0 5.0 6.0 7.5 ns

tCH Clock HIGH 1.7 2.0 2.5 3.0 ns

tCL Clock LOW 1.7 2.0 2.5 3.0 ns

Output Times

tCO Data Output Valid After CLK Rise 2.6 2.8 3.5 4.0 ns

tDOH Data Output Hold After CLK Rise 1.0 1.0 1.5 1.5 ns

tCLZ Clock to Low-Z[13, 14, 15] 0 0 0 0 ns

tCHZ Clock to High-Z[13, 14, 15] 2.6 2.8 3.5 4.0 ns

tOEV OE LOW to Output Valid 2.6 2.8 3.5 4.0 ns

tOELZ OE LOW to Output Low-Z[13, 14, 15] 0 0 0 0 ns

tOEHZ OE HIGH to Output High-Z[1 3, 14, 15] 2.6 2.8 3.5 4.0 ns

Set-up Times

tAS Address Set-up Before CLK Rise 1.2 1.2 1.5 1.5 ns

tALS ADV/LD Set-up Before CLK Rise 1.2 1.2 1.5 1.5 ns

tWES GW, BW[A:B] Set-Up Before CLK Rise 1.2 1.2 1.5 1.5 ns

tCENS CEN Set-up Before CLK Rise 1.2 1.2 1.5 1.5 ns

tDS Data Input Set-up Before CLK Rise 1.2 1.2 1.5 1.5 ns

tCES Chip Enable Set-up Before CLK Rise 1.2 1.2 1.5 1.5 ns

Hold Times

tAH Address Hold After CLK Rise 0.3 0.5 0.5 0.5 ns

tALH ADV/LD Hold after CLK Rise 0.3 0.5 0.5 0.5 ns

tWEH GW, BW[A:B] Hold After CLK Rise 0.3 0.5 0.5 0.5 ns

tCENH CEN Hold After CLK Rise 0.3 0.5 0.5 0.5 ns

tDH Data Input Hold After CLK Rise 0.3 0.5 0.5 0.5 ns

tCEH Chip Enable Hold After CLK Rise 0.3 0.5 0.5 0.5 ns

Shaded areas conta in advance information.

Notes:

12.This part has a voltage regulator internally; tpower i s t he time that the power needs to be supplied above VDD minimum initially before a read or write operation

can be initiated.

13.tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test condit ions shown in p art (b) of AC Test Loads. T ransition is mea sured ± 200 mV f rom steady-sta te voltage.

14.At any given voltage and temperature, t OEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus co ntention between SRAMs when sharing the same

data bus. Th ese specifications do not imply a b us contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed

to achieve tri-state prior to Low-Z under the same system conditions.

15.This parameter is sampled and not 100% tested.

16.Timing reference l evel is 1.5V when VDDQ = 3.3V and i s 1. 25V when VDDQ = 2.5V.

17.Test conditions shown in (a) of AC Test Loads unless otherwise noted.

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Document #: 38-05514 Rev. *A Page 10 of 13

Switching Waveforms

Read/Write Timing[18, 19, 20]

WRITE

D(A1)

123456789

CLK

tCYC

CEH

CES

CEN

CENH

CENS

BW[A:B]

ADV/LD

ADDRESS A1 A2 A3 A4 A5 A6 A7

Data

n-Out (DQ)

CLZ

D(A1) D(A2) D(A5)Q(A4)Q(A3)

D(A2+1)

DOH

CHZ

WRITE

D(A2) BURST

WRITE

D(A2+1)

READ

Q(A3) READ

Q(A4) BURST

READ

Q(A4+1)

WRITE

D(A5) READ

Q(A6) WRITE

D(A7) DESELECT

OEV

OELZ

OEHZ

DOH

DON’T CARE UNDEFINED

Q(A6)

Q(A4+1)

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Document #: 38-05514 Rev. *A Page 11 of 13

NOP, STALL, and DESELECT Cycles[18, 19, 21]

ZZ Mode Timing[22, 23]

Notes:

18.For this waveform ZZ is tied low.

19.When CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

20.Order of the Burst sequence is determined by the status of the MODE (0= Linea r, 1= Interleaved). Burst operations are optional.

21.The IG NOR E CLO CK EDG E or STALL cycle (Clock 3) illustrated CEN being used to create a p ause. A write is not performed during this cycle.

22.Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.

23.DQs are in high-Z when exiting ZZ sleep mode.

Switching Waveforms (continued)

READ

Q(A3)

45678910

CLK

CEN

[A:B]

ADV/LD

ADDRESS A3 A4 A5

D(A4)

Data

In-Out (DQ)

Q(A5)

WRITE

D(A4) STALLWRITE

D(A1)

123

READ

Q(A2) STALL NOP READ

Q(A5) DESELECT CONTINUE

DESELECT

DON’T CARE UNDEFINED

CHZ

D(A1) Q(A2) Q(A3)

tZZ

SUPPLY

CLK

tZZREC

LL INPUTS

(except ZZ)

IDDZZ

tZZI

tRZZI

DESELECT or READ Only

PRELIMINARY CY7C1352G

Document #: 38-05514 Rev. *A Page 12 of 13

© Cypress Semi con duct or Cor po rati on , 20 04 . The information con t a in ed he re i n is subject to change wi t hou t n oti ce. C ypr ess S em ic onductor Corporation assumes no resp onsibility f or the u se

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypr ess. Furtherm ore, Cypress doe s not authorize i ts

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant inju ry to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Ordering Information

Speed

(MHz) Ordering Code Package

Name Package Type Operating

Range

250 CY7C1352G-250AXC A101 Lead-Free 10 0-Lead Thin Quad Flat Pack(14 x 20 x 1.4mm) Commercial

CY7C1352G-250AXI A101 Lead-Free 100-Lea d Thin Quad Flat Pack(14 x 20 x 1.4mm) Industrial

200 CY7C1352G-200AXC A101 Lead-Free 10 0-Lead Thin Quad Flat Pack(14 x 20 x 1.4mm) Commercial

CY7C1352G-200AXI A101 Lead-Free 100-Lea d Thin Quad Flat Pack(14 x 20 x 1.4mm) Industrial

166 CY7C1352G-166AXC A101 Lead-Free 10 0-Lead Thin Quad Flat Pack(14 x 20 x 1.4mm) Commercial

CY7C1352G-166AXI A101 Lead-Free 100-Lea d Thin Quad Flat Pack(14 x 20 x 1.4mm) Industrial

133 CY7C1352G-133AXC A101 Lead-Free 10 0-Lead Thin Quad Flat Pack(14 x 20 x 1.4mm) Commercial

CY7C1352G-133AXI A101 Lead-Free 100-Lea d Thin Quad Flat Pack(14 x 20 x 1.4mm) Industrial

Shaded areas cont ain advance informa tion. Please cont act your loca l cypress sales represent ative to order p arts t hat are not listed in the ord ering informat ion table.

Package Diagram

ZBT is a trademark of Integrated Device Technology. NoBL and No Bus Latency are trademarks of Cypress Semiconductor

Corporation. All product and company names mentioned in this document are trademarks of their respec tive holders.

100-Pin Thin Plas tic Quad Flatpa c k (1 4 x 20 x 1. 4 m m) A 10 1

51-85050-*A

PRELIMINARY CY7C1352G

Document #: 38-05514 Rev. *A Page 13 of 13

Document History Page

Document Title: CY7C1352G 4-Mbit (256Kx18) Pip elined SRAM with NoBL™ Architecture

Document Number: 38-05514

REV. ECN NO. Issue Date Orig. of

Change Description of Change

** 224362 See ECN RKF New data sheet

*A 288431 See ECN VBL Deleted 100 MHz and 225 MHz

Changed TQFP package in Ordering Information section to lead-free TQFP