Enpirion® Power Datasheet
EP5388QI 800mA PowerSoC
Sy nchronous Buc k Regulat o r
With In tegrated In ductor
Product Overview
The EP5388QI is a synchronous buck
converter with integrated Inductor, PWM
controller, MOSFETS, and Compensation
providing the smallest possible solution size.
The EP5388QI requires only two small MLCC
capacitors to make a complete solution.
Integration of the inductor greatly simplifies
des ign, c ontains nois e, reduc es part c ount, and
reduces solution footprint. Low output ripple
ens ures c om patibility w ith RF s ys tems.
The EP5388QI operates at a switching
frequency of 4 MHz, enabling this
unprecedented level of integration and small
external components. Type III voltage mode
control is used to provide high noise immunity
and wide c ontrol loop bandw idth.
The small footprint makes this part ideal for
space constrained portable applications.
Shutdown current of <1uA extends battery life
Output voltage level is programmed via a 3-pin
VID selector providing seven pre-programmed
output voltages along with an option for
external resistor divider.
Applications
• Noise sensitive RF applications
• Area constrained applications
• Wireless data applications
• Portable gam ing devic es
• Pers onal Media Players
• Advanced Mobile Processors, DSP, IO,
Memory, Video, Multimedia Engines
Ordering Information
P ar t Number
Tem p Rati ng (°C)
Package
EP5388QI
-40 to +85
16-pi n QF N T&R
EVB-EP5388QI
EP5388QI E val uati on Board
Product Highlights
Featuring Integrated Inductor Technology
• 3mm x 3mm x 1.1mm QFN package
• Only t wo low cost MLCC caps required
• 4 MHz switching frequency
• Hi gh effi ciency, up to 94%
• Up to 800mA continuous output current
• W ide 2. 4V t o 5.5V inpu t r ange
• VOUT Range 0.6V to V IN – 0.5V
• 3-P in VID output voltage programming
• 100% duty cycle capable
• Less than 1 µA st andby curr ent
• Low VOUT ripple for RF compati bili ty
• Short circuit and over current protection
• UVLO and thermal protecti on
• RoHS c om pliant; MSL 3 260° C r eflow
Typical Application Circuit
V
IN
V
Sense
V
in
V
S1
V
S2
V
S0
EP5388QI
47uF
1206
4.7µF
0603
V
OUT
V
out
GND
ENABLE
V
FB
Voltage
Select
Figure 1. Typical ap pl ication circuit.
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02377 October 11, 2013 Rev D
EP5388QI
Pin Description
Figure 2. EP5388QI Package P i n-out.
PIN
NAME
FUNCTION
1, 15, 16 NC(SW)
No C onnec t. Thes e pins are inter nally c onnec ted to the c om m on dr ain
output of the internal MO SFETs . NC (S W ) pins are not to be elec tr ic ally
c onnec ted to any external s ignal, ground, or voltage. How ever, they
must be soldered to the PC B. Failure to follow this guideline m ay res ult
in part m alfunc tion or dam age.
2,3
PGND
Pow er Ground
4 VFB
Feedbac k pin for external divider option. When us ing the external
divider option ( VS0= VS1= VS2= high) c onnec t this pin to the c enter of
the exter nal divider. Set the divider s uc h that VFB = 0.6V. The “ground”
s ide of the external divider s hould be c onnec ted to AGND
5 VSENSE
Sens e pin for pres et output voltages . R efer to application s ec tion for
proper configuration
6
AGND
Analog ground. This is the quiet ground for the internal c ontrol c irc uitr y
7,8 VOUT
Regulated O utput Voltage. R efer to applic ation s ec tion for proper layout
and dec oupling.
9 NC
No C onnec t. This pin s hould not be elec tr ic ally c onnec ted to any
external s ignal, voltage, or ground. This pin m ay be c onnec ted
inter nally. How ever, this pin m us t be s older ed to the P CB .
10, 11,
12 VS0,VS1,VS2
Output voltage select. VS2=pin10 VS1=pin11, VS0=pin12. Selects one
of s even pres et output voltages or c hoos e external divider by c onnecting
pins to logic high or low . (refer to s ec tion on output voltage s elec t for
more detail).
13
ENABLE
O utput enable. E nable = logic high, disable = logic low .
14
VIN
Input voltage pin. R efer
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02377 October 11, 2013 Rev D
EP5388QI
Functional Block Diagram
Voltage
Select
DAC
Switch
VREF
(+)
(-)
Error
Amp
V
SENSE
V
FB
V
OUT
VS0 VS1 VS2
Package Boundry
P-Drive
N-Drive
UVLO
Thermal Limit
Current Limit
Soft Start
Sawtooth
Generator
(+)
(-)PWM
Comp
V
IN
ENABLE
GND
Logic
Compensation
Network
NC(SW)
Figure 3. Funct ional block diagram.
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02377 October 11, 2013 Rev D
EP5388QI
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond
recommended operating conditions is not implied. Stress beyond absolute maximum ratings may
cause permanent damage to the device. Exposure to absolute maximum rated conditions for
extended per iods m ay affec t devic e reliability.
PARAMETER
SYMBOL
MIN
MAX
UNITS
I nput Supply Voltage
VIN
-0.3
7.0
V
Voltages on: ENABLE , VSENSE, VS0-VS2
-0.3
VIN + 0.3
V
Voltage on: VFB
-0.3
2.7
V
Storage T emperature Range
TSTG
-65
150
°C
Ref low T emp, 10 Sec, MSL3 JEDEC J -STD-020C
260
°C
ESD Rating (based on Human Body Model)
2000
V
Recommended Operating Conditions
PARAMETER
SYMBOL
MIN
MAX
UNITS
I nput Voltage Range
VIN
2.4
5.5
V
Output Voltage Range
VOUT
0.603
VIN – 0.5
V
Output Current
IOUT
0
800
mA
Operating Ambient T emperature
TA
-40
+85
°C
Operating Junction T emperature
TJ
-40
+125
°C
Thermal Characteristics
PARAMETER
SYMBOL
TYP
UNITS
T hermal Resistance: Junction to A mbient (0 LFM)
θJA
100
°C/W
T hermal Overload T rip Point
TJ-TP
+150
°C
T hermal Overload T rip Point Hysteresis
15
°C
Electrical Characteristics
NOTE: TA = -40°C to + 85°C unles s otherw is e noted. Typic al values are at TA = 25°C, V IN = 3.6V.
CIN =4.7µF 0603 MLC C, COUT = 47uF 1206 MLCC.
PARAMETER
SYMBOL
T ES T CO NDIT IONS
MIN
TYP
MAX
UNITS
VOUT Initial Accuracy
∆VOUT Initl
TA = 25C, 2.4V ≤ VIN ≤ 5.5V
-2%
+2%
Line Regulation
∆VOUT_linel
2.4V ≤ VIN ≤ 5.5V
0.0566
%/V
Load Regulation
∆VOUT_load
0A ≤ ILOAD ≤ 800mA
0.0003
%/mA
T emperature Variation
∆VOUT templ
-40°C ≤ TA ≤ +85°C
0.0078
%/°C
Overal l V
OUT
Accuracy
(Line, Load, and
Temperature combined) ∆VOUT_All
2.4V ≤ V
IN
≤ 5.5V
-40°C ≤ TA ≤ +85°C
0A
≤
ILOAD
≤
800mA
-3% +3%
Dropout Resistance
RDROPOUT
400
500
mΩ
Dynamic Voltage Slew
Rate
Vslew 0.975 1.5 2.025 V/mS
Continuous Output
Current
IOUT
-20°C ≤ T
A
≤ +85°C
-40°C ≤ TA ≤ +85°C
800
750
mA
Shut-Dow n Current
ISD
Enable = Low
0.75
µA
PFET OCP T hreshold
ILIM
1000
mA
Feedback Pin Volt age
VFB
0.603
V
Feedback Pin I nput
Current
IFB 100 nA
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02377 October 11, 2013 Rev D
EP5388QI
PARAMETER
SYMBOL
T ES T CO NDIT IONS
MIN
TYP
MAX
UNITS
VS0-VS1, Enabl e Voltag e
Threshold
VTH
Pin = Low
Pin = High
0.0
1.4
0.4
VIN
VS0-VS2 Pin I nput
Current
IVSX 1 nA
Operating Frequency
FOSC
4
MHz
PFET On Resistance
RDS(ON)
340
mΩ
NFET On Resistance
RDS(ON)
270
mΩ
Soft-Start Operation
Soft-Start Slew Rate
V
SS
VID pr ogramming mode
0.975
1.5
2.025
V/mS
V
OUT
R ise Time
T
SS
VFB programming mode
0.784
1.2
1.628
mS
Typical Performance Characteristics
Efficiency, VIN = 3.3V, VOUT = 1.2V , 1.5V,1.8V, 2.5V. Efficiency, VIN = 3.7V , VOUT = 1.2 V, 1.5V ,1.8V, 2.5V .
Efficiency, VIN = 5V, VOUT = 1.2V , 1.5V,1 .8V , 2.5V, 3.3V. Output Ripple, VIN = 5V, VOUT = 1.2V; Load = 500mA.
50
55
60
65
70
75
80
85
90
95
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80
Load Current (A)
Efficiency (%)
50
55
60
65
70
75
80
85
90
95
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80
Load Current (A)
Efficiency (%)
50
55
60
65
70
75
80
85
90
95
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80
Load Current (A)
Efficiency (%)
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02377 October 11, 2013 Rev D
EP5388QI
Output Ripple, VIN = 5V, VOUT = 1.8V; Load = 500mA. Output Ripple, VIN = 5V, VOUT = 2.5V; Load = 500mA.
Output Ripple, VIN = 5V, VOUT = 3.3V; Load = 500mA. Output Ripple, VIN = 3.3V, VOUT = 1.2V; Load = 500m A .
Output Ripple, VIN = 3.3V, VOUT = 1.8V; Load = 500mA . Output Ripple, VIN = 3.3V, VOUT = 2.5V; Load = 500 m A .
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02377 October 11, 2013 Rev D
EP5388QI
Transient, VIN = 5.0V, VOUT = 1.2V , Load = 0-800mA. Transient, VIN = 5.0V, VOUT = 3.3V, Load = 0-800mA.
Transient, VIN =3.3V, VOUT = 1.2V, Load = 0-800mA. Transient, VIN = 3.3V, VOUT = 1.8V, Load = 0-800mA.
Startup, VIN = 3.6V, V OUT = 1.5V, Load = 500mA. Shutdown, VIN = 3.6V, VOUT = 1.5V, Load = 500m A.
Enable in light blue; Vout in Dark blue. Enable in light blue; Vout in Dark blue.
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02377 October 11, 2013 Rev D
EP5388QI
Detailed Description
Functional Overview
The EP5388QI is a complete DCDC converter
solution requiring only two low cost MLCC
capacitors. MOSFET switches, PWM
controller, Gate-drive, compensation, and
inductor are integrated into the tiny 3mm x
3mm x 1.1m m pac kage to provide the s m alles t
footprint possible while maintaining high
efficiency, low ripple, and high performance.
The converter uses voltage mode control to
provide the simplest implementation and high
noise immunity. The device operates at a
4MHz switching frequency. The high switching
frequency allows for a wide control loop
bandwidth providing excellent transient
performance. The high switching frequency
further enables the use of very small
components making possible this
unprec edented level of integr ation.
Altera’s proprietary power MOSFET technology
provides very low switching loss at frequencies
of 4 MHz and higher, allowing for the use of
very small internal components, and high
performance. Integration of the magnetics
virtually eliminates the design/layout issues
normally associated with switch-mode DCDC
converters. All of this enables much easier
and faster incorporation into various
applications to meet demanding EMI
requirements.
Output voltage is chosen from seven preset
values via a three pin VID voltage select
scheme. An external divider option enables
the selection of any voltage in VIN to 0.6V
range. This reduces the number of
components that must be qualified and
reduces inventory burden. The VID pins can
be toggled on the fly to implement glitch free
dynam ic voltage s c aling.
Protection features include under-voltage lock-
out (UVLO), over-current protection (OCP),
short circuit protection, and thermal overload
protection.
Integrated Inductor
Altera has introduced the world’s first product
family featuring integrated inductors. The
EP5388QI utilizes a proprietary low loss
integrated inductor. The use of an internal
inductor localizes the noises associated with
the output loop currents. The inherent shielding
and compact construction of the integrated
inductor reduces the radiated noise that
couples into the traces of the circuit board.
Further, the package layout is optimized to
reduce the electrical path length for the AC
ripple currents that are a major source of
radiated emissions from DCDC converters.
The integrated inductor significantly reduces
parasitic effects that can harm loop stability,
and m akes layout very s im ple.
Stable Over Wide Range of Operating
Conditions
The EP5388QI utilizes an internal type III
compensation network and is designed to
provide a high degree of stability over a wide
range of operating conditions. The device
operates over the entire input and output
voltage range with no external modifications
required. The very high switching frequency
allow s for a very w ide c ontrol loop bandw idth.
S o ft S ta rt
Internal soft start circuits limit in-rush current
when the device starts up from a power down
condition or when the “ENABLE” pin is
asserted “high”. Digital control circuitry limits
the VOUT ramp rate to levels that are safe for
the Power MOSFETS and the integrated
inductor.
The EP5388QI has two soft start operating
modes. When VOUT is programmed using a
preset voltage in VID mode, the device has a
constant slew rate. When the EP5388QI is
configured in external resistor divider mode,
the device has a constant VOUT ramp time.
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02377 October 11, 2013 Rev D
EP5388QI
Output voltage slew rate and ramp time is
given in the Elec tric al C harac teris tic s Table.
Excess bulk capacitance on the output of the
device can cause an over-current condition at
s tar tup.
When operating in VID mode, the maximum
total capacitance on the output, including the
output filter capacitor and bulk and decoupling
c apac itanc e, at the load, is given as :
COUT_TOTAL_MAX = COUT_Filter + COUT_BULK = 700uF
When the EP5388QI output voltage is
programmed using and external resistor divider
the m axim um total c apac itanc e on the output is
given as:
COUT_TOTAL_MAX = 1.251x10-3/VOUT Farads
The above number and formula assume a no
load condition at startup.
Over Current/Short Circuit Protection
The current limit function is achieved by
sensing the current flowing through a sense P-
MOSFET which is compared to a reference
current. When this level is exceeded the P-
FET is turned off and the N-FET is turned on,
pulling VOUT low. This condition is maintained
for a per iod of 1m S and then a norm al s oft s tar t
is initiated. If the over current condition still
persists, this cycle will repeat in a “hiccup”
mode.
Under Vol t age Lock out
During initial power up an under voltage
lockout circuit will hold-off the switching
circuitry until the input voltage reaches a
sufficient level to insure proper operation. If
the voltage drops below the UVLO threshold
the lockout circuitry will again disable the
switching. Hysteresis is included to prevent
chattering between states.
Enable
The ENABLE pin provides a means to shut
down the converter or enable normal
operation. A logic low will disable the converter
and cause it to shut down. A logic high will
enable the converter into normal operation. In
shutdown mode, the device quiescent current
will be les s than 1 uA.
NOTE: This pin m us t not be left floating.
Thermal Shutdown
When excessive power is dissipated in the
chip, the junction temperature rises. Once the
junction temperature exceeds the thermal
shutdown temperature the thermal shutdown
circuit turns off the converter output voltage
thus allowing the device to cool. When the
junction temperature decreases by 15C°, the
device will go through the normal startup
process.
Application Information
Output V oltage S elect
To provide the highest degree of flexibility in
choosing output voltage, the EP5388QI uses a
3 pin VID, or Voltage ID, output voltage select
arrangement. This allows the designer to
c hoos e one of s even pr es et voltages , or to us e
an external voltage divider. Internally, the
output of the VID multiplexer sets the value for
the voltage reference DAC, which in turn is
connected to the non-inverting input of the
error amplifier. This allows the use of a single
feedback divider with constant loop gain and
optimum compensation, independent of the
output voltage selected.
Table 1 shows the various VS0-VS2 pin logic
states and the associated output voltage
levels . A logic “ 1” indic ates a c onnec tion to VIN
or to a “high” logic voltage level. A logic “0”
indicates a connection to ground or to a “low”
logic voltage level. These pins can be either
hardwired to VIN or GND or alternatively can be
driven by standard logic levels. Logic low is
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02377 October 11, 2013 Rev D
EP5388QI
defined as VLOW ≤ 0.4V. Logic high is defined
as VHIGH ≥ 1.4V. Any level between these two
values is indeterminate. These pins must not
be left floating.
VS2
VS1
VS0
VOUT
0
0
0
3.3V
0
0
1
2.5V
0
1
0
1.8V
0
1
1
1.5V
1
0
0
1.25V
1
0
1
1.2V
1
1
0
0.8V
1
1
1
User
Selectable
External V oltage D ivider
As described above, the external voltage
divider option is chosen by connecting the
VS0, VS1, and VS2 pins to VIN or logic “high”.
The EP5388QI uses a separate feedback pin,
VFB, when using the external divider. VSENSE
must be connected to VOUT as indicated in
Figure 4.
VIN VSense
Vin
V
S1
V
S2
V
S0
EP5388QI 47µF
1206
4.7uF
0603
VOUT
Vout
GND
ENABLE
Ra
Rb
VFB
Figure 4. External Divider application circuit.
The output voltage is selected by the following
formula:
( )
Rb
Ra
OUT
VV += 1603.0
Ra must be chosen as 200KΩ to m aintain loop
gain. Then R b is given as:
Ω
−
=603.0
10206.1
5
OUT
b
Vx
R
VOUT can be programmed over the range of
0.6V to VIN-0.5V.
Dynamically Adjustable Output
The EP5388QI is designed to allow for
dynamic switching between the predefined VID
voltage levels. The inter-voltage slew rate is
optimized to prevent excess undershoot or
overshoot as the output voltage levels
trans ition. The s lew rate is identic al to the s oft-
start slew rate of 1.5V /mS.
Dynamic transitioning between internal VID
s ettings and the exter nal divider is not allowed.
Power-Up/Down Sequencing
During power-up, ENABLE should not be
asserted before VIN. During power down, the
VIN should not be powered down before the
ENABLE. Tying PVIN and ENABLE together
during power-up or power-down meets this
requirement.
Pre-Bias Start-up
The EP5388QI does not support startup into a
pre-biased condition. Be sure the output
capacitors are not charged or the output of the
EP5388QI is not pre-biased when the
EP5388QI is first enabled.
Input and Output Capacitors
The input capacitance requirement is 4.7uF
0603 MLCC. Altera recommends that a low
ESR MLCC capacitor be used. The input
c apac itor m us t us e a X5R or X7R or equivalent
dielectric formulation. Y5V or equivalent
dielectric formulations lose capacitance with
frequency, bias, and with temperature, and are
not suitable for switch-mode DC-DC converter
input filter applications.
A variety of output capacitor c onfigur ations are
possible depending on footprint and ripple
requirements. For applications where VIN
range is up to 5.5V, it is r ec om m ended to us e a
single 47uF 1206 MLCC capacitor. Ripple
performance can be improved by using 2 x
22uF 0805 MLCC capacitors.
Table 1. VI D voltage s elect settings .
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02377 October 11, 2013 Rev D
EP5388QI
A single 10uF 0805 MLCC can be used if VOUT
programming is accomplished using an
external divider, with the addition of a 10pF
phase lead capacitor as shown in Figure 5.
Note that in this configuration, VSENSE should
NO T be c onnec ted to VOUT.
As described in the Soft Start section, there is
a limitation on the maximum bulk capacitance
that can be placed on the output of this device.
Pleas e refer to that s ec tion for m ore details .
The output capacitor must use a X5R or X7R
or equivalent dielectric formulation. Y5V or
equivalent dielectric formulations lose
capacitance with frequency, bias, and
temperature and are not suitable for switch-
mode DC-DC converter output filter
applications.
V
IN V
Sense
V
in
V
S1
V
S2
V
S0
EP5388QI
10µF
0805
4.7uF
0603
V
OUT
V
out
GND
ENABLE
Ra
Rb
V
FB
10pF
Figure 5. Applicati ons circuit f or COUT = 1 x 10uF 0805.
Layout Considerations*
*Optimized PCB layout file is downloadable from the
Altera webs i te to assure fi rs t pass desi gn succ ess.
Refer to figure 6 for the following layout
recommendations.
Recommendation 1: The input and output
filter capacitors should be placed as close to
the EP5388QI as possible to reduce EMI from
input and output loop AC currents. This
reduces the physical area of these AC current
loops.
Recommendation 2: The system ground
plane should be the first layer immediately
below the surface layer (PCB layer 2). If it is
not possible to make PCB layer 2 the system
ground plane, a local ground island should be
created on PCB layer 2 under the Altera
Enpirion device and including the area under
the input and output filter capacitors. This
ground plane, or ground island, should be
continuous and uninterrupted underneath the
Altera Enpirion device and the input and output
filter capacitors.
Recommendation 3: The surface layer
ground pour should include a “slit” as s how n in
figure 6 to separate the input and output AC
loop currents. This will help reduce noise
coupling from the input current loop to the
output c urr ent loop.
Recommendation 4: Multiple small vias
(approximately 0.25mm finished diameter)
should be used to connect the ground
terminals of the input and output capacitors,
and the surface ground pour under the device,
to the system ground plane. If a local ground
island is used on PCB layer 2, the vias should
connect to the ground island and continue
down to the PCB system ground plane.
Recommendation 5: The AGND pin should
be connected to the system ground plane
using a via as described in recommendation 4.
AGND must NOT be connected to the surface
layer ground pour.
Recommendation 6: As with any switch-
mode DC-DC converter, do not run any
sensitive signal or control lines under the
converter package.
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02377 October 11, 2013 Rev D
EP5388QI
Package Dimensions
Fi gure 8. E P5388Q I P ackage Di m ens i ons.
Contact Information
Altera Corporation
101 Innovation D rive
San Jos e, C A 95134
Phone: 408-544-7000
www.altera.com
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02377 October 11, 2013 Rev D
