LTC2153-14 14-Bit 310Msps ADC Description Features n n n n n n n n n n n n The LTC(R)2153-14 is a 310Msps 14-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. It is perfect for demanding communications applications with AC performance that includes 68.8dB SNR and 88dB spurious free dynamic range (SFDR). The 1.25GHz input bandwidth allows the ADC to undersample high frequencies with good performance. The latency is only six clock cycles. 68.8dBFS SNR 88dB SFDR Low Power: 401mW Total Single 1.8V Supply DDR LVDS Outputs Easy-to-Drive 1.32VP-P Input Range 1.25GHz Full Power Bandwidth S/H Optional Clock Duty Cycle Stabilizer Low Power Sleep and Nap Modes Serial SPI Port for Configuration Pin-Compatible 12-Bit Version 40-Lead (6mm x 6mm) QFN Package DC specs include 1.2LSB INL (typ), 0.35LSB DNL (typ) and no missing codes over temperature. The transition noise is 2.11LSBRMS. The digital outputs are double data rate (DDR) LVDS. Applications n n n n n n The ENC+ and ENC- inputs can be driven differentially with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. Communications Cellular Basestations Software Defined Radios Medical Imaging High Definition Video Testing and Measurement Instruments L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical Application LTC2153-14 32K Point 2-Tone FFT, fIN = 71MHz and 69MHz, 310Msps VDD OVDD CLOCK S/H CLOCK/DUTY CYCLE CONTROL 14-BIT PIPELINED ADC CORRECTION LOGIC OUTPUT DRIVERS 0 -20 DDR LVDS OGND GND 215314 TA01a AMPLITUDE (dBFS) ANALOG INPUT D12_13 * * * D0_1 -40 -60 -80 -100 -120 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 215314 TA01b 215314fa For more information www.linear.com/LTC2153-14 1 LTC2153-14 Absolute Maximum Ratings Pin Configuration (Notes 1, 2) D10_11- D10_11+ D12_13- D12_13+ GND SDO SDI SCK CS PAR/SER TOP VIEW 40 39 38 37 36 35 34 33 32 31 VDD 1 30 OVDD VDD 2 29 D8_9+ GND 3 28 D8_9- AIN+ 4 27 CLKOUT+ AIN- 5 26 CLKOUT - 41 GND GND 6 25 D6_7+ SENSE 7 24 D6_7- VREF 8 23 D4_5+ VCM 9 22 D4_5- GND 10 21 OGND OVDD D2_3+ D2_3- D0_1+ D0_1- OF + OF - GND ENC- 11 12 13 14 15 16 17 18 19 20 ENC+ Supply Voltage VDD, OVDD................................................. -0.3V to 2V Analog Input Voltage AIN+, AIN -, PAR/SER, SENSE (Note 3)......................... -0.3V to (VDD + 0.2V) Digital Input Voltage ENC+, ENC- (Note 3)................. -0.3V to (VDD + 0.3V) CS, SDI, SCK (Note 4)............................ -0.3V to 3.9V SDO (Note 4).............................................. -0.3V to 3.9V Digital Output Voltage................. -0.3V to (OVDD + 0.3V) Operating Temperature Range LTC2153C................................................. 0C to 70C LTC2153I..............................................-40C to 85C Storage Temperature Range................... -65C to 150C UJ PACKAGE 40-LEAD (6mm x 6mm) PLASTIC QFN TJMAX = 150C, JA = 34C/W EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2153CUJ-14#PBF LTC2153IUJ-14#PBF LTC2153CUJ-14#TRPBF LTC2153UJ-14 40-Lead (6mm x 6mm) Plastic QFN 0C to 70C LTC2153IUJ-14#TRPBF LTC2153UJ-14 40-Lead (6mm x 6mm) Plastic QFN -40C to 85C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2 215314fa For more information www.linear.com/LTC2153-14 LTC2153-14 Converter Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) PARAMETER CONDITIONS MIN Resolution (No Missing Codes) l 14 TYP MAX UNITS Bits Integral Linearity Error Differential Analog Input (Note 6) l -7.5 1.2 7.5 LSB Differential Linearity Error Differential Analog Input l -1 0.35 1 LSB Offset Error (Note 7) l -15 5 15 mV Gain Error Internal Reference External Reference l -4.5 1.5 1 3 %FS %FS Offset Drift Full-Scale Drift Internal Reference External Reference Transition Noise 20 V/C 30 10 ppm/C ppm/C 2.11 LSBRMS Analog Input The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Analog Input Range (AIN+ - AIN-) 1.74V < VDD < 1.9V l VIN(CM) Analog Input Common Mode (AIN+ + AIN-)/2 Differential Analog Input (Note 8) l VCM - 20mV VCM VCM + 20mV V VSENSE External Voltage Reference Applied to SENSE External Reference Mode l 1.230 1.250 1.270 V l -1 1 A 1.32 VP-P IIN1 Analog Input Leakage Current 0 < AIN+, AIN- < VDD, No Encode IIN2 PAR/SER Input Leakage Current 0 < PAR/SER < VDD l -1 1 A IIN3 SENSE Input Leakage Current 1.23V < SENSE < 1.27V l -1 1 A tAP Sample-and-Hold Acquisition Delay Time 1 tJITTER Sample-and-Hold Acquisition Delay Jitter 0.15 CMRR Analog Input Common Mode Rejection Ratio BW-3B Full-Power Bandwidth ns psRMS 75 dB 1250 MHz Dynamic Accuracy The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. AIN = -1dBFS. (Note 5) SYMBOL PARAMETER CONDITIONS SNR Signal-to-Noise Ratio 15MHz Input 70MHz Input 140MHz Input SFDR Spurious Free Dynamic Range 2nd or 3rd Harmonic 15MHz Input 70MHz Input 140MHz Input Spurious Free Dynamic Range 4th Harmonic or Higher S/(N+D) Signal-to-Noise Plus Distortion Ratio 15MHz Input 70MHz Input 140MHz Input 15MHz Input 70MHz Input 140MHz Input l l l l MIN TYP MAX UNITS 66 68.8 68.4 67.7 dBFS dBFS dBFS 70 88 85 79 dBFS dBFS dBFS 80 98 95 90 dBFS dBFS dBFS 65 68.7 68.4 67.2 dBFS dBFS dBFS 215314fa For more information www.linear.com/LTC2153-14 3 LTC2153-14 Internal Reference Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) PARAMETER CONDITIONS VCM Output Voltage IOUT = 0 MIN TYP MAX 0.439 * VDD - 18mV 0.439 * VDD 0.439 * VDD + 18mV VCM Output Temperature Drift UNITS 37 VCM Output Resistance -1mA < IOUT < 1mA VREF Output Voltage IOUT = 0 ppm/C 4 1.225 1.250 VREF Output Temperature Drift 1.275 V 30 VREF Output Resistance -400A < IOUT < 1mA VREF Line Regulation 1.74V < VDD < 1.9V V ppm/C 7 0.6 mV/V Power Requirements The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) SYMBOL PARAMETER MIN TYP MAX VDD Analog Supply Voltage (Note 9) CONDITIONS l 1.74 1.8 1.9 UNITS V OVDD Output Supply Voltage (Note 9) l 1.74 1.8 1.9 V l IVDD Analog Supply Current 190 206 mA IOVDD Digital Supply Current 1.75mA LVDS Mode 3.5mA LVDS Mode l l 33 53 40 60 mA mA PDISS Power Dissipation 1.75mA LVDS Mode 3.5mA LVDS Mode l l 401 437 443 479 mW mW PSLEEP Sleep Mode Power Clock Disabled Clocked at fS(MAX) <5 <5 mW mW PNAP Nap Mode Power Clocked at fS(MAX) 124 mW Digital Inputs And Outputs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ENCODE INPUTS (ENC+, ENC-) VID Differential Input Voltage (Note 8) l 0.2 VICM Common Mode Input Voltage Internally Set Externally Set (Note 8) l 1.1 V 1.2 1.5 V V RIN Input Resistance (See Figure 2) 10 k CIN Input Capacitance (Note 8) 2 pF DIGITAL INPUTS (CS, SDI, SCK) VIH High Level Input Voltage VDD = 1.8V l VIL Low Level Input Voltage VDD = 1.8V l IIN Input Current VIN = 0V to 3.6V l CIN Input Capacitance (Note 8) 1.3 V -10 0.6 V 10 A 3 pF SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO Is Used) ROL Logic Low Output Resistance to GND VDD = 1.8V, SDO = 0V IOH Logic High Output Leakage Current SDO = 0V to 3.6V COUT Output Capacitance (Note 8) 4 200 l -10 10 4 A pF 215314fa For more information www.linear.com/LTC2153-14 LTC2153-14 DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) SYMBOL PARAMETER DIGITAL DATA OUTPUTS VOD Differential Output Voltage VOS Common Mode Output Voltage RTERM On-Chip Termination Resistance CONDITIONS 100 Differential Load, 3.5mA Mode 100 Differential Load, 1.75mA Mode 100 Differential Load, 3.5mA Mode 100 Differential Load, 1.75mA Mode Termination Enabled, OVDD = 1.8V l l l l MIN TYP MAX UNITS 247 125 1.125 1.125 350 175 1.250 1.250 100 454 250 1.375 1.375 mV mV V V Timing Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) fS tL Sampling Frequency ENC Low Time (Note 8) tH ENC High Time (Note 8) (Note 9) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l l l l MIN 10 1.5 1.2 1.5 1.2 TYP 1.61 1.61 1.61 1.61 MAX 310 50 50 50 50 UNITS MHz ns ns ns ns UNITS DIGITAL DATA OUTPUTS MIN TYP MAX tD ENC to Data Delay CL = 5pF (Note 8) l 1.7 2 2.3 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1.3 1.6 2 ns tSKEW DATA to CLKOUT Skew tD - tC (Note 8) l 0.3 0.4 0.55 ns Pipeline Latency 6 6 Cycles SPI Port Timing (Note 8) tSCK SCK Period tS CS to SCK Set-Up Time tH Write Mode Readback Mode CSDO= 20pF, RPULLUP = 2k l 40 250 5 ns ns ns SCK to CS Hold Time l 5 ns tDS SDI Set-Up Time l 5 ns tDH SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid Readback Mode, CSDO = 20pF, RPULLUP = 2k Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND with GND and OGND shorted (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: When these pin voltages are taken below GND they will be clamped by internal diodes. When these pin voltages are taken above VDD they will not be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND without latchup. l l l 125 ns Note 5: VDD = OVDD = 1.8V, fSAMPLE = 310MHz, differential ENC+/ENC- = 2VP-P sine wave, input range = 1.32VP-P with differential drive, unless otherwise noted. Note 6: Integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Offset error is the offset voltage measured from -0.5LSB when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111 in 2's complement output mode. Note 8: Guaranteed by design, not subject to test. Note 9: Recommended operating conditions. 215314fa For more information www.linear.com/LTC2153-14 5 LTC2153-14 Typical Performance Characteristics LTC2153-14: Integral Nonlinearity (INL) LTC2153-14: Differential Nonlinearity (DNL) LTC2153-14: 32K Point FFT, fIN = 15MHz, -1dBFS, 310Msps 0.50 2.0 0 1.5 -20 DNL ERROR (LSB) INL ERROR (LSB) 0.5 0 -0.5 AMPLITUDE (dBFS) 0.25 1.0 0 -0.25 -1.0 0 4096 8192 12288 OUTPUT CODE 16383 -0.50 -80 4096 8192 12288 OUTPUT CODE 16383 -120 -20 -20 -20 -40 -60 -80 -100 -100 -120 AMPLITUDE (dBFS) 0 -80 0 20 40 60 80 100 120 140 FREQUENCY (MHz) -120 0 20 40 -20 -20 -80 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 215314 G07 6 -60 -80 -120 0 20 40 0 LTC2153-14: 32K Point FFT, fIN = 421MHz, -1dBFS, 310Msps -20 -40 -60 -80 -120 60 80 100 120 140 FREQUENCY (MHz) 215314 G06 LTC2153-14: 32K Point FFT, fIN = 383MHz, -1dBFS, 310Msps -100 -100 -120 60 80 100 120 140 FREQUENCY (MHz) AMPLITUDE (dBFS) 0 AMPLITUDE (dBFS) 0 -60 -40 215314 G05 LTC2153-14: 32K Point FFT, fIN = 223MHz, -1dBFS, 310Msps 60 80 100 120 140 FREQUENCY (MHz) -100 215314 G04 -40 40 LTC2153-14: 32K Point FFT, fIN = 185MHz, -1dBFS, 310Msps 0 -60 20 215314 G03 0 -40 0 215314 G02 LTC2153-14: 32K Point FFT, fIN = 150MHz, -1dBFS, 310Msps AMPLITUDE (dBFS) AMPLITUDE (dBFS) 0 215314 G01 LTC2153-14: 32K Point FFT, fIN = 70MHz, -1dBFS, 310Msps AMPLITUDE (dBFS) -60 -100 -1.5 -2.0 -40 -40 -60 -80 -100 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 215314 G08 -120 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 215314 G09 215314fa For more information www.linear.com/LTC2153-14 LTC2153-14 Typical Performance Characteristics 0 -60 -80 -100 -40 -60 -80 -100 0 20 40 -120 60 80 100 120 140 FREQUENCY (MHz) 0 20 40 100 15000 80 SFDR (dBFS) 20000 8212 8216 215314 G13 20 40 60 LTC2153-14: SNR vs Input Level, fIN = 70MHz, 1.32V Range, 310Msps 50 dBc 75 90 80 70 70 65 SNR (dBFS) 30 dBc 30 10 LTC2153-14: SFDR vs Input Frequency, -1dBFS, 1.32V Range, 310Msps 40 40 20 0 215314 G14 50 dBFS 60 0 -90 -80 -70 -60 -50 -40 -30 -20 -10 AMPLITUDE (dBFS) 60 60 80 100 120 140 FREQUENCY (MHz) 215314 G12 dBFS 20 8200 8204 8208 OUTPUT CODE 0 70 40 SFDR (dBFS) COUNT -120 60 80 100 120 140 FREQUENCY (MHz) 120 8196 -80 LTC2153-14: SFDR vs Input Level, fIN = 70MHz, 1.32V Range, 310Msps LTC2153-14: Shorted Input Histogram 0 8192 -60 215314 G11 25000 5000 -40 -100 215314 G10 10000 LTC2153-14: 32K Point 2-Tone FFT, fIN = 71MHz and 69MHz, 310Msps -20 AMPLITUDE (dBFS) -40 -120 0 -20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -20 LTC2153-14: 32K Point FFT, fIN = 907MHz, -1dBFS, 310Msps SNR (dBFS) 0 LTC2153-14: 32K Point FFT, fIN = 567MHz, -1dBFS, 310Msps 0 -60 -50 -40 -30 -20 AMPLITUDE (dBFS) -10 0 215314 G15 LTC2153-14: SNR vs Input Frequency, -1dBFS, 1.32V Range, 310Msps 60 55 50 20 45 10 0 0 100 200 300 400 500 600 700 800 900 1000 INPUT FREQUENCY (MHz) 215314 G16 40 0 100 200 300 400 500 600 700 800 900 1000 INPUT FREQUENCY (MHz) 215314 G17 215314fa For more information www.linear.com/LTC2153-14 7 LTC2153-14 Typical Performance Characteristics LTC2153-14: IOVDD vs Sample Rate, 15MHz Sine Wave Input, -1dBFS LTC2153-14: Frequency Response 200 -0.5 55 190 -1.0 LVDS CURRENT 3.5mA 180 IVDD (mA) 45 40 35 160 140 25 20 170 150 LVDS CURRENT 1.75mA 30 INPUT AMPLITUDE (dBFS) 60 50 IOVDD (mA) LTC2153-14: IVDD vs Sample Rate, 15MHz Sine Wave Input, -1dBFS 0 50 100 150 200 250 SAMPLE RATE (Msps) 300 130 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 0 215314 G18 62 186 124 248 SAMPLE RATE (Msps) 310 215314 G19 -4.5 100 1000 INPUT FREQUENCY (MHz) 215314 G20 Pin Functions VDD (Pins 1, 2): 1.8V Analog Power Supply. Bypass to ground with 0.1F ceramic capacitor. Pins 1, 2 can share a bypass capacitor. GND (Pins 3, 6, 10, 13, 35, Exposed Pad Pin 41): ADC Power Ground. The exposed pad must be soldered to the PCB ground. AIN+ (Pin 4): Positive Differential Analog Input. AIN- (Pin 5): Negative Differential Analog Input. SENSE (Pin 7): Reference Programming Pin. Connecting SENSE to VDD selects the internal reference and a 0.66V input range. An external reference between 1.23V and 1.27V applied to SENSE selects an input range of 0.528 * VSENSE. 8 VREF (Pin 8): Reference Voltage Output. Bypass to ground with a 2.2F ceramic capacitor. Nominally 1.25V. VCM (Pin 9): Common Mode Bias Output; nominally equal to 0.439 * VDD. VCM should be used to bias the common mode of the analog inputs. Bypass to ground with a 0.1F ceramic capacitor. ENC+ (Pin 11): Encode Input. Conversion starts on the rising edge. ENC- (Pin 12): Encode Complement Input. Conversion starts on the falling edge. OVDD (Pins 20, 30): 1.8V Output Driver Supply. Bypass to ground with a 0.1F ceramic capacitor. 215314fa For more information www.linear.com/LTC2153-14 LTC2153-14 Pin Functions OGND (Pin 21): LVDS Driver Ground. SDO (Pin 36): Serial Interface Data Output. In serial programming mode, (PAR/SER = 0V), SDO is the optional serial interface data output. Data on SDO is read back from the mode control registers and can be latched on the falling edge of SCK. SDO is an open-drain N-channel MOSFET output that requires an external 2k pull-up resistor from 1.8V to 3.3V. If readback from the mode control registers is not needed, the pull-up resistor is not necessary and SDO can be left unconnected. SDI (Pin 37): Serial Interface Data Input. In serial programming mode, (PAR/SER = 0V), SDI is the serial interface data input. Data on SDI is clocked into the mode control registers on the rising edge of SCK. In parallel programming mode (PAR/SER = VDD), SDI selects 3.5mA or 1.75mA LVDS output current (see Table 2). SCK (Pin 38): Serial Interface Clock Input. In serial programming mode, (PAR/SER = 0V), SCK is the serial interface clock input. In parallel programming mode (PAR/ SER = VDD), SCK controls the sleep mode (see Table 2). CS (Pin 39): Serial Interface Chip Select Input. In serial programming mode, (PAR/SER = 0V), CS is the serial interface chip select input. When CS is low, SCK is enabled for shifting data on SDI into the mode control registers. In parallel programming mode (PAR/SER = VDD), CS controls the clock duty cycle stabilizer (see Table 2). PAR/SER (Pin 40): Programming Mode Selection Pin. Connect to ground to enable the serial programming mode. CS, SCK, SDI and SDO become a serial interface that control the A/D operating modes. Connect to VDD to enable the parallel programming mode where CS, SCK and SDI become parallel logic inputs that control a reduced set of the A/D operating modes. PAR/SER should be connected directly to ground or the VDD of the part and not be driven by a logic signal. LVDS Outputs (DDR LVDS) The following pins are differential LVDS outputs. The output current level is programmable. There is an optional internal 100 termination resistor between the pins of each LVDS output pair. D0_1-/D0_1+ to D12_13-/D12_13+ (Pins 16/17, 18/19, 22/23, 24/25, 28/29, 31/32, 33/34): Double-Data Rate Digital Outputs. Two data bits are multiplexed onto each differential output pair. The even data bits (D0, D2, D4, D6, D8, D10, D12) appear when CLKOUT+ is low. The odd data bits (D1, D3, D5, D7, D9, D11, D13) appear when CLKOUT+ is high. CLKOUT -, CLKOUT+ (Pins 26, 27): Data Output Clock. The digital outputs normally transition at the same time as the falling and rising edges of CLKOUT+. The phase of CLKOUT+ can also be delayed relative to the digital outputs by programming the mode control registers. OF-, OF+ (Pins 14, 15): Over/Underflow Digital Output. OF+ is high when an overflow or underflow has occurred. This underflow is valid only when CLKOUT+ is low. In the second half clock cycle, the overflow is set to 0. 215314fa For more information www.linear.com/LTC2153-14 9 LTC2153-14 Functional Block Diagram VDD OVDD ANALOG INPUT 14-BIT PIPELINED ADC S/H VCM 0.1F GND CORRECTION LOGIC OUTPUT DRIVERS VCM BUFFER D12_13 * * * D0_1 OGND BUFFER CLOCK DDR LVDS CLOCK/DUTY CYCLE CONTROL CS SCK SDI SDO PAR/SER SPI VREF 2.2F 1.25V REFERENCE GND SENSE RANGE SELECT GND 215314 F01 Figure 1. Functional Block Diagram 10 215314fa For more information www.linear.com/LTC2153-14 LTC2153-14 Timing Diagrams Double Data Rate Output Timing, All Outputs Are Differential LVDS tAP N N+3 N+2 N+1 tL tH ENC- ENC+ CLKOUT+ CLKOUT - tC D0_1- D0N-6 D0_1+ D1N-6 D0N-5 D1N-5 D0N-4 D1N-4 D12N-6 D13N-6 D12N-5 D13N-5 D12N-4 D13N-4 OFN-6 INVALID OFN-5 INVALID OFN-4 INVALID tD D12_13- D12_13+ OF- OF+ 215314 TD01 tSKEW SPI Port Timing (Readback Mode) tS tDS tDH tSCK tH CS SCK tDO SDI SDO R/W A6 A5 A4 A3 A2 A1 A0 XX D7 HIGH IMPEDANCE XX D6 XX D5 XX D4 XX D3 XX D2 XX XX D1 D0 SPI Port Timing (Write Mode) CS SCK SDI SDO R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 215314 TD02 HIGH IMPEDANCE 215314fa For more information www.linear.com/LTC2153-14 11 LTC2153-14 APPLICATIONS INFORMATION CONVERTER OPERATION INPUT DRIVE CIRCUITS The LTC2153-14 is a 14-bit 310Msps A/D converter powered by a single 1.8V supply. The analog inputs must be driven differentially. The encode inputs should be driven differentially for optimal performance. The digital outputs are double data rate LVDS. Additional features can be chosen by programming the mode control registers through a serial SPI port. Input Filtering ANALOG INPUT The analog input is a differential CMOS sample-andhold circuit (Figure 2). The input must be driven differentially around a common mode voltage set by the VCM output pin, which is nominally 0.439 * VDD. For the 1.32V input range, the input should swing from VCM - 0.33V to VCM + 0.33V. There should be 180 phase difference between the inputs. If possible, there should be an RC lowpass filter right at the analog inputs. This lowpass filter isolates the drive circuitry from the A/D sample-and-hold switching, and also limits wide band noise from the drive circuitry. Figure 3 shows an example of an input RC filter. The RC component values should be chosen based on the application's specific input frequency. Transformer-Coupled Circuits Figure 3 shows the analog input being driven by an RF transformer with the common mode supplied through a pair of resistors via the VCM pin. At higher input frequencies a transmission line balun transformer (Figures 4 and 5) has better balance, resulting in lower A/D distortion. 10 LTC2153-14 VDD RON 20 + 2pF 0.1F AIN 4.7 IN 2pF LTC2153-14 AIN+ 25 VDD RON 20 AIN- VCM 0.1F 2pF 2pF 10pF 0.1F 4.7 25 AIN- T1: MACOM ETC1-1T VDD 215314 F03 Figure 3. Analog Input Circuit Using a Transformer. Recommended for Input Frequencies from 5MHz to 70MHz 1.2V 10 10k ENC+ VCM 0.1F 0.1F ENC- LTC2153-14 4.7 IN AIN+ 45 0.1F 215314 F02 Figure 2. Equivalent Input Circuit. Only One of Two Analog Channels Is Shown 0.1F 100 45 T1: MABA T2: WBC1-1L 007159-000000 4.7 AIN- 215314 F04 Figure 4. Recommended Front-End Circuit for Input Frequencies from 15MHz to 150MHz 12 215314fa For more information www.linear.com/LTC2153-14 LTC2153-14 Applications Information Amplifier Circuits VCM AIN+ AIN- At very high frequencies an RF gain block will often have lower distortion than a differential amplifier. If the gain block is single-ended, then a transformer circuit (Figures 3 and 5) should convert the signal to differential before driving the A/D. The A/D cannot be driven single-ended. LTC2153-14 4.7 IN Figure 6 shows the analog input being driven by a high speed differential amplifier. The output of the amplifier is AC coupled to the A/D so the amplifier's output common mode voltage can be optimally set to minimize distortion. 0.1F 10 0.1F 45 100 0.1F 45 0.1F 4.7 T1: MABA 007159-000000 215314 F05 Figure 5. Recommended Front-End Circuit for Input Frequencies from 150MHz to 900MHz 50 The LTC2153-14 has an internal 1.25V voltage reference. For a 1.32V input range with internal reference, connect SENSE to VDD. For a 1.32V input range with an external reference, apply a 1.25V reference voltage to SENSE (Figure 7). VCM 0.1F 50 Reference LTC2153-14 Encode Input 3pF 0.1F 4.7 INPUT 0.1F 4.7 3pF AIN+ AIN- 3pF 215314 F06 The signal quality of the encode inputs strongly affects the A/D noise performance. The encode inputs should be treated as analog signals--do not route them next to digital traces on the circuit board. The encode inputs are internally biased to 1.2V through 10k equivalent resistance (Figure 8). If the common mode of the driver is within 1.1V to 1.5V, it is possible to drive the encode inputs directly. Otherwise a transformer or Figure 6. Front-End Circuit Using a High Speed Differential Amplifier LTC2153-14 VREF 5 VDD LTC2153-14 1.25V 1.2V 2.2F SCALER/ BUFFER SENSE ADC REFERENCE SENSE DETECTOR ENC+ ENC- 215314 F07 Figure 7. Reference Circuit 10k 215314 F08 Figure 8. Equivalent Encode Input Circuit 215314fa For more information www.linear.com/LTC2153-14 13 LTC2153-14 Applications Information coupling capacitors are needed (Figures 9 and 10). The maximum (peak) voltage of the input signal should never exceed VDD +0.1V or go below -0.1V. this case, care should be taken to make the clock a 50% (5%) duty cycle. Clock Duty Cycle Stabilizer DIGITAL OUTPUTS For good performance the encode signal should have a 50% (5%) duty cycle. If the optional clock duty cycle stabilizer circuit is enabled, the encode duty cycle can vary from 30% to 70% and the duty cycle stabilizer will maintain a constant 50% internal duty cycle. The duty cycle stabilizer is enabled via SPI Register A2 (see Table 3) or by CS in parallel programming mode. The digital outputs are double-data rate LVDS signals. Two data bits are multiplexed and output on each differential output pair. There are seven LVDS output pairs (D0_1+/D0_1- through D12_13-/D12_13+). Overflow (OF+/OF -) and the data output clock (CLKOUT+/CLKOUT-) each have an LVDS output pair. By default the outputs are standard LVDS levels: 3.5mA output current and a 1.25V output common mode voltage. For applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. In LTC2153-14 VDD 1.2V 0.1F 10k 50 100 0.1F 50 T1: MACOM ETC1-1-13 215314 F09 Figure 9. Sinusoidal Encode Drive LTC2153-14 VDD 1.2V 0.1F PECL OR LVDS INPUT ENC+ 10k 100 0.1F ENC- 215314 F10 Figure 10. PECL or LVDS Encode Drive 14 215314fa For more information www.linear.com/LTC2153-14 LTC2153-14 Applications Information Programmable LVDS Output Current The default output driver current is 3.5mA. This current can be adjusted by serially programming mode control register A3 (see Table 3). Available current levels are 1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA. Optional LVDS Driver Internal Termination In most cases, using just an external 100 termination resistor will give excellent LVDS signal integrity. In addition, an optional internal 100 termination resistor can be enabled by serially programming mode control register A3. The internal termination helps absorb any reflections caused by imperfect termination at the receiver. When the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. Overflow Bit The overflow output bit (OF) outputs a logic high when the analog input is either overranged or underranged. The overflow bit has the same pipeline latency as the data bits. When CLKINV is set to 0 in the SPI register A2, the OF signal is valid when CLKOUT+ is low, as shown in the Timing Diagrams section. Phase Shifting the Output Clock To allow adequate set-up and hold time when latching the output data, the CLKOUT+ signal may need to be phase shifted relative to the data output bits. Most FPGAs have this feature; this is generally the best place to adjust the timing. Alternatively, the ADC can also phase shift the CLKOUT+/ CLKOUT- signals by serially programming mode control register A2. The output clock can be shifted by 0, 45, 90, or 135. To use the phase shifting feature the clock duty cycle stabilizer must be turned on. Another control register bit can invert the polarity of CLKOUT+ and CLKOUT-, independently of the phase shift. The combination of these two features enables phase shifts of 45 up to 315 (Figure 11). ENC+ D0-D13, OF CLKOUT+ MODE CONTROL BITS PHASE SHIFT CLKINV CLKPHASE1 CLKPHASE0 0 0 0 0 45 0 0 1 90 0 1 0 135 0 1 1 180 1 0 0 225 1 0 1 270 1 1 0 315 1 1 1 215314 F11 Figure 11. Phase Shifting CLKOUT 215314fa For more information www.linear.com/LTC2153-14 15 LTC2153-14 Applications Information DATA FORMAT CLKOUT Table 1 shows the relationship between the analog input voltage, the digital data output bits and the overflow bit. By default the output data format is offset binary. The 2's complement format can be selected by serially programming mode control register A4. (1.32V Range) OF D13-D0 (OFFSET BINARY) D13 D13/D0 D12 D13-D0 (2's COMPLEMENT) >0.66V 1 11 1111 1111 1111 01 1111 1111 1111 +0.66V 0 11 1111 1111 1111 01 1111 1111 1111 +0.6599194V 0 11 1111 1111 1110 01 1111 1111 1110 +0.0000806V 0 10 0000 0000 0001 00 0000 0000 0001 +0.000000V 0 10 0000 0000 0000 00 0000 0000 0000 -0.0000806V 0 01 1111 1111 1111 11 1111 1111 1111 -0.0001611V 0 01 1111 1111 1110 11 1111 1111 1110 -0.6599194V 0 00 0000 0000 0001 10 0000 0000 0001 -0.66V 0 00 0000 0000 0000 10 0000 0000 0000 < -0.66V 1 00 0000 0000 0000 10 0000 0000 0000 Digital Output Randomizer D12/D0 * * * RANDOMIZER ON D1 D1/D0 D0 D0 215314 F12 Figure 12. Functional Equivalent of Digital Output Randomizer PC BOARD Interference from the A/D digital outputs is sometimes unavoidable. Digital interference may be from capacitive or inductive coupling or coupling through the ground plane. Even a tiny coupling factor can cause unwanted tones in the ADC output spectrum. By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized which reduces the unwanted tone amplitude. The digital output is randomized by applying an exclusiveOR logic operation between the LSB and all other data output bits. To decode, the reverse operation is applied--an exclusive-OR operation is applied between the LSB and all other bits. The LSB, OF and CLKOUT outputs are not affected. The output randomizer is enabled by serially programming mode control register A4. 16 OF OF Table 1. Output Codes vs Input Voltage AIN+ - AIN- CLKOUT CLKOUT FPGA OF D13/D0 LTC2153-14 D13 D12/D0 D1/D0 D0 * * * D12 D1 D0 215314 F13 Figure 13. Decoding a Randomized Digital Output Signal 215314fa For more information www.linear.com/LTC2153-14 LTC2153-14 Applications Information Alternate Bit Polarity Sleep Mode Another feature that may reduce digital feedback on the circuit board is the alternate bit polarity mode. When this mode is enabled, all of the odd bits (D1, D3, D5, D7, D9, D11, D13) are inverted before the output buffers. The even bits (D0, D2, D4, D6, D8, D10, D12), OF and CLKOUT are not affected. This can reduce digital currents in the circuit board ground plane and reduce digital noise, particularly for very small analog input signals. The A/D may be placed in sleep mode to conserve power. In sleep mode the entire A/D converter is powered down, resulting in < 5mW power consumption. If the encode input signal is not disabled the power consumption will be higher (up to 5mW at 310MHz). Sleep mode is enabled by mode control register A1 (serial programming mode), or by SCK (parallel programming mode). The digital output is decoded at the receiver by inverting the odd bits (D1, D3, D5, D7, D9, D11, D13.) The alternate bit polarity mode is independent of the digital output randomizer--either both or neither function can be on at the same time. The alternate bit polarity mode is enabled by serially programming mode control register A4. Digital Output Test Patterns To allow in-circuit testing of the digital interface to the A/D, there are several test modes that force the A/D data outputs (OF, D13 to D0) to known values: The amount of time required to recover from sleep mode depends on the size of the bypass capacitor on VREF . For the suggested value in Figure 1, the A/D will stabilize after 0.1ms + 2500 * tp where tp is the period of the sampling clock. Nap Mode In nap mode the A/D core is powered down while the internal reference circuits stay active, allowing faster wake-up. Recovering from nap mode requires at least 100 clock cycles. Nap mode is enabled by setting register A1 in the serial programming mode. All 0s: All outputs are 0 Wake-up time from nap mode is guaranteed only if the clock is kept running, otherwise sleep mode wake-up conditions apply. Alternating: Outputs change from all 1s to all 0s on alternating samples DEVICE PROGRAMMING MODES All 1s: All outputs are 1 Checkerboard: Outputs change from 101010101010101 to 010101010101010 on alternating samples. The digital output test patterns are enabled by serially programming mode control register A4. When enabled, the test patterns override all other formatting modes: 2's complement, randomizer, alternate-bit polarity. The operating modes of the LTC2153-14 can be programmed by either a parallel interface or a simple serial interface. The serial interface has more flexibility and can program all available modes. The parallel interface is more limited and can only program some of the more commonly used modes. Parallel Programming Mode Output Disable The digital outputs may be disabled by serially programming mode control register A3. All digital outputs including OF and CLKOUT are disabled. The high impedance disabled state is intended for long periods of inactivity, it is not designed for multiplexing the data bus between multiple converters. To use the parallel programming mode, PAR/SER should be tied to VDD. The CS, SCK and SDI pins are binary logic inputs that set certain operating modes. These pins can be tied to VDD or ground, or driven by 1.8V, 2.5V, or 3.3V CMOS logic. Table 2 shows the modes set by CS, SCK and SDI. 215314fa For more information www.linear.com/LTC2153-14 17 LTC2153-14 Applications Information Table 2. Parallel Programming Mode Control Bits (PAR/SER = VDD) PIN DESCRIPTION CS Clock Duty Cycle Stabilizer Control Bit 0 = Clock Duty Cycle Stabilizer Off 1 = Clock Duty Cycle Stabilizer On SCK Power Down Control Bit 0 = Normal Operation 1 = Sleep Mode (entire ADC is powered down) SDI LVDS Current Selection Bit 0 = 3.5mA LVDS Current Mode 1 = 1.75mA LVDS Current Mode If serial programming is used, the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. The first serial command must be a software reset which will reset all register data bits to logic 0. To perform a software reset it is necessary to write 1 in register A0 (Bit D7). After the reset is complete, Bit D7 is automatically set back to zero. This register is write-only. GROUNDING AND BYPASSING Serial Programming Mode To use the serial programming mode, PAR/SER should be tied to ground. The CS, SCK, SDI and SDO pins become a serial interface that program the A/D control registers. Data is written to a register with a 16-bit serial word. Data can also be read back from a register to verify its contents. Serial data transfer starts when CS is taken low. The data on the SDI pin is latched at the first sixteen rising edges of SCK. Any SCK rising edges after the first sixteen are ignored. The data transfer ends when CS is taken high again. The first bit of the 16-bit input word is the R/W bit. The next seven bits are the address of the register (A6:A0). The final eight bits are the register data (D7:D0). If the R/W bit is low, the serial data (D7:D0) will be written to the register set by the address bits (A6:A0). If the R/W bit is high, data in the register set by the address bits (A6:A0) will be read back on the SDO pin (see the Timing Diagrams). During a readback command the register is not updated and data on SDI is ignored. The SDO pin is an open-drain output that pulls to ground with a 200 impedance. If register data is read back through SDO, an external 2k pull-up resistor is required. If serial data is only written and readback is not needed, then SDO can be left floating and no pull-up resistor is needed. Table 3 shows a map of the mode control registers. 18 Software Reset The LTC2153-14 requires a printed circuit board with a clean unbroken ground plane in the first layer beneath the ADC. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, OVDD, VCM, VREF pins. Bypass capacitors must be located as close to the pins as possible. Size 0402 ceramic capacitors are recommended. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The analog inputs, encode signals, and digital outputs should not be routed next to each other. Ground fill and grounded vias should be used as barriers to isolate these signals from each other. HEAT TRANSFER Most of the heat generated by the LTC2153-14 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the PC board. This pad should be connected to the internal ground planes by an array of vias. 215314fa For more information www.linear.com/LTC2153-14 LTC2153-14 Applications Information Table 3. Serial Programming Mode Register Map (PAR/SER = GND). X indicates an unused bit that is read back as 0 REGISTER A0: RESET REGISTER (ADDRESS 00h) Write Only D7 D6 D5 D4 D3 D2 D1 D0 RESET X X X X X X X RESET Bit 7 Software Reset Bit 0 = Reset Disabled 1 = Software Reset. All mode control registers are reset to 00h. This bit is automatically set back to zero after the reset is complete. Unused Bits Bits 6-0 REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h) D7 D6 D5 D4 D3 D2 D1 D0 X X X X SLEEP NAP 0 0 Bits 7-4 Unused Bit Bit 3 SLEEP 0 = Normal Operation 1 = Power Down Entire ADC Bit 2 NAP 0 = Normal Mode 1 = Low Power Mode Must be set to 0 Bit 1-0 REGISTER A2: TIMING REGISTER (ADDRESS 02h) D7 X D6 D5 D4 D3 D2 D1 D0 X X X CLKINV CLKPHASE1 CLKPHASE0 DCS Bits 7-4 Unused Bit Bit 3 CLKINV Output Clock Invert Bit 0 = Normal CLKOUT Polarity (as shown in the Timing Diagrams) 1 = Inverted CLKOUT Polarity Bits 2-1 Output Clock Phase Delay Bits CLKPHASE1:CLKPHASE0 00 = No CLKOUT Delay (as shown in the Timing Diagrams) 01 = CLKOUT+/CLKOUT- delayed by 45 (Clock Period * 1/8) 10 = CLKOUT+/CLKOUT- delayed by 90 (Clock Period * 1/4) 11 = CLKOUT+/CLKOUT- delayed by 135 (Clock Period * 3/8) Note: If the CLKOUT phase delay feature is used, the clock duty cycle stabilizer must also be turned on. Bit 0 DCS Clock Duty Cycle Stabilizer Bit 0 = Clock Duty Cycle Stabilizer Off 1 = Clock Duty Cycle Stabilizer On 215314fa For more information www.linear.com/LTC2153-14 19 LTC2153-14 Applications Information REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h) D7 X D6 D5 D4 D3 D2 D1 D0 X X ILVDS2 ILVDS1 ILVDS0 TERMON OUTOFF Bits 7-5 Unused Bit Bits 4-2 ILVDS2:ILVDS0 LVDS Output Current Bits 000 = 3.5mA LVDS Output Driver Current 001 = 4.0mA LVDS Output Driver Current 010 = 4.5mA LVDS Output Driver Current 011 = Not Used 100 = 3.0mA LVDS Output Driver Current 101 = 2.5mA LVDS Output Driver Current 110 = 2.1mA LVDS Output Driver Current 111 = 1.75mA LVDS Output Driver Current Bit 1 TERMON LVDS Internal Termination Bit 0 = Internal Termination Off 1 = Internal Termination On. LVDS output driver current is 2x the current set by ILVDS2:ILVDS0 Bit 0 OUTOFF Digital Output Mode Control Bits 0 = Digital Outputs Are Enabled 1 = Digital Outputs Are Disabled (High Impedance) REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h) D7 OUTTEST2 D6 D5 D4 D3 D2 D1 D0 OUTTEST1 OUTTEST0 ABP 0 DTESTON RAND TWOSCOMP Bits 7-5 OUTTEST2:OUTTEST0 Digital Output Test Pattern Bits 000 = All Digital Outputs = 0 001 = All Digital Outputs = 1 010 = Alternating Output Pattern. OF, D13-D0 alternate between 000 0000 0000 0000 and 111 1111 1111 1111 100 = Checkerboard Output Pattern. OF, D13-D0 alternate between 101 0101 0101 0101 and 010 1010 1010 1010 Bit 4 ABP Alternate Bit Polarity Mode Control Bit 0 = Alternate Bit Polarity Mode Off 1 = Alternate Bit Polarity Mode On Bit 3 Must Be Set to 0 Bit 2 Enable the digital output test patterns (set by Bits 7-5) DTESTON 0 = Normal Mode 1 = Enable the Digital Output Test Patterns Bit 1 Data Output Randomizer Mode Control Bit RAND 0 = Data Output Randomizer Mode Off 1 = Data Output Randomizer Mode On Bit 0 TWOSCOMP Two's Complement Mode Control Bit 0 = Offset Binary Data Format 1 = Two's Complement Data Format Note 1: Other bit combinations are not used. 20 215314fa For more information www.linear.com/LTC2153-14 LTC2153-14 Applications Information 215314 F14 Silkscreen Top 215314 F15 Inner Layer 1 GND 215314 F16 Inner Layer 2 215314 F17 Inner Layer 3 215314fa For more information www.linear.com/LTC2153-14 21 LTC2153-14 Applications Information 215314 F18 Inner Layer 4 22 215314 F19 Inner Layer 5 215314 F20 Bottom Layer 6 215314fa For more information www.linear.com/LTC2153-14 LTC2153-14 TYPICAL APPLICATION LTC2153-14 Schematic C35 0.1F VDD D10_11- C34 0.1F D10_11+ C12 0.1F SDO SDI SCK CS PAR/SER D12_13- L5 BEAD 0.2F SENSE 6 7 8 9 10 41 C21 0.1F AINA- D10_11- 31 D12_13- 33 D10_11+ 32 LTC2153-14 GND D8_9- 28 CLKOUT - 26 D6_7+ SENSE VREF 25 D6_7- 24 D4_5- 22 23 D4_5+ VCM GND GND 30 27 CLKOUT+ OGND 21 D8_9+ D8_9- CLKOUT+ CLKOUT - D6_7+ D6_7 - D4_5+ D4_5- 215314 TA02 OVDD 0.1F D2_3+ D2_3- 0.1F D0_1+ VCM 10 C16 2.2F OVDD DD 5 R16 100 AINA+ 0.1F 29 D8_9+ 19 D2_3+ 20 OV 4 GND OF + R19 10 3 VDD 17 D0_1+ 18 D2_3- R14 10 VDD SDO 36 GND 35 D12_13+ 34 2 15 OF + 16 D0_1- 1 D0_1- AINA- C13 2.2F SCK 38 SDI 37 SENSE AINA+ OVDD R9 1k TP3 13 GND 14 OF - C11 47F 1210 OF - + PAR/SER 40 CS 39 C10 1F 11 CLK+ 12 CLK- REGULATED 1.8V VDD OVDD D12_13+ L4 BEAD 0.1F 100 CLK+ CLK- 215314fa For more information www.linear.com/LTC2153-14 23 LTC2153-14 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UJ Package 40-Lead Plastic QFN (6mm x 6mm) (Reference LTC DWG # 05-08-1728 Rev O) 0.70 0.05 6.50 0.05 5.10 0.05 4.42 0.05 4.50 0.05 (4 SIDES) 4.42 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 6.00 0.10 (4 SIDES) 0.75 0.05 R = 0.10 TYP R = 0.115 TYP 39 40 0.40 0.10 PIN 1 TOP MARK (SEE NOTE 6) 1 4.50 REF (4-SIDES) 4.42 0.10 2 PIN 1 NOTCH R = 0.45 OR 0.35 45 CHAMFER 4.42 0.10 (UJ40) QFN REV O 0406 0.200 REF 0.00 - 0.05 NOTE: 1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 24 0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD 215314fa For more information www.linear.com/LTC2153-14 LTC2153-14 Revision History REV DATE DESCRIPTION A 12/14 Changed pipeline latency to 6 PAGE NUMBER Updated G15 5 and 11 7 215314fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of itsinformation circuits as described herein will not infringe on existing patent rights. For more www.linear.com/LTC2153-14 25 LTC2153-14 Typical Application LTC2153-14: 32K Point 2-Tone FFT, fIN = 71MHz and 69MHz, 310Msps VDD OVDD CLOCK S/H 14-BIT PIPELINED ADC CORRECTION LOGIC D12_13 * * * D0_1 OUTPUT DRIVERS DDR LVDS OGND CLOCK/DUTY CYCLE CONTROL -20 AMPLITUDE (dBFS) ANALOG INPUT 0 -40 -60 -80 GND 215314 TA03a -100 -120 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 215314 TA03b Related Parts PART NUMBER DESCRIPTION COMMENTS LTC2208 16-Bit, 130Msps, 3.3V ADC, LVDS Outputs 1250mW, 77.7dB SNR, 100dB SFDR, 64-Lead QFN Package LTC2158-14 14-Bit, 310Msps, 1.8V Dual ADC, DDR LVDS Outputs 724mW, 68.8dB SNR, 88dB SFDR, 64-Lead QFN Package LTC2157-14/LTC2156-14/ LTC2155-14 14-Bit, 250Msps/210Msps/170Msps, 1.8V Dual ADC, DDR LVDS Outputs 650mW/616mW/567mW, 70dB SNR, 90dB SFDR, 64-Lead QFN Package LTC2157-12/LTC2156-12/ LTC2155-12 12-Bit, 250Msps/210Msps/170Msps, 1.8V Dual ADC, DDR LVDS Outputs 628mW/692mW/545mW, 70dB SNR, 90dB SFDR, 64-Lead QFN Package LTC2242-12/LTC2241-12/ LTC2240-12 12-Bit, 250Msps/210Msps/170Msps, 2.5V ADC, LVDS Outputs 740mW/585mW/445mW, 65.5dB SNR, 80dB SFDR, 64-Lead QFN Package LT(R)5517 40MHz to 900MHz Direct Conversion Quadrature Demodulator High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator LT5527 400MHz to 3.7GHz High Linearity Downconverting Mixer 24.5dBm IIP3 at 900MHz, 23.5dBm IIP3 at 3.5GHz, NF = 12.5dB, 50 Single-Ended RF and LO Ports LT5575 800MHz to 2.7GHz Direct Conversion Quadrature Demodulator High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator, Integrated RF and LO Transformer LTC6409 10GHz GBW, 1.1nV/Hz Differential Amplifier/ ADC Driver 88dB SFDR at 100MHz, Input Range Includes Ground 52mA Supply Current, 3mm x 2mm QFN Package LTC6412 800MHz, 31dB Range, Analog-Controlled Variable Gain Amplifier Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz, 10dB Noise Figure, 4mm x 4mm QFN-24 Package LTC6420-20 1.8GHz Dual Low Noise, Low Distortion Differential ADC Drivers for 300MHz IF Fixed Gain 10V/V, 1nV/Hz Total Input Noise, 80mA Supply Current per Amplifier, 3mm x 4mm QFN-20 Package LTM(R)9002 14-Bit Dual Channel IF/Baseband Receiver Subsystem Integrated High Speed ADC, Passive Filters and Fixed Gain Differential Amplifiers LTM9003 12-Bit Digital Predistortion Receiver Integrated 12-Bit ADC Down-Converter Mixer with 0.4GHz to 3.8GHz Input Frequency Range ADCs RF Mixers/Demodulators Amplifiers/Filters Receiver Subsystems 26 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC2153-14 (408) 432-1900 FAX: (408) 434-0507 www.linear.com/LTC2153-14 215314fa LT 1214 REV A * PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2011