844011AGLFT - Integrated Device Technology

DATA SHEET

FemtoClock® Crystal-to-LVDS

Clock Generator

ICS844011

General Description

The ICS844011 is a Fibre Channel Clock Generator. The

ICS844011 uses an 18pF parallel resonant crystal. For Fibre

Channel applications, a 26.5625MHz crystal is used. The

ICS844011 has excellent <1ps phase jitter performance, over the

637kHz - 10MHz integration range. The ICS844011 is packaged in a

small 8-pin TSSOP, making it ideal for use in systems with limited

board space.

Features

•One differential LVDS clock output pair

•Crystal interface designed for 18pF parallel resonant crystals

•VCO range: 490MHz – 680MHz

•RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal

(637kHz - 10MHz): 0.97ps (typical)

•RMS phase jitter @ 100MHz, (637kHz - 10MHz):

0.77ps (typical)

•Full 3.3V or 2.5V operating supply

•Available in lead-free (RoHS 6) package

•0°C to 70°C ambient operating temperature

Common Configuration Table – Fibre Channel

Inputs

Output Frequency (MHz)Crystal Frequency (MHz) M N Multiplication Value M/N

26.5625 24 6 4 106.25

25 24 6 4 100

OSC Phase

Detector

VCO

490MHz - 680MHz

M = ÷24 (fixed)

N = ÷6 (fixed)

XTAL_IN

XTAL_OUT

Pullup

VDDA

GND

XTAL_OUT

XTAL_IN

VDD

Block Diagram Pin Assignment

ICS844011

8-lead TSSOP

4.40mm x 3.0mm x 0.925mm

package body

G Package

Top View

ICS844011 Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS CLOCK GENERATOR

Pin Description and Characteristic Tables

Table 1. Pin Descriptions

NOTE: Pullup refers to an internal input resistor. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Function Table

Table 3. OE Control Function Table

Number Name Type Description

DDA Power Analog power supply.

2GNDPower Power supply ground.

XTAL_OUT,

XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.

5 OE Input Pullup Output enable pin. LVCMOS/LVTTL interface levels.

6, 7 nQ, Q Output Differential clock output. LVDS interface levels.

DD Power Core supply pin.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

CIN Input Capacitance 4pF

RPULLUP Input Pullup Resistor 51 kΩ

Input

Output EnableOE

0 Output Q, nQ pair is disabled in high-impedance state.

1 (default) Output Q, nQ is enabled.

ICS844011 Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS CLOCK GENERATOR

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect product reliability.

DC Electrical Characteristics

Table 4A. Power Supply DC Characteristics, VDD = 3.3V±5%, TA = 0°C to 70°C

Table 4B. Power Supply DC Characteristics, VDD = 2.5V±5%, TA = 0°C to 70°C

Table 4C. LVCMOS/LVTTL Input DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = 0°C to 70°C

Item Rating

Supply Voltage, VDD 4.6V

Inputs, VI

XTAL_IN

Other Input

0V to VDD

-0.5V to VDD + 0.5V

Outputs, IO

Continuous Current

Surge Current

10mA

15mA

Package Thermal Impedance, θJA 129.5°C/W (0 mps)

Storage Temperature, TSTG -65°C to 150°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VDD Core Supply Voltage 3.135 3.3 3.465 V

VDDA Analog Supply Voltage VDD – 0.12 3.3 VDD V

IDD Power Supply Current 108 mA

IDDA Analog Supply Current 12 mA

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VDD Core Supply Voltage 2.375 2.5 2.625 V

VDDA Analog Supply Voltage VDD – 0.12 2.5 VDD V

IDD Power Supply Current 102 mA

IDDA Analog Supply Current 12 mA

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VIH Input High Voltage VDD = 3.3V 2 VDD + 0.3 V

VDD = 2.5V 1.7 VDD + 0.3 V

VIL Input Low Voltage VDD = 3.3V -0.3 0.8 V

VDD = 2.5V -0.3 0.7 V

IIH Input High Current OE VDD = VIN = 3.465V or 2.625V 5 µA

IIL Input Low Current OE VDD = 3.465V or 2.625V, VIN = 0V -150 µA

ICS844011 Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS CLOCK GENERATOR

Table 4D. LVDS DC Characteristics, VDD = 3.3V±5%, TA = 0°C to 70°C

Table 4E. LVDS DC Characteristics, VDD = 2.5V±5%, TA = 0°C to 70°C

Table 5. Crystal Characteristics

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VOD Differential Output Voltage 250 350 450 mV

∆VOD VOD Magnitude Change 50 mV

VOS Offset Voltage 1.1 1.3 1.5 V

∆VOS VOS Magnitude Change 50 mV

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VOD Differential Output Voltage 250 350 450 mV

∆VOD VOD Magnitude Change 50 mV

VOS Offset Voltage 0.9 1.2 1.5 V

∆VOS VOS Magnitude Change 50 mV

Parameter Test Conditions Minimum Typical Maximum Units

Mode of Oscillation Fundamental

Frequency 25 26.5625 MHz

Equivalent Series Resistance (ESR) 50 Ω

Shunt Capacitance 7pF

ICS844011 Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS CLOCK GENERATOR

AC Characteristics

Table 6A. AC Characteristics, VDD = 3.3V±5%, TA = 0°C to 70°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device

is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal

equilibrium has been reached under these conditions.

NOTE 1: Please refer to the phase noise plot.

Table 6B. AC Characteristics, VDD = 2.5V±5%, TA = 0°C to 70°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device

is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal

equilibrium has been reached under these conditions.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fOUT Output Frequency 100 106.25 MHz

tjit(Ø) RMS Phase Jitter (Random);

NOTE 1

106.25MHz, Integration Range:

637kHz – 10MHz 0.97 ps

100MHz, Integration Range:

637kHz – 10MHz 0.77 ps

tR / tFOutput Rise/Fall Time 20% to 80% 150 400 ps

odc Output Duty Cycle 48 52 %

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fOUT Output Frequency 100 106.25 MHz

tjit(Ø) RMS Phase Jitter (Random)

106.25MHz, Integration Range:

637kHz – 10MHz 1.26 ps

100MHz, Integration Range:

637kHz – 10MHz 0.98 ps

tR / tFOutput Rise/Fall Time 20% to 80% 150 400 ps

odc Output Duty Cycle 48 52 %

ICS844011 Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS CLOCK GENERATOR

Typical Phase Noise at 106.25MHz (3.3V)

Noise Power dBc

Offset Frequency (Hz)

ICS844011 Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS CLOCK GENERATOR

Parameter Measurement Information

3.3V LVDS Output Load Test Circuit

Output Duty Cycle/Pulse Width/Period

Differential Output Voltage Setup

Output Rise/Fall Time

2.5V LVDS Output Load Test Circuit

RMS Phase Jitter

Offset Voltage Setup

SCOPE

nQx

3.3V±5%

POWER SUPPLY

+–

Float GND

VDD

VDDA

tPERIOD

PERIOD

odc = x 100%

100

out

DC Input VOD/∆ VOD

VDD

20%

80% 80%

20%

SCOPE

nQx

2.5V±5%

POWER SUPPLY

+–

Float GND

VDD

VDDA

Offset Frequency

f1f2

Phase Noise Plot

Area Under Curve Defined by the Offset Frequency Markers

RMS Phase Jitter =

Noise Power

2 * * ƒ

out

LVDS

DC Input

/∆ V

ICS844011 Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS CLOCK GENERATOR

Applications Information

Overdriving the XTAL Interface

The XTAL_IN input can be overdriven by an LVCMOS driver or by one

side of a differential driver through an AC coupling capacitor. The

XTAL_OUT pin can be left floating. The amplitude of the input signal

should be between 500mV and 1.8V and the slew rate should not be

less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be

reduced from full swing to at least half the swing in order to prevent

signal interference with the power rail and to reduce internal noise.

Figure 1A shows an example of the interface diagram for a high

speed 3.3V LVCMOS driver. This configuration requires that the sum

of the output impedance of the driver (Ro) and the series resistance

(Rs) equals the transmission line impedance. In addition, matched

termination at the crystal input will attenuate the signal in half. This

can be done in one of two ways. First, R1 and R2 in parallel should

equal the transmission line impedance. For most 50Ω applications,

R1 and R2 can be 100Ω. This can also be accomplished by removing

R1 and changing R2 to 50Ω. The values of the resistors can be

increased to reduce the loading for a slower and weaker LVCMOS

driver. Figure 1B shows an example of the interface diagram for an

LVPECL driver. This is a standard LVPECL termination with one side

of the driver feeding the XTAL_IN input. It is recommended that all

components in the schematics be placed in the layout. Though some

components might not be used, they can be utilized for debugging

purposes. The datasheet specifications are characterized and

guaranteed by using a quartz crystal as the input.

Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface

Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface

VCC XTAL_OUT

XTAL_IN

100

Zo = 50 ohmsRs

Zo = Ro + Rs

.1uf

LVCMOS Driver

XTA L _ O U T

XTA L _ I N

Zo = 50 ohms C2

.1uf

LVPECL Driver

Zo = 50 ohms

ICS844011 Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS CLOCK GENERATOR

LVDS Driver Termination

For a general LVDS interface, the recommended value for the

termination impedance (ZT) is between 90Ω and 132Ω. The actual

value should be selected to match the differential impedance (Z0) of

your transmission line. A typical point-to-point LVDS design uses a

100Ω parallel resistor at the receiver and a 100Ω differential

transmission-line environment. In order to avoid any

transmission-line reflection issues, the components should be

surface mounted and must be placed as close to the receiver as

possible. IDT offers a full line of LVDS compliant devices with two

types of output structures: current source and voltage source. The

standard termination schematic as shown in Figure 2A can be used

with either type of output structure. Figure 2B, which can also be

used with both output types, is an optional termination with center tap

capacitance to help filter common mode noise. The capacitor value

should be approximately 50pF. If using a non-standard termination, it

is recommended to contact IDT and confirm if the output structure is

current source or voltage source type. In addition, since these

outputs are LVDS compatible, the input receiver’s amplitude and

common-mode input range should be verified for compatibility with

the output.

LVDS Termination

LVDS

Driver

LVDS

Driver

LVDS

Receiver

LVDS

Receiver

ZO ≈ ZT

Figure 2A. Standard Termination

Figure 2B. Optional Termination

ICS844011 Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS CLOCK GENERATOR

Schematic Layout

Figure 3 shows an example of ICS844011 application schematic in

which the device is operated at VDD = 3.3V. The schematic example

focuses on functional connections and is intended as an example

only and may not represent the exact user configuration. Refer to the

pin description and functional tables in the datasheet to ensure the

logic control inputs are properly set. For example OE can be

configured from an FPGA instead of set with pull up and pull down

resistors as shown.

As with any high speed analog circuitry, the power supply pins are

vulnerable to random noise, so to achieve optimum jitter performance

isolation of the VDD pin from power supply is required. In order to

achieve the best possible filtering, it is recommended that the

placement of the filter components be on the device side of the PCB

as close to the power pins as possible. If space is limited, the 0.1uF

capacitor on the VDD pin must be placed on the device side with

direct return to the ground plane though vias. The remaining filter

components can be on the opposite side of the PCB.

Power supply filter recommendations are a general guideline to be

used for reducing external noise from coupling into the devices. The

filter performance is designed for wide range of noise frequencies.

This low-pass filter starts to attenuate noise at approximately 10kHz.

If a specific frequency noise component is known, such as switching

power supply frequencies, it is recommended that component values

be adjusted and if required, additional filtering be added. Additionally,

good general design practices for power plane voltage stability

suggests adding bulk capacitances in the local area of all devices.

Figure 3. ICS844011 Application Schematic

3.3V

0.1uF

10uF

VDD

FB1

BLM18BB221SN1

Place 0.1uF bypass

caps directly

adjacent to the

respective VDD and

VDDA pins.

0.1uF

RU2

Not I nst all

VCC

RU1

VCC

RD2

RD1

Not Install

Set Logic

Input to '1'

To Logic

Input

pins

Logic Control Input Examples

Set Logic

Input to '0'

To Logic

Input

pins

VDDA

R1 10

10uF

0. 1u F

VDDAVDD

33pF

27pF

25MHz (18pf )

VDDA 1

nQ 6

XTAL _ O UT

XTAL _ I N

VD D 8

GND

LVDS Receiv er

Zo = 50 Ohm

100

ICS844011 Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS CLOCK GENERATOR

Power Considerations

This section provides information on power dissipation and junction temperature for the ICS844011.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS844011 is the sum of the core power plus the analog power plus the power dissipated in the load(s).

The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.

• Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (108mA + 12mA) = 415.8mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The

maximum recommended junction temperature for HiPerClockS devices is 125°C.

The equation for Tj is as follows: Tj = θJA * Pd_total + TA

Tj = Junction Temperature

θJA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and

a multi-layer board, the appropriate value is 129.5°C/W per Table 7 below.

Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:

70°C + 0.416W * 129.5°C/W = 123.9°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 7. Thermal Resistance θJA for 8 Lead TSSOP, Forced Convection

θJA by Velocity

Meters per Second 012.5

Multi-Layer PCB, JEDEC Standard Test Boards 129.5°C/W 125.5°C/W 123.5°C/W

ICS844011 Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS CLOCK GENERATOR

Reliability Information

Table 8. θJA vs. Air Flow Table for a 8-lead TSSOP

Transistor Count

The transistor count for ICS844011 is: 2533

Package Outline and Package Dimensions

Package Outline - G Suffix for 8 Lead TSSOP Table 9. Package Dimensions

Reference Document: JEDEC Publication 95, MO-153

θJA vs. Air Flow

Meters per Second 012.5

Multi-Layer PCB, JEDEC Standard Test Boards 129.5°C/W 125.5°C/W 123.5°C/W

All Dimensions in Millimeters

Symbol Minimum Maximum

A1.20

A1 0.05 0.15

A2 0.80 1.05

b0.19 0.30

c0.09 0.20

D2.90 3.10

E6.40 Basic

E1 4.30 4.50

e0.65 Basic

L0.45 0.75

α0° 8°

aaa 0.10

ICS844011 Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS CLOCK GENERATOR

Ordering Information

Table 10. Ordering Information

Part/Order Number Marking Package Shipping Packaging Temperature

844011AGLF 011AL Lead-Free, 8-lead TSSOP Tube 0°C to 70°C

844011AGLFT 011AL Lead-Free, 8-lead TSSOP Tape & Reel 0°C to 70°C

ICS844011 Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS CLOCK GENERATOR

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,

including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not

guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the

suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any

license under intellectual property rights of IDT or any third parties.

IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to sig-

nificantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third

party owners.

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