DATA SH EET
Product specification
Supersedes data of 1995 Apr 25 1997 Sep 05
DISCRETE SEMICONDUCTORS
BF998WR
N-channel dual-gate MOS-FET
1997 Sep 05 2
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF998WR
FEATURES
High forward tran sfer admittance
Short channel trans i stor with high forward transfer
admittance to input capacitance ratio
Low noise gain controlled amplifier up to 1 GHz.
APPLICATIONS
VHF and UHF applications with 12 V supply voltage,
such as television tuners and professional
communications equipm ent.
DESCRIPTION
Depletion type field-effect transistor in a plastic
microminiature SOT343R package with s ource and
substrate interconnected. The transistor is protected
against excessive input voltage surges by integrated
back-to-back diodes between gates and source.
PINNING
CAUTION
The device is supplie d in an antistatic package. The
gate-source inpu t must be protected against static
discharge during transport or handling.
PIN SYMBOL DESCRIPTION
1s, bsource
2 d drain
3g
2gate 2
4g
1gate 1
Fig.1 Simplified outline (SOT 343R) and symbol.
Marking code: MB.
MAM198
Top view
21
34
s,b
d
g1
g2
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VDS drain-source voltage 12 V
IDdrain current 30 mA
Ptot total power dissipation 300 mW
Tjoperating junction temperature 150 C
yfsforward transfer admittance 24 mS
Cig1-s input capacitance at gate 1 2.1 pF
Crs reverse transfer capacitance f = 1 MHz 25 fF
F noise figure f = 800 MHz 1dB
1997 Sep 05 3
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF998WR
LIMITING VALUES
In accordance with the Absolute Maximum Rating S ystem (IEC 134).
Note
1. Device mounted on a printed-circuit board.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDS drain-source voltage 12 V
IDdrain current 30 mA
IG1 gate 1 current 10 mA
IG2 gate 2 current 10 mA
Ptot total power dissipation up to Tamb =45C; see Fig.2; note 1 300 mW
Tstg storage temperature 65 +150 C
Tjoperating junction temperature +150 C
Fig.2 Power derating curve.
handbook, halfpage
0 50 100 200
0
MLD154
150
400
200
300
100
Ptot
(mW)
T ( C)
amb o
1997 Sep 05 4
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF998WR
THERMAL CHARACTE RISTI CS
Notes
1. Device mounted on a printed-circuit board.
2. Ts is the temperature at the sold ering point of the source lead.
STATIC CHARACTERISTICS
Tj=25C; unless otherwise specified.
DYNAMIC CHARACTERISTICS
Common source; Tamb =25C; VG2-S =4V; I
D=10mA; V
DS = 8 V; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth j-a thermal resistance from junction to ambient note 1 350 K/W
Rth j-s thermal resistance from junction to soldering point note 2; Ts=90C200K/W
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V(BR)G1-SS gate 1-source breakdown voltage VG2-S =V
DS =0; I
G1-S =10mA 6 20 V
V(BR)G2-SS gate 2-source breakdown voltage VG1-S =V
DS =0; I
G2-S =10mA 6 20 V
V(P)G1-S gate 1-source cut-off voltage VG2-S =4V; V
DS =8V; I
D=20A2.5 V
V(P)G2-S gate 2-source cut-off voltage VG1-S =0; V
DS =8V; I
D=20A2V
IDSS drain-source current VG2-S =4V; V
DS =8V; V
G1-S =0 2 18 mA
IG1-SS gate 1 cut-off current VG2-S =V
DS =0; V
G1-S =5V 50 nA
IG2-SS gate 2 cut-off current VG1-S =V
DS =0; V
G2-S =5V 50 nA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
yfsforward transfer admittance pulsed; Tj=25C2225mS
Cig1-s input capacitance at gate 1 f = 1 MHz 2.1 2.5 pF
Cig2-s input capacitance at gate 2 f = 1 MHz 1.2 pF
Cos drain-source capacitance f = 1 MHz 1.05 pF
Crs reverse transfer capacitance f = 1 MHz 25 fF
F noise figure f = 200 MHz; GS=2mS; B
S=B
Sopt 0.6 dB
f=800MHz; G
S= 3.3 mS; BS=B
Sopt 1dB
1997 Sep 05 5
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF998WR
Fig.3 Transfer characterist ics ; typical values.
VDS =8V.
Tamb =25C.
0
24
16
8
011
MGC471
ID
(mA)
V (V)
G1 S
V = 4 V 3 V
2 V
1 V
0 V
G2 S
Fig.4 Output characteristics; typical values.
VG2-S =4V.
Tamb =25C.
0
24
16
8
0210
MGC470
468
ID
(mA)
V (V)
DS
0.4 V
0.3 V
0.2 V
0.1 V
−0.1 V
0 V
V =
G1 S
−0.2 V
−0.3 V
−0.4 V
−0.5 V
VDS =8V; V
G2 =4V; T
amb =25C.
Fig.5 Drain current as a function of gate 1 voltage;
typical values.
−1600 400
24
0
8
16
MGC472
−1200 −800 −400 0
max typ
min
ID
(mS)
V (mV)
G1
Fig.6 Forward transfer admittance as a function
of drain current; ty pic al v alues.
VDS =8V; T
amb =25C.
020
30
0
6
MGC473
12
18
24
4 8 12 16
yfs
(mS)
I (mA)
D
V = 0 V
G2 − S0.5 V
4 V
3 V
2 V
1 V
1997 Sep 05 6
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF998WR
Fig.7 Forward transfer admittance as a function
of gate 1 voltage; typical values.
VDS =8V; T
amb =25C.
−11
30
0
6
MGC474
12
18
24
0V (V)
G1-S
yfs
(mS)
3 V
2 V
1 V
0 V
V = 4 V
G2 S
Fig.8 Output cap acitance a s a function of
drain-source voltage; typical values.
VG2-S = 4 V; f = 1 MHz; Tamb =25C.
414
1.5
1.0
1.1
MGC475
1.2
1.3
1.4
6 8 10 12VDS(V)
Cos
(pF)
12 mA
10 mA
8 mA
ID =
Fig.9 Gate 1 input capacitance as a function of
gate 1-source voltage; typical values.
VDS =8V; V
G2-S =4V; f=1MHz; T
amb =25C.
−2.4 −1.6 −0.8 0.8
2.4
1.4
2.2
MGC476
0
2.0
1.8
1.6
Cis
(pF)
V (mV)
G1-S
Fig.10 Gate 1 input capacitance as a function of
gate 2-source voltag e; typic al values.
VDS =8V; V
G1-S =0V; f=1MHz; T
amb =25C.
642 −2
2.4
2.3
2.1
2.0
2.2
MGC477
0
Cis
(pF)
V (V)
G2-S
1997 Sep 05 7
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF998WR
Fig.11 Input admittance as a function of the
frequency; typi ca l valu es.
VDS =8V; V
G2-S =4V.
ID=10mA; T
amb =25C.
103
MGC466
102
10
10 2
1
10
10 1
yis
(mS)
f (MHz)
bis
gis
VDS =8V; V
G2-S =4V.
ID=10mA; T
amb =25C.
Fig.12 Reverse transfer admittance and phase as
a function of freq uency; typical values.
103
MGC467
102
10
103
102
10
1
yrs
103
10
10
1
2
(μS)
f (MHz)
rs
yrs
(deg)
rs
ϕ
ϕ
Fig.13 Forward transfer admittance and phase as
a function of freque ncy; typical values.
VDS =8V; V
G2-S =4V.
ID=10mA; T
amb =25C.
103
MGC468
102
10
1
102
10
1
10
10
2
yfs
(mS) yfs
f (MHz)
(deg)
fs
fs
ϕ
ϕ
Fig.14 Output admittance as a function of the
frequency; typical values.
VDS =8V; V
G2-S =4V.
ID=10mA; T
amb =25C.
10
3
MGC469
10
2
10
10
1
10
1
10
2
yos
(mS)
f (MHz)
bos
gos
1997 Sep 05 8
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF998WR
Fig.15 Gain control testcircuit at f = 200 MHz.
VDD =12V; G
S=2mS; G
L= 0.5 mS.
L1 = 45 nH; 4 turns 0.8 mm copper wire, internal diameter 4 mm.
L2 = 160 nH; 3 turns 0.8 mm copper wire, internal diameter 8 mm.
Tapped at approximately half a turn from the cold side, to adjust GL= 0.5 mS. C1 adjusted for GS=2mS.
VAGC
1 nF1 nF
50 Ω
input
50 Ω
input
1 nF
1 nF
L1
L2
20 μH
47 μF
1 nF 1 nF
1 nF
1 nF
47
kΩ
1.8
kΩ
360
Ω
140 kΩ
1 nF
VDD
VDD
15 pF 10 pF
100
kΩ
330
kΩ
Vtun
D1
BB405
C1
5.5 pF
330
kΩ
D2
BB405
input Vtun
output MGC481
1997 Sep 05 9
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF998WR
VDD =12V; G
S= 3.3 mS; GL=1mS.
L1 = L4 = 200 nH; 11 turns 0.5 mm copper wire, without spacing, internal diameter 3 mm.
L2 = 2 cm, silvered 0.8 mm copper wire, 4 mm above ground plane.
L3 = 2 cm, silvered 0.5 mm copper wire, 4 mm above ground plane.
Fig.16 Gain control test circuit at f = 800 MHz.
VAGC
1 nF
1 nF
1 nF
50 Ω
input
50 Ω
input
1 nF
270
kΩ
360
Ω
1.8
kΩ
140
kΩ
100 kΩ
VDD
VDD
1 nF
MGC480
VDD
1 nF
1 nF
L1
L2
C1
2-18 pF C2
0.5-3.5 pF
C3
0.5-3.5 pF
;;
;;
L3
L4
C4
4-40 pF
;;
Fig.17 Automatic gain control characteristics
measured in circui t of Fig.15.
VDD = 12 V; f = 200 MHz; Tamb =25C.
010
0
−50
−40
MGC479
−30
−20
−10
2468
IDSS=
max
typ
min
ΔGtr
(dB)
VAGC(V)
VDD = 12 V; f = 800 MHz; Tamb =25C.
Fig.18 Automatic gain control characteristics
measured in circuit of Fig.16.
010
0
−50
−40
MGC478
−30
−20
−10
2468
IDSS=
max
typ
min
ΔGtr
(dB)
VAGC(V)
1997 Sep 05 10
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF998WR
PACKAGE OUTLINE
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
SOT343R
D
A
A1
Lp
Q
detail X
c
HE
E
vMA
AB
0 1 2 mm
scale
X
21
43
Plastic surface-mounted package; reverse pinning; 4 leads SOT343R
wMB
97-05-21
06-03-16
bp
UNIT A1
max bpcD E
b1HELpQwv
mm 0.1
1.1
0.8 0.4
0.3 0.25
0.10
0.7
0.5 2.2
1.8 1.35
1.15
e
2.2
2.0
1.3
e1
0.2
y
0.10.21.15
DIMENSIONS (mm are the original dimensions)
0.45
0.15 0.23
0.13
e1
A
e
y
b1
1997 Sep 05 11
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF998WR
DATA SHEET STATUS
Notes
1. Please consult the most recently issued documen t b efore initiating or completing a design.
2. The product status of device (s) described in this document may have changed since this document was publishe d
and may differ in case of multiple devices. The latest product status information is available on th e Internet at
URL http://www.nxp.com.
DOCUMENT
STATUS(1) PRODUCT
STATUS(2) DEFINITION
Objective data sheet Development This document contains data from the objective specification for product
development.
Preliminary data sheet Qualification This document contains data from the preliminary specification.
Product data sheet Production This document contains the pr oduct specification.
DEFINITIONS
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provided in a Product data she et shall define the
specification of the product as agre ed between NXP
Semiconductors and its custo m er, unless NXP
Semiconductors and cus to mer have explicitly agreed
otherwise in writing. In no event however, shall an
agreement be valid in which th e NXP Semiconductors
product is deemed to offer functions and qualities beyond
those described in the Product data sheet.
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Applications Applications that are described herein for
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Customers are responsible for the design and operation of
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design and opera ting safeguards to minimi ze the ris ks
associated with their ap plications and produ cts.
1997 Sep 05 12
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF998WR
NXP Semiconductors does not accept any liability related
to any default, damage, cost s or problem which is based
on any weakness or default in the customer’s applications
or products, or the applic ation or use by customer’s th ird
party customer(s). Customer is responsible for doing all
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customer(s). NXP does not accept any liability in this
respect.
Limiting values Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stress ratings only and
(proper) operat ion of the device at these or any other
conditions above those given in the Recommended
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
Constant or repeated exposure to limiting values will
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reliability of the device.
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Semiconductors products are sold subje ct to the general
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Quick refer ence data The Quick reference data is an
extract of th e product data given in the Li miting values and
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All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this do cum en t d oes not form part o f an y q uotation or contra ct, is b elieve d t o b e a ccur ate a nd re liable and may be changed
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Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimer s. No cha ng es were made to the technical content, except for package outline
drawings which were updated to the latest version.
Printed in The Netherlands R77/02/pp13 Date of release: 1997 Sep 05
