© Semiconductor Components Industries, LLC, 2012
May, 2019 − Rev. 6
1Publication Order Number:
NTJD1155L/D
NTJD1155L
MOSFET – Power,
P-Channel, High Side Load
Switch with Level-Shift,
SC-88
8 V, +1.3 A
The NTJD1155L integrates a P and N−Channel MOSFET in a single
package. This device is particularly suited for portable electronic
equipment where low control signals, low battery voltages and high
load currents are needed. The P−Channel device is specifically
designed as a load switch using ON Semiconductor state−of−the−art
trench technology. The N−Channel, with an external resistor (R1),
functions as a level−shift to drive the P−Channel. The N−Channel
MOSFET has internal ESD protection and can be driven by logic
signals as low as 1.5 V. The NTJD1155L operates on supply lines from
1.8 to 8.0 V and can drive loads up to 1.3 A with 8.0 V applied to both
VIN and VON/OFF.
Features
•Extremely Low RDS(on) P−Channel Load Switch MOSFET
•Level Shift MOSFET is ESD Protected
•Low Profile, Small Footprint Package
•VIN Range 1.8 to 8.0 V
•ON/OFF Range 1.5 to 8.0 V
•These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating Symbol Value Unit
Input Voltage (VDSS, P−Ch) VIN 8.0 V
ON/OFF Voltage (VGS, N−Ch) VON/OFF 8.0 V
Continuous Load Current
(Note 1)
Steady
State
TA = 25°CIL±1.3 A
TA = 85°C±0.9
Power Dissipation
(Note 1)
Steady
State
TA = 25°CPD0.40 W
TA = 85°C 0.20
Pulsed Load Current tp = 10 msILM ±3.9 A
Operating Junction and Storage Temperature TJ,
TSTG
−55 to
150
°C
Source Current (Body Diode) IS−0.4 A
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL260 °C
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Junction−to−Ambient – Steady State (Note 1) RqJA 320 °C/W
Junction−to−Foot – Steady State (Note 1) RqJF 220
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1
2,3
5
6
SIMPLIFIED SCHEMATIC
SC−88
(SOT−363)
CASE 419B
STYLE 30
MARKING
DIAGRAM
TB = Device Code
M = Date Code
G= Pb−Free Package
(Note: Microdot may be in either location)
PIN ASSIGNMENT
3
D2
1
S1
S2
4
2
D2
G1
5
D1/G2
6
4
Q2
Q1
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†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
8.0 V 170 mW @ −2.5 V
130 mW @ −4.5 V
RDS(on) TYP
±1.3 A
ID MAXV(BR)DSS
260 mW @ −1.8 V
Device Package Shipping†
ORDERING INFORMATION
NTJD1155LT1G,
NTJD1155LT2G
SC−88
(Pb−Free)
3000/Tape & Reel
1
TB M G
G
1
NTJD1155L
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3
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic Symbol Test Condition Min Typ Max Unit
OFF CHARACTERISTICS
Q2 Drain−to−Source Breakdown Voltage VIN VGS2 = 0 V, ID2 = 250 mA−8.0 V
Forward Leakage Current IFL VGS1 = 0 V,
VDS2 = −8.0 V
TJ = 25°C 1.0 mA
TJ = 125°C 10
Q1 Gate−to−Source Leakage Current IGSS VDS1 = 0 V, VGS1 = ±8.0 V ±100 nA
Q1 Diode Forward On−Voltage VSD IS = −0.4 A, VGS1 = 0 V −0.8 −1.1 V
ON CHARACTERISTICS
ON/OFF Voltage VON/OFF 1.5 8.0 V
Q1 Gate Threshold Voltage VGS1(th) VGS1 = VDS1, ID = 250 mA0.4 1.0 V
Input Voltage VIN VGS1 = VDS1, ID = 250 mA1.8 8.0 V
Q2 Drain−to−Source On Resistance RDS(on) VON/OFF = 1.5 V VIN = 4.5 V
IL = 1.2 A
130 175 mW
VIN = 2.5 V
IL = 1.0 A
170 220
VIN = 1.8 V
IL = 0.7 A
260 320
Load Current ILVDROP ≤ 0.2 V, VIN = 5.0 V,
VON/OFF = 1.5 V
1.0 A
VDROP ≤ 0.3 V, VIN = 2.5 V,
VON/OFF = 1.5 V
1.0
1
2,3
5
6
Figure 1. Load Switch Application
4
Q2
Q1
6
C1
CO
CI
R1
R2
R2
ON/OFF
VIN VOUT
LOAD
GND
Components Description Values
R1 Pullup Resistor Typical 10 kW to 1.0 MW*
R2 Optional Slew−Rate Control Typical 0 to 100 kW*
CO, CIOutput Capacitance Usually < 1.0 mF
C1 Optional In−Rush Current Control Typical ≤ 1000 pF
*Minimum R1 value should be at least 10 x R2 to ensure Q1 turn−on.
NTJD1155L
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4
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
0
0.70
0.25
1.50.5
IL (AMPS)
VDROP (V)
0.15
0.05
0
Figure 2. Vdrop vs. IL @ Vin = 2.5 V Figure 3. Vdrop vs. IL @ Vin = 4.5 V
0.2
0.0
Figure 4. On−Resistance vs. Input Voltage
VIN (VOLTS)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
Figure 5. On−Resistance Variation with
Temperature
−50 0−25 25
1.3
1.1
0.7
50 125100
Figure 6. Normalized On−Resistance Variation
with Temperature
TJ, JUNCTION TEMPERATURE (°C)
TJ = 25°C
0.8
TJ = 125°C
75 150
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
1.0
1.7
1.0 8.0
Figure 7. Switching Variation
R2 @ Vin = 4.5 V, R1 = 20 kW
3.02.5
0.4
0.10
0.20
0.30
IL = 1 A
VON/OFF = 1.5 to 8 V
TJ = 25°C
0.6
1.5
08
R2 (kW)
44
0
TIME (ms)
28
16
241
td(off)
3.0 5.0 7.0
0.06
0.01
TJ, JUNCTION TEMPERATURE (°C)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
0.31
0.16
Vin = 5 V
0.21
Vin = 1.8 V
0.9
56
0.45
0.40
0.35
0.50
0.55
0.60
0.65
2.0
TJ = 125°C
0
0.25
1.50.5
IL (AMPS)
VDROP (V)
0.15
0.05
0
TJ = 25°C
1.0 3.02.5
0.10
0.20
0.30
0.45
0.40
0.35
0.50
2.0
TJ = 125°C
2.0 4.0 6.0 −50 0−25 25 50 12510075 150
0.11
0.26
Vin = 5 V
Vin = 1.8 V
IL = 1 A
VON/OFF = 1.5 V
Ci = 10 mF
Co = 1 mF
37
td(on)
tr
tf
40
24
12
36
20
8
32
4
IL = 1 A
VON/OFF = 1.5 to 8 V
IL = 1 A
VON/OFF = 1.5 to 8 V
0.3
0.1
0.5
0.7
NTJD1155L
www.onsemi.com
5
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
Figure 8. Switching Variation
R2 @ Vin = 4.5 V, R1 = 20 kW
08
R2 (kW)
22
0
TIME (ms)
14
8
241
td(off)
56
IL = 1 A
Von/off = 3 V
Ci = 10 mF
Co = 1 mF
37
td(on)
tr
tf
20
12
6
18
10
4
16
2
r(t), EFFECTIVE TRANSIENT THERMAL RESPONSE
SQUARE WAVE PULSE DURATION TIME t, (s)
0.1
10
0.01
SINGLE PULSE
RqJC(t) = r(t) RqJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RqJC(t)
P(pk)
t1
t2
DUTY CYCLE, D = t1/t2
100 10001010.10.010.001
1
0.2
D = 0.5
0.01
0.02
0.1
0.05
Normalized to RqJA at Steady State ( 1 inch pad)
Figure 9. Switching Variation
R2 @ Vin = 2.5 V, R1 = 20 kW
08
R2 (kW)
0
TIME (ms)
28
16
241
td(off)
56
IL = 1 A
VON/OFF = 1.5 V
Ci = 10 mF
Co = 1 mF
37
td(on)
tr
tf
40
24
12
36
20
8
32
4
Figure 10. Switching Variation
R2 @ Vin = 2.5 V, R1 = 20 kW
08
R2 (kW)
0
TIME (ms)
8
241
td(off)
56
IL = 1 A
Von/off = 3 V
Ci = 10 mF
Co = 1 mF
37
td(on)
tr
tf
12
6
10
4
2
Figure 11. FET Thermal Response
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
DATE 11 DEC 2012
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-
SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDI-
TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOOT.
Cddd M
123
A1
A
c
654
E
b
6X
XXXMG
G
XXX = Specific Device Code
M = Date Code*
G= Pb−Free Package
GENERIC
MARKING DIAGRAM*
1
6
STYLES ON PAGE 2
1
DIM MIN NOM MAX
MILLIMETERS
A−−− −−− 1.10
A1 0.00 −−− 0.10
ddd
b0.15 0.20 0.25
C0.08 0.15 0.22
D1.80 2.00 2.20
−−− −−− 0.043
0.000 −−− 0.004
0.006 0.008 0.010
0.003 0.006 0.009
0.070 0.078 0.086
MIN NOM MAX
INCHES
0.10 0.004
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
E1 1.15 1.25 1.35
e0.65 BSC
L0.26 0.36 0.46
2.00 2.10 2.20
0.045 0.049 0.053
0.026 BSC
0.010 0.014 0.018
0.078 0.082 0.086
(Note: Microdot may be in either location)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.65
0.66
6X
DIMENSIONS: MILLIMETERS
0.30
PITCH
2.50
6X
RECOMMENDED
TOP VIEW
SIDE VIEW END VIEW
bbb H
B
SEATING
PLANE
DETAIL A E
A2 0.70 0.90 1.00 0.027 0.035 0.039
L2 0.15 BSC 0.006 BSC
aaa 0.15 0.006
bbb 0.30 0.012
ccc 0.10 0.004
A-B D
aaa C
2X 3 TIPS
D
E1
D
e
A
2X
aaa H D
2X
D
L
PLANE
DETAIL A
H
GAGE
L2
C
ccc C
A2
6X
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42985B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
SC−88/SC70−6/SOT−363
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
STYLE 1:
PIN 1. EMITTER 2
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
6. COLLECTOR 2
STYLE 3:
CANCELLED
STYLE 2:
CANCELLED
STYLE 4:
PIN 1. CATHODE
2. CATHODE
3. COLLECTOR
4. EMITTER
5. BASE
6. ANODE
STYLE 5:
PIN 1. ANODE
2. ANODE
3. COLLECTOR
4. EMITTER
5. BASE
6. CATHODE
STYLE 6:
PIN 1. ANODE 2
2. N/C
3. CATHODE 1
4. ANODE 1
5. N/C
6. CATHODE 2
STYLE 7:
PIN 1. SOURCE 2
2. DRAIN 2
3. GATE 1
4. SOURCE 1
5. DRAIN 1
6. GATE 2
STYLE 8:
CANCELLED
STYLE 11:
PIN 1. CATHODE 2
2. CATHODE 2
3. ANODE 1
4. CATHODE 1
5. CATHODE 1
6. ANODE 2
STYLE 9:
PIN 1. EMITTER 2
2. EMITTER 1
3. COLLECTOR 1
4. BASE 1
5. BASE 2
6. COLLECTOR 2
STYLE 10:
PIN 1. SOURCE 2
2. SOURCE 1
3. GATE 1
4. DRAIN 1
5. DRAIN 2
6. GATE 2
STYLE 12:
PIN 1. ANODE 2
2. ANODE 2
3. CATHODE 1
4. ANODE 1
5. ANODE 1
6. CATHODE 2
STYLE 13:
PIN 1. ANODE
2. N/C
3. COLLECTOR
4. EMITTER
5. BASE
6. CATHODE
STYLE 14:
PIN 1. VREF
2. GND
3. GND
4. IOUT
5. VEN
6. VCC
STYLE 15:
PIN 1. ANODE 1
2. ANODE 2
3. ANODE 3
4. CATHODE 3
5. CATHODE 2
6. CATHODE 1
STYLE 17:
PIN 1. BASE 1
2. EMITTER 1
3. COLLECTOR 2
4. BASE 2
5. EMITTER 2
6. COLLECTOR 1
STYLE 16:
PIN 1. BASE 1
2. EMITTER 2
3. COLLECTOR 2
4. BASE 2
5. EMITTER 1
6. COLLECTOR 1
STYLE 18:
PIN 1. VIN1
2. VCC
3. VOUT2
4. VIN2
5. GND
6. VOUT1
STYLE 19:
PIN 1. I OUT
2. GND
3. GND
4. V CC
5. V EN
6. V REF
STYLE 20:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTOR
STYLE 22:
PIN 1. D1 (i)
2. GND
3. D2 (i)
4. D2 (c)
5. VBUS
6. D1 (c)
STYLE 21:
PIN 1. ANODE 1
2. N/C
3. ANODE 2
4. CATHODE 2
5. N/C
6. CATHODE 1
STYLE 23:
PIN 1. Vn
2. CH1
3. Vp
4. N/C
5. CH2
6. N/C
STYLE 24:
PIN 1. CATHODE
2. ANODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
STYLE 25:
PIN 1. BASE 1
2. CATHODE
3. COLLECTOR 2
4. BASE 2
5. EMITTER
6. COLLECTOR 1
STYLE 26:
PIN 1. SOURCE 1
2. GATE 1
3. DRAIN 2
4. SOURCE 2
5. GATE 2
6. DRAIN 1
STYLE 27:
PIN 1. BASE 2
2. BASE 1
3. COLLECTOR 1
4. EMITTER 1
5. EMITTER 2
6. COLLECTOR 2
STYLE 28:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
STYLE 29:
PIN 1. ANODE
2. ANODE
3. COLLECTOR
4. EMITTER
5. BASE/ANODE
6. CATHODE
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
DATE 11 DEC 2012
STYLE 30:
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
6. DRAIN 1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42985B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
SC−88/SC70−6/SOT−363
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
www.onsemi.com
1
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