128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect Features AS8C403600 AS8C401800 Description 128K x 36, 256K x 18 memory configurations Supports high system speed: Commercial: - 150MHz 3.8ns clock access time TheAS8C403600/1800 are high- speed SRAMs organized as 128K x 36/256K x 18. The AS8C403600/401800 SRAMs contain write, data, address and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer,as theAS8C403600/1800 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will be pipelined for one cycle before it is available on the next rising clock edge. If burst mode operation is selected ((ADV=LOW), the subsequent three cycles of output data will be available to the user on the next three rising clock edges. The order of these three addresses are defined by the internal burst counter and the LBO input pin. The AS8C403600/1800 SRAMs utilize the latest high- performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP). LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control ( GW), l ( byte write enable (BWE), and byte writes (BWx) 3.3V core power supply Power down controlled by ZZ input 3.3V I/O Optional - Boundary Scan JTAG Interface (IEEE 1149.1 compliant) Packaged in a JEDEC Standard 100-pin plastic thin quad flatpack (TQFP). Pin Description Summary A0-A17 Address In puts Input Synchronous CE Chip Enab le Input Synchronous CS0, CS1 Chip Se lects Input Synchronous OE Output Enable Input Asynchronous GW Global Write Enable Input Synchronous Byte Write Enable Input Synchronous BW1, BW2, BW3, BW4 Individual By te Write Se lects Input Synchronous CLK Clock Input N/A ADV Burst Ad dress Advance Input Synchronous ADSC Address Status (Cache Controller) Input Synchronous ADSP Address S tatus (Processor) Input Synchronous LBO Linear / Interleaved Burst Order Input DC TMS Test Mode Select Input Synchronous TDI Test Data Input Input Synchronous TCK Test Clock Input N/A TDO Test Data Output Output Synchronous Input Asynchronous I/O Synchronous BWE (1) ZZ Sleep Mode I/O0-I/O31, I/OP1-I/OP4 Data Input / Ou tput VDD, V DDQ Core P ower, I/O P ower Supply N/A VSS Ground Supply N/A NOTE: 1. BW3 and BW4 are not applicable for the AS8C401800. September 2010 1 DSC-5279/05 AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial Temperature Range Pin Definitions(1) Symbol Pin Function I/O Active Description A0-A17 Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK and ADSC Lo w o r ADSP Low and CE Lo w. ADSC Address Status (Cache Controller) I LOW Synchronous Address Status from Cache Controller. ADSC i s an active LOW i nput that i s used to l oad the address registers with new addresses. ADSP Address Status (Processor) I LOW Synchronous Address Status from Processor. ADSP i s an ac tive LOW i nput that is us ed to l oad the address registers with new addresses. ADSP is gated by CE. ADV Burst Address Advance I LOW Synchronous Address Advance. ADV i s an a ctive L OW i nput that i s u sed to advance the i nternal burst c ounter, controlling burst access after the initial address is loaded. When the i nput is HIGH the burst c ounter i s n ot i ncremented; th at i s, th ere i s n o a ddress a dvance. BWE Byte Wr ite Enable I LOW Synchronous byte write enable gates the byte write inputs BW1-BW4. If BWE is LOW at the rising edge of CLK then BWx i nputs a re p assed to the next s tage i n the c ircuit. If BWE is HIGH then the byte write inputs are blocked and only GW c an i nitiate a w rite cycle. BW1-BW4 Individual Byte Write E nables I LOW Synchronous byte write enables. BW1 controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc. Any active byte write causes all outputs to be disabled. CE Chip Enable I LOW Synchronous c hip enable. CE is used with CS0 and CS1 to e nable the AS8C403600/1800. CE al so g ates ADSP. CLK Clock I N/A This i s the clock i nput. A ll ti ming references fo r the d evice a re made with respect to th is i nput. CS0 Chip Se lect 0 I HIGH Synchronous active HIGH c hip select. CS 0 is used with CE and CS1 to e nable th e c hip. CS1 Chip Se lect 1 I LOW Synchronous active LOW chip select. CS1 is used with CE and CS0 to e nable the c hip. GW Global Write Enable I LOW Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising edge of CLK. GW supersedes individual byte write enables. I/O0-I/O31 I/OP1-I/OP4 Data Input/Output I/O N/A Synchronous d ata i nput/output (I/O) p ins. B oth the d ata i nput p ath a nd d ata o utput p ath are registered and triggered by the rising edge of CLK. LBO Linear B urst Order I LOW Asynchronous burst order s election input. When LBO is HIGH, the interleaved burst sequence is selected. When LBO is LOW the Linear burst sequence is selected. LBO i s a s tatic i nput and must not change state while the device is operating. OE Output E nable I LOW Asynchronous o utput e nable. When OE is LOW the data output drivers are enabled on the I/O pins if the chip is also se lected. When OE i s HIGH the I/O pins are in a high-impedance state. TMS Test ModeSelect I N/A Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup. TDI Test Data Input I N/A Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an internal pullup. TCK Test Clock I N/A Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK, while test outputs are driven from the falling edge of TCK. This pin has an internal pullup. TDO Test Da taOutput O N/A Serial output of registers placed between TDI and TDO. This output is active depending on the state of the TAP controller. ZZ Sleep Mode I HIGH Asynchronous sleep mode input. ZZ HIGH will g ate the CLK internally and power down the AS8C403600/1800 to its lo west p ower consumption le vel. Data retention is g uaranteed i n Sl eep Mode.This p in has an internal pull down. VDD Power S upply N/A N/A 3.3V c ore p ower s upply. VDDQ Power Supply N/A N/A 3.3V I/O Supply. VSS Ground N/A N/A Ground. NC No Connect N/A N/A NC pins are not e lectrically c onnected to th e d evice. NOTE: 1. All synchronous inputs must meet specified setup and hold times with respect to CLK. 6.42 2 5279 tbl 02 AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial Temperature Range Functional Block Diagram LBO ADV CLK 2 Binary Counter ADSC Burst Logic Q0 CLR ADSP Q1 CLK EN ADDRESS REGISTER A0 - A16/17 GW BWE INTERNAL ADDRESS Burst Sequence CEN 17/18 A0* A1* 128K x 36/ 256K x 18BIT MEMORY ARRAY 2 A0,A1 A2-A17 36/18 17/18 Byte 1 Write Register 36/18 Byte 1 Write Driver BW1 9 Byte 2 Write Register Byte 2 Write Driver BW2 9 Byte 3 Write Register Byte 3 Write Driver BW3 9 Byte 4 Write Register Byte 4 Write Driver BW4 9 OUTPUT REGISTER CE CS0 CS1 D Q Enable Register DATA INPUT REGISTER CLK EN ZZ Powerdown D Q Enable Delay Register OE OE I/O0 -- I/O31 I/OP1 -- I/OP4 OUTPUT BUFFER 36/18 5279 drw 01 TMS TDI TCK TRST (Optional) JTAG (SA Version) TDO 6.42 3 AS8 , AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Absolute Maximum Ratings(1) Symbol Rating Recommended Operating Temperature and Supply Voltage Commercial & Industrial Unit Grade Temperature(1) VSS VDD V DDQ Commercial 0C to + 70C 0V 3.3V5% 3.3V5% Industrial -40C to +85C 0V 3.3V5% 3.3V5% VTERM(2) Terminal Voltage with Respect to G ND -0.5 to +4.6 V VTERM(3,6) Terminal Voltage with Respect to G ND -0.5 to VDD V VTERM(4,6) Terminal Voltage with Respect to G ND -0.5 to V DD +0.5 V VTERM(5,6) Terminal Voltage with Respect to G ND -0.5 to V DDQ +0.5 V Commercial Operating Temperature -0 to + 70 o C Industrial Operating Temperature -40 to + 85 o C Temperature Under Bias -55 to + 125 o C TA (7) TBIAS TSTG Storage Temperature -55 to + 125 o Power Dissipation 2.0 W IOUT DC Output Current 50 mA Recommended DC Operating Conditions Symbol CIN Input Capacitance CI/O I/O Cap acitance Unit VIN = 3dV 5 pF VOUT = 3dV 7 Typ. Max. Unit Core Supply Voltage 3.135 3.3 3.465 V VDDQ I/O Supp ly Voltage 3.135 3.3 3.465 V VSS Supply Voltage 0 0 0 V VIH Input High Voltage - Inputs 2.0 ____ VDD +0.3 VIH Input High Voltage - I/O 2.0 ____ Input Low Voltage -0.3 (2) ____ V (1) VDDQ +0.3 0.8 V V NOTES: 1. VIH (max) = V DDQ + 1.0V for pulse width less than tCYC/2, once per cycle. 2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle. (TA = +25C, f = 1.0MHz) Max. Min. 5279 tbl 06 100 Pin TQFP Ca pacitance Conditions Parameter VDD VIL 5279 tbl 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDD terminals only. 3. VDDQ terminals only. 4. Input terminals only. 5. I/O terminals only. 6. This is a steady-state DC parameter that applies after the power supplies have ramped up. Power supply sequencing is not necessary; however, the voltage on any input or I/O pin cannot exceed VDDQ during power supply ramp up. 7. TA is the "instant on" case temperature. Parameter(1) 5279 tbl 04 NOTES: 1. TA is the "instant on" case temperature. C PT Symbol Commercial Temperature Range pF 5279 t bl 07 NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. 6.42 4 IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperat ure Ranges A6 A7 CE CS0 BW4 BW3 BW2 BW1 CS1 VDD VSS CLK GW BWE OE ADSC ADSP ADV A8 A9 Pin Configuration - 128K x 36 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 I/OP3 I/O16 I/O17 VDDQ VSS I/O18 I/O19 I/O20 I/O21 VSS VDDQ I/O22 I/O23 VDD / NC(1) VDD NC VSS I/O24 I/O25 VDDQ VSS I/O26 I/O27 I/O28 I/O29 VSS VDDQ I/O30 I/O31 I/OP4 1 80 2 79 3 4 78 77 5 76 6 75 7 74 8 73 9 72 71 10 11 70 12 69 13 68 14 67 15 66 16 65 64 17 18 19 63 62 20 61 21 60 22 59 23 24 58 57 25 56 26 55 27 54 28 53 29 52 30 51 I/OP2 I/O15 I/O14 VDDQ VSS I/O13 I/O12 I/O11 I/O10 VSS VDDQ I/O9 I/O8 VSS NC VDD ZZ(2) I/O7 I/O6 VDDQ VSS I/O5 I/O4 I/O3 I/O2 VSS VDDQ I/O1 I/O0 I/OP1 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC VSS VDD NC NC A10 A11 A12 A13 A14 A15 A16 LBO A5 A4 A3 A2 A1 A0 5279 drw 02 TQFP Top View NOTES: 1. Pin 14 can either be directly connected to V DD, or connected to an input voltage 2. Pin 64 can be left unconnected and the device will always remain in active mode. VIH, or left unconnected. 6.42 5 , IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperat ure Ranges A6 A7 CE CS0 NC NC BW2 BW1 CS1 VDD VSS CLK GW BWE OE ADSC ADSP ADV A8 A9 Pin Configuration - 256K x 18 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC NC NC 1 80 2 79 3 VDDQ VSS NC NC I/O8 I/O9 VSS VDDQ I/O10 I/O11 VDD / NC(1) VDD NC VSS I/O12 I/O13 VDDQ VSS I/O14 I/O15 I/OP2 NC VSS VDDQ NC NC NC 4 78 77 5 76 6 75 7 74 8 73 9 72 71 10 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 28 54 53 29 52 30 51 A10 NC NC VDDQ VSS NC I/OP1 I/O7 I/O6 VSS VDDQ I/O5 I/O4 VSS NC VDD ZZ(2) I/O3 I/O2 VDDQ VSS I/O1 I/O0 NC NC VSS VDDQ NC NC NC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 LBO A5 A4 A3 A2 A1 A0 NC NC VSS VDD NC NC A11 A12 A13 A14 A15 A16 A17 5279 drw 03 TQFP Top View NOTES: 1. Pin 14 can either be directly connected to V DD, or connected to an input voltage 2. Pin 64 can be left unconnected and the device will always remain in active mode. 6.42 6 VIH, or left unconnected. , AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial Temperature Range DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 3.3V 5%) Symbol Parameter Test Conditions Min. Max. Unit 5 A |ILI| Input Le akage Current VDD = Max., V IN = 0V to V DD ___ |ILZZ| ZZ, LBO and J TAG Input Le akage Current(1) VDD = Max., V IN = 0V to V DD ___ 30 A |ILO| Output Leakage Current VOUT = 0V to V DDQ , Device Deselected ___ 5 A VOL Output Low Voltage IOL = +8mA, V DD = Min. ___ 0.4 V VOH Output High Voltage IOH = -8mA, VDD = Min. 2.4 ___ V NOTE: 1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to V 5279 tbl 08 DD and the ZZ pin will be internally pulled to V SS if they are not actively driven in the application. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) 150MHz Symbol Parameter Test Conditions 133MHz Com'l Ind Com'l Ind Unit IDD Operating Power Supply Current Device Selected, Outputs Open, V DD = M ax., VDDQ = M ax., VIN > VIH or < VIL, f = f MAX(2) 295 305 250 260 mA ISB1 CMOS Standby Po wer Supply Current Device Deselected, Outputs Open, V DD = M ax., VDDQ = M ax., VIN > VHD or < VLD, f = 0 (2,3) 30 35 30 35 mA ISB2 Clock Run ning Power Supply Current Device Deselected, Outputs Open, V DD = M ax., VDDQ = M ax., VIN > VHD or < VLD, f = f MAX(2,3) 105 115 100 110 mA IZZ Full Sleep Mode Supply Current ZZ > VHD, VDD = M ax. 30 35 30 35 mA 5279 t bl 0 9 NOTES: 1. All values are maximum guaranteed values. 2. At f = f MAX, inputs are cycling at the maximum frequency of read cycles of 1/ Tcyc while ADSC = LOW; f= 0 means no input lines are changing. 3. For I/Os V HD = V DDQ - 0.2V, V LD = 0.2V. For other inputs V HD = V DD - 0.2V, V LD = 0.2V. AC Test Conditions AC Test Load (VDDQ = 3.3V) Input P ulse Levels 50 0 to 3V I/O Input R ise/Fall Times 2ns Input Timing Reference L evels 1.5V Output Timing Reference Le vels 1.5V 6 See Figure 1 5 AC Test Load VDDQ/2 Z0 = 50 5279 drw 06 , Figure 1. AC Test Load 5279 tbl 10 4 tCD 3 (Typical, ns) 2 1 20 30 50 80 100 Capacitance (pF) Figure 2. Lumped Capacitive Load, Typical Derating 6.42 7 200 5279 drw 07 , AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial Temperature Range Synchronous Truth Table(1,3) Operation Address Used CE CS0 CS1 ADSP ADSC ADV GW BWE BWx OE (2) CLK I/O Deselected Cycle, ower Pown D None H X X X L X X X X X - HI-Z Deselected Cycle, ower Pown D None L X H L X X X X X X - HI-Z Deselected Cycle, ower Pown D None L L X L X X X X X X - HI-Z Deselected Cycle, ower Pown D None L X H X L X X X X X Deselected Cycle, ower Pown D None L L X X L X X X X X - HI-Z Read Cy cle, B egin B urst External L H L L X X X X X L - DOUT Read Cy cle, B egin B urst External L H L L X X X X X H - HI-Z Read Cy cle, B egin B urst External L H L H L X H H X L - DOUT Read Cy cle, B egin B urst External L H L H L X H L H L - DOUT Read Cy cle, B egin B urst External L H L H L X H L H H - HI-Z Write Cycle, Begin Burst External L H L H L X H L L X - DIN Write Cycle, Begin Burst External L H L H L X L X X X - DIN Read Cycle, Continue B urst Next X X X H H L H H X L - DOUT Read Cycle, Continue B urst Next X X X H H L H H X H - HI-Z Read Cycle, Continue B urst Next X X X H H L H X H L - DOUT Read Cycle, Continue B urst Next X X X H H L H X H H - HI-Z Read Cycle, Continue B urst Next H X X X H L H H X L - DOUT Read Cycle, Continue B urst Next H X X X H L H H X H - HI-Z Read Cycle, Continue B urst Next H X X X H L H X H L - DOUT Read Cycle, Continue B urst Next H X X X H L H X H H - HI-Z Write Cycle, Continue B urst Next X X X H H L H L L X - DIN Write Cycle, Continue B urst Next X X X H H L L X X X - DIN Write Cycle, Continue B urst Next H X X X H L H L L X - DIN Write Cycle, Continue B urst Next H X X X H L L X X X - DIN Read Cycle, S uspend B urst Current X X X H H H H H X L - DOUT Read Cycle, S uspend B urst Current X X X H H H H H X H - HI-Z Read Cycle, S uspend B urst Current X X X H H H H X H L - DOUT Read Cycle, S uspend B urst Current X X X H H H H X H H - HI-Z Read Cycle, S uspend B urst Current H X X X H H H H X L - DOUT Read Cycle, S uspend B urst Current H X X X H H H H X H - HI-Z Read Cycle, S uspend B urst Current H X X X H H H X H L - DOUT Read Cycle, S uspend B urst Current H X X X H H H X H H - HI-Z Write Cycle, Suspend Burst Current X X X H H H H L L X - DIN Write ycle, Cuspend S urst B Current X X X H H H L X X X - DIN Write Cycle, Suspend Burst Current H X X X H H H L L X - DIN Write Cycle, Suspend Burst Current H X X X H H L X X X - DIN HI-Z - 5279 tbl 11 NOTES: 1. L = V IL, H = V IH, X = Don't Care. 2. OE is an asynchronous input. 3. ZZ = low for this table. 6.42 8 AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial Temperature Range Synchronous Write Function Truth Table(1, 2) Operation GW BWE BW1 BW2 BW3 BW4 Read H H X X X X Read H L H H H H Write all B ytes L X X X X X Write all B ytes H L L L L L Write B yte 1 (3) H L L H H H Write B yte 2 (3) H L H L H H Write B yte 3 (3) H L H H L H Write B yte 4 (3) H L H H H L 5279 tbl 12 NOTES: 1. L = V IL, H = V IH, X = Don't Care. 2. BW3 and BW4 are not applicable for the AS8C401800. 3. Multiple bytes may be selected during the same cycle. Asynchronous Truth Table(1) Operation(2) OE ZZ I/O Status Power Read L L Data O ut Active Read H L High-Z Active Write X L High-Z - Data In Active Deselected X L High-Z Standby Sleep Mode X H High-Z Sleep 5279 tbl 13 NOTES: 1. L = V IL, H = V IH, X = Don't Care. 2. Synchronous function pins must be biased appropriately to satisfy operation requirements. Interleaved Burst SequenceTable (LBO=VDD) Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Address 0 0 0 1 1 0 1 1 Second Address 0 1 0 0 1 1 1 0 Third Address 1 0 1 1 0 0 0 1 Fourth Address(1) 1 1 1 0 0 1 0 0 5279 tbl 14 NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state. Linear Burst Sequence Table (LBO=VSS) Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Address 0 0 0 1 1 0 1 1 Second Address 0 1 1 0 1 1 0 0 Third Address 1 0 1 1 0 0 0 1 Fourth Address(1) 1 1 0 0 0 1 1 0 NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state. 6.42 9 5279 tbl 15 AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial Temperature Range AC Electrical Characteristics (VDD = 3.3V 5%, Commercial and Industrial Temperature Ranges) 150MHz Symbol Parameter 133MHz Min. Max. Min. Max. Unit tCYC Clock Cycle Time 6.7 ____ 7.5 ____ ns tCH(1) Clock High P ulse Width 2.6 ____ 3 ____ ns tCL(1) Clock Low Pulse Width 2.6 ____ 3 ____ ns Output Parameters tCD Clo ck High to Valid Data ____ 3.8 ____ 4.2 ns tCDC Clock High to Data Cha nge 1.5 ____ 1.5 ____ ns tCLZ(2) Clock High to Output Active 0 ____ 0 ____ ns tCHZ(2) Clock High to Data Hi gh-Z 1.5 3.8 1.5 4.2 ns tOE Output Enable Access Time ____ 3.8 ____ 4.2 ns tOLZ(2) Output Enable Lo w to Output Active 0 ____ 0 ____ ns tOHZ(2) Output Enable High to Output High-Z ____ 3.8 ____ 4.2 ns tSA Address Setup Time 1.5 ____ 1.5 ____ ns tSS Address Status Setup Time 1.5 ____ 1.5 ____ ns tSD Data In S etup Time 1.5 ____ 1.5 ____ ns tSW Write Setup Time 1.5 ____ 1.5 ____ ns tSAV Address Advance Setup Time 1.5 ____ 1.5 ____ ns tSC Chip Enable/Select S etup Time 1.5 ____ 1.5 ____ ns tHA Address Hold Time 0.5 ____ 0.5 ____ ns tHS Address Status Hold Time 0.5 ____ 0.5 ____ ns tHD Data In Ho ld Time 0.5 ____ 0.5 ____ ns tHW Write Hold Time 0.5 ____ 0.5 ____ ns tHAV Address Advance Hold Time 0.5 ____ 0.5 ____ ns tHC Chip Enable/Select Hold Time 0.5 ____ 0.5 ____ ns Set Up Times Hold Times Sleep M ode and Configuration P arameters tZZPW ZZ Pulse Width 100 ____ 100 ____ ns tZZR(3) ZZ Recovery Time 100 ____ 100 ____ ns tCFG (4) Configuration Set-up Time 27 ____ 30 ____ ns NOTES: 1. Measured as HIGH above VIH and LOW below VIL. 2. Transition is measured 200mV from steady-state. 3. Device must be deselected when powered-up from sleep mode. 4. tCFG is the minimum time required to configure the device based on the 5279 tbl 16 LBO input. LBO is a static input and must not change during normal operation. 6.42 10 6.42 11 Output Disabled tSC tSA tSS tHS Ax Pipelined Read tOLZ tOE tHC tHA O1(Ax) Ay (1) tCH tCLZ tOHZ tCD tSW tCL tSAV O1(Ay) tCDC tHAV O2(Ay) tHW Burst Pipelined Read O3(Ay) ADV HIGH suspends burst O4(Ay) (Burst wraps around to its initial state) O1(Ay) tCHZ O2(Ay) 5279 drw 08 , NOTES: 1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the externaless addr Ay; O2 (Ay) represents the next output data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. 2. ZZ input is LOW and LBO is Don't Care for this cycle. 3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS 0 is HIGH. DATAOUT OE ADV (Note 3) CE, CS1 GW, BWE, BWx ADDRESS ADSC ADSP CLK tCYC IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperat ure Ranges Timing Waveform of Pipelined Read Cycle(1,2) 6.42 12 tSA tHA tSS tHS tCLZ tCD Single Read Ax (2) tOE O1(Ax) tOHZ tSW Ay tCH Pipelined Write I1(Ay) tSD tHD tCL tHW Az tOLZ tCD O2(Az) Pipelined Burst Read O1(Az) tCDC 5279 drw 09 O3(Az) , NOTES: 1. Device is selected through entire cycle; CE and CS1 are LOW, CS 0 is HIGH. 2. ZZ input is LOW and LBO is Don't Care for this cycle. 3. O1 (Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the externalss addre Ay; O1 (Az) represents the first output from the external address Az; O2 (Az) represents the next output data in the burst sequence of the base address Az, etc. where A0 and A1 are advancing for the four word burst i n the sequence defined by the state of the LBO input. DATAOUT DATAIN OE ADV GW ADDRESS ADSP CLK tCYC IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperat ure Ranges Timing Waveform of Combined Pipelined Read and Write Cycles(1,2,3) 6.42 13 O4(Aw) Ax Burst Read tHC O3(Aw) tSC tSA tHA tSS tHS Ay tCL Single Write tOHZ I1(Ax) I1(Ay) I2(Ay) Burst Write I2(Ay) (ADV HIGH suspends burst) tSAV GW is ignored when ADSP initiates a cycle and is sampled on the next clock rising edge tCH I3(Ay) tHAV I4(Ay) tSD I1(Az) tHW tSW Az I3(Az) 5279 drw 10 Burst Write I2(Az) tHD , NOTES: 1. ZZ input is LOW, BWE is HIGH and LBO is Don't Care for this cycle. 2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input om the fr external address Ax. I1 (Ay) represents the first input from the external address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advan cing for the four word burst in the sequence defined by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst. 3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS 0 is HIGH. DATAOUT DATAIN OE ADV (Note 3) CE, CS1 GW ADDRESS ADSC ADSP CLK tCYC IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperat ure Ranges Timing Waveform of Write Cycle No. 1 - GW Controlled(1,2,3) 6.42 14 tHC Burst Read O3(Aw) tSC tSA tHA tSS tHS O4(Aw) Ax Ay tCL Single Write tOHZ I1(Ax) I1(Ay) Burst Write I2(Ay) (ADV suspends burst) BWx is ignored when ADSP initiates a cycle and is sampled on next clock rising edge BWE is ignored when ADSP initiates a cycle and is sampled on next clock rising edge tCH I2(Ay) I3(Ay) I4(Ay) tSD Extended Burst Write I1(Az) tSAV tHW tSW tHW tSW Az I2(Az) tHD 5279 drw 11 I3(Az) , NOTES: 1. ZZ input is LOW, GW is HIGH and LBO is Don't Care for this cycle. 2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input om the fr external address Ax. I1 (Ay) represents the first input from the external address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advan cing for the four word burst in the sequence defined by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst. 3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS 0 is HIGH. DATAOUT DATAIN OE ADV (Note 3) CE, CS1 BWx BWE ADDRESS ADSC ADSP CLK tCYC IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperat ure Ranges Timing Waveform of Write Cycle No. 2 - Byte Controlled(1,2,3) 6.42 15 tSS tSC tSA tHS Ax Single Read tOLZ tOE tHC tHA O1(Ax) tCH tCL tZZPW Snooze Mode tZZR NOTES: 1. Device must power up in deselected Mode 2. LBO is Don't Care for this cycle. 3. It is not necessary to retain the state of the input registers throughout the Power-down cycle. CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS 4. CS0 timing transitions are identical but inverted to the ZZ DATAOUT OE ADV (Note 4) CE, CS1 GW ADDRESS ADSC ADSP CLK tCYC 0 is HIGH. Az 5279 drw 12 IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperat ure Ranges Timing Waveform of Sleep (ZZ) and Power-Down Modes(1,2,3) , AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial Temperature Range Non-Burst Read Cycle Timing Waveform CLK ADSP ADSC ADDRESS Av Aw Ax Ay Az GW, BWE, BWx CE, CS1 CS0 OE (Av) DATAOUT (Aw) (Ax) (Ay) NOTES: 1. ZZ input is LOW,ADV is HIGH andLBO is Don't Care for this cycle. 2. (Ax) represents the data for address Ax, etc. 3. For read cycles,ADSP and ADSC function identically and are therefore interchangable. , 5279 drw 14 Non-Burst Write Cy cle Timing Wa veform CLK ADSP ADSC ADDRESS Av Aw Ax Ay Az (Ax) (Ay) (Az) GW CE, CS1 CS0 DATAIN (Av) (Aw) NOTES: 1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle. 2. (Ax) represents the data for address Ax, etc. 3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW. 4. For write cycles, ADSP and ADSC have different limitations. 6.42 16 , 5279 drw 15 AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial Temperature Range ORDERING INFORMATION Alliance Organization VCC Range AS8C403600-QC150N 128K x 36 3.1 - 3.4V 100 pin TQFP Commercial: 0 C - 70C 150 AS8C401800-QC150N 256K x 18 3.1 - 3.4V 100 pin TQFP Commercial: 0 C - 70C 150 Package Operating Temp Speed Mhz PART NUMBERING SYSTEM AS8C Sync. SRAM prefix Device 40 = M Conf. 18= x18 36 = x36 Mode Package 01= ZBT 00 = Pipelined 25 = Flow- Thru Q = 100 Pin TQFP Operating Temp 0 ~ 70C N Speed 150MHz N= Leadfree ORDERING INFORMATION Alliance VCC Range Organization AS6C8016A -55ZIN 512K x 16 AS6C8016A -55BIN Package 2.7 - 5.5V 512K x 16 2.7 - 5.5V Speed ns Operating Temp 44pin TSOP II Industrial ~ -40 C - 85 C 55 48ball FBGA Industrial ~ -40 C - 85 C 55 PART NUMBERING SYSTEM AS6C 8016 -55 Device Number low power SRAM prefix (R) Alliance Memory, Inc. 551 Taylor way, Suite#1, San Carlos, CA 94070 Tel: 650-610-6800 Fax: 650-620-9211 Copyright (c) Alliance Memory All Rights Reserved Part Number: AS8C403600/401800 Document Version: v. 1.0 www.alliancememory.com (c) Copyright 2003 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. 176.42 80 = 8M 16 = x16 Access Time X X Package Option Temperature Range Z - 44pin TSOP I = Industrial B = 48ball TFBGA (-40 to + 85 C) N N = Lead Free RoHS compliant part