September 2010
DSC-5279/05
1
Features
◆◆
◆◆
◆128K x 36, 256K x 18 memory configurations
◆◆
◆◆
◆Supports high system speed:
Commercial:
– 150MHz 3.8ns clock access time
◆◆
◆◆
◆LBO input selects interleaved or linear burst mode
◆◆
◆◆
◆Self-timed write cycle with global write control ( l (GW), byte
write enable (BWE), and byte writes (BWx)
◆◆
◆◆
◆3.3V core power supply
◆◆
◆◆
◆Power down controlled by ZZ input
◆◆
◆◆
◆3.3V I/O
◆◆
◆◆
◆Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
◆◆
◆◆
◆Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP).
Description
TheAS8C403600/1800 are high- speed SRAMs organized as
128K x 36/256K x 18. The AS8C403600/401800 SRAMs contain write,
data, address and control registers. Internal logic allows the SRAM to
generate a self-timed write based upon a decision which can be left until
the end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer,as the AS8C403600/1800 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected ((ADV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the LBO input pin.
The AS8C403600/1800 SRAMs utilize the latest high- performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP).
Pin Description Summary
NOTE:
1. BW3 and BW4 are not applicable for the AS8C401800.
A
0
-A
17
Addre ss In puts Input Synchronous
CE Chip Enab le Input Synchronous
CS
0
, CS
1
Chip Se lects Input Synchronous
OE Output Enable Input Asynchronous
GW Global Write Enable Input Synchronous
BWE Byte Write Enable Input Synchronous
BW
1
, BW
2
, BW
3
, BW
4
(1)
Individual By te Write Se lects Input Synchronous
CLK Clock Input N/A
ADV Burst Ad dress Advance Input Synchronous
ADSC Address Status (Cache Controller) Input Synchronous
ADSP Address S tatus (Processor) Input Synchronous
LBO Linear / Interleaved Burst Order Input DC
TMS Test Mode Select Input Synchronous
TDI Test D ata Input Input Synchronous
TCK Test Clock Input N/A
TDO Test D ata Output Output Synchronous
ZZ Sleep Mode Input Asynchronous
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
Data Input / Ou tput I/O Synchronous
V
DD
, V
DDQ
Core P ower, I/O Power Supply N/A
V
SS
Ground Supply N/A
128K x 36, 256K x 18
3.3V Synchronous SRAMs
3.3V I/O, Pipelined Outputs
Burst Counter, Single Cycle Deselect
AS8C403600
AS8C401800
6.42
2
AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial Temperature Range
Pin Definitions
(1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
Symbol Pin Function I/O Active Description
A
0
-A
17
Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge
of C LK and ADSC Lo w o r ADSP Low and CE Lo w.
ADSC Address Status
(Cache Controller) ILOW
Synchronous Address Status from Cache Controller. ADSC i s a n active LOW i nput th at i s used to l o ad
the address registers with new addresses.
ADSP Address Status
(Processor) ILOW
Synchronous Address Status from Processor. ADSP i s a n ac tive LO W i np ut t hat is us ed to l oad t he
address registers with new addresses. ADSP is gated by CE.
ADV Burst Address
Advance ILOW
Synchronous Address Advance. ADV i s a n a ctive L OW i nput th at i s u se d to a d vance the i nternal
burst counter, controlling burst access after the initial address is lo aded. When the input is HIGH the
burst c ounter i s n ot i ncremented ; th at i s, th ere i s n o a ddress a dvance.
BWE Byte Wr ite Enable I LOW
Synchronous byte write enable gates the byte write inputs BW
1
-BW
4
. If BWE is LOW at the rising
edge of CLK then BWx i nputs a re p assed to the n ext s tage i n the c ircuit. If BWE is HIGH then the
byte write inputs are blocked and only GW c an i nitiate a w rite cycle.
BW
1
-BW
4
Individual Byte
Write E nables ILOW
Synchronous byte write enables. BW
1
controls I/O
0-7
, I/O
P1
, BW
2
controls I/O
8-15
, I/O
P2
, etc. Any
active byte write causes all outputs to be disabled.
CE Chip Enable I LOW Synchronous c hip enable. CE is used with CS
0
and CS
1
to e nable the AS8C403600/1800. CE also g ates
ADSP.
CLK Clock I N/A This i s the clock i nput. A ll ti ming r eferences fo r th e d e vice a re made with r espe ct t o th is i nput.
CS
0
Chip Se lect 0 I HIGH Synchronous active HIGH c hip select. CS
0
is used with CE and CS
1
to e nable th e c hip.
CS
1
Chip Se lect 1 I LOW Synchronous active LOW chip select. CS
1
is used with CE and CS
0
to e nable th e c hip.
GW Global Write
Enable ILOW
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising
edge of CLK. GW supersedes individual byte write enables.
I/O
0
-I/O
31
I/O
P1
-I/O
P4
Data In p ut/Output I/O N/A Synchronous d ata i np ut/output ( I/O) p ins. B oth th e d ata i nput p ath a nd d ata o utput p ath are registered
and triggered by the rising edge of CLK.
LBO Linear B urst Order I LOW
Asynchronous burst order s election input. When LBO is HIGH, the interleaved burst sequence is
selected. When LBO is LOW the Linear burst sequence is selected. LBO i s a s tatic i nput and m ust
not change state while the device is operating.
OE Output E nable I LOW Asynchronous o utput e nable. When OE is LOW the data output drivers are enabled on the I/O pins if
the chip is also se lected. When OE is HIGH the I/O pins are in a high-impedance state.
TMS Test M o deSelec t I N/A Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal
pullup.
TDI Test D ata In put I N/A Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has
an internal pullup.
TCK Te s t C lo c k I N/A Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of
TCK, while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.
TDO Test Da taOutput O N/A Serial output of registers placed between TDI and TDO. This output is active depending on the state
of the TAP controller.
ZZ Sleep Mode I HIGH
Asynchronous sleep mode input. ZZ HIGH will g ate the CLK internally and power down the
AS8C403600/1800 to its lo west p ower consumption le vel. Data retention is g uaranteed in Sl eep
Mode.This p in has an internal pull down.
V
DD
Power S upply N/A N/A 3.3V c ore p o we r s upp ly.
V
DDQ
Power Supply N/A N/A 3.3V I/O Supply.
V
SS
Ground N/A N/A Ground.
NC No C onne ct N/A N/A NC pins a re n ot e lec trically c onnec ted to th e d evice.
5279 tbl 02
6.42AS8
AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial Temperature Range
3
Functional Block Diagram
A
0-
A
16/17
ADDRESS
REGISTER
CLR
A1*
A0*
17/18
2
17/18
A
2
–A
17
128K x 36/
256K x 18-
BIT
MEMORY
ARRAY
INTERNAL
ADDRESS
A
0
,A
1
BW
4
BW
3
BW
2
BW
1
Byte 1
Write Register
36/18 36/18
ADSP
ADV
CLK
ADSC
CS
0
CS
1
Byte 1
Write Driver
Byte 2
Write Driver
Byte 3
Write Driver
Byte 4
Write Driver
Byte 2
Write Register
Byte 3
Write Register
Byte 4
Write Register
9
9
9
9
GW
CE
BWE
LBO
I/O
0
— I/O
31
I/O
P1
—I/O
P4
OE
DATA INPUT
REGISTER
36/18
OUTPUT
BUFFER
OUTPUT
REGISTER
DQ
DQ
Enable
Register
Enable
Delay
Register
OE
Burst
Sequence
CEN
CLK EN
CLK EN
Q1
Q0
2
Burst
Logic
Binary
Counter
5279 drw 01
ZZ
Powerdown
,
JTAG
(SA Version)
TMS
TDI
TCK
TRST
(Optional)
TDO
6.42
4
AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial Temperature Range
100 Pin T QFP Ca pacitance
(TA = +25°C, f = 1.0 MHz)
Recommended Operating
Temperature and Suppl y Voltage
Absolute Maximum Ratings
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed VDDQ during power supply ramp up.
7. TA is the "instant on" case temperature.
Recommended DC Operating
Conditions
NOTES:
1. VIH (max) = V DDQ + 1.0V for pulse width less than tCYC/2, once per cycle.
2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
Symbol Rating
Commercial &
Industrial Unit
V
TERM
(2)
Terminal Voltage with
Respect to G ND
-0.5 to +4.6 V
V
TERM
(3,6)
Terminal Voltage with
Respect to G ND
-0.5 to V
DD
V
V
TERM
(4,6)
Terminal Voltage with
Respect to G ND
-0.5 to V
DD
+0.5 V
V
TERM
(5,6)
Terminal Voltage with
Respect to G ND
-0.5 to V
DDQ
+0.5 V
T
A
(7)
Commercial
Operating Temperature
-0 to + 70
o
C
Industrial
Operating Temperature
-40 to + 85
o
C
T
BIAS
Temperature
Under Bias
-55 to + 125
o
C
T
STG
Storage
Temperature
-55 to + 125
o
C
P
T
Power Dissipation 2.0 W
I
OUT
DC Output Current 50 mA
5279 tbl 03
Grade Temperature
(1)
V
SS
V
DD
V
DDQ
Commercial 0°C to + 70°C 0V 3.3V±5% 3.3V±5%
Industrial -40°C to +85°C 0V 3.3V±5% 3.3V±5%
5 2 79 t bl 04
Symbol Parameter Min. Typ. Max. Unit
V
DD
Core Supply Voltage 3.135 3.3 3.465 V
V
DDQ
I/O Supp ly Voltage 3.135 3.3 3.465 V
V
SS
Supply Voltage 0 0 0 V
V
IH
Input High Voltage - Inputs 2.0
___ _
V
DD
+0.3 V
V
IH
Input High Voltage - I/O 2.0
___ _
V
DDQ
+0.3
(1 )
V
V
IL
Input Low Voltage -0.3
(2)
___ _
0.8 V
5279 tbl 06
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 5 pF
C
I/O
I/O Cap acitance V
OUT
= 3dV 7 pF
5279 t bl 07
NOTES:
1. TA is the "instant on" case temperature.
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.42
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperat ure Ranges
5
Pin Configuration – 128K x 36
TQFP
Top View
NOTES:
1. Pin 14 can either be directly connected to V DD, or connected to an input voltage ≥ VIH, or left unconnected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 8189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
CS
0
BW
4
BW
3
BW
2
BW
1
CS
1
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
NC
NC
LBO
A
14
A
13
A
12
A
11
A
10
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
I/O
31
I/O
30
V
DDQ
V
SS
I/O
29
I/O
28
I/O
27
I/O
26
V
SS
V
DDQ
I/O
25
I/O
24
V
SS
V
DD
I/O
23
I/O
22
V
DDQ
V
SS
I/O
21
I/O
20
I/O
19
I/O
18
V
SS
V
DDQ
I/O
17
I/O
16
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O
14
V
DDQ
V
SS
I/O
13
I/O
12
I/O
11
I/O
10
V
SS
V
DDQ
I/O
9
I/O
8
V
SS
V
DD
I/O
7
I/O
6
V
DDQ
V
SS
I/O
5
I/O
4
I/O
3
I/O
2
V
SS
V
DDQ
I/O
1
I/O
0
5279 drw 02
V
DD
/NC
(1)
I/O
15
I/O
P3
NC
I/O
P4
A
15
A
16
I/O
P1
NC
I/O
P2
ZZ
(2)
,
6.42
6
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperat ure Ranges
Pin Configuration – 256K x 18
10099989796959493929190 8786858483828189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
CS
0
NC
NC
BW
2
BW
1
CS
1
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
NC
NC
LBO
A
15
A
14
A
13
A
12
A
11
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
NC
NC
V
DDQ
V
SS
NC
I/O
P2
I/O
15
I/O
14
V
SS
V
DDQ
I/O
13
I/O
12
V
SS
V
DD
I/O
11
I/O
10
V
DDQ
V
SS
I/O
9
I/O
8
NC
NC
V
SS
V
DDQ
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
V
DDQ
V
SS
NC
I/O
P1
I/O
7
I/O
6
V
SS
V
DDQ
I/O
5
I/O
4
V
SS
V
DD
I/O
3
I/O
2
V
DDQ
V
SS
I/O
1
I/O
0
NC
NC
V
SS
V
DDQ
NC
NC
5279 drw 03
V
DD
/NC
(1)
NC
NC
NC
NC
A
16
A
17
NC
NC
A
10
ZZ
(2)
,
TQFP
Top View
NOTES:
1. Pin 14 can either be directly connected to V DD, or connected to an input voltage ≥ VIH, or left unconnected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial Temperature Range
7
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1)
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)
Figure 2. Lumped Capacitive Load, Typical Derating
Figure 1. AC Test Load
AC Test LoadAC Test Conditions
(VDDQ = 3.3V)
NOTE:
1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to V DD and the ZZ pin will be internally pulled to V SS if they are not actively driven in the application.
NOTES:
1. All values are maximum guaranteed values.
2. At f = f MAX, inputs are cycling at the maximum frequency of read cycles of 1/ Tcyc while ADSC = LOW; f=0 means no input lines are changing.
3. For I/Os V HD = V DDQ - 0.2V, V LD = 0.2V. For other inputs V HD = V DD - 0.2V, V LD = 0.2V.
V
DDQ
/2
50Ω
I/O Z
0
=50Ω
5279 drw 06
,
1
2
3
4
20 30 50 100 200
ΔtCD
(Typical, ns)
Capacitance (pF)
80
5
6
5279 drw 07
,
Symbol Parameter Test Conditions Min. Max. Unit
|I
LI
| Input Le akage Current V
DD
= Max., V
IN
= 0V to V
DD
___
5µA
|I
LZZ
|ZZ, LBO and J TAG Input Le akage Current
(1 )
V
DD
= Max., V
IN
= 0V to V
DD
___
30 µA
|I
LO
| Output Leakage Current V
OUT
= 0V to V
DDQ
, Device Deselected
___
5µA
V
OL
Output Low Voltage I
OL
= +8mA, V
DD
= Min.
___
0.4 V
V
OH
Output High Voltage I
OH
= -8mA, V
DD
= Min. 2.4
___
V
5279 tbl 08
Symbol Parameter Test Conditions
150MHz 133MHz
UnitCom'l Ind Com'l Ind
I
DD
Operating Power Supply
Current
Device Selected, Outputs Open, V
DD
= Max.,
V
DDQ
= Max., V
IN
> V
IH
or < V
IL
, f = f
MAX
(2)
295 305 250 260 mA
I
SB1
CMOS Standby Power
Supply Current
Device Deselected, Outputs Open, V
DD
= Max.,
V
DDQ
= Max., V
IN
> V
HD
or < V
LD
, f = 0
(2,3)
30 35 30 35 mA
I
SB2
Clock Run ning Power
Supply Current
Device Deselected, Outputs Open, V
DD
= Max.,
V
DDQ
= Max., V
IN
> V
HD
or < V
LD
, f = f
MAX
(2,3)
105 115 100 110 mA
I
ZZ
Full Sleep Mode Supply
Current
ZZ > V
HD,
V
DD
= Max. 30 35 30 35 mA
5279 t bl 0 9
Input P ulse Leve ls
Input R ise /Fall T imes
Input T iming Reference L evels
Output Timing Reference Le vels
AC Test Load
0 to 3V
2ns
1.5V
1.5V
See Figure 1
5 2 79 t bl 10
6.42
8
AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial Temperature Range
Synchronous Truth Table(1,3)
NOTES:
1. L = V IL, H = V IH, X = Don’t Care.
2. OE is an asynchronous input.
3. ZZ = low for this table.
Operation Address
Used
CE CS
0
CS
1
ADSP ADSC ADV GW BWE BWxOE
(2)
CLK I/O
Deselected Cycle, Power Down NoneHXX X L XXXXX -HI-Z
Deselected Cycle, Power Down NoneLXH L X XXXXX -HI-Z
Deselected Cycle, Power Down NoneLLX L X XXXXX-HI-Z
Deselected Cycle, Power Down NoneLXHX L XXXXX -HI-Z
Deselected Cycle, Power Down NoneLLX X L XXXXX -HI-Z
Read Cy cle, B egin B urst External L H L L X X X X X L - D
OUT
Read Cy cle, B egin B urst External L H L L X X X X X H - HI-Z
Read Cy cle, B egin B urst External L H L H L X H H X L - D
OUT
Read Cy cle, B egin B urst External L H L H L X H L H L - D
OUT
Read Cy cle, B egin B urst External L H L H L X H L H H - HI-Z
Write Cycle, Begin Burst External L H L H L X H L L X - D
IN
Write Cycle, Begin Burst External L H L H L X L X X X - D
IN
Read C ycle, C ontinue Burst Next X X X H H L H H X L - D
OUT
Read C ycle, C ontinue Burst Next X X X H H L H H X H - HI-Z
Read C ycle, C ontinue Burst Next X X X H H L H X H L - D
OUT
Read C ycle, C ontinue Burst Next X X X H H L H X H H - HI-Z
Read C ycle, C ontinue Burst Next H X X X H L H H X L - D
OUT
Read C ycle, C ontinue Burst Next H X X X H L H H X H - HI-Z
Read C ycle, C ontinue Burst Next H X X X H L H X H L - D
OUT
Read C ycle, C ontinue Burst Next H X X X H L H X H H - HI-Z
Write Cycle, Continue B urst Next X X X H H L H L L X - D
IN
Write Cycle, Continue B urst Next X X X H H L L X X X - D
IN
Write Cycle, Continue B urst Next H X X X H L H L L X - D
IN
Write Cycle, Continue B urst Next H X X X H L L X X X - D
IN
Read C ycle, S uspend B urst Current X X X H H H H H X L - D
OUT
Read C ycle, S uspend B urst Current X X X H H H H H X H - HI-Z
Read C ycle, S uspend B urst Current X X X H H H H X H L - D
OUT
Read C ycle, S uspend B urst Current X X X H H H H X H H - HI-Z
Read C ycle, S uspend B urst Current H X X X H H H H X L - D
OUT
Read C ycle, S uspend B urst Current H X X X H H H H X H - HI-Z
Read C ycle, S uspend B urst Current H X X X H H H X H L - D
OUT
Read C ycle, S uspend B urst Current H X X X H H H X H H - HI-Z
Write Cycle, Suspend Burst Current X X X H H H H L L X - D
IN
Write Cycle, Suspend Burst CurrentXXX H H HLXXX-D
IN
Write Cycle, Suspend Burst Current H X X X H H H L L X - D
IN
Write Cycle, Suspend Burst Current H X X X H H L X X X - D
IN
5279 tbl 11
6.42
AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial Temperature Range
9
Linear Burst Sequence T able (LBO=VSS)
Synchronous Write Function Truth Table(1, 2)
Asynchronous Truth Table(1)
Interleaved Burst Sequence Table (LBO=VDD)
NOTES:
1. L = V IL, H = V IH, X = Don’t Care.
2. BW3 and BW4 are not applicable for the AS8C401800.
3. Multiple bytes may be selected during the same cycle.
NOTES:
1. L = V IL, H = V IH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Operation GW BWE BW
1
BW
2
BW
3
BW
4
Read HHXXXX
Read HLHHHH
Write all Bytes L X X X X X
Write all Bytes H L L L L L
Write B yte 1
(3 )
HL L HHH
Write B yte 2
(3 )
HLHLHH
Write B yte 3
(3 )
HLHHLH
Write B yte 4
(3 )
HLHHHL
5279 tbl 12
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 1 0 1 1 0 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1)
11000110
5279 tbl 15
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 0 0 1 1 1 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1)
11100100
5279 tbl 14
Operation
(2)
OE ZZ I/O Status Power
Read L L Data O ut Active
Read H L High-Z Active
Write X L High-Z – Data In Active
Deselected X L High-Z Standby
Sleep Mode X H High-Z Sleep
5279 tbl 13
6.42
10
AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial Temperature Range
AC Electrical Characteristics
(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)
NOTES:
1. Measured as HIGH above VIH and LOW below VIL.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
150MHz 133MHz
Symbol Parameter Min. Max. Min. Max. Unit
t
CY C
Clock Cycle Time 6.7
____
7.5
____
ns
t
CH
(1 )
Clock High P ulse W idth 2.6
____
3
____
ns
t
CL
(1)
Clock Low Pulse Width 2.6
____
3
____
ns
Output Parameters
t
CD
Clo ck High to V alid Data
____
3.8
____
4.2 ns
t
CDC
Clock Hi gh to Data Cha nge 1.5
____
1.5
____
ns
t
CL Z
(2)
Clock High to Output Active 0
____
0
____
ns
t
CHZ
(2)
Clock High to Data Hi gh-Z 1.5 3.8 1.5 4.2 ns
t
OE
Output Enable Access Time
____
3.8
____
4.2 ns
t
OL Z
(2)
Output Enable Lo w to Output Active 0
____
0
____
ns
t
OHZ
(2)
Output Enable High to Output High-Z
____
3.8
____
4.2 ns
Set Up Times
t
SA
Address Setup Time 1.5
____
1.5
____
ns
t
SS
Address Status Setup Time 1.5
____
1.5
____
ns
t
SD
Data In S etup Time 1.5
____
1.5
____
ns
t
SW
Write Setup Time 1.5
____
1.5
____
ns
t
SAV
Address Advance Setup Time 1.5
____
1.5
____
ns
t
SC
Chip Enable/Select Setup Time 1.5
____
1.5
____
ns
Hold Times
t
HA
Address Hold Time 0.5
____
0.5
____
ns
t
HS
Address Status Hold Time 0.5
____
0.5
____
ns
t
HD
Data In Ho ld Time 0.5
____
0.5
____
ns
t
HW
Write Hold Time 0.5
____
0.5
____
ns
t
HAV
Address Advance Hold Time 0.5
____
0.5
____
ns
t
HC
Chip Enable/Select Hold Time 0.5
____
0.5
____
ns
Sleep M ode and Configuration P arameters
t
ZZP W
ZZ Pulse Width 100
____
100
____
ns
t
ZZR
(3)
ZZ R ecovery Time 100
____
100
____
ns
t
CFG
(4 )
Configuration S et-up Time 27
____
30
____
ns
52 79 t bl 16
6.42
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperat ure Ranges
11
NOTES:
1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence
of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. ZZ input is LOW and LBO is Don't Care for this cycle.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS 0 is HIGH.
Timing Waveform of Pipelined Read Cycle(1,2)
t
CHZ
t
SA
t
SC
t
HS
G
W,BWE,BWx
t
SW
t
CL
t
SAV
t
HW
t
HAV
CLK
ADSC
(1)
ADDRESS
t
CYC
t
CH
t
HA
t
HC
t
OE
t
OHZ
OEt
CD
t
OLZ
O1(Ax)
DATA
OUT
t
CDC
O1(Ay)O3(Ay)O2(Ay)
O2(Ay)
t
CLZ
ADV
CE,CS
1
(Note3)
Pipelined
ReadBurstPipelinedRead
Output
Disabled
AxAy
t
SS
O1(Ay)
(Burstwrapsaround
to its initialstate)
O4(Ay)
5279drw08
ADSP
ADVHIGHsuspends
burst
,
6.42
12
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperat ure Ranges
NOTES:
1. Device is selected through entire cycle; CE and CS1 are LOW, CS 0 is HIGH.
2. ZZ input is LOW and LBO is Don't Care for this cycle.
3. O1 (Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the external address Ay; O1 (Az) represents the first output from the external address Az; O2 (Az) represents
the next output data in the burst sequence of the base address Az, etc. where A0 and A1 are advancing for the four word burst i n the sequence defined by the state of the LBO input.
Timing Waveform of Combined Pipelined Read and Write Cycles(1,2,3)
CLK
ADSP
ADDRESS
GW
ADV
OE
DAT
A
OUT
t
CYC
t
CH
t
CL
t
HA
t
SW
t
HW
t
CLZ
AxAyAz
t
HS
I1(Ay)
t
SD
t
HD
t
OLZ
t
CD
t
CDC
DAT
A
IN
(2)
t
OE
O1(Az)
O1(Az)
Single ReadPipelinedBurstRead
Pipelined
Write
O1(Ax)
t
OHZ
t
SS
t
SA
O3(Az)
O2(Az)
5279drw09
t
CD
,
6.42
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperat ure Ranges
13
NOTES:
1. ZZ input is LOW, BWE is HIGH and LBO is Don't Care for this cycle.
2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external
address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advan cing for the four word burst in the sequence defined
by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS 0 is HIGH.
Timing Waveform of Write Cycle No. 1 - GW Controlled(1,2,3)
A
DDRESS
CLK
ADSP
ADSC
t
CYC
t
SS
t
HS
t
CH
t
CL
t
HA
t
SA
AxAyAz
ADV
DAT
A
OUT
OE
t
HC
t
SD
I1(Ax)I1(Az)
I2(Ay)
tHD
t
OHZ
DATA
IN
t
HAV
O3(Aw)O4(Aw)
CE,CS
1
t
HW
GW
t
SW
(Note3)
I2(Az)
BurstWrite
BurstReadBurstWrite
Single
Write
I3(Az)
I4(Ay)
I3(Ay)
I2(Ay)
t
SAV
(ADVHIGHsuspendsburst)
I1(Ay)
GWis ignoredwhenADSPinitiatesacycle andis sampledonthenextclockrisingedge
t
SC
5279drw10
,
6.42
14
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperat ure Ranges
Timing Waveform of Write Cycle No. 2 - Byte Controlled
(1,2,3)
A
DDRESS
CLK
ADSP
ADSC
t
CYC
t
SS
t
HS
t
CH
t
CL
t
HA
t
SA
AxAy
t
HW
BWx
ADV
DAT
A
OUT
OE
t
HC
t
SD
Single
Write BurstWrite
I1(Ax)I2(Ay)I2(Ay)
(ADVsuspendsburst)
I2(Az)
tHD
Burst
ReadExtended
BurstWrite
t
OHZ
DATA
IN
t
SAV
t
SW
O4(Aw)
CE,CS
1
t
HW
BWE
t
SW
(Note3)
I1(Az)
Az
I4(Ay)
I1(Ay)I4(Ay)
I3(Ay)
t
SC
BWEis ignoredwhenADSPinitiatesacycle andis sampledonnextclockrisingedge
BWxis ignoredwhenADSPinitiatesacycle andis sampledonnextclockrisingedge
I3(Az)
O3(Aw)
5279drw11
,
NOTES:
1. ZZ input is LOW, GW is HIGH and LBO is Don't Care for this cycle.
2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external
address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advan cing for the four word burst in the sequence defined
by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS 0 is HIGH.
6.42
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperat ure Ranges
15
Timing Waveform of Sleep (ZZ) and Power-Down Modes(1,2,3)
t
CYC
t
SS
t
CL
t
CH
t
HA
t
SA
t
SC
t
HC
t
OE
t
OLZ
t
HS
CLK
ADSP
ADSC
A
DDRESS
GW
CE,CS
1
ADV
DATA
OUT
OE
ZZ
Single ReadSnoozeMode
tZZPW
5279drw12
O1(Ax)
Ax
(Note 4)
tZZR
Az
,
NOTES:
1. Device must power up in deselected Mode
2. LBO is Don't Care for this cycle.
3. It is not necessary to retain the state of the input registers throughout the Power-down cycle.
4. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS 0 is HIGH.
6.42
16
AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial Temperature Range
CLK
ADSP
GW,BWE,BWx
CE, CS
1
CS
0
ADDRESS
ADSC
DATA
OUT
OE
Av Aw Ax Ay Az
(Av) (Aw) (Ax) (Ay)
5279 drw 14
,
Non-Burst Read Cycle Timing Waveform
NOTES:
1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. For read cycles, ADSP and ADSC function identically and are therefore interchangable.
NOTES:
1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only GW writes are shown, the functionality ofBWE and BWx together is the same asGW.
4. For write cycles, ADSP and ADSC have different limitations.
Non-Burst Write Cy cle Timing Waveform
CLK
ADSP
GW
CE, CS
1
CS
0
ADDRESS
ADSC
DATA
IN
Av Aw Ax AzAy
(Av) (Aw) (Ax) (Az)(Ay)
5279 drw 15
,
6.42
AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial Temperature Range
17
Packa
AS6C 8016 -55 X X N
Device Number Package OptionTemperature Range
80 = 8M Z- 44pin TSOP I = Industrial
low power
SRAM prefix16 = x16
Access
TimeB = 48ball TFBGA (-40 to + 85 C)
N = Lead Free
RoHS
compliant part
Alliance Organization VCC
Range Package Operating Temp Speed
Mhz
AS8C403600-QC150N 128K x 36 3.1- 3.4V 100 pin TQFP Commercial: 0 C - 70C 150
AS8C401800-QC150N 256K x 18 3.1- 3.4V 100 pin TQFP Commercial: 0 C - 70C 150
PART NUMBERING SYSTEM
®
Alliance Memory, Inc.
551 Taylor way, Suite#1,
San Carlos, CA 94070
Tel: 650-610-6800
Fax: 650-620-9211
www.alliancememory.com
Copyright © Alliance Memory
All Rights Reserved
Part Number: AS8C403600/401800
Document Version: v. 1.0
© Copyright 2003 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of
Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this
document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any
time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in
this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide,
any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any
product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or
warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in
Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's
Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights,
trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in
life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of
Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all
claims arising from such use.
ORDERING INFORMATION
ORDERING INFORMATION
Alliance OrganizationVCC
Range Package Operating TempSpeed
ns
AS6C8016A-55ZIN512K x 16 2.7- 5.5V44pin TSOP IIIndustrial ~ -40 C - 85 C 55
AS6C8016A-55BIN512K x 16 2.7- 5.5V48ball FBGAIndustrial ~ -40 C - 85 C 55
PART NUMBERING SYSTEM
AS6C 8016 -55 X X N
Device Number Package OptionTemperature Range
80 = 8M Z- 44pin TSOP I = Industrial
low power
SRAM prefix16 = x16
Access
TimeB = 48ball TFBGA (-40 to + 85 C)
N = Lead Free
RoHS
compliant part
AS8C
01= ZBT Q = 100 Pin TQFP
Sync.
SRAM prefix
18= x18
36 = x36 25 = Flow- Thru
0 ~ 70C 150MHz N= Leadfree
40 = M 00 = Pipelined
Speed
Device Conf. Mode Package Operating Temp N
