KH29LV800CTTC-70G - Macronix International Co., Ltd.

P/N:PM1222

KH29LV800C T/B

8M-BIT [1Mx8/512K x16] CMOS SINGLE VOLTAGE

3V ONLY FLASH MEMORY

• Ready/Busy# pin (RY/BY#)

- Provides a hardware method of detecting program or

erase operation completion

• Sector protection

- Hardware method to disable any combination of

sectors from program or erase operations

- Temporary sector unprotected allows code changes

in previously locked sectors

• CFI (Common Flash Interface) compliant

- Flash device parameters stored on the device and

provide the host system to access

• 100,000 minimum erase/program cycles

• Latch-up protected to 100mA from -1V to VCC+1V

• Boot Sector Architecture

- T = Top Boot Sector

- B = Bottom Boot Sector

• Package type:

- 48-pin TSOP

- All Pb-free devices are RoHS Compliant

• Compatibility with JEDEC standard

- Pinout and software compatible with single-power

supply Flash

• 10 years data retention

FEATURES

• Extended single - supply voltage range 2.7V to 3.6V

• 1,048,576 x 8/524,288 x 16 switchable

• Single power supply operation

- 3.0V only operation for read, erase and program

operation

• Fast access time: 70/90ns

• Low power consumption

- 20mA maximum active current

- 0.2uA typical standby current

• Command register architecture

- Byte/word Programming (9us/11us typical)

- Sector Erase (Sector structure 16K-Bytex1,

8K-Bytex2, 32K-Bytex1, and 64K-Byte x15)

• Auto Erase (chip & sector) and Auto Program

- Automatically erase any combination of sectors with

Erase Suspend capability

- Automatically program and verify data at specified

address

• Erase suspend/Erase Resume

- Suspends sector erase operation to read data from,

or program data to, any sector that is not being erased,

then resumes the erase

• Status Reply

- Data# polling & Toggle bit for detection of program

and erase operation completion.

GENERAL DESCRIPTION

The KH29LV800C T/B is a 8-mega bit Flash memory

organized as 1M bytes of 8 bits or 512K words of 16

bits. MXIC's Flash memories offer the most cost-effec-

tive and reliable read/write non-volatile random access

memor y. The KH29LV800C T/B is packaged in 48-pin

TSOP. It is designed to be reprogrammed and erased in

system o r in standard EPROM pro grammers.

The standard KH29LV800C T/B offers access time as

fast as 55ns, allowing o peratio n of high-speed micropro-

cessors without wait states. To eliminate bus conten-

tion, the KH29LV800C T/B has separate chip enable

(CE#) and output enable (OE#) controls.

MXIC's Flash memories augment EPROM functionality

with in-circuit electrical erasure and pro gramming. The

KH29LV800C T/B uses a co mmand register to manage

this functio nality . The command register allows for 100%

TTL level control inputs and fixed power supply levels

during erase and pro gramming, while maintaining maxi-

mum EPR OM compatibility.

MXIC Flash technology reliably stores memory contents

even after 100,000 erase and pro gram cycles. The MXIC

cell is designed to optimize the erase and programming

mechanisms. In addition, the combination of advanced

tunnel oxide processing and low internal electric fields

for erase and program operations produces reliable cy-

cling. The KH29LV800C T/B uses a 2.7V~3.6V VCC

supply to perform the High Reliability Erase and auto

Program/Erase algorithms.

The highest degree of latch-up protection is achieved

with MXIC's proprietary non-epi process. Latch-up pro-

tection is proved for stresses up to 100 milliamperes on

address and data pin from -1V to VCC + 1V.

REV. 1.2, DEC. 09, 2005

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

PIN CONFIGURATIONS

PIN DESCRIPTION

SYMBOL PIN NAME

A0~A18 Address Input

Q0~Q14 Data Input/Output

Q15/A-1 Q15(Word mode)/LSB addr(Byte mode)

CE# Chip Enable Input

WE# Write Enable Input

BYTE# Word/Byte Selection input

RESET# Hardware Reset Pin

OE# Output Enable Input

R Y/BY# Ready/Busy Output

VCC P ower Supply Pin (2.7V~3.6V)

GND Ground Pin

48 TSOP (Standard Type) (12mm x 20mm)

A15

A14

A13

A12

A11

A10

WE#

RESET#

RY/BY#

A18

A17

A16

BYTE#

GND

Q15/A-1

Q14

Q13

Q12

VCC

Q11

Q10

OE#

GND

CE#

KH29LV800C T/B

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

BLOCK STRUCTURE

TABLE 1: KH29LV800CT SECTOR ARCHITECTURE

Note: Byte mode:address range A18:A-1, word mode:address range A18:A0.

Sector Sector Size Address range Sector Address

Byte Mode W ord Mode Byte Mode (x8) W ord Mode (x16) A18 A17 A16 A15 A14 A13 A12

SA0 64Kbytes 32Kwords 00000h-0FFFFh 00000h-07FFFh 0000XXX

SA1 64Kbytes 32Kwords 10000h-1FFFFh 08000h-0FFFFh 0001XXX

SA2 64Kbytes 32Kwords 20000h-2FFFFh 10000h-17FFFh 0010XXX

SA3 64Kbytes 32Kwords 30000h-3FFFFh 18000h-1FFFFh 0011XXX

SA4 64Kbytes 32Kwords 40000h-4FFFFh 20000h-27FFFh 0100XXX

SA5 64Kbytes 32Kwords 50000h-5FFFFh 28000h-2FFFFh 0101XXX

SA6 64Kbytes 32Kwords 60000h-6FFFFh 30000h-37FFFh 0110XXX

SA7 64Kbytes 32Kwords 70000h-7FFFFh 38000h-3FFFFh 0111XXX

SA8 64Kbytes 32Kwords 80000h-8FFFFh 40000h-47FFFh 1000XXX

SA9 64Kbytes 32Kwords 90000h-9FFFFh 48000h-4FFFFh 1001XXX

SA10 64Kbytes 32Kwords A0000h-AFFFFh 50000h-57FFFh 1010XXX

SA11 64Kbytes 32Kwords B0000h-BFFFFh 58000h-5FFFFh 1011XXX

SA12 64Kbytes 32Kwords C0000h-CFFFFh 60000h-67FFFh 1100XXX

SA13 64Kbytes 32Kwords D0000h-DFFFFh 68000h-6FFFFh 1101XXX

SA14 64Kbytes 32Kwords E0000h-EFFFFh 70000h-77FFFh 1110XXX

SA15 32Kbytes 16Kwords F0000h-F7FFFh 78000h-7BFFFh 11110XX

SA16 8Kbytes 4Kwords F8000h-F9FFFh 7C000h-7CFFFh 111110 0

SA17 8Kbytes 4Kwords FA000h-FBFFFh 7D000h-7DFFFh 111110 1

SA18 16Kbytes 8Kwords FC000h-FFFFFh 7E000h-7FFFFh 111111X

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KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

Sector Sector Size Address range Sector Address

Byte Mode W ord Mode Byte Mode (x8) W ord Mode (x16) A18 A17 A16 A15 A14 A13 A12

SA0 16Kbytes 8Kwords 00000h-03FFFh 00000h-01FFFh 000000X

SA1 8Kbytes 4Kwords 04000h-05FFFh 02000h-02FFFh 000001 0

SA2 8Kbytes 4Kwords 06000h-07FFFh 03000h-03FFFh 000001 1

SA3 32Kbytes 16Kwords 08000h-0FFFFh 04000h-07FFFh 00001XX

SA4 64Kbytes 32Kwords 10000h-1FFFFh 08000h-0FFFFh 0001XXX

SA5 64Kbytes 32Kwords 20000h-2FFFFh 10000h-17FFFh 0010XXX

SA6 64Kbytes 32Kwords 30000h-3FFFFh 18000h-1FFFFh 0011XXX

SA7 64Kbytes 32Kwords 40000h-4FFFFh 20000h-27FFFh 0100XXX

SA8 64Kbytes 32Kwords 50000h-5FFFFh 28000h-2FFFFh 0101XXX

SA9 64Kbytes 32Kwords 60000h-6FFFFh 30000h-37FFFh 0110XXX

SA10 64Kbytes 32Kwords 70000h-7FFFFh 38000h-3FFFFh 0111XXX

SA11 64Kbytes 32Kwords 80000h-8FFFFh 40000h-47FFFh 1000XXX

SA12 64Kbytes 32Kwords 90000h-9FFFFh 48000h-4FFFFh 1001XXX

SA13 64Kbytes 32Kwords A0000h-AFFFFh 50000h-57FFFh 1010XXX

SA14 64Kbytes 32Kwords B0000h-BFFFFh 58000h-5FFFFh 1011XXX

SA15 64Kbytes 32Kwords C0000h-CFFFFh 60000h-67FFFh 1100XXX

SA16 64Kbytes 32Kwords D0000h-DFFFFh 68000h-6FFFFh 1101XXX

SA17 64Kbytes 32Kwords E0000h-EFFFFh 70000h-77FFFh 1110XXX

SA18 64Kbytes 32Kwords F0000h-FFFFFh 78000h-7FFFFh 1111XXX

TABLE 2: KH29LV800CB SECTOR ARCHITECTURE

Note: Byte mode:address range A18:A-1, word mode:address range A18:A0.

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

BLOCK DIAGRAM

CONTROL

INPUT

LOGIC

PROGRAM/ERASE

HIGH V OLTA GE

WRITE

STATE

MACHINE

(WSM)

STATE

FLASH

ARRAY

X-DECODER

ADDRESS

LATCH

AND

BUFFER Y-PASS GATE

Y-DECODER

ARRAY

SOURCE

HV COMMAND

DATA

DECODER

COMMAND

DATA LATCH

I/O BUFFER

PGM

DATA

PROGRAM

DATA LATCH

SENSE

AMPLIFIER

Q0-Q15/A-1

A0-A18

CE#

OE#

WE#

RESET#

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

AUTOMATIC PROGRAMMING

The KH29LV800C T/B is b yte progr ammable using the

Automatic Pro gramming algo rithm. The Auto matic Pro-

gramming algorithm makes the external system do not

need to have time out sequence nor to verify the data

programmed. The typical chip programming time at room

temperature o f the KH29L V800C T/B is less than 10 sec-

onds.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires the

user to only write program set-up commands (including

2 unlock write cycle and A0H) and a program command

(program data and address). The de vice automatically

times the programming pulse width, provides the pro-

gram v erificatio n, and counts the number of sequences.

A status bit similar to DATA# polling and a status bit

to ggling between consecutive read cycles, pro vide feed-

back to the user as to the status of the programming

operatio n. Refer to write operation status, table 8, for more

inf o rmatio n on these status bits.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulses

according to MXIC's Automatic Chip Erase algorithm.

Typical erasure at ro om temperature is acco mplished in

less than 25 second. The Automatic Erase algorithm

automatically programs the entire array prior to electri-

cal erase. The timing and verificatio n of electrical erase

are controlled internally within the device.

AUTOMATIC SECTOR ERASE

The KH29LV800C T/B is sector(s) erasable using MXIC's

Auto Sector Erase algorithm. The Automatic Sector

Erase algorithm automatically programs the specified

secto r(s) prio r to electrical erase . The timing and verifi-

catio n of electrical erase are co ntrolled internally within

the device. An erase operation can erase one sector,

multiple sectors, or the entire device.

AUTOMATIC ERASE ALGORITHM

MXIC's A utomatic Erase algorithm requires the user to

write commands to the command register using stan-

dard micro processo r write timings. The device will auto-

matically pre-progr am and verify the entire arra y. Then

the device automatically times the erase pulse width,

provides the erase verification, and counts the number

of sequences. A status bit toggling between consecu-

tive read cycles provides feedback to the user as to the

status of the erasing operation.

machine which controls the erase and programming cir-

cuitry. During write cycles, the co mmand register inter-

nally latches address and data needed for the program-

ming and erase operations. During a system write cycle,

addresses are latched on the falling edge, and data are

latched on the rising edge of WE# or CE#, whichever

happens first.

MXIC's Flash technology combines years of EPROM

e xperience to pro duce the highest le v els of quality, reli-

ability, and cost effectiveness. The KH29LV800C T/B

electrically erases all bits simultaneously using Fowler-

No rdheim tunneling. The bytes are programmed by us-

ing the EPROM programming mechanism of hot elec-

tron injection.

During a program cycle, the state-machine will control

the program sequences and command register will not

respond to any command set. During a Sector Erase

cycle, the command register will only respond to Erase

Suspend command. After Erase Suspend is completed,

the device stays in read mode. After the state machine

has completed its task, it will allow the command regis-

ter to respond to its full command set.

AUTOMATIC SELECT

The auto select mode provides manufacturer and de-

vice identification, and sector protection verification,

thro ugh identifier co des o utput on Q7~Q0. This mo de is

mainly adapted for programming equipment on the de-

vice to be programmed with its programming algorithm.

When programming by high voltage method, automatic

select mode requires VID (11.5V to 12.5V) on address

pin A9 and other address pin A6, A1 and A0 as referring

to Table 3. In addition, to access the automatic select

codes in-system, the host can issue the automatic se-

lect co mmand thro ugh the command register witho ut re-

quiring VID, as shown in table 5.

To verify whether or not secto r being pro tected, the sec-

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KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

tor address must appear on the appropriate highest order

address bit (see Table 1 and Table 2). The rest of address

bits, as shown in table 3, are do n't care. Once all neces-

sary bits have been set as required, the programming

equipment may read the corresponding identifier code on

Q7~Q0.

A18 A11 A9 A8 A6 A5 A1 A0

Description Mode CE# OE# WE# | | | | Q15~Q0

A12 A10 A7 A2

Manufacturer Code L L H X X VID X L X L L C2H

Read Device ID Word L L H X X VID X L X L H 22DAH

Silicon (Top Boot Block) Byte L L H X X VID X L X L H XXDAH

ID Device ID Word L L H X X VID X L X L H 225BH

(Bottom Boot Block) Byte L L H X X VID X L X L H XX5BH

XX01H

Sector Protection L L H SA X VID X L X H L (protected)

Verification XX00H

(unprotected)

TABLE 3. KH29LV800C T/B AUTO SELECT MODE OPERATION

NO TE:SA=Secto r Address , X=Do n't Care , L=Lo gic Low, H=Lo gic High

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

QUERY COMMAND AND COMMON FLASH

INTERFACE (CFI) MODE ( for KH29LV800C T/

KH29L V800C T/B is capable o f operating in the CFI mode.

This mode all the host system to determine the manu-

facturer o f the device such as o perating parameters and

co nfiguratio n. Two co mmands are required in CFI mo de.

Query command of CFI mode is placed first, then the

Reset co mmand exits CFI mo de. These are described in

Table 6.

The single cycle Query command is valid only when the

device is in the Read mode, including Erase Suspend,

Standby mode, and Read ID mode; however, it is ig-

nored otherwise.

The Reset command exits from the CFI mode to the

Read mode, or Erase Suspend mode, or read ID mode.

The command is valid only when the device is in the

CFI mode.

TABLE 4-1. CFI mode: Identification Data Values

(All values in these tables are in hexadecimal)

Description Address Address Data

(Byte Mode) (Word Mode)

Query-unique ASCII string "QRY" 2 0 1 0 0051

22 11 0052

24 12 0059

Primary vendor command set and control interface ID code 2 6 1 3 0002

28 14 0000

Address for primary algorithm extended query table 2A 1 5 0040

2C 16 0000

Alternate vendor command set and control interface ID code (none) 2E 1 7 0000

30 18 0000

Address for secondary algorithm extended query table (none) 32 19 0000

34 1A 0000

TABLE 4-2. CFI Mode: System Interface Data Values

(All values in these tables are in hexadecimal)

Description Address Address Data

(Byte Mode) (Word Mode)

VCC supply, minimum (2.7V) 3 6 1B 0027

VCC supply, maximum (3.6V) 3 8 1 C 0036

VPP supply, minimum (none) 3A 1 D 0000

VPP supply, maximum (none) 3 C 1E 0000

Typical timeout for single word/byte write (2N us) 3E 1F 0004

Typical timeout for Minimum size buffer write (2N us) 4 0 2 0 0000

Typical timeout for individual block erase (2N ms) 4 2 2 1 000A

Typical timeout for full chip erase (2N ms) 4 4 22 0000

Maximum timeout for single word/byte write times (2N X Typ) 4 6 2 3 0005

Maximum timeout for buffer write times (2N X Typ) 48 24 0000

Maximum timeout for individual block erase times (2N X Typ) 4A 25 0004

Maximum timeout for full chip erase times (not supported) 4C 2 6 0000

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KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

TABLE 4-3. CFI Mode: Device Geometry Data Values

(All values in these tables are in hexadecimal)

Description Address Address Data

(Byte Mode) (Word Mode)

Device size (2N bytes) 4E 27 0014

Flash device interface code (refer to the CFI publication 100) 5 0 2 8 0002

52 29 0000

Maximum number of bytes in multi-byte write (not supported) 5 4 2A 0000

56 2B 0000

Number of erase block regions 5 8 2 C 0004

Erase block region 1 information (refer to the CFI publication 100) 5A 2 D 0000

5C 2E 0000

5E 2F 0040

60 30 0000

Erase block region 2 information 6 2 31 0001

64 32 0000

66 33 0020

68 34 0000

Erase block region 3 information 6A 3 5 0000

6C 36 0000

6E 37 0080

70 38 0000

Erase block region 4 information 7 2 39 000E

74 3A 0000

76 3B 0000

78 3C 0001

TABLE 4-4. CFI Mode: Primar y Vendor-Specific Extended Query Data Values

(All values in these tables are in hexadecimal)

Description Address Address Data

(Byte Mode) (Word Mode)

Query-unique ASCII string "PRI" 8 0 4 0 0050

82 41 0052

84 42 0049

Major version number, ASCII 8 6 43 0031

Minor version number, ASCII 8 8 44 0030

Address sensitive unlock (0=required, 1= not required) 8A 4 5 0000

Erase suspend (2= to read and write) 8 C 4 6 0002

Sector protect (N= # of sectors/group) 8E 4 7 0001

Temporary sector unprotected (1=supported) 90 48 0001

Sector protect/unprotected scheme 92 49 0004

Simultaneous R/W operation (0=not supported) 94 4A 0000

Burst mode type (0=not supported) 9 6 4B 0000

Page mode type (0=not supported) 98 4 C 0000

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KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus

Command Bus Cycle Cycle Cycle Cycle Cycle Cycle

Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Reset 1 XXXH F0H

Read 1 RA RD

Read Silicon ID Word 4 555H AAH 2AAH 55H 555H 90H ADI DDI

Byte 4 AAAH AAH 555H 55H AAAH 90H ADI DDI

Sector Protect Word 4 555H AAH 2AAH 55H 555H 90H (SA) XX00H

Verify x02H XX01H

Byte 4 AAAH AAH 555H 55H AAAH 90H (SA) 00H

x04H 01H

Program Word 4 555H AAH 2AAH 55H 555H A0H PA PD

Byte 4 AAAH AAH 555H 55H AAAH A0H PA PD

Chip Erase Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H

Byte 6 AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H AAAH 10H

Sector Erase Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H

Byte 6 AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H SA 30H

Sector Erase Suspend 1 XXXH B0H

Sector Erase Resume 1 XXXH 3 0H

CFI Query Word 1 55H 98

Byte 1 AAH 98

TABLE 5. KH29LV800C T/B COMMAND DEFINITIONS

Note:

1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacturer code,A1=0, A0 = 1 for device code. A2-A18=do not care.

(Refer to table 3)

DDI = Data of Device identifier : C2H for manufacture code, 22DA/DA(Top), and 225B/5B(Bottom) for device code.

X = X can be VIL or VIH

RA=Address of memory location to be read.

RD=Data to be read at location RA.

2. PA = Address of memory location to be programmed.

PD = Data to be programmed at location PA.

SA = Address of the sector.

3. The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or

555H to Address A10~A-1 in byte mode.

Address bit A11~A18=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA).

Write Sequence may be initiated with A11~A18 in either state.

4. For Sector Protect Verify operation: If read out data is 01H, it means the sector has been protected. If read out data is 00H,

it means the sector is still not being protected.

5. Any number of CFI data read cycle are permitted.

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KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

TABLE 6. KH29LV800C T/B BUS OPERATION

NOTES:

1. Manufacturer and device codes may also be accessed via a command register wr ite sequence. Refer to Table 5.

2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.

3. Refer to Table 5 for valid Data-In during a write operation.

4. X can be VIL or VIH.

5. Code=00H/XX00H means unprotected.

Code=01H/XX01H means protected.

6. A18~A12=Sector address for sector protect.

7. The sector protect and chip unprotected functions may also be implemented via programming equipment.

sequences. Note that the Erase Suspend (B0H) and

Erase Resume (30H) commands are valid only while the

Sector Erase operation is in progress.

COMMAND DEFINITIONS

Device operations are selected by writing specific ad-

dress and data sequences into the command register.

Writing incorrect address and data values or writing them

in the improper sequence will reset the device to the

read mo de. Table 5 defines the v alid register co mmand

ADDRESS Q8~Q15

DESCRIPTION CE# OE# WE#RESET# A18 A10 A9 A8 A6 A5 A1 A0 Q0~Q7 BYTE BYTE

A12 A11 A7 A2 =VIH =VIL

Read L L H H AIN Dout Dout Q8~Q14

=High Z

Q15=A-1

Write L H L H AIN DIN(3) DIN

Reset X X X L X High Z High Z High Z

Temporary sector unlock X X X VID AIN DIN DIN High Z

Output Disable L H H H X High Z High Z High Z

Standby Vcc±X X Vcc± X High Z High Z High Z

0.3V 0.3V

Sector Protect L H L VID SA X X X L X H L DIN X X

Chip Unprotected L H L VID X X X X H X H L DIN X X

Sector Protection Verify L L H H SA X VID X L X H L CODE(5) X X

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KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

REQUIREMENTS FOR READING ARRAY

DATA

To read array data from the outputs, the system must

drive the CE# and OE# pins to VIL. CE# is the power

control and selects the device. OE# is the output control

and gates array data to the output pins. WE# should

remain at VIH.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No command

is necessary in this mode to obtain array data. Standard

microprocessor read cycles that assert valid address

on the device address inputs produce valid data on the

device data outputs. The device remains enabled for read

access until the command register contents are altered.

WRITE COMMANDS/COMMAND SEQUENCES

To program data to the device or erase sectors of memory

, the system must driv e WE# and CE# to VIL, and OE#

to VIH.

An erase o peration can erase one sector, multiple secto rs

, o r the entire device. Table indicates the address space

that each sector occupies. A "sector address" consists

of the address bits required to uniquely select a sector .

The "Writing specific address and data commands or

sequences into the command register initiates device

operations. Table 1 defines the v alid register command

sequences. Writing inco rrect address and data values o r

writing them in the improper sequence resets the device

to reading array data. Section has details on erasing a

sector or the entire chip, or suspending/resuming the

erase operation.

After the system writes the autoselect command

sequence, the device enters the autoselect mode. The

system can then read autoselect codes from the internal

Q7-Q0. Standard read cycle timings apply in this mode.

Refer to the Autoselect Mode and Auto select Co mmand

Sequence sectio n fo r more info rmatio n.

ICC2 in the DC Characteristics table represents the

active current specification f or the write mo de . The "A C

Characteristics" section contains timing specification

table and timing diagrams fo r write operations.

STANDBY MODE

When using both pins of CE# and RESET#, the device

enter CMOS Standby with both pins held at Vcc ± 0.3V.

If CE# and RESET# are held at VIH, but not within the

range of VCC ± 0.3V, the device will still be in the standby

mo de, but the standby current will be larger. During Auto

Algo rithm o peration, Vcc active current (Icc2) is required

even CE# = "H" until the operation is completed. The

device can be read with standard access time (tCE) from

either of these standby modes, before it is ready to read

data.

OUTPUT DISABLE

With the OE# input at a logic high level (VIH), output

fro m the devices are disabled. This will cause the output

pins to be in a high impedance state.

RESET# OPERATION

The RESET# pin provides a hardware method of resetting

the device to reading array data. When the RESET# pin

is driven low for at least a period of tRP, the device

immediately terminates any operation in progress, tri-

states all output pins, and ignores all read/write

commands for the duration of the RESET# pulse. The

device also resets the internal state machine to reading

array data. The operatio n that was interrupted sho uld be

reinitiated once the device is ready to accept another

command sequence, to ensure data integrity

Current is reduced for the duration of the RESET# pulse.

When RESET# is held at VSS±0.3V, the device draws

CMOS standby current (ICC4). If RESET# is held at VIL

but not within VSS±0.3V, the standby current will be

greater.

The RESET# pin ma y be tied to system reset circuitry.

A system reset wo uld that also reset the Flash memo ry ,

enabling the system to read the boot-up firmware from

the Flash memory.

If RESET# is asserted during a program or erase

o peratio n, the RY/BY# pin remains a "0" (b usy) until the

internal reset operation is complete, which requires a

time of tREADY (during Embedded Algorithms). The

system can thus mo nito r R Y/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is completed within a

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KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

time o f tREAD Y (no t during Embedded Algo rithms). The

system can read data tRH after the RESET# pin returns

to VIH.

Refer to the AC Characteristics tables for RESET#

parameters and to Figure 22 f or the timing diagram.

READ/RESET COMMAND

The read or reset o peration is initiated by writing the read/

reset command sequence into the command register.

Micro processor read cycles retrie ve array data. The de-

vice remains enabled fo r reads until the co mmand regis-

ter co ntents are altered.

If pro gram-f ail or erase-fail happen, the write o f F0H will

reset the device to abort the operation. A valid com-

mand must then be written to place the device in the

desired state.

SILICON-ID READ COMMAND

Flash memories are intended for use in applications where

the lo cal CPU alters memo ry co ntents. As such, manu-

facturer and device co des must be accessible while the

device resides in the target system. PROM program-

mers typically access signature codes by raising A9 to

a high vo ltage (VID). However , multiplexing high voltage

onto address lines is not generally desired system de-

sign practice.

The KH29L V800C T/B contains a Silicon-ID-Read opera-

tio n to supple traditional PROM pro gramming metho dol-

o gy. The o peratio n is initiated by writing the read silico n

ID co mmand sequence into the command register. Fo l-

lowing the command wr ite, a read cycle with A1=VIL,

A0=VIL retrieves the manufacturer co de of C2H/00C2H.

A read cycle with A1=VIL, A0=VIH returns the device

co de of DAH/22D AH fo r KH29LV800CT, 5BH/225BH fo r

KH29LV800CB.

SET-UP AUTOMATIC CHIP/SECTOR ERASE

COMMANDS

Chip erase is a six-bus cycle operation. There are two

"unlo c k" write cycles. These are f o llo wed by writing the

"set-up" co mmand 80H. Two mo re "unlock" write cycles

are then followed by the chip erase command 10H or

secto r erase co mmand 30H.

The Auto matic Chip Erase does not require the device to

be entirely pre-pro grammed prior to ex ecuting the Auto-

matic Chip Erase. Upon executing the Automatic Chip

Erase, the device will automatically program and verify

the entire memo ry fo r an all-zero data pattern. When the

device is automatically verified to co ntain an all-zero pat-

tern, a self-timed chip erase and verify begin. The erase

and verify operatio ns are completed when the data on Q7

is "1" at which time the device returns to the Read mode.

The system is no t required to pro vide any co ntro l o r tim-

ing during these operations.

When using the Automatic Chip Erase algor ithm, note

that the erase auto matically terminates when adequate

erase margin has been achieved for the memory array

(no erase verificatio n command is required).

If the Erase o peratio n was unsuccessful, the data o n Q5

is "1" (see Table 8), indicating the erase operation ex-

ceed internal timing limit.

The automatic erase begins o n the rising edge o f the last

WE# o r CE# pulse, whiche ver happens first in the co m-

mand sequence and terminates when the data on Q7 is

"1" at which time the device returns to the Read mode,

o r the data on Q6 sto ps toggling fo r two co nsecutive read

cycles at which time the device returns to the Read mode.

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KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

READING ARRAY DATA

The device is automatically set to reading array data

after device power-up. No commands are required to re-

trieve data. The device is also ready to read array data

after completing an Automatic Program or Automatic

Erase algorithm.

After the device accepts an Erase Suspend command,

the device enters the Erase Suspend mode. The sys-

tem can read array data using the standard read tim-

ings, except that if it reads at an address within erase-

suspended sectors, the device outputs status data. Af-

ter completing a programming operation in the Erase

Suspend mode, the system may once again read array

data with the same exception. See Erase Suspend/Erase

Resume Commands” for more information on this mode.

The system must issue the reset command to re-en-

able the device for reading array data if Q5 goes high, or

while in the autoselect mode. See the "Reset Command"

section, next.

RESET COMMAND

Writing the reset command to the device resets the de-

vice to reading array data. Address bits are don't care

for this command.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to reading arra y

data. Once erasure begins, however , the device igno res

reset commands until the operation is complete.

The reset command may be written between the se-

quence cycles in a program command sequence before

programming begins. This resets the device to reading

array data (also applies to programming in Erase Sus-

pend mode). Once programming begins, however, the

device ignores reset commands until the operation is

complete.

The reset command may be written between the se-

quence cycles in an SILICON ID READ command se-

quence. Once in the SILICON ID READ mode, the reset

command must be written to return to reading array data

(also applies to SILICON ID READ during Erase Sus-

pend).

If Q5 goes high during a program or erase operation,

writing the reset command returns the device to read-

ing array data (also applies during Erase Suspend).

Pins A0 A1 Q15~Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code (Hex)

Manufacture code Word VIL VIL 00H 1 1 0 0 0 0 1 0 00C2H

Byte VIL VIL X 1 1 0 0 0 0 1 0 C2H

Device code Word VIH VIL 22H 1 1 0 1 1 0 1 0 22DAH

for KH29L V800CT Byte VIH VIL X 1 1 0 1 1 0 1 0 DAH

Device code Word VIH VIL 22H 0 1 0 1 1 0 1 1 225BH

for KH29L V800CB Byte VIH VIL X 0 1 0 1 1 0 1 1 5BH

Sector Protection Word X VIH X 0 0 0 0 0 0 0 1 01H (Protected)

Ver ification Byte X VIH X 0 0 0 0 0 0 0 0 00H (Unprotected)

TABLE 7. SILICON ID CODE

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KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

SECTOR ERASE COMMANDS

The Automatic Sector Erase does not require the de-

vice to be entirely pre-programmed prior to executing

the Automatic Sector Erase Set-up command and Au-

tomatic Sector Erase command. Upon executing the

Automatic Sector Erase command, the device will auto-

matically program and verify the sector(s) memory for

an all-zero data pattern. The system is not required to

provide any control or timing during these operations.

When the sector(s) is automatically verified to contain

an all-zero pattern, a self-timed sector erase and verify

begin. The erase and verify operations are complete

when either the data on Q7 is "1" at which time the de-

vice returns to the Read mode, or the data on Q6 stops

toggling for two consecutive read cycles at which time

the device returns to the Read mode. The system is not

required to provide any control or timing during these

operations.

When using the Automatic sector Erase algorithm, note

that the erase automatically terminates when adequate

erase margin has been achieved for the memory array

(no erase verification command is required). Sector

erase is a six-bus cycle operation. There are two "un-

lock" write cycles. These are followed by writing the

set-up command 80H. Two more "unlock" write cycles

are then followed by the sector erase command 30H.

The secto r address is latched on the falling edge o f WE#

or CE#, whichever happens later, while the command

(data) is latched on the rising edge of WE# or CE#,

whichever happens first. Sector addresses selected are

loaded into internal register on the sixth falling edge of

WE# or CE#, whichever happens later. Each succes-

sive secto r load cycle started by the falling edge of WE#

or CE#, whichever happens later must begin within 50us

fro m the rising edge of the preceding WE# or CE#, which-

ever happens first. Otherwise, the loading period ends

and internal auto secto r erase cycle starts . (Mo nito r Q3

to determine if the sector erase timer window is still open,

see section Q3, Sector Erase Timer.) Any command other

than Sector Erase (30H) or Erase Suspend (B0H) during

the time-out period resets the device to read mode.

ERASE SUSPEND

This command only has meaning while the state ma-

chine is executing Automatic Sector Erase operation,

and therefore will only be responded during Automatic

Secto r Erase operation. When the Erase Suspend Com-

mand is issued during the sector erase operation, the

device requires a maximum 20us to suspend the sector

erase o peration. However , when the Erase Suspend com-

mand is written during the sector erase time-out, the

device immediately terminates the time-out period and

suspends the erase operation. After this command has

been executed, the command register will initiate erase

suspend mode. The state machine will return to read

mo de automatically after suspend is ready . At this time,

state machine only allows the command register to re-

spond to Erase Resume, program data to , or read data

from any sector not selected for erasure.

The system can determine the status of the program

operation using the Q7 or Q6 status bits, just as in the

standard program operation. After an erase-suspend pro-

gram operation is complete, the system can once again

read array data within non-suspended sectors.

ERASE RESUME

This command will cause the command register to clear

the suspend state and return back to Sector Erase mode

but only if an Erase Suspend command was previously

issued. Erase Resume will not have any effect in all

other conditions. Another Erase Suspend command can

be written after the chip has resumed erasing. However ,

a delay time must be required after the erase resume

command (1.5ms for KH29LV800C T/B), if the system

implements an endless erase suspend/resume loop, or

the number of erase suspend/resume is exceeded 1024

times. The erase times will be expended if the erase

behavior always be suspended. (Please refer to MXIC

Flash Application Note for details.)

WORD/BYTE PROGRAM COMMAND SEQUENCE

The device programs one byte of data for each program

operation. The command sequence requires four bus

cycles, and is initiated by writing two unlock write cycles,

followed by the program set-up command. The program

address and data are written next, which in turn initiate

the Embedded Program algorithm. The system is not

required to provide further controls or timings. The device

automatically generates the program pulses and verifies

the programmed cell margin. Table 1 shows the address

and data requirements for the byte program command

sequence.

When the Embedded Program algorithm is complete,

the device then returns to reading array data and

addresses are no longer latched. The system can

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

WRITE OPERATION STATUS

The device provides several bits to determine the sta-

tus of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/

BY#. Table 10 and the following subsections describe

the functions of these bits. Q7, RY/BY#, and Q6 each

offer a method for determining whether a program or erase

operation is complete or in progress. These three bits

are discussed first.

Q7: Data# Polling

The D ATA# po lling bit, Q7, indicates to the ho st system

whether an Automatic Algorithm is in progress or com-

pleted, or whether the device is in Erase Suspend. DAT A#

po lling is valid after the rising edge o f the final WE# pulse

in the program or erase command sequence.

During the Automatic Program algorithm, the device out-

puts on Q7 the complement of the datum programmed

to Q7. This Q7 status also applies to pro gramming dur-

ing Erase Suspend. When the Auto matic Pro gram algo-

rithm is complete, the device outputs the datum pro-

gr ammed to Q7. The system must provide the pro gram

address to read valid status information on Q7. If a pro-

gram address falls within a pro tected secto r, DA TA# poll-

ing on Q7 is active for approximately 1 us, then the de-

vice returns to reading array data.

During the Auto matic Erase algorithm, DAT A# po lling pro-

duces a "0" on Q7. When the Automatic Erase algo-

determine the status of the program operation by using

Q7, Q6, or RY/BY#. See "Write Operation Status" for

information on these status bits.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the programming

operation. The Byte Program command sequence should

be reinitiated once the device has reset to reading array

data, to ensure data integrity.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed from a

"0" back to a "1". Attempting to do so may halt the

operation and set Q5 to "1" , or cause the DATA# polling

algorithm to indicate the operation was successful.

However, a succeeding read will show that the data is

still "0". Only erase operations can convert a "0" to a

"1".

rithm is co mplete, o r if the device enters the Erase Sus-

pend mo de, D ATA# polling produces a "1" o n Q7. This is

analogous to the complement/true datum out-put de-

scribed for the Automatic Program algorithm: the erase

function changes all the bits in a sector to "1" prior to

this, the device outputs the "complement," or "0". The

system must provide an address within any of the sec-

tors selected for erasure to read valid status information

on Q7.

After an erase command sequence is written, if all sec-

to rs selected fo r erasing are pro tected, DATA# polling on

Q7 is active for approximately 100 us, then the device

returns to reading array data. If not all selected sectors

are protected, the Automatic Erase algorithm erases the

unprotected sectors, and ignores the selected sectors

that are protected.

When the system detects Q7 has changed from the

complement to true data, it can read valid data at Q7-Q0

on the following read cycles. This is because Q7 may

change asynchronously with Q0-Q6 while Output En-

ab le (OE#) is asserted low .

RY/BY# : Ready/Busy

The RY/BY# is a dedicated, open-drain output pin that

indicates whether an Automatic Erase/Program algorithm

is in progress or complete. The RY/BY# status is valid

after the rising edge o f the final WE# o r CE#, whichever

happens first, in the command sequence. Since RY/BY#

is an open-drain output, several RY/BY# pins can be

tied to gether in par allel with a pull-up resisto r to VCC .

If the output is low (Busy), the device is actively erasing

or programming. (This includes programming in the Erase

Suspend mode.) If the output is high (Ready), the de-

vice is ready to read array data (including during the

Erase Suspend mode), or is in the standby mode.

Table 8 shows the outputs for RY/BY# during write op-

eration.

Q6:Toggle BIT I

To ggle Bit I o n Q6 indicates whether an A utomatic Pro-

gram or Erase algorithm is in progress or complete, or

whether the device has entered the Erase Suspend mode.

Toggle Bit I may be read at any address, and is valid

after the rising edge o f the final WE# o r CE#, whichever

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KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

During an Automatic Program or Erase algorithm opera-

tion, successive read cycles to any address cause Q6

to toggle. The system may use either OE# or CE# to

co ntrol the read cycles. When the o peratio n is complete,

Q6 stops toggling.

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, Q6 toggles and

returns to reading array data. If not all selected sectors

are protected, the Automatic Erase algorithm erases the

unprotected sectors, and ignores the selected sectors

that are protected.

The system can use Q6 and Q2 together to determine

whether a sector is actively erasing or is erase sus-

pended. When the device is actively erasing (that is, the

Automatic Erase algorithm is in progress), Q6 toggling.

When the device enters the Erase Suspend mode, Q6

stops toggling. However, the system must also use Q2

to determine which sectors are erasing or erase-sus-

pended. Alternatively, the system can use Q7.

If a program address f alls within a protected sector , Q6

toggles for approximately 2 us after the program com-

mand sequence is written, then returns to reading array

data.

Q6 also toggles during the erase-suspend-program mode,

and stops toggling once the Automatic Program algo-

rithm is complete.

Table 8 shows the outputs f or To ggle Bit I on Q6.

Q2:Toggle Bit II

The "To ggle Bit II" o n Q2, when used with Q6, indicates

whether a par ticular sector is actively erasing (that is,

the Automatic Erase algorithm is in process), or whether

that sector is erase-suspended. Toggle Bit II is valid

after the rising edge o f the final WE# o r CE#, whichever

happens first, in the command sequence.

Q2 toggles when the system reads at addresses within

those sectors that have been selected for erasure. (The

system may use either OE# or CE# to control the read

cycles.) But Q2 cannot distinguish whether the sector

is actively erasing or is erase-suspended. Q6, by com-

parison, indicates whether the device is actively eras-

ing, or is in Erase Suspend, but cannot distinguish which

sectors are selected for erasure. Thus , bo th status bits

are required for sectors and mode information. Refer to

Table 8 to co mpare outputs for Q2 and Q6.

Reading Toggle Bits Q6/ Q2

Whenever the system initially begins reading toggle bit

status, it must read Q7-Q0 at least twice in a row to

determine whether a to ggle bit is toggling. Typically , the

system would note and store the value of the toggle bit

after the first read. After the second read, the system

would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has

co mpleted the pro gram o r erase o peratio n. The system

can read array data on Q7-Q0 on the following read cycle.

How ever, if after the initial two read cycles , the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of Q5 is high

(see the section on Q5). If it is, the system should then

determine again whether the toggle bit is toggling, since

the toggle bit may have stopped toggling just as Q5 went

high. If the toggle bit is no longer toggling, the device

has successfully completed the program or erase op-

eration. If it is still toggling, the device did not complete

the operation successfully, and the system must write

the reset command to return to reading array data.

The remaining scenario is that system initially determines

that the toggle bit is toggling and Q5 has not gone high.

The system may continue to monitor the toggle bit and

Q5 through successive read cycles, determining the sta-

tus as described in the previous paragraph. Alterna-

tively, it may choose to perform other system tasks. In

this case, the system m ust start at the beginning o f the

algorithm when it returns to determine the status of the

operation.

Exceeded Timing Limits

Q5 will indicate if the program or erase time has ex-

ceeded the specified limits (internal pulse count). Under

these conditions Q5 will produce a "1". This time-out

condition indicates that the program or erase cycle was

not successfully completed. Data# Polling and Toggle

Bit are the only operating functions of the device under

this condition.

happens first, in the command sequence (prior to the

program or erase operation), and during the sector time-

out.

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

If this time-out condition occurs during sector erase op-

eratio n, it specifies that a particular secto r is bad and it

may no t be reused. However , other sectors are still func-

tional and may be used for the program or erase opera-

tion. The device must be reset to use other sectors.

Write the Reset command sequence to the device, and

then execute program o r erase command sequence. This

allows the system to continue to use the other active

sectors in the device.

If this time-out condition occurs during the chip erase

operation, it specifies that the entire chip is bad or com-

bination of sectors are bad.

Status Q7 Q6 Q5 Q3 Q2 RY/BY#

(Note1) (Note2)

Byte Program in Auto Program Algorithm Q7 # Toggle 0 N/A No 0

Toggle

Auto Erase Algorithm 0 Toggle 0 1 Toggle 0

Erase Suspend Read 1 No 0 N/A Toggle 1

(Erase Suspended Sector) Toggle

In Progress Erase Suspended Mode Erase Suspend Read Data Data Data Data Data 1

(Non-Erase Suspended Sector)

Erase Suspend Program Q7# Toggle 0 N/A N/A 0

Byte Program in Auto Program Algorithm Q7 # Toggle 1 N/A No 0

Toggle

Exceeded

Time Limits Auto Erase Algorithm 0 Toggle 1 1 Toggle 0

Erase Suspend Program Q7# Toggle 1 N/A N/A 0

TABLE 8. WRITE OPERATION STATUS

Note:

1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.

See "Q5:Exceeded Timing Limits " for more information.

If this time-out condition occurs during the byte program-

ming operation, it specifies that the entire sector con-

taining that byte is bad and this sector may not be re-

used, (other sectors are still functional and can be re-

used).

The time-out condition will not appear if a user tries to

program a non blank location without erasing. Please

note that this is not a device failure condition since the

device was incorrectly used.

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

POWER SUPPLY DECOUPLING

In order to reduce power switching effect, each device

should have a 0.1uF ceramic capacitor connected be-

tween its VCC and GND .

POWER-UP SEQUENCE

The KH29L V800C T/B powers up in the Read only mode.

In addition, the memory contents may only be altered

after successful completion of the predefined command

sequences.

TEMPORARY SECTOR UNPROTECTED

This feature allows temporary unprotected of previously

pro tected secto r to change data in-system. The Tempo-

rary Sector Unprotected mode is activated by setting

the RESET# pin to VID(11.5V -12.5V). During this mode,

formerly protected sectors can be programmed or erased

as un-protected sector. Once VID is remove from the

RESET# pin, all the previously protected sectors are

protected again.

SECTOR PROTECTION

The KH29LV800C T/B features hardware secto r pro tec-

tion. This feature will disable both program and erase

operations for these sectors protected. To activate this

mode, the programming equipment must force VID on

address pin A9 and OE# (suggest VID = 12V). Pro-

gramming of the protection circuitry begins on the falling

edge of the WE# pulse and is ter minated on the r ising

edge. Please refer to sector protect algorithm and wave-

form.

To verify pro gramming o f the protection circuitry , the pro-

gramming equipment must fo rce VID o n address pin A9

( with CE# and OE# at VIL and WE# at VIH). When

A1=VIH, A0=VIL, A6=VIL, it will produce a logical "1"

code at de vice output Q0 f or a pro tected sector . Other-

wise the device will produce 00H for the unprotected

sector. In this mo d e , the addresses , except f or A1, are

do n't care. Address locations with A1 = VIL are reserved

to read manufacturer and device codes. (Read Silicon

ID)

It is also possible to determine if the sector is protected

in the system by writing a Read Silicon ID command.

Sector Erase Timer

After the completion of the initial sector erase command

sequence, the sector erase time-out will begin. Q3 will

remain low until the time-o ut is complete. DATA# po lling

and T o ggle Bit are valid after the initial secto r erase co m-

mand sequence.

If DATA# polling or the Toggle Bit indicates the device

has been written with a valid erase command, Q3 may

be used to determine if the sector erase timer window is

still open. If Q3 is high ("1") the internally controlled

erase cycle has begun; attempts to write subsequent

commands to the device will be ignored until the erase

o peratio n is co mpleted as indicated by DATA# po lling o r

Toggle Bit. If Q3 is low ("0"), the device will accept

additional sector erase commands. To insure the com-

mand has been accepted, the system software should

check the status of Q3 prior to and following each sub-

sequent sector erase command. If Q3 were high on the

second status check, the command may not have been

accepted.

DATA PROTECTION

The KH29LV800C T/B is designed to offer protection

against accidental erasure or programming caused by

spurious system level signals that may exist during power

transition. During power up the device automatically re-

sets the state machine in the Read mode. In addition,

with its control register architecture, alteration of the

memory contents only occurs after successful comple-

tion of specific command sequences. The device also

incorpo rates several features to prevent inadvertent write

cycles resulting from VCC power-up and power-down tran-

sition or system noise.

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns(typical) on CE# or WE#

will not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE# = VIL,

CE# = VIH or WE# = VIH. To initiate a write cycle CE#

and WE# must be a logical zero while OE# is a logical

one.

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

P erfo rming a read o peratio n with A1=VIH, it will produce

a logical "1" at Q0 for the protected sector.

CHIP UNPROTECTED

The KH29L V800C T/B also features the chip unpro tected

mode, so that all sectors are unpro tected after chip un-

pro tected is completed to incorporate any changes in the

code. It is recommended to protect all sectors before

activating chip unprotected mo de.

To activate this mode, the pro gramming equipment must

force VID on control pin OE# and address pin A9. The

CE# pins must be set at VIL. Pins A6 must be set to

VIH. Refer to chip unprotected algorithm and waveform

for the chip unprotected algorithm. The unprotection

mechanism begins o n the falling edge o f the WE# pulse

and is terminated on the rising edge.

It is also possible to determine if the chip is unprotected

in the system by writing the Read Silicon ID command.

P erfo rming a read o peratio n with A1=VIH, it will produce

00H at data o utputs (Q0-Q7) f o r an unpro tected secto r .

It is noted that all sectors are unprotected after the chip

unprotected algorithm is completed.

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

ABSOLUTE MAXIMUM RATINGS

Storage T emperature

Plastic Packages . . . . . . . . . . . . . ..... -65oC to +150oC

Ambient Temperature

with Power Applied. . . . . . . . . . . . . .... -65oC to +125oC

Vo ltage with Respect to Gro und

VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V

A9, OE#, and

RESET# (Note 2) . . . . . . . . . . . ....-0.5 V to +12.5 V

All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is -0.5 V.

During voltage transitions, input or I/O pins may over-

shoot VSS to -2.0 V for periods of up to 20 ns. See

Figure 6. Maximum DC voltage on input or I/O pins is

VCC +0.5 V. During voltage transitions, input or I/O

pins ma y ov ershoo t to VCC +2.0 V f or periods up to

20 ns.

2. Minimum DC input voltage on pins A9, OE#, and

RESET# is -0.5 V. During vo ltage transitio ns, A9, OE#,

and RESET# may overshoot VSS to -2.0 V for peri-

ods of up to 20 ns. See Figure 6. Maximum DC input

voltage o n pin A9 is +12.5 V which ma y overshoot to

14.0 V for periods up to 20 ns.

3. No mo re than one output may be shorted to gro und at

a time. Duration of the short circuit should not be

greater than one second.

Stresses above those listed under "Absolute Maximum

Ratings" may cause permanent damage to the device.

This is a stress rating only; functional operation of the

device at these or any other conditions above those in-

dicated in the operational sections of this data sheet is

not implied. Exposure of the device to absolute maxi-

mum rating conditions for extended periods may affect

device reliability.

OPERATING RATINGS

Commercial (C) Devices

Ambient Temperature (TA ) . . . . . . . . . . . . 0°C to +70°C

VCC Supply Voltages

VCC for full voltage range. . . . . . . . . . . +2.7 V to 3.6 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

CAPACITANCE TA = 25oC, f = 1.0 MHz

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

CIN1 Input Capacitance 8 pF VIN = 0V

CIN2 Control Pin Capacitance 12 pF VIN = 0V

COUT Output Capacitance 12 pF VOUT = 0V

NOTES:

1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.

VIL min. = -2.0V for pulse width is equal to or less than 20 ns.

2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns

If VIH is over the specified maxim um v alue, read operation cannot be guar anteed.

3. Automatic sleep mode enable the low power mode when addresses remain stable for tACC +30ns.

TABLE 9. DC CHARACTERISTICS TA = -40oC to 85oC, VCC = 2.7V~3.6V

Symbol PARAMETER MIN. TYP MAX. UNIT CONDITIONS

ILI Input Leakage Current ± 1 uA VIN = VSS to VCC

ILIT A9 Input Leakage Current 3 5 uA VCC=VCC max; A9=12.5V

ILO Output Leakage Current ± 1 uA VOUT = VSS to VCC, VCC=VCC max

ICC1 VCC Active Read Current 7 1 2 mA CE#=VIL, OE#=VIH @5MHz

2 4 mA (Byte Mode) @1MHz

7 12 mA CE#=VIL, OE#=VIH @5MHz

2 4 mA (Word Mode) @1MHz

ICC2 VCC Active write Current 1 5 3 0 mA CE#=VIL, OE#=VIH

ICC3 VCC Standby Current 0.2 5 uA CE#; RESET#=VCC ± 0.3V

ICC4 VCC Standby Current 0.2 5 uA RESET#=VSS ± 0.3V

During Reset

ICC5 Automatic sleep mode 0.2 5 uA VIH=VCC ± 0.3V; VIL=VSS ± 0.3V

VIL Input Low Voltage(Note 1) -0.5 0.8 V

VIH Input High Voltage 0.7xVCC VCC+ 0.3 V

VID Voltage for Automatic

Select and Temporary 11.5 12.5 V VCC=3.3V

Sector Unprotected

VOL Output Low Voltage 0.45 V IOL = 4.0mA, VCC= VCC min

VOH1 Output High Voltage(TTL) 0.85xVCC IOH = -2mA, VCC=VCC min

VOH2 Output High Voltage VCC-0.4 IOH = -100uA, VCC min

(CMOS)

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

NOTES:

1. Not 100% tested.

2. tDF is defined as the time at which the output achieves

the open circuit condition and data is no longer driven.

TEST CONDITIONS:

•Input pulse levels: 0V/3.0V.

•Input rise and fall times is equal to or less than 5ns.

•Output load: 1 TTL gate + 100pF (Including scope and

jig), for 29LV800C T/B-90. 1 TTL gate + 30pF (Includ-

ing scope and jig) for 29LV800C T/B-70

•Reference levels for measuring timing: 1.5V.

AC CHARACTERISTICS

TABLE 10. READ OPERATIONS

29LV800C-70 29LV800C-90

SYMBOL PARAMETER MIN. MAX. MIN. MAX. UNIT CONDITIONS

tRC Read Cycle Time (Note 1) 70 9 0 ns

tACC Address to Output Delay 7 0 9 0 ns CE#=OE#=VIL

tCE CE# to Output Delay 7 0 90 n s OE#=VIL

tOE OE# to Output Delay 30 35 ns CE#=VIL

tDF OE# High to Output Float (Note 2) 0 25 0 30 ns CE#=VIL

tOEH Output Enable Read 0 0 ns

Hold Time To ggle and 10 10 ns

Data# Polling

tOH Address to Output hold 0 0 ns CE#=OE#=VIL

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

SWITCHING TEST CIRCUITS

SWITCHING TEST WAVEFORMS

TEST POINTS

3.0V

AC TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0".

Input pulse rise and fall times are < 5ns.

OUTPUT

INPUT

DEVICE UNDER

TEST

DIODES=IN3064

OR EQUIVALENT

CL 6.2K ohm

2.7K ohm +3.3V

CL=100pF Including jig capacitance

CL=30pF for KH29LV800C T/B-70

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

FIGURE 1. READ TIMING WAVEFORMS

Addresses

CE#

OE#

tACC

WE#

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VIH

VIL

HIGH Z HIGH Z

D ATA V alid

tOE

tOEH tDF

tCE

tACC

tRC

Outputs

RESET#

tOH

ADD V alid

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

AC CHARACTERISTICS

TABLE 11. Erase/Program Operations

Parameter Speed Options

Std. Description 70 90 Unit

tWC Write Cycle Time (Note 1) Mi n 7 0 9 0 ns

tAS Address Setup Time Min 0 ns

tAH Address Hold Time Min 4 5 ns

tDS Data Setup Time MIn 3 5 4 5 ns

tDH Data Hold Time Min 0 ns

tOES Output Enable Setup Time Min 0 ns

tGHWL Read Recovery Time Before Write Min 0 ns

(OE# High to WE# Low)

tCS CE# Setup Time Min 0 ns

tCH CE# Hold Time Min 0 ns

tWP Write Pulse Width Min 3 5 ns

tWPH Write Pulse Width High Min 3 0 ns

tWHWH1 Programming Operation (Note 2) Typ 9/11 us

(Byte/Word program time)

tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec

tVCS VCC Setup Time (Note 1) Min 5 0 us

tRB Recovery Time from RY/BY# Mi n 0 ns

tBUSY Program/Erase Valid to RY/BY# Delay Max 9 0 ns

tWPP1 Write Pulse Width for Sector Protect Mi n 1 0 0 ns

(A9, OE# Control) Typ 10 us

tWPP2 Write Pulse Width for Chip Unprotected Min 1 00 ns

(A9, OE# Control) Typ 12 ms

tBAL Sector Address Load Time Max 5 0 us

NOTES:

1. Not 100% tested.

2. See the "Erase and Programming P erf ormance" sectio n f or more inf ormation.

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

Parameter Speed Options

Std. Description 70 90 Unit

tWC Write Cycle Time (No te 1) Min 7 0 9 0 ns

tAS Address Setup Time Min 0 ns

tAH Address Hold Time Min 4 5 ns

tDS Data Setup Time Min 3 5 4 5 ns

tDH Data Ho ld Time Min 0 ns

tOES Output Enable Setup Time Min 0 ns

tGHEL Read Reco very Time Befo re Write Min 0 ns

tWS WE# Setup Time Min 0 ns

tWH WE# Ho ld Time Min 0 ns

tCP CE# Pulse Width Min 3 5 ns

tCPH CE# Pulse Width High Min 3 0 ns

tWHWH1 Programming Byte Typ 9 us

Operation(note2) Word Typ 11 us

tWHWH2 Secto r Erase Operation (note2) Typ 0.7 sec

NOTE:

1. Not 100% tested.

2. See the "Erase and Programming P erf ormance" sectio n f or more inf ormation.

AC CHARACTERISTICS TA = -40oC to 85oC, VCC = 2.7V~3.6V

TABLE 12. Alternate CE# Controlled Erase/Program Operations

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

FIGURE 2. COMMAND WRITE TIMING WAVEFORM

Addresses

CE#

OE#

WE#

DIN

tDS

tAH

Data

tDH

tCS tCH

tCWC

tWPH

tWP

tOES

tAS

VCC

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

ADD V alid

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

AUTOMATIC PROGRAMMING TIMING WAVEFORM

FIGURE 3. AUTOMATIC PROGRAMMING TIMING WAVEFORM

One byte data is programmed. Verify in fast algorithm

and additional verification by external control are not re-

quired because these operations are executed automati-

cally by internal control circuit. Programming comple-

tion can be verified by DA TA# polling and toggle bit check-

ing after auto matic programming starts. Device outputs

DATA# during programming and DATA# after program-

ming on Q7. (Q6 is for toggle bit; see toggle bit, DATA#

polling, timing waveform)

tWC

Address

OE#

CE#

A0h

555h PA

PD Status DOUT

PA PA

NOTES:

1.PA=Program Address, PD=Program Data, DOUT is the true data the program address

tAS

tAH

tGHWL

tCH

tWP

tDS tDH

tWHWH1

Read Status Data (last two cycle)Program Command Sequence(last two cycle)

tBUSY tRB

tCS tWPH

tVCS

WE#

Data

RY/BY#

VCC

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

FIGURE 4. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Program Data/Address

Write Data A0H Address 555H

YES

Verify Word Ok ?

YES

Auto Program Completed

Data Poll

from system

Increment

Address

Last Address ?

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

FIGURE 5. CE# CONTROLLED PROGRAM TIMING WAVEFORM

tWC

tWH

tGHEL

tWHWH1 or 2

tCP

Address

WE#

OE#

CE#

Data DQ7

Data Polling

DOUT

RESET#

RY/BY#

NOTES:

1.PA=Program Address, PD=Program Data, DOUT=Data Out, DQ7=complement of data written to device.

2.Figure indicates the last two bus cycles of the command sequence.

tAH

tAS

PA for program

SA for sector erase

555 for chip erase

tRH

tDH

tDS

tWS

A0 for program

55 for erase

tCPH

tBUSY

PD for program

30 for sector erase

10 for chip erase

555 for program

2AA for erase

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

All data in chip are erased. External erase verification is

not required because data is verified automatically by

internal control circuit. Erasure completion can be veri-

fied by D ATA# polling and toggle bit checking after auto-

matic erase starts. Device outputs 0 during erasure

and 1 after erasure on Q7. (Q6 is for toggle bit; see toggle

bit, D ATA# po lling, timing wa vef o rm)

FIGURE 6. AUTOMATIC CHIP ERASE TIMING WAVEFORM

AUTOMATIC CHIP ERASE TIMING WAVEFORM

tWC

Address

OE#

CE#

55h

2AAh 555h

10h

Progress Complete

VA VA

NOTES:

SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").

tAS

tAH

tGHWL

tCH

tWP

tDS tDH

tWHWH2

Read Status Data Erase Command Sequence(last two cycle)

tBUSY tRB

tCS tWPH

tVCS

WE#

Data

RY/BY#

VCC

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

FIGURE 7. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data AAH Address 555H

Write Data 80H Address 555H

YES

NO Data=FFh ?

Write Data 10H Address 555H

Write Data 55H Address 2AAH

Data Pall from System

Auto Chip Erase Completed

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

FIGURE 8. AUTOMATIC SECTOR ERASE TIMING WAVEFORM

Sector indicated by A12 to A18 are erased. External

erase verify is not required because data are verified

automatically by internal control circuit. Erasure comple-

tio n can be verified by DA TA# polling and toggle bit check-

ing after automatic erase starts. De vice outputs 0 dur-

ing erasure and 1 after erasure on Q7. (Q6 is for toggle

bit; see toggle bit, DATA# po lling, timing w av ef orm)

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

tWC

Address

OE#

CE#

55h

2AAh Sector

Address 1

Sector

Address 0

30h

Progress Complete

VA VA

30h

NOTES:

SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").

Sector

Address n

tAS

tAH

tBAL

tGHWL

tCH

tWP

tDS tDH

tWHWH2

Read Status Data Erase Command Sequence(last two cycle)

tBUSY tRB

tCS tWPH

tVCS

WE#

Data

RY/BY#

VCC

30h

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

FIGURE 9. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data AAH Address 555H

Write Data 80H Address 555H

Write Data 30H Sector Address

Write Data 55H Address 2AAH

Data Poll from System

Auto Sector Erase Completed

Last Sector

to Erase

YES

Data=FFh

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

FIGURE 10. ERASE SUSPEND/ERASE RESUME FLOWCHART

Note:

1. If the system implements an endless erase suspend/resume loop, or the number of erase suspend/resume is

exceeded 1024 times, then the delay time must be put into consideration.

2. Delay timing: 1.5ms f o r KH29LV800C T/B .

START

Write Data B0H

Toggle Bit checking Q6

not toggled

ERASE SUSPEND

YES

Write Data 30H

Delay Time(Note 2)

Continue Erase

Reading or

Programming End

Read Array or

Program

Another

Erase Suspend ? NO

YES

ERASE RESUME

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

FIGURE 11. IN-SYSTEM SECTOR PROTECT/UNPRO TECTED TIMING W A VEFORM (RESET# Control)

Sector Protect =150us

Chip Unprotect =15ms

1us

VID

VIH

Data

SA, A6

A1, A0

CE#

WE#

OE#

Valid* Valid*

Status

Valid*

Sector Protect or Chip Unprotect

40h60h60h

Verify

RESET#

Note: When sector protect, A6=0, A1=1, A0=0. When chip unprotect, A6=1, A1=1, A0=0.

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

FIGURE 12. SECTOR PROTECT TIMING WAVEFORM (A9, OE# Control)

tOE

Data

OE#

WE#

12V

CE#

tOESP

tWPP 1

tVLHT

Verify

01H F0H

A18-A12 Sector Address

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

FIGURE 13. SECTOR PROTECTION ALGORITHM (A9, OE# Control)

START

Set Up Sector Addr

PLSCNT=1

Sector Protection

Complete

Data=01H?

Yes

OE#=VID, A9=VID, CE#=VIL

A6=VIL

Activate WE# Pulse

Time Out 150us

Set WE#=VIH, CE#=OE#=VIL

A9 should remain VID

Read from Sector

Addr=SA, A1=1

Protect Another

Sector?

Remove VID from A9

Write Reset Command

Device Failed

PLSCNT=32?

Yes

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

FIGURE 14. IN-SYSTEM SECTOR PROTECTION ALGORITHM WITH RESET#=VID

START

PLSCNT=1

First Write

Cycle=60H

Yes

RESET#=VID

Wait 1us

Set up sector address

Write 60H to sector address

with A6=0, A1=1, A0=0

Verify sector protect :

write 40H with A6=0,

A1=1, A0=0

Wait 150us

Increment PLSCNT

Read from sector address

Remove VID from RESET#

Temporary Sector

Unprotect Mode

Reset PLSCNT=1

Data=01H

Yes

PLSCNT=25?

Protect another

sector?

Write reset command

Sector protect complete

Device failed

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

FIGURE 15. IN-SYSTEM CHIP UNPROTECTION ALGORITHM WITH RESET#=VID

START

PLSCNT=1

First Write

Cycle=60H ?

Yes

RESET#=VID

Wait 1us

Set up first sector address

Chip unprotect :

write 60H with

A6=1, A1=1, A0=0

Verify chip unprotect

write 40H to sector address

with A6=1, A1=1, A0=0

Wait 50ms

Increment PLSCNT

Read from sector address

with A6=1, A1=1, A0=0

Remove VID from RESET#

Temporary Sector

Unprotect Mode

Set up next sector address

All sector

protected?

Yes

Data=00H

Yes

No Protect all sectors

PLSCNT=1000?

Last sector

verified?

Write reset command

Chip unprotect complete

Device failed

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

FIGURE 16. TIMING WAVEFORM FOR CHIP UNPROTECTION (A9, OE# Control)

Notes: tVLHT (Vo ltage transition time)=4us min.

tWPP1 (Write pulse width for secto r pro tect)=100ns min, 10us(Typ .)

tWPP2 (Write pulse width for chip unpro tected)=100ns min, 12ms(Typ.)

tOESP (OE# setup time to WE# active)=4us min.

tOE

Data

OE#

WE#

12V

Vcc 3V

12V

Vcc 3V

CE#

tOESP

tWPP 2

tVLHT

Verify

00H

Sector Address

A18-A12

F0H

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

FIGURE 17. CHIP UNPROTECTION ALGORITHM (A9, OE# Control)

START

Protect All Sectors

PLSCNT=1

Chip Unprotect

Complete

Data=00H?

Yes

Set OE#=A9=VID

CE#=VIL,A6=1

Activate WE# Pulse

Time Out 50ms

Set OE#=CE#=VIL

A9=VID,A1=1

Set Up First Sector Addr

All sectors have

been verified?

Remove VID from A9

Write Reset Command

Device Failed

PLSCNT=1000?

Increment

PLSCNT

Read Data from Device

Yes

Increment

Sector Addr

* It is recommended before unprotect whole chip, all sectors should be protected in advance.

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

FIGURE 18. DATA# POLLING ALGORITHM

WRITE OPERATION STATUS

Read Q7~Q0

Add.=VA(1)

Read Q7~Q0

Add.=VA

Start

Q7 = Data ?

Q5 = 1 ?

Q7 = Data ?

FAIL Pass

(2)

Yes

NOTE : 1.VA=Valid address for programming

2.Q7 should be re-checked even Q5="1" because Q7 may change

simultaneously with Q5.

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

FIGURE 19. TOGGLE BIT ALGORITHM

Read Q7-Q0

Q5= 1?

Read Q7~Q0 Twice

Program/Erase Operation

Not Complete,Write

Reset Command

Program/Erase

operation Complete

Toggle bit Q6=

Toggle?

Toggle Bit Q6 =

Toggle ? NO

(Note 1)

(Note 1,2)

YES

Note:1.Read toggle bit twice to determine whether or not it is toggling.

2. Recheck toggle bit because it may stop toggling as Q5 change to "1".

Start

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

FIGURE 20. DATA# Polling Timings (During Automatic Algorithms)

RY/BY#

NOTES:

1. VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle.

2. CE# must be toggled when DATA# polling.

tDF

tCE

tACC

tRC

tCH

tOE

tOEH

tOH

tBUSY

Address

CE#

OE#

WE#

DQ7

Q0-Q6

Status Data Status Data

Complement Complement Valid DataTrue

VAVAVA

High Z

Valid DataTrue

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

FIGURE 21. Toggle Bit Timings (During Automatic Algorithms)

NOTES:

1. VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle,

and array data read cycle.

2. CE# must be toggled when toggle bit toggling.

tDF

tCE

tACC

tRC

tCH

tOE

tOEH

tBUSY

High Z

tOH

Address

CE#

OE#

WE#

Q6/Q2

RY/BY#

Valid Status

(first read)

Valid Status

(second read) (stops toggling)

Valid Data

VA VA

Valid Data

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

FIGURE 22. RESET# TIMING WAVEFORM

TABLE 13. AC CHARACTERISTICS

Parameter Std Description T est Setup All Speed Options Unit

tREAD Y1 RESET# PIN Low (During Automatic Algorithms) MAX 2 0 us

to Read o r Write (See No te)

tREADY2 RESET# PIN Low (NOT During Auto matic MAX 500 ns

Algo rithms) to Read o r Write (See No te)

tRP RESET# Pulse Width (During A uto matic Algo rithms) MIN 5 00 ns

tRH RESET# High Time Befo re Read (See No te) MIN 5 0 ns

tRB R Y/BY# Recovery Time (to CE#, OE# go lo w) MIN 0 ns

Note: Not 100% tested

tRH

tRB

tREADY1

tRP

tREADY2

RY/BY#

CE#, OE#

RESET#

Reset Timing NOT during Automatic Algorithms

Reset Timing during Automatic Algorithms

RY/BY#

CE#, OE#

RESET#

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

FIGURE 23. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from byte

mode to word mode)

AC CHARACTERISTICS

TABLE 14. WORD/BYTE CONFIGURATION (BYTE#)

Parameter Description Speed OptionsUnit JEDEC

Std -55 -70 -90

tELFL/tELFH CE# to BYTE# Switching Low o r High Max 5 ns

tFLQZ BYTE# Switching Low to Output HIGH Z Max 2 5 25 3 0 ns

tFHQV BYTE# Switching High to Output Active Mi n 5 5 70 90 ns

tFHQV

tELFH

DOUT

(Q0-Q7) DOUT

(Q0-Q14)

VA DOUT

(Q15)

CE#

OE#

BYTE#

Q0~Q14

Q15/A-1

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

FIGURE 24. BYTE# TIMING WA VEFORM FOR READ OPERATIONS (BYTE# switching from w or d

mode to byte mode)

FIGURE 25. BYTE# TIMING WAVEFORM FOR PROGRAM OPERATIONS

tFLQZ

tELFH

DOUT

(Q0-Q7)

DOUT

(Q0-Q14)

DOUT

(Q15)

CE#

OE#

BYTE#

Q0~Q14

Q15/A-1

tAS tAH

The falling edge of the last WE# signal

CE#

WE#

BYTE#

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

TABLE 15. TEMPORARY SECTOR UNPROTECTED

Parameter Std. Description Test Setup All Speed Options Unit

tVI DR VID Rise and F all Time (See No te) Mi n 5 0 0 ns

tRSP RESET# Setup Time fo r Tempo rary Secto r Unpro tected Mi n 4 us

Note:

Not 100% tested

FIGURE 26. TEMPORARY SECTOR UNPROTECTED TIMING DIAGRAM

FIGURE 27. Q6 vs Q2 for Erase and Erase Suspend Operations

RESET#

CE#

WE#

RY/BY#

tVIDR tVIDR

Program or Erase Command Sequence

12V

0 or Vcc 0 or Vcc

tRSP

NOTES:

The system can use OE or CE to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended

WE#

Enter Embedded

Erasing Erase

Suspend Enter Erase

Suspend Program

Erase

Suspend

Program

Erase Suspend

Read Erase

Erase

Resume

Erase

Complete

Erase

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

FIGURE 28. TEMPORARY SECTOR UNPROTECTED ALGORITHM

Start

RESET# = VID (Note 1)

Perform Erase or Program Operation

RESET# = VIH

Temporary Sector Unprotect Completed(Note 2)

Operation Completed

2. All previously protected sectors are protected again.

Note : 1. All protected sectors are temporary unprotected.

VID=11.5V~12.5V

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

FIGURE 29. ID CODE READ TIMING WAVEFORM

tACC

tCE

tACC

tOE

tOH tOH

tDF

DATA OUT

C2H/00C2H DAH/5BH (Byte)

22DAH/225BH (Word)

VID

VIH

VIL

ADD

A2-A8

A10-A18

CE#

OE#

WE#

ADD

DATA OUT

DATA

Q0-Q15

VCC

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

RECOMMENDED OPERATING CONDITIONS

At Device P ower-Up

AC timing illustrated in Figure A is reco mmended f or the supply voltages and the co ntro l signals at device power-up .

If the timing in the figure is igno red, the device ma y not operate correctly.

Figure A. AC Timing at Device P ower-Up

No tes :

1. Sampled, no t 100% tested.

2. This specificatio n is applied for no t o nly the device pow er-up but also the no rmal o peratio ns.

Symbol Parameter Notes Min. Max. Unit

tVR VCC Rise Time 1 2 0 500000 us/V

tR Input Signal Rise Time 1, 2 2 0 us/V

tF Input Signal Fall Time 1, 2 2 0 us/V

VCC

ADDRESS

CE#

WE#

OE#

DATA

tVR

tACC

tR or tF

tCE

VCC(min)

GND

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH High Z

VOL

WP#/ACC VIH

VIL

Valid

Ouput

Valid

Address

tR or tF

tOE

tF tR

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

LIMITS

PARAMETER MIN. TYP.(2) MAX.(3) UNITS

Sector Erase Time 0.7 1 5 s ec

Chip Erase Time 1 4 sec

Byte Programming Time 9 30 0 us

Word Programming Time 11 360 us

Chip Programming Time Byte Mode 9 27 sec

Word Mode 5.8 17 sec

Erase/Program Cycles 100,000 Cycles

TABLE 16. ERASE AND PROGRAMMING PERFORMANCE (1)

Note: 1. Not 100% Tested, Excludes external system le vel ov er head.

2. Typical values measured at 25°C, 3V .

3. Maximum values measured at 25°C , 2.7V.

MIN. MAX.

Input Voltage with respect to GND on OE#, RESET#, A9 -1.0V 12.5V

Input Voltage with respect to GND on all power pins, Address pins, CE# and WE# -1.0V VCC + 1.0V

Input Voltage with respect to GND on all I/O pins -1.0V VCC + 1.0V

Current -100mA +100mA

Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.

TABLE 17. LATCH-UP CHARACTERISTICS

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

ORDERING INFORMATION

P ART NO. ACCESS OPERA TING STANDBY PACKA GE Remark

TIME (ns) Current MAX. (mA) Current MAX. (uA)

KH29LV800CTTC-70 70 30 5 48 Pin TSOP

(Normal T ype)

KH29LV800CBTC-70 7 0 3 0 5 48 Pin TSOP

(Normal T ype)

KH29LV800CTTC-90 90 30 5 48 Pin TSOP

(Normal T ype)

KH29LV800CBTC-90 9 0 3 0 5 48 Pin TSOP

(Normal T ype)

KH29LV800CTTC-70G 7 0 3 0 5 48 Pin TSOP PB free

(Normal T ype)

KH29LV800CBTC-70G 7 0 3 0 5 48 Pin TSOP PB free

(Normal T ype)

KH29LV800CTTC-90G 9 0 3 0 5 48 Pin TSOP PB free

(Normal T ype)

KH29LV800CBTC-90G 9 0 3 0 5 48 Pin TSOP PB free

(Normal T ype)

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

PART NAME DESCRIPTION

KH 29 LV 70C T T C G

OPTION:

G: Lead-free package

blank: normal

SPEED:

70: 70ns

90: 90ns

TEMPERATURE RANGE:

C: Commercial (0˚C to 70˚C)

PACKAGE:

T: TSOP

BOOT BLOCK TYPE:

T: Top Boot

B: Bottom Boot

REVISION:

DENSITY & MODE:

800: 8M, x8/x16 Boot Block

TYPE:

L, LV: 3V

DEVICE:

29:Flash

800

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

PACKAGE INFORMATION

P/N:PM1222

KH29LV800C T/B

REV. 1.2, DEC. 09, 2005

REVISION HISTORY

Revision No. Description Page Date

1. 1 1. Modified "Package Information" P58 JUL/01/2005

1.2 1. Modified content error P47,48,54 DEC/09/2005

2. Added descriptio n abo ut Pb-free devices are RoHS Co mpliant P1

KH29LV800C T/B

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