ASIC
17
Asynchronous Inputs
A problem arises at the interface between a synchronous
circuit and an external asynchronous input. At the flip-flop
which captures the asynchronous input, there is a probabil-
ity of metastability occurring. This section suggests some
circuits which capture an external asynchronous input with
a minimal risk of metastability.
Note: For large designs, inter-block communication is similar to
external asynchronous interfacing.
Non-recommended Circuits
Not recommended is any circuit using a complicated feed-
back loop to capture an asynchronous input. The function
of such circuits is obscure, and they run the risk of creating
more problems than they solve. They are also very sensi-
tive to noise, and their function can be altered by place-
ment and routing delays.
Recommended Circuits
There are two recommended approaches to the problem of
capturing an asynchronous input signal:
1. Two (or more) D-type registers in series to reduce
the probability of metastability (Figure 24).
2. Use an asynchronous handshake circuit (Figure
25).
In all cases, the asynchronous event is a rising edge on the
d (external) input to the first flip-flop. The pulse width of this
signal is indeterminate, but is at least one clock cycle. The
asynchronous event may occur simultaneously with a rising
clock edge.
A general point which applies to all situations where meta-
stability is possible is as follows:
•The rise and fall times of both the clock and data signals
are significant: fast edges reduce the probability of
metastability.
Two D-type flip-flops in series to capture an
asynchronous input
If the first flip-flop goes into a metastable state, the proba-
bility that it will still be in that state at the next rising clock
edge is low. Should this, however, occur, the metastable
state is propagated to the d (internal) output and into the
rest of the circuit. The probability of this situation is reduced
by additional flip-flops in series.
Figure 24. Two D-type flip-flops in series to capture an asynchronous input
The common characteristics of circuits of this nature are as
follows:
•In order for the d (external) rising edge to cause a rising
edge on the d (internal) output, there must be at least
one clock cycle between asynchronous inputs during
which d (external) is low. This reduces the maximum
frequency for the recognition of external events to half
that of the internal clock frequency.
•If the flip-flop which receives the asynchronous d
(external) rising edge settles (after a period of
metastability) into the state with q = 0, the external input
is lost unless it persists beyond the next rising clock
edge.
•Metastability can be caused by a rising or a falling edge
on the d (external) input.
DQ
CK QB
DQ
CK QB