L9341 (R) QUAD LOW SIDE DRIVER DU/DT AND DI/DT CONTROL PWM CONTROLLED OUTPUT CURRENT SHORT CURRENT PROTECTION AND DIAGNOSTIC INTEGRATED FLYBACK DIODE UNDERVOLTAGE SHUTDOWN OVERVOLTAGE AND UNDERVOLTAGE DIAGNOSTIC OVERTEMPERATURE DIAGNOSTIC MULTIPOWER BCD TECHNOLOGY Multiwatt 15 c u d DESCRIPTION The L9341 is a monolithic integrated circuit realized in Multipower BCD-II mixed technology. The driver is intended for inductive loads in synchronous PWM applications, especially for valve driv- e t le so VCC UNDERVOLTAGE SHUTDOWN 4 (s) ct I cc 10uF u d o r P e t e l o 10nF s b O b O DIAGNOSTIC Vs Is 220nF VS 7 C BAT V flyth COMP2 OUT1 2 I OUT1 10nF di / dt & du / dt CONTROL C O1 I outs DRIVER SHORT CURRENT PROTECTION 12 R ext 12.4k RES1 CHANNEL 1 9 RES2 BIAS SERIAL INTERFACE & PWM CONTROLL 10 CS 3 OUT2 CHANNEL 2 1 I C SCLK 11 CHANNEL 3 5 SDO OUT2 O2 10nF OUT3 SDI 15 I OUT3 C O3 13 10nF OSC OUT4 6 CHANNEL 4 C OSC GND 14 I OUT4 C O4 8 September 2003 D BAT COMP1 Voffth THERMAL FLAG REXT o r P ers. The output voltage and current rise and fall slopes du/dt and di/dt are controlled. BLOCK & APPLICATION DIAGRAM Vcc ) s t( ORDERING NUMBERS: L9341V L9341H 10nF I GND 1/10 L9341 PIN CONNECTION (Top view) c u d ABSOLUTE MAXIMUM RATINGS Symbol VCC VS Vspmax Vst Vin Vout Iout Parameter e t le VCC Voltage Range VS Voltage Range VS Voltage Range for t 400ms Schaffner Transient Pulses on VS o s b O - Input Voltage Range for SDI; SCLK;CS;RES1;RES2 Output Voltage Range for all Outputs: Negative Positive ) s ( ct o r P Unit V -0.3 to 24 -2 to 40 see note 1 V V V - 0.3 intern. clamped to VS V V -2 +2 A A -5 5 see note 2 A A 1500 V Value Unit Output Current for all Outputs: Negative Positive for Transient with t < 10ms Negative Positive Schaffner Transient Pulses on Output r P e t e l o s b O Value -0.3 to 6 -0.3to VCC+0.3 u d o VESD ) s t( ESD Voltage Capability (MIL 883 C) THERMAL DATA Symbol Parameter Rth j-case Thermal Resistance Junction to Case 3 C/W Rth j-amb Tsdh Thermal Resistance Junction to Ambient mounted on PC Board Thermal Hysteresis 35 20 C/W C Tj > 150 C Tsd Thermal Diagnostic Notes: 1. Schaffner transient specification: DIN 40839 test waveforms of the following type: 1, 2, 3a, 3b, 5 and 6. The pulses are applied to the application circuit according to fig. 3. 2. The maximum output current results from the Schaffner pulses specified in note 1. 2/10 L9341 ELECTRICAL CHARACTERISTICS (Unless otherwise specified: 8V VS 24V; 4.7V VCC 5.3V; - 40 C Tj 150C; IO 1A (note 3); IO 1.5A; Vsp = VS for t 400ms; VOUTP = VOUT for t 400ms; Rext = 12.4K 1%). Symbol Iccq Isq Vccu Parameter Test Condition 3 Max. Unit All Outputs Off 1 3 mA Vs Quiescent Current Vcc Undervoltage Threshold All Outputs Off See Note 4 14 4 25 4.7 mA V Vcc Range for RES1 and RES2 Operation Ron On Resistance Io = 1A Io off Off State Output Current Outputs Off 1.4V Vo Vs Voutp = Vsp = 40V Igndf Typ. Vcc Quiescent Current Vccr Voutf Min. Output Voltage During Flyback 3 V Tj = 125C Tj = 25C 1 1 2.5 Io = 1A Output Off Tj = 25C Tj = 125C Current to GND during Flyback (see note 5) Io = 1A Output Off Vs = 24V Vsp = 40V Vsp - Vo = 40V 17 20 750 450 m m 4 10 mA mA Vs +1.3 Vs +1.1 V V ) s t( 44 52 500 mA mA A Vcc+0.3 V 0.3*Vcc V 0.3 1 V - 10 5 - 10 10 10 10 A A A c u d Ioutr Reverse Leakage Current VinH High Input Level of SCLK, SDI, CS, RES1, RES2 0.7*Vcc VinL Low Input Level of SCLK, SDI, CS, RES1, RES2 - 0.3 VREShys Hysteresis of Reset Inputs RES1, RES2 IinRESH Input Current on RES1,RES2 RESi = H; -2V Vsp 8V RESi = H; 8V Vsp 40V Iin Input Current on SCLK,SDI,CS - 2V Vsp 40V VSDOH VSDOL ISDOZ High Level SDO Output Voltage Low Level SDO Output Voltage SDO Tristate High-Z Leakage Current ISDO = -1mA -2V Vsp 40V ISDO = 1mA -2V Vsp 40V 0 VSDO Vcc - 2V Vsp 40V 0.9*Vcc 0 Vcc 0.4 V V - 10 10 A PWMduty Kf Vflyth PWM Duty Cycle Frequency Accuracy Constant Flyback Diagnostic Comparator Threshold See Note 6 40 Vsp 8V Vs 8V 0.93*Kfn Vs - 1 1.5 Voffth Ioutl tdpo Sov u d o r P e o s b O - 1/16 15/16 Kfn 1.07*Kfn Vs - 0.4 V V Off State Diagnostic Comparator Threshold 1.5 2 V Output Current Limitation Threshold see Note 7 Delay Time PWM Signal to Out. Output Voltage Rise and Fall (from 10 to 90% of Vo) Fig. 2 Slope | du/dt | 1.5 5 1.0 2.5 15 10 A s V/s 25 125 mA/s t e l o s b O Soc ct (s) e t le o r P Output Current Rise and Fall Slope |di/dt| 0.1 Io 1.5A (from 10 to 90% of Io) Notes: 1 T Io (t) dt ; T 0 4. The outputs are switced off for Vcc Vccu. The logic is not reseted. For a reset, RES1 or RES2 must be used. 5. This current is measured in the GND - terminal when one single output is in flyback and consists of the supply current added to the value of the output current source and the leakage current of the flyback diode. This leakage current is less than 1% of the nominal flyback current. fosc Kf 6. The PWM frequency is defined by an external capacitor. The PWM oscillator frequency is: fpwm = 1A/V and kin = 15 10-6; with fosc = 32 Cosc the range is: 300Hz fpwm 3000Hz. The OSC Pin can be alternatively driven by an external TTL / CMOS signal. 7. For Iout Ioutl an internal comparator switches the corresponding output off for the current PWM cycle. 3. The mean value is Io = 3/10 L9341 Figure 1: Logic Diagram of PWM Generation. INTERNAL CLOCK CLK 14 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM1 PWM2 PWM3 PWM4 Figure 2: Output Switching Diagram. c u d +12V Vs 220 nF Is f 5 20 mH D If DMOS Internal PWM Signal Output Voltage V OUT I out ID Current through Low Side Switch 10 nF V out GND Current through Flyback Diode (s) Is t c u d o r P e e t le du/dt out o r P 12V t dpo 5% du/dt 0 1A o s b O ID t dpo ) s t( di/dt di/dt 0 5% 1A di/dt If di/dt Figure 3: Test Circuit for Schaffner Pulses. t e l o +12V s b O +5V Vs VCC 10 uF 220 nF D1 -2V to 40 V Schaffner Generator OUT1 OUT2 OUT3 OUT4 GND 4 x 1 nF 4 x 10 nF 4/10 0 L9341 Figure 4: Synchronous Serial Interface Protocol. CS SCLK SDI MSB 14 13 12 11 3 2 1 LSB SDO MSB 14 13 12 11 3 2 1 LSB CS t clcl t chcl t ch t clch tcl c u d t chch SCLK t su th 15 SDI t clz 0 td t oh 15 SDO ) s ( ct u d o e t le 14 Clock Frequency tch tcl tcicl tchcl Width of Clock Input High Puls Widh of Clock Input Low Puls Clock Low Before CS Low Clock High After CS Low min. 200ns min. 200ns min. 200ns min. 200ns Clock Low Before CS High Clock High After CS High SDO Low-Z CS Low min. 200ns min. 200ns min. 0ns tzch tsu th SDO High-Z CS High SDI Input Setup Time SDI Input Hold Time min. 80ns min. 80ns td toh SDO Output Delay Time (CL = 50pF) SDO Output Hold Time tclch tchch tciz s b O t e l o o r P t zch 0 o s b O - fclock r P e ) s t( min. DC max. 2MHz max. 400ns max. 400ns max. 100ns min. 0ns 5/10 L9341 Figure 5: PWM Generation Function Table. Bit 3 - 0 PWM1 PWM2 PWM3 PWM4 OUTPUT 0000 0001 15/16 1/16 15/16 15/16 15/16 1/16 15/16 15/16 OFF ON 0010 2/16 14/16 2/16 14/16 ON 0011 3/16 13/16 3/16 13/16 ON 0100 4/16 12/16 4/16 12/16 ON 0101 5/16 11/16 5/16 11/16 ON 0110 6/16 10/16 6/16 10/16 ON 0111 1000 7/16 8/16 9/16 8/16 7/16 8/16 9/16 8/16 ON ON 1001 9/16 7/16 9/16 7/16 ON 1010 10/16 6/16 10/16 6/16 ON 1011 11/16 5/16 11/16 5/16 ON 1100 12/16 4/16 12/16 4/16 ON 1101 1110 13/16 14/16 3/16 2/16 13/16 14/16 3/16 2/16 1111 15/16 1/16 15/16 1/16 d o r uc P e let o s b O - Figure 6: PWM Information From Microcontroller to QLSD. Bit. Nr. Name 0 P10 1 P11 2 3 4 5 P12 P13 P20 P21 6 7 r P e 6/10 PWM Duty Cycle for Channel 1 / Bit 1 PWM Duty Cycle for Channel 1 / Bit 2 PWM Duty Cycle for Channel 1 / Bit 3 : MSB PWM Duty Cycle for Channel 2 / Bit 0 : LSB PWM Duty Cycle for Channel 2 / Bit 1 : P22 P23 PWM Duty Cycle for Channel 2 / Bit 2 : PWM Duty Cycle for Channel 2 / Bit 3 : MSB P30 P31 P32 P33 PWM Duty Cycle for Channel 3 / Bit 0 : LSB PWM Duty Cycle for Channel 3 / Bit 1 : PWM Duty Cycle for Channel 3 / Bit 2 : PWM Duty Cycle for Channel 3 / Bit 3 : MSB 12 13 14 P40 P41 P42 PWM Duty Cycle for Channel 4 / Bit 0 : LSB PWM Duty Cycle for Channel 4 / Bit 1: PWM Duty Cycle for Channel 4 / Bit 2 : 15 P43 PWM Duty Cycle for Channel 4 / Bit 3 : MSB t e l o s b O u d o ) s ( ct Contents PWM Duty Cycle for Channel 1 / Bit 0: LSB 8 9 10 11 ) s t( ON ON ON L9341 Figure 7: Diagnostic Information from QLSD to Microcontroller. Bit Nr. Name 0 1 F11 F12 COMP1 State at Positive Edge of PWM1 (0: Vout1 > Vflyth; 1: Vout1 < Vflyth) COMP2 State at Negative Edge of PWM1 (1: Vout1 > Voffth; 0 : Vout1 < Vofth) Contents 2 3 F21 F22 4 5 F31 F32 COMP1 State at Positive Edge of PWM2 (0: Vout2 > Vflyth; 1: Vout2 < Vflyth) COMP2 State at Negative Edge of PWM2 (1: Vout2 > Vofth; 0 : Vout2 < Vofth) COMP1 State at Positive Edge of PWM3 (0: Vout3 > Vflyth; 1: Vout3 < Vflyth) 6 7 F41 F42 8 RES1 Logic State of RES1 Input (0: RES1 = L ; 1: RES1 = H) COMP2 State at Negative Edge of PWM3 (1: Vout3 > Voffth; 0 : Vout3 < Vofth) COMP1 State at Positive Edge of PWM4 (0: Vout4 > Vflyth; 1: Vout4 < Vflyth) COMP2 State at Negative Edge of PWM4 (1: Vout4 > Voffth; 0 : Vout4 < Vofth) 9 RES2 Logic State of RES2 Input (0: RES2 = L ; 1: RES2 = H) 10 11 TSDF C1 Thermal Diagnostic Flag ( 0: Overtemperature ; 1:Normal ) Current at Negative Edge of PWM1 ( 0: Iout > Ioutl ; 1: Iout < Ioutl) 12 13 C2 C3 Current at Negative Edge of PWM2 ( 0: Iout > Ioutl ; 1: Iout < Ioutl) Current at Negative Edge of PWM3 ( 0: Iout > Ioutl ; 1: Iout < Ioutl) 14 C4 15 1 Current at Negative Edge of PWM4 ( 0: Iout > Ioutl ; 1: Iout < Ioutl) Framing Information (always 1) c u d Figure 8. e t le PWM ID V OUT ) s ( ct tC o r P e t dPO t e l o t s b O o s b O - du ) s t( o r P PWM V OUT t dPO tV tV t PWMON min PWMOFF min Sample point COMP1 Sample point COMP2 Sample point COMP2 Sample point COMP1 Fig. A Fig.1 Fig. Fig.2B Note: For safty diagnostic take notice of the following conditions: tPWMON tdPOMAX + tC + tV (see Fig. A) tPWMOFF tdPOMAX + tV (see Fig. B) tC = ID SOCMIN tV = Voutfmax SOVMIN 7/10 L9341 FUNCTIONAL DESCRIPTION The U511 is a PWM quad low side driver for inductive loads. The duty cycle of the internal generated PWM signal is set by a microcontroller via a serial interface for each output. An output slope limitation for both dv/dt and di /dt is implemented to reduce RFI. The PWM generation is realized avoiding a simultaneous output switching. As a result, di/dt becomes smaller. Integrated flyback diodes clamp the output voltage during the flyback phase of the low side switches. The driver is protected against short circuit. An undervoltage shutdown circuit switches off all outputs if Vcc is less then Vccu. Below the shutdown voltage all outputs remain in off state regardless of the input state. After each malfunction which resets the driver, only the serial link interface can reactivate the normal function. In case of overcurrent (Iout = Iout1), an internal comparator switches the output off. The overcurrent information can be read via the serial link for each driver separately at the negative edge of the corresponding PWM signal. The interface to the microcontroller is realized with a 16 bit synchronous serial peripheral interface (SPI). If CS is switched low, the serial link becomes active and SDO goes to low impedance. At the rising edge of the SCLK signal, one of the 16 bit of data stored in a shift register appear sequencely at SDO. These data contain the 8 error flags, the status of thermal diagnostic flag and the external reset sources RES1, RES2 and the overcurrent flgs c1...c4. The last bit is framing information (see fig. 7). At each falling edge of SCLK, one of the 16 bits of data sent by the microcontroller is transferred via the SDI input to the driver. These data contain the duty-cycle information for the internal PWM generation (4 times 4 bit). ) s ( ct u d o r P e t e l o s b O 8/10 On the rising edge of CS the previously stored information is transferred to the circuits. SDO become now high impedance and SDI is inactive. The serial interface of the QLSD is cascadable with the serial link interface of another QLSD, thus obtaining a 32 bit serial link information wich can control eight inductive loads. For a safety data transfer the takeover of data bits is only realized when the number of SCLK - clocks is n x 16 (n 1). The PWM duty cycle is set by 4 bit for each output independently via the serial link. If all four bits for an output are zero, the output is turned off, but the error diagnosis will work correctly (see fig. 5 and 6). The PWM frequency is defined by an external capacitor on the OSC pin. Rext defines through the reference current the output current slope, the diagnostic current sink and the internal oscillator frequency (together with Cosc). For error diagnosis the voltage on the output is measured during the on and off state of the particular output driver. Upon the rising edge of the PWM signal (at this moment the power output is off and will be switched on) the status of COMP1 is stored into an internal latch. On the falling edge of the PWM signal ( the power output is on and will be switched off) the status of COMP2 is stored into another internal latch. This information can be read via the serial link for each output driver separately (see fig. 7). The thermal diagnostic switch the thermal flag to 0 in case of overtemperature T Tsd. It will be switched to 1 with the hysteresis Tsdth in case of T < Tsd - Tsdh. To avoid male functions due to extensive noise or spikes at the supply pins VCC, VS and Rext must be blocked externally via capacitors. c u d o s b O - e t le o r P ) s t( L9341 mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 5 0.197 B 2.65 0.104 C 1.6 D 0.063 1 E 0.49 OUTLINE AND MECHANICAL DATA 0.039 0.55 0.019 0.022 F 0.66 0.75 0.026 G 1.02 1.27 1.52 0.040 0.050 0.060 0.030 G1 17.53 17.78 18.03 0.690 0.700 0.710 H1 19.6 0.772 H2 20.2 0.795 L 21.9 22.2 22.5 0.862 0.874 0.886 L1 21.7 22.1 22.5 0.854 0.870 0.886 L2 17.65 18.1 0.695 L3 17.25 17.5 17.75 0.679 0.689 0.699 L4 10.3 10.7 10.9 0.406 0.421 0.429 0.713 L7 2.65 2.9 0.104 M 4.25 4.55 4.85 0.167 0.179 0.191 M1 4.63 5.08 5.53 0.182 0.200 0.218 c u d 0.114 S 1.9 2.6 0.075 0.102 S1 1.9 2.6 0.075 0.102 Dia1 3.65 3.85 0.144 0.152 ) s ( ct ) s t( o r P Multiwatt15 V e t le o s b O - u d o r P e t e l o s b O 9/10 L9341 c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2003 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 10/10