SPIDER - TLE 7240SL
8 Channel Protected Low-Side Relay Switch
Data Sheet, Rev. 1.4, October 2011
Automotive Power
Data Sheet 2 Rev. 1.4, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7240SL
Table of Contents
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3 Voltage and Current naming definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5 Input and Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1.1 Limp Home Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.2 Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.2.1 Inductive Output Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2.2 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3 Input and Power Stages Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 Over Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2 Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.3 Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.4 Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7 Diagnosis Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.1 Diagnosis Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.1 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.2 Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.3 SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.3.1 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.4 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
11 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table of Contents
PG-SSOP-24-7
Type Package Marking
SPIDER - TLE 7240SL PG-SSOP-24-7 TLE7240SL_A
Data Sheet 3 Rev. 1.4, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER-TLE7240SL
SPIDER - TLE 7240SL
1Overview
Features
• 4 input pins providing flexible PWM configuration
• Limp home functionality (direct driving) provided by a dedicated pin
• 16 bit SPI for diagnostics and control
• Daisy chain capability also compatible with 8bit SPI devices
• Very wide range of digital supply voltage
• Green Product (RoHS compliant)
• AEC Qualified
Description
The SPIDER - TLE 7240SL is a eight channel low-side switch in PG-SSOP-24-7 package providing embedded
protective functions.
It is especially designed as relay driver in automotive applications.
A serial peripheral interface (SPI) is utilized for control and diagnosis of the device and the load.
For direct control and PWM there are four input pins available.
The device is monolithically integrated. The power transistors are built by N-channel MOSFETs.
Diagnostic Features
• latched diagnostic information via SPI register
• Overtemperature monitoring
• Overload detection in ON state
• Open load detection in OFF state
Table 1 Basic Electrical data
Digital supply voltage VDD 3.0 V ... 5.5 V
Analog supply voltage VDDA 4.5 V ... 5.5 V
Max. ON State resistance at Tj = 150°C for each channel RDS(ON,max) 3.0 Ω
Nominal load current IL (nom) 210 mA
Overload switch off threshold ID (OVL,max) 950 mA
Output leakage current per channel at 25 °C ID (STB,max) 1 µA
Drain to Source clamping voltage VDS(AZ) 41 V
Maximum SPI clock frequency fSCLK,max 5 MHz
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7240SL
Overview
Data Sheet 4 Rev. 1.4, 2011-10-21
Protection Functions
• Short circuit
• Over load
• Over temperature
• Electrostatic discharge (ESD)
Application
• All types of resistive, inductive and capacitive loads
• Especially designed for driving relays in automotive applications
Detailed Description
The SPIDER - TLE 7240SL is a eight channel low-side relay switch designed for typical automotive relays
providing embedded protective functions. The PG-SSOP-24-7 package is used to get a footprint optimized
solution. The 16 bit serial peripheral interface (SPI) is utilized for control and diagnosis of the device and the loads.
The SPI interface provides daisy chain capability.
The SPIDER - TLE 7240SL is equipped with four input pins that can be individually routed to the output control of
their dedicated channels thus offering flexibility in design and PCB layout. The input multiplexer is controlled via
SPI.
There is a dedicated limp home pin LHI which provides a straightforward usage of the input pins as dedicated
driver for four outputs.
The device provides full diagnosis of the load, which is open load as well as short circuit detection. The SPI
diagnosis bits indicate latched fault conditions that may have occurred.
Each output stage is protected against short circuit. In case of over load, the affected channel switches off. There
are temperature sensors available for each channel to protect the device in case of over temperature.
The device is supplied by two power supply lines. The analog supply supports 5 V, the digital supply offers a very
wide flexibility in supply voltage ranging from 3.0 V up to 5.5 V.
The power transistors are built by N-channel vertical power MOSFETs. The inputs are ground referenced CMOS
compatible. The device is monolithically integrated in Smart Power Technology.
In terms of PCB layout improvement, all output pins are available at one side of the device. The other side bundles
the signals to the micro-controller.
Data Sheet 5 Rev. 1.4, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7240SL
Block Diagram
2 Block Diagram
Figure 1 Block Diagram for the SPIDER - TLE 7240SL
Blockdiagram .emf
GND
CS
SI
SCLK
SO
SPI
control,
diagnostic
and
protective
functions
diagnosis
register
VDDAVDD
RST OUT3
OUT2
OUT1
OUT7
OUT6
OUT5
OUT4
OUT8
stand-by control
input mux and
control
IN1
IN2
IN3
IN4
LHI
open load
detection
temperature
sensor
gate
control
short circuit
detection
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7240SL
Pin Configuration
Data Sheet 6 Rev. 1.4, 2011-10-21
3 Pin Configuration
3.1 Pin Assignment
Figure 2 Pin Configuration
3.2 Pin Definitions and Functions
20
Pin Symbol I/O 1) Function
Power Supply
13 VDD - Digital Supply Voltage; Connected to 3.3V or 5V Voltage with Reverse
protection Diode and Filter against EMC
24 VDDA - Analog Supply Voltage; Connected to 5V Voltage with Reverse
protection Diode and Filter against EMC
1,2,11,12 GND - Ground; common ground for digital, analog and power
Power Stages
3OUT1 OOutput Channel 1; Drain of power transistor channel 1
4OUT2 OOutput Channel 2; Drain of power transistor channel 2
5OUT3 OOutput Channel 3; Drain of power transistor channel 3
6OUT4 OOutput Channel 4; Drain of power transistor channel 4
7OUT5 OOutput Channel 5; Drain of power transistor channel 5
8OUT6 OOutput Channel 6; Drain of power transistor channel 6
9OUT7 OOutput Channel 7; Drain of power transistor channel 7
10 OUT8 O Output Channel 8; Drain of power transistor channel 8
Inputs
17 IN1 I PD Control Input; Digital input 3.3 V or 5V. In case of not used keep open.
16 IN2 I PD Control Input; Digital input 3.3 V or 5V. In case of not used keep open.
Pinout.emf
(top view)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OUT2
OUT3
OUT4
OUT5
GND
GND
OUT1
GND
GND
OUT6
OUT7
OUT8
IN2
IN3
CS
SCLK
IN1
SI
SO
RST
LHI
IN4
VDDA
VDD
Data Sheet 7 Rev. 1.4, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7240SL
Pin Configuration
15 IN3 I PD Control Input; Digital input 3.3 V or 5V. In case of not used keep open.
14 IN4 I PD Control Input; Digital input 3.3 V or 5V. In case of not used keep open.
18 LHI I PD Limp Home; Digital input 3.3 V or 5V. In case of not used keep open.
21 RST IPDReset input pin; Digital input 3.3 V or 5V. Low active
SPI
23 CS IPUSPI chip select; Digital input 3.3 V or 5V. Low active
20 SCLK I PD serial clock; Digital input 3.3 V or 5V.
22 SI I PD serial data in; Digital input 3.3 V or 5V.
19 SO O serial data out; Digital output with voltage level referring to VDD.
1) O: Output, I: Input,
PD: pull-down resistor integrated,
PU: pull-up resistor integrated
Pin Symbol I/O 1) Function
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7240SL
Pin Configuration
Data Sheet 8 Rev. 1.4, 2011-10-21
3.3 Voltage and Current naming definition
Figure 3 shows all the terms used in this data sheet, with associated convention for positive values.
Figure 3 Terms
Terms.emf
GND
I
GND
I
D1
OUT1
OUT2
I
D3
OUT3
I
D2
V
DD
I
DD
VDD
V
RST
I
RST
RST
I
DDA
VDDA
V
DDA
OUT4
I
D5
OUT5
OUT6
I
D7
OUT7
I
D4
I
D6
OUT8
I
D8
V
DS1
V
bat
V
DS6
V
DS8
V
DS7
V
DS2
V
DS4
V
DS3
V
DS5
I
IN 1
IN1
I
IN 2
IN2
V
IN 1
V
CS
V
SC L K
V
SI
SO
SCLK
SI
CS
V
SO
I
CS
I
SC L K
I
SI
I
SO
I
IN 3
IN3
I
IN 4
IN4
V
IN 2
V
IN 3
V
IN 4
I
LHI
LHI
V
LHI
Data Sheet 9 Rev. 1.4, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7240SL
General Product Characteristics
4 General Product Characteristics
4.1 Absolute Maximum Ratings
Absolute Maximum Ratings 1)
Unless otherwise specified: Tj = -40 ⋅C to +150 ⋅C; VDD = 3.0 V to VDDA, VDDA= 4.5V to 5.5V
all voltages with respect to ground, positive current flowing into pin
1) Not subject to production test, specified by design.
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Max.
Power Supply
4.1.1 Digital supply voltage VDD -0.3 5.5 V –
4.1.2 Analog supply voltage VDDA -0.3 5.5 V –
4.1.3 Output voltage for short circuit protection
(single pulse)
VOUT 036 V–
Power Stages
4.1.4 Load current ID-0.5 0.5 A –
4.1.5 Voltage at power transistor VDS – 41 V active clamped
4.1.6 Maximum energy dissipation one
channel
EAS mJ 2)Vbat=16V,
Vclamp=45V,
2) Pulse shape represents inductive switch off: ID(t) = ID(0) × (1 - t/tpulse); 0 < t < tpulse
single pulse – 25
Tj(0) = 150 °C
ID(0) =0.40 A
repetitive (1 · 104 cycles)
EAR
–13
Tj(0) = 105 °C
ID(0) =0.30 A
repetitive (1 · 106 cycles) – 11
Tj(0) = 105 °C
ID(0) =0.30 A
Logic Pins
4.1.7 IN1,IN2,IN3,IN4;Voltage at input pins VIN -0.3 5.5 V –
4.1.8 RST; Voltage at reset pin VRST -0.3 5.5 V –
4.1.9 LHI; Voltage at limp home input pin VLHI -0.3 5.5 V –
4.1.10 CS; Voltage at chip select VCS -0.3 VDD + 0.3 V 3)
3) level must not exceed VDD+0.3V < 5.5 V
4.1.11 SCLK; Voltage at serial clock pin VSCLK -0.3 VDD + 0.3 V 3)
4.1.12 SI; Voltage at serial input pin VSI -0.3 VDD + 0.3 V 3)
4.1.13 SO; Voltage at serial output pin VSO -0.3 VDD + 0.3 V 3)
Temperatures
4.1.14 Junction Temperature Tj-40 150 °C–
4.1.15 Storage Temperature Tstg -55 150 °C–
ESD Susceptibility
4.1.16 ESD Resistivity VESD -4 4 kV HBM4)
4) ESD susceptibility, HBM according to EIA/JESD 22-A114
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7240SL
General Product Characteristics
Data Sheet 10 Rev. 1.4, 2011-10-21
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
4.2 Functional Range
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3 Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards.
For more information, go to www.jedec.org.
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Max.
4.2.1 Digital supply voltage VDD 3.0 5.5 V –
4.2.1 Analog supply voltage VDDA 4.5 5.5 V –
4.2.2 extended supply range VDDA 4.0 4.5 parameter deviations are
possible
4.2.3 Digital Supply current in reset mode IDD(RST) –10µATj = 85 °C
4.2.4 Digital supply current
(all channels active)
IDD(ON) –0.5mAVDD = VDDA = 5 V
VRST = VCS = VDD
VSCLK = 0 V
VIN = 0 V
4.2.5 Analog supply current
(all channels active)
IDDA(ON) –5mA–
4.2.6 Analog supply turn-ON time tDDA(ON) 15 – µs VDDA = 0V to 5V (linear)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
4.3.7 Junction to Soldering Point RthJSP ––25K/W
1) 2)
1) Not subject to production test, specified by design
2) Specified RthJSP value is simulated at natural convection on a cold plate setup (all pins are fixed to ambient temperature).
Ta = 25 °C. LS1 to LS8 are dissipating 1 W power (0.125 W each).
4.3.8 Junction to Ambient
(1s0p+600mm2Cu)
RthJA –68–K/W
1) 3)
3) Specified RthJA value is according to Jedec JESD51-2,-3 at natural convection on FR4 1s0p board; The product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with additional heatspreading copper area of 600mm2
and 70 µm thickness. Ta = 25 °C, LS1 to LS8 are dissipating 1 W power (0.125 W each).
4.3.9 Junction to Ambient (2s2p) RthJA –62–K/W
1) 4)
4) Specified RthJA value is according to Jedec JESD51-2,-7 at natural convection on FR4 2s2p board; The product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 µm Cu, 2 x 35 µm Cu).
Ta = 25 °C, LS1 to LS8 are dissipating 1 W power (0.125 W each).
Data Sheet 11 Rev. 1.4, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7240SL
Input and Power Stages
5 Input and Power Stages
The SPIDER - TLE 7240SL is a eight channel low-side relay switch.
The power stages are built by N-channel vertical power MOSFET transistors.
5.1 Power Supply
The SPIDER - TLE 7240SL is supplied by two power supply lines VDD and VDDA.
The digital power supply line VDD is designed to be functional at a very wide voltage range. The analog power
supply VDDA supports 5 V supply.
There are power-on reset functions implemented for both supply lines. After start-up of the power supply, all SPI
registers are reset to their default values and the device is in idle mode. Capacitors at pins VDD -GND and VDDA -
GND are recommended.
There is a reset pin available. Low level at this pin causes all registers to be set to their default values and the
quiescent supply currents are minimized.
5.1.1 Limp Home Mode
The SPIDER - TLE 7240SL offers the capability of driving dedicated channels during eventual fail-safe operation
of the system. This limp home mode is activated by a high signal at pin LHI. In this mode, the SPI registers are
reset and the input pins are directly routed to their corresponding channels OUT1 to OUT4, see Table 2 for details.
OUT5 to OUT8 are turned off in limp home mode. Furthermore, the SPI is ignored and all input pin are referred to
VDDA in order to ensure a defined operation mode if the digital supply or the microcontroller fail.
A high signal on LHI overrides a Reset signal on RST. In case of a limp home during standby the device will
therefore wake up and enter the limp home mode.
After limp home operation all registers are reset and the device enters in standby mode following low logic RST
state, or returns to idle (all channels OFF). Next SPI transmission will receive a TER Flag.
Table 2 Routing during limp home mode
5.2 Input Circuit
There are four input pins available at SPIDER - TLE 7240SL, which can be configured to be used for control of
the output stages. The INn parameter of the SPI selects the input pin to be used. Figure 4 shows the input circuit
of SPIDER - TLE 7240SL.
During Limp home mode a default routing is switched and the SPI commands are ignored.
Input controlled
Output
IN1 OUT1
IN2 OUT2
IN3 OUT3
IN4 OUT4
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7240SL
Input and Power Stages
Data Sheet 12 Rev. 1.4, 2011-10-21
Figure 4 Input matrix and logic
The current sink to ground ensures that the channels switch off in case of open input pin. The zener diode protects
the input circuit against ESD pulses. After power-on reset, the device enters idle mode (all channel OFF).
5.2.1 Inductive Output Clamp
When switching off inductive loads, the potential at pin OUT rises to VDS(CL) potential, because the inductance
intends to continue driving the current. The voltage clamping is necessary to prevent destruction of the device,
see Figure 5 for details. Nevertheless, the maximum allowed load inductance is limited.
InputLogic.emf
I
IN 3
IN3
I
IN 2
IN2
I
IN 1
IN1
Channel 8
LHIIN8
OFF
OFF
OFF
Channel 7
LHIIN7
OFF
OFF
OFF
Channel 6
LHIIN6
OFF
OFF
OFF
Channel 5
LHIIN5
OFF
OFF
OFF
Channel 2
LHIIN2
OFF
OFF
Channel 3
LHIIN3
OFF
OFF
Channel 4
LHI
IN4
OFF
OFF
I
IN 4
IN4
Channel 1
LHI
IN1
OFF
IN1
IN2
IN3
IN4
ON
ON
ON
ON
OFF
ON
ON
ON
ON
I
LHI
LHI LHI
Data Sheet 13 Rev. 1.4, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7240SL
Input and Power Stages
Figure 5 Output Clamp Implementation
Maximum Load Inductance
During demagnetization of inductive loads, energy has to be dissipated in the SPIDER - TLE 7240SL. This energy
can be calculated with following equation:
Following equation simplifies under the assumption of RL = 0:
The maximum energy, which is converted into heat, is limited by the thermal design of the component.
5.2.2 Timing Diagrams
The power transistors are switched on and off with a dedicated slope via the IN bits of the serial peripheral
interface SPI. The switching times tON and tOFF are designed equally.
Figure 6 Switching a Resistive Load
In input mode, a high signal at the input pin is equivalent to a SPI ON command and a low signal to SPI OFF
command respectively. Please refer to Section 8.3 for details on operation modes.
OutputClamp.emf
Vbat
ID
VDS(CL)
OUT
VDS
GND
L,
RL
EV
DS(CL)
Vbat V–DS(CL)
RL
------------------------------------ ln⋅1RLIL
⋅
Vbat V–DS(CL)
------------------------------------–
IL
+L
RL
------
⋅⋅=
E1
2
---LIL
21Vbat
Vbat V–DS(CL)
------------------------------------–
⋅=
CS
VDS
t
SwitchOn . e m f
tON tOFF
t
20%
80%
SPI: ON SPI: OFF
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7240SL
Input and Power Stages
Data Sheet 14 Rev. 1.4, 2011-10-21
5.3 Input and Power Stages Characteristics
Note: Characteristics show the deviation of parameter at given supply voltage and junction temperature. Typical
values show the typical parameters expected from manufacturing.
Electrical Characteristics: Supply and Input
All voltages with respect to ground, positive current flowing into pin
unless otherwise specified: VDD = 3.0 V to VDDA, VDDA= 4.5V to 5.5V, Tj = -40 ⋅C to +150 ⋅C
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
Power Supply
5.3.1 Digital supply voltage VDD 3.0 – 5.5 V –
5.3.2 Digital supply current, all channels
ON
IDD(ON) ––0.5mAVDD = VDDA = 5 V
VRST = VCS = VDD
VSCLK = 0 V
VIN = 0 V
5.3.3 Digital supply stand-by current, all
channels in stand-by mode
IDD(STB)
–
–
–
–
–
–
20
20
40
µAfSCLK = 0 Hz
VCS = VDD
Tj = 25 °C 1)
Tj = 85 °C 1)
Tj = 150 °C
5.3.4 Digital supply reset current IDD(RST)
–
–
–
–
–
–
10
10
20
µAVRST =VLHI = 0 V
Tj = 25 °C 1)
Tj = 85 °C 1)
Tj = 150 °C
5.3.5 Digital power-on reset threshold
voltage
VDD(PO) ––2.7V–
5.3.6 Analog supply voltage VDDA 4.5 – 5.5 V –
5.3.7 Analog supply current
all channels ON
IDDA(ON) ––5mA–
5.3.8 Analog supply stand-by current
all channels in stand-by mode
IDDA(STB)
–
–
–
–
–
–
20
20
40
µAVCS = VDD
VSI = 0 V
VSCLK = 0 V
Tj = 25 °C 1)
Tj = 85 °C 1)
Tj = 150 °C
5.3.9 Analog supply reset current IDDA(RST) –
–
–
–
–
–
–
–
5
5
20
µAVRST =VLHI = 0 V
Tj = 25 °C 1)
Tj = 85 °C 1)
Tj = 150 °C
5.3.10 Analog power-on reset threshold
voltage
VDDA(PO) ––4.0V–
Data Sheet 15 Rev. 1.4, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7240SL
Input and Power Stages
Output characteristics
5.3.11 On-State resistance per channel RDS(ON) –1.5–ΩIL = 180 mA
Tj = 25 °C 1)
–2.23.0 IL = 180 mA
Tj = 150 °C
5.3.12 Nominal load current IL(nom) 210 – – mA 1)all channels on
Ta = 85 °C
Tj,max = 150 °C
based on Rthja,2s2p
5.3.13 Output leakage current in stand-by
mode
(per channel)
ID(STB)
–
–
–
–
–
–
1
2
5
µAVDS = 13.5 V
Tj = 25 °C 1)
Tj = 85 °C 1)
Tj = 150 °C
5.3.14 Output clamping voltage VDS(CL) 41 – 54 V –
Input Characteristics
5.3.15 L level of pins IN1..IN4 and LHI VIN(L) 0–0.6
V–
5.3.16 H level of pins IN1..IN4 and LHI VIN(H) 2.0 – 5.5 V2)
5.3.17 L-input pull-down current through pin IN IIN(L) 31280
µA1) VIN = 0.6 V
5.3.18 H-input pull-down current through pin
IN
IIN(H) 10 40 80 µAVDD = 5.5 V
VIN = VDD
Reset Characteristics
5.3.19 L level of pin RST VRST(L) 0 – 0.2*
VDD
–
5.3.20 H level of pin RST VRST(H) 0.4*
VDD
–VDD –
5.3.21 L-input pull-down current through pin
RST
IRST(L) 31280
µA1) VRST = 0.6 V
5.3.22 H-input pull-down current through pin
RST
IRST(H) 10 40 80 µAVDD = 5.5 V
VRST = VDD
Timings
5.3.23 Reset wake-up time twu(RST) ––200µs–
5.3.24 Reset and LHI signal duration tRST(L) 50 – – µs–
5.3.25 Turn-on time
VDS = 20% Vbat
tON –3050µsVbat = 13.5 V
resistive load
all channels IDS = 180 mA
5.3.26 Turn-off time
VDS = 80% Vbb
tOFF –3050µsVbat = 13.5 V
resistive load
all channels IDS = 180 mA
1) Not subject to production test, specified by design.
2) level must not exceed VDD+0.3V < 5.5 V
Electrical Characteristics: Supply and Input
All voltages with respect to ground, positive current flowing into pin
unless otherwise specified: VDD = 3.0 V to VDDA, VDDA= 4.5V to 5.5V, Tj = -40 ⋅C to +150 ⋅C
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7240SL
Protection Functions
Data Sheet 16 Rev. 1.4, 2011-10-21
6 Protection Functions
The device provides embedded protective functions. Integrated protection functions are designed to prevent IC
destruction under fault conditions described in this data sheet. Fault conditions are considered as “outside” normal
operating range. Protection functions are not designed for continuous repetitive operation.
6.1 Over Load Protection
The SPIDER - TLE 7240SL is protected in case of over load or short circuit of the load. After time tOFF(OVL), the
over loaded channel n switches off and the according diagnosis flag Dn is set.The channel can be switched on
after clearing the diagnosis flag. Please refer to Figure 7 for details.
Figure 7 Shut down at over load
The current sink to ground ensures that the channels switch off in case of open input pin. The zener diode protects
the input circuit against ESD pulses. After power-on reset, the device enters idle mode.
6.2 Over Temperature Protection
A temperature sensor for each channel causes an overheated channel n to switch off to prevent destruction and
the according diagnosis flag Dn is set. The channel can be switched on after clearing the diagnosis flag. Please
refer to Chapter 7.1 for information on diagnosis features.
6.3 Reverse Polarity Protection
In case of reverse polarity, the intrinsic body diode of the power transistor causes power dissipation. The reverse
current through the intrinsic body diode of the power transistor has to be limited by the connected load. The VDD
and VDDA supply pins must be protected against reverse polarity externally. The over temperature and over load
protection is not active during reverse polarity.
IN1
I
OUT1
t
t
OverLoad.emf
t
OFF(OVL)
I
OUT(OVL)
D1 = 1
b
IN1 = 01
b
D1 = 0
b
D1 = 0
b
Program OUT 1 to
STANDBY and to
IN1 again
Data Sheet 17 Rev. 1.4, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7240SL
Protection Functions
6.4 Protection Characteristics
Note: Characteristics show the deviation of parameter at given supply voltage and junction temperature. Typical
values show the typical parameters expected from manufacturing.
Electrical Characteristics: Protection
All voltages with respect to ground, positive current flowing into pin
unless otherwise specified: VDD = 3.0 V to VDDA, VDDA= 4.5V to 5.5V, Tj = -40 ⋅C to +150 ⋅C
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
Over Load Protection
6.4.1 Over load detection current ID(OVL) 0.5 – 0.95 A –
all channels –
6.4.2 Over load shut-down delay time tOFF(OVL) 3–50µs–
Over Temperature Protection
6.4.3 Thermal shut down temperature Tj(SC) 150 1701)
1) Not subject to production test, specified by design
–°C–
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7240SL
Diagnosis Features
Data Sheet 18 Rev. 1.4, 2011-10-21
7 Diagnosis Features
The SPI of SPIDER - TLE 7240SL provides diagnosis information about the device and about the load. There are
following diagnosis flags implemented:
The diagnosis information of the protective functions of channel n is latched in the diagnosis flag Dn.
The open load diagnosis of channel n is latched in the diagnosis flag OLn.
Both flags are cleared by programming the specific channel to Standby (STB).
7.1 Diagnosis Characteristics
Note: Characteristics show the deviation of parameter at given supply voltage and junction temperature. Typical
values show the typical parameters expected from manufacturing.
Failure Mode Comment
Open Load or short circuit
to ground
Diagnosis, when channel n is switched on: none
Diagnosis, when channel n is switched off: according to voltage level at the output pin, flag OLn
is set after time td(OL).
When the channel is in OFF there is Diagnosis active, in Standby the Diagnosis is not enabled
Over Temperature When over temperature occurs, the according diagnosis flag Dn is set. If the affected channel n
was active it is switched off.
The diagnosis flags are latched until they have been cleared by programming the channel STB.
Over Load
(Short Circuit)
When over load is detected at channel n, the affected channel is switched off after time tOFF(OVL)
and the dedicated diagnosis flag Dn is set.
The diagnosis flags are latched until they have been cleared by programming the channel STB
Electrical Characteristics: Diagnosis
All voltages with respect to ground, positive current flowing into pin
unless otherwise specified: VDD = 3.0 V to VDDA, VDDA= 4.5V to 5.5V, Tj = -40 ⋅C to +150 ⋅C
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
OFF State Diagnosis
7.1.1 Open load detection threshold
voltage
VDS(OL) 1.0 – 2.5 V –
7.1.2 Output pull-down diagnosis current
per channel
ID(PD) ––80 µAVDS = 13.5 V
7.1.3 Open load diagnosis delay time td(OL) 30 – 200 µs–
ON State Diagnosis
7.1.4 Over load detection current ID(OVL) 0.5 – 0.95 A –
7.1.5 Over load detection delay time tOFF(OVL) 3–50µs–
Data Sheet 19 Rev. 1.4, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7240SL
Serial Peripheral Interface (SPI)
8 Serial Peripheral Interface (SPI)
The diagnosis and control interface is based on a serial peripheral interface (SPI).
The SPI is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CS. Data is
transferred by the lines SI and SO at the data rate given by SCLK. The falling edge of CS indicates the beginning
of a data access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising
edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter ensures that data is
taken only, when a multiple of 8 bit has been transferred, while the minimum of 16 bit is also taken into
consideration. Therefore the interface provides daisy chain capability even with 8 bit SPI devices.
Figure 8 Serial peripheral interface
The SPI protocol is described in Section 8.3. It is reset to the default values after power-on reset.
8.1 SPI Signal Description
CS - Chip Select:
The system micro controller selects the SPIDER - TLE 7240SL by means of the CS pin. Whenever the pin is in
low state, data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are ignored
and SO is forced into a high impedance state.
CS High to Low transition:
• The diagnosis information is transferred into the shift register.
• SO changes from high impedance state to high or low state depending on the logic OR combination between
the transmission error flag (TER) and the signal level at pin SI. As a result, even in daisy chain configuration,
a high signal indicates a faulty transmission. The transmission error flag is set after any kind of reset, so a reset
between two SPI commands is indicated. For details, please refer to Figure 9. This information stays available
to the first rising edge of SCLK.
Figure 9 Transmission Error Flag on SO Line
14 13 12 11
14 13 12 11MSB
MSB
SPI.emf
LSB6 5 4 3 2 1
LSB6 5 4 3 2 1
10 9 8
10 9 8
7
7
SO
SI
CS
SCLK
time
TE R. em f
SI
SPI
OR
TER
0
1
SO
CS
SCLK
S
SO
S
SI
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7240SL
Serial Peripheral Interface (SPI)
Data Sheet 20 Rev. 1.4, 2011-10-21
CS Low to High transition:
Data from shift register is transferred into the input matrix register only, when after the falling edge of CS exactly
a multiple (1, 2, 3, …) of eight SCLK signals have been detected, while the minimum valid length is of course 16
clocks for the 16 register bits of SPIDER-TLE7240SL.
SCLK - Serial Clock:
This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling
edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock.
It is essential that the SCLK pin is in low state whenever chip select CS makes any transition.
SI - Serial Input:
Serial input data bits are shifted in at this pin, the most significant bit first. SI information is read on the falling edge
of SCLK. Please refer to Section 8.3 for further information.
SO - Serial Output:
Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CS pin
goes to low state. New data will appear at the SO pin following the rising edge of SCLK. Please refer to Section 8.3
for further information.
8.2 Daisy Chain Capability
The SPI of SPIDER - TLE 7240SL provides daisy chain capability. In this configuration several devices are
activated by the same CS signal MCS. The SI line of one device is connected with the SO line of another device
(see Figure 10), which builds a chain. The ends of the chain are connected with the output and input of the master
device, MO and MI respectively. The master device provides the master clock MCLK, which is connected to the
SCLK line of each device in the chain.
Figure 10 Daisy Chain Configuration
In the SPI block of each device, there is one shift register where one bit from SI line is shifted in each SCLK. The
bit shifted out can be seen at SO. After 16 SCLK cycles, the data transfer for one SPIDER-TLE7240SL has been
finished. In single chip configuration, the CS line must go high to make the device accept the transferred data. In
daisy chain configuration the data shifted out at device #1 has been shifted in to device #2. When using multiple
devices in daisy chain, the number of bits must be correspond with the number of register bits. Figure 11 is
showing a example with 3 SPI devices, where #1 and #3 are 16 bit SPI and #2 has a 8 bit SPI. To get a successful
transmission, there have to be 2* 16 bit + 1* 8bit shifted through the devices. After that, the MCS line must go high.
SI
device 1
SPI
SCLK
SO
CS
SI
device 2
SPI
SCLK
SO
CS
SI
device 3
SPI
SCLK
SO
CS
MO
MI
MCS
MCLK
SPI _DasyChain.emf
Data Sheet 21 Rev. 1.4, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7240SL
Serial Peripheral Interface (SPI)
Figure 11 Data Transfer in Daisy Chain Configuration
8.3 SPI Protocol
The SPI protocol of the SPIDER - TLE 7240SL provides two registers. The input register and the diagnosis
register. The diagnosis register contains eight pairs of diagnosis flags, the input register contains the input
multiplexer configuration. After power-on reset, all register bits are set to 1 and the device is in idle mode.
Note: If all channels are programmed to Standby, the device changes to power down status with minimum current
consumption (sleep mode).
SI Default: FFFFH
1514131211109876543210
IN8 IN7 IN6 IN5 IN4 IN3 IN2 IN1
Field Bits Type Description
INn
(n = 8 - 1)
15:14,
13:12,
11:10,
9:8,
7:6,
5:4,
3:2,
1:0
WInput Register Channel n
00BStand-by Mode:
Channel is switched off.
Diagnosis flags are cleared.
Diagnosis current is disabled.
01BInput Mode:
Channel is switched according to signal at input pin.
Diagnosis current is enabled in OFF-state.
10BON Mode:
Channel is switched on.
11BOFF Mode:
Channel is switched off.
Diagnosis current is enabled.
MI
MO
MCS
MCLK
SI device 3 SI device 2 SI device 1
SO device 3 SO device 2 SO device 1
time
SPI_DasyChain2.emf
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7240SL
Serial Peripheral Interface (SPI)
Data Sheet 22 Rev. 1.4, 2011-10-21
8.3.1 Timing Diagrams
Figure 12 Timing Diagram
SO Reset Value: 10000H
CS1) 1514131211109876543210
TEROL8D8OL7D7OL6D6OL5D5OL4D4OL3D3OL2D2OL1D1
1) This bit is valid between CS hi -> lo and first SCLK lo -> hi transition.
Field Bits Type Description
TER CS R Transmission Error
0 Previous transmission was successful (modulo 8 clocks received, minimum 16 bit).
1Previous transmission failed or first transmission after reset.
OLn
(n = 8 - 1)
15,13,
11,9,7,
5, 3, 1
ROpen Load Flag of channel n
0Normal operation.
1 Open load has occurred in OFF state.
Dn
(n = 8 - 1)
14,12,
10,8,6,
4, 2, 0
RDiagnosis Flag of channel n
0Normal operation.
1 Over load or over temperature switch off has occurred in ON state.
CS
SCLK
SI
tCS ( l ead) tCS(td)
tCS (l ag)
tSCLK(H) tSCLK(L)
tSCLK(P)
tSI(su) tSI(h)
SO
tSO(v)
tSO(en) tSO(dis)
0.7V
cc
0.2V
cc
0.7V
cc
0.2V
cc
0.7V
cc
0.2V
cc
0.7V
cc
0.2V
cc
SPI Timing.emf
Data Sheet 23 Rev. 1.4, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7240SL
Serial Peripheral Interface (SPI)
8.4 SPI Characteristics
Note: Characteristics show the deviation of parameter at given supply voltage and junction temperature. Typical
values show the typical parameters expected from manufacturing.
Electrical Characteristics: Serial Peripheral Interface (SPI)
All voltages with respect to ground, positive current flowing into pin
unless otherwise specified: VDD = 3.0 V to VDDA, VDDA= 4.5V to 5.5V, Tj = -40 ⋅C to +150 ⋅C
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
Input Characteristics (CS, SCLK, SI)
8.4.1 L level of pin
CS
SCLK
SI
VCS(L)
VSCLK(L)
VSI(L)
0 – 0.2*
VDD
–
8.4.2 H level of pin
CS
SCLK
SI
VCS(H)
VSCLK(H)
VSI(H)
0.4*
VDD
–VDD –
8.4.3 L-input pull-up current through CS ICS(L) 31740µAVCS = 0 V
8.4.4 H-input pull-up current through CS ICS(H) 31540µA1)
VCS = 0.4*VDD
8.4.5 L-input pull-down current through
pin
SCLK
SI
ISCLK(L)
ISI(L)
31280µA1)
VSCLK = 0.6 V
VSI = 0.6 V
8.4.6 H-input pull-down current through
pin
SCLK
SI
ISCLK(H)
ISI(H)
10 40 80 µA
VSCLK = VDD
VSI = VDD
Output Characteristics (SO)
8.4.7 L level output voltage VSO(L) 0–0.6VISO = -2 mA
8.4.8 H level output voltage VSO(H) VDD -
0.4 V
–VDD ISO = 1.5 mA
8.4.9 Output tristate leakage current ISO(OFF) -10 – 10 µAVCS = VDD
Timings
8.4.10 Serial clock frequency fSCLK 0–5MHz
1)
8.4.11 Serial clock period tSCLK(P) 200 – – ns 1)
8.4.12 Serial clock high time tSCLK(H) 50 – – ns 1)
8.4.13 Serial clock low time tSCLK(L) 50 – – ns 1)
8.4.14 Enable lead time (falling CS to
rising SCLK)
tCS(lead) 250 – – ns 1)
8.4.15 Enable lag time (falling SCLK to
rising CS)
tCS(lag) 250 – – ns 1)
8.4.16 Transfer delay time (rising CS to
falling CS)
tCS(td) 250 – – ns 1)2)
8.4.17 Data setup time (required time SI to
falling SCLK)
tSI(su) 20 – – ns 1)
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7240SL
Serial Peripheral Interface (SPI)
Data Sheet 24 Rev. 1.4, 2011-10-21
8.4.18 Output enable time (falling CS to
SO valid)
tSO(en) ––200nsCL = 50 pF 1)
8.4.19 Output disable time (rising CS to
SO tri-state)
tSO(dis) ––200nsCL = 50 pF 1)
8.4.20 Output data valid time with
capacitive load
tSO(v) ––100nsCL = 50 pF 1)
1) Not subject to production test, specified by design.
2) Diagnosis flag update needs the time specified in Chapter 7.1 to get valid information
Electrical Characteristics: Serial Peripheral Interface (SPI)
All voltages with respect to ground, positive current flowing into pin
unless otherwise specified: VDD = 3.0 V to VDDA, VDDA= 4.5V to 5.5V, Tj = -40 ⋅C to +150 ⋅C
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
Data Sheet 25 Rev. 1.4, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7240SL
Application Information
9 Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
Figure 13 shows a simplified application circuit. VDD and VDDA need to be externally reverse polarity protected.
Figure 13 Application Diagram
Note: This is a very simplified example of an application circuit. The function must be verified in the real application.
For further information you may contact http://www.infineon.com/spider
GND
SPI
GND
GND
VCC
V
bat
+5V
VDD
VDD
100nF
SO
SCLK
SI
CS
IN2
IN1
TLE7240SL.emf
SPI
OUT1
OUT2
OUT3
OUT4
OUT8
low-side
gate control
IN3
LHI Limp Home Signal
(eg WD out of SBC TLE 8264 G Hermes)
IN4
OUT5
OUT6
OUT7
VDDA
µC
XC2000
RST
KL15 R ela y
KL50 R ela y
Wiper Relay
Horn Relay
GPIO
Limp Home Circuit
Possibility to co ntrol OUT 1 -
4 via Inputs IN1-4 during
malfunction of µC
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7240SL
Package Outlines
Data Sheet 26 Rev. 1.4, 2011-10-21
10 Package Outlines
Figure 14 PG-SSOP-24-7 (Plastic Dual Small Outline Package)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-
free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Please specify the package needed (e.g. green package) when placing an order
PG-SSOP-24-5, -6
1) Does not include plastic or metal protrusion of 0.15 max. per side
112
24 13
2) Does not include dambar protrusion of 0.13 max.
8.65
±0.1
0.65
0.25
2) M
C0.17 B 24x
±0.05
A
A
Index Marking
B
(1.47)
1.75 MAX.
0.1 B
Seating Plane
±0.1
3.9
1)
0.35 x 45˚
8˚ MAX.
±0.25
0.64
±0.2
C
6
M
0.2
8˚ MAX.
±
0.07
0.175
0˚...8˚
+0.06
0.19
8
˚
MAX.
C
0˚...8˚
1)
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.Dimensions in mm
Data Sheet 27 Rev. 1.4, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7240SL
Revision History
11 Revision History
Version Date Changes
Rev. 1.4 2011-10-21 Marking changed to TLE7240SL_A
Rev. 1.3 2011-05-23 parameter 4.1.6 on page 9, condition and max limit values changed
Rev. 1.2 2011-03-24 new parameter 4.2.6 on page 10 “Analog Supply Turn-ON time” added;
power on threshold 5.3.10 adjusted to functional range stated at 4.2;
rephrased note at page 21 and removed “fast” from 00B status description;
removed note at 5.2.2 Timing Diagrams below Figure 6 because not relevant;
5.1 Power Supply on page 11: change from “device is in standby mode” to “device
is in idle mode” after power-on reset (as already described on page 12, 16 and 21)
Rev. 1.1 2009-04-15 fixed a typo in Figure3, Figure4,Figure7 and Chapter 8.3
IN and OUT channel numbering starts now everywhere with 1
Rev. 1.0 2009-04-02 released Datasheet
Edition 2011-10-21
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2011 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
