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PT0082(10/10) Ver: 7
1
Data Sheet
PT7A7511-15/7521-25/7531-35
µP Supervisor Circuits
Features
z Precision supply-voltage monitor
- 4.63V (PT7A7511, 7521, 7531)
- 4.38V (PT7A7512, 7522, 7532)
- 3.08V (PT7A7513, 7523, 7533)
- 2.93V (PT7A7514, 7524, 7534)
- 2.63V (PT7A7515, 7525, 7535)
z 200ms reset pulse width
z Debounced TTL/CMOS-compatible manual-
reset input
z Independent watchdog timer 1.6sec time-out (not
available for PT7A7531 - 7535)
z Reset output signal:
- Active-low only (PT7A7511 - 7515)
- Active-high only (PT7A7521 - 7525)
- Active-high and active-low (PT7A7531 - 7535)
z Voltage monitor for power-fail or low battery
warning
z Guaranteed RESET/RESET valid at VCC=1.2V
Description
The PT7A751X/752X/753X family microprocessor
(µP) supervisory circuits are targeted to improve
reliability and accuracy of power-supply circuitry in
µP’s systems. These devices reduce the complexity and
number of components required to monitor power-
supply and battery functions.
The main functions are:
1. Asserting reset output during power-up, power-
down and brownout conditions for µP system.
2. Detecting power failure or low-battery
conditions with a 1.25V threshold detector.
3. Watchdog functions (not for PT7A753x)
Applications
z Power-supply circuitry in µP systems
Ordering Information
Part Number Package Part Number Package
PT7A751xPE Lead free DIP-8 PT7A751xWE Lead free and Green SOIC-8
PT7A752xPE Lead free DIP-8 PT7A752xWE Lead free and Green SOIC-8
PT7A753xPE Lead free DIP-8 PT7A753xWE Lead free and Green SOIC-8
Note: “X” refers to voltage range, see below table.
Suffix: X—Monitored Voltage and Function Comparison
Part No. Reset
Threshold Reset Active
Low or High Nom. Reset
Time (ms), tRS Nom. Watch dog
Time (sec), tWD Power Fail
Comp. Manual
Reset Input
PT7A7511 4.63V LOW 200 1.6 1.25V detector Yes
PT7A7521 4.63V HIGH 200 1.6 1.25V detector Yes
PT7A7531 4.63V LOW, HIGH 200 unavailable 1.25V detector Yes
PT7A7512 4.38V LOW 200 1.6 1.25V detector Yes
PT7A7522 4.38V HIGH 200 1.6 1.25V detector Yes
PT7A7532 4.38V LOW, HIGH 200 unavailable 1.25V detector Yes
PT7A7513 3.08V LOW 200 1.6 1.25V detector Yes
PT7A7523 3.08V HIGH 200 1.6 1.25V detector Yes
PT7A7533 3.08V LOW, HIGH 200 unavailable 1.25V detector Yes
PT7A7514 2.93V LOW 200 1.6 1.25V detector Yes
PT7A7524 2.93V HIGH 200 1.6 1.25V detector Yes
PT7A7534 2.93V LOW, HIGH 200 unavailable 1.25V detector Yes
PT7A7515 2.63V LOW 200 1.6 1.25V detector Yes
PT7A7525 2.63V HIGH 200 1.6 1.25V detector Yes
PT7A7535 2.63V LOW, HIGH 200 unavailable 1.25V detector Yes
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PT0082(10/10) Ver: 7
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Data Sheet
PT7A7511-15/7521-25/7531-35
µP Supervisor Circuits
Block Diagram
Block Diagram of PT7A7511-7515/7521-7525
Vcc
250uA
V
RST
1.25V
Watchdog
Transition Detector Watchdog Timer
WDI WDO
Timebase for Reset
& Watchdog
Reset Generator
MR
Vcc
PFI
RESET
(RESET)
PFO
Block Diagram of PT7A7531-35
Reset Generator
MR
Vcc
PFI
PFO
RESET
1.25V
V
RST
Vcc
250uA RESET
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PT0082(10/10) Ver: 7
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Data Sheet
PT7A7511-15/7521-25/7531-35
µP Supervisor Circuits
Pin Configuration
Top View
1
2
3
4
8
7
6
5
MR
V CC
GND
PFI
WDO
RESET
WDI
PFO
PT7A7511P-7515P
PT7A7511W-7515W
8-Pin PDIP/8-Pin SOIC
1
2
3
4
8
7
6
5
MR
V CC
GND
PFI
WDO
RESET
WDI
PFO
PT7A7521P-7525P
PT7A7521W-7525W
8-Pin PDIP/8-Pin SOIC
1
2
3
4
8
7
6
5
MR
V CC
GND
PFI
RESET
RESET
NC
PFO
PT7A7531P-7535P
PT7A7531W-7535W
8-Pin PDIP/8-Pin SOIC
Pin Description
Pin Type Description
MR I Manual-Reset: triggers a reset pulse when pulled below 0.8V, active low. It has an internal 250mA pull-
up current and be driven from a TTL or CMOS logic line as well as shorted to ground with a switch.
VCC Power
Supply Voltage.
GND Ground Ground Reference for all signals.
PFI I
Power-Fail Voltage Monitor Input. When PFI is less than 1.25V, PFO goes low. Connect PFI to GND
or Vcc when not used.
PFO O
Power-Fail Output: it gets low and sinks current when PFI is less than 1.25V; otherwise PFO stays high.
WDI I
Watchdog Input: If WDI remains high or low for 1.6sec, the internal watchdog timer runs out and WDO
goes low. Floating WDI or connecting WDI to a high-impedance three-state buffer disables the watchdog
feature. The internal watchdog timer clears whenever reset is asserted. WDI is three-stated, or WDI sees a
rising or falling edge.
RESET O
Reset Output pulses: low for 200ms when triggered, and stays low whenever Vcc is below the reset
threshold. It remains low for 200ms after Vcc rises above the reset threshold or MR goes from low to
high. A watchdog timeout will not trigger RESET unless WDO is connected to MR.
WDO O
Watchdog Output: pulls low when the internal watchdog timer finishes its 1.6sec count and does not go
high again until the watchdog is cleared. WDO also goes low during low-line conditions. Whenever Vcc
is below the reset threshold, WDO stays low; however, unlike RESET, WDO does not have minimum
pulse width. As soon as Vcc rises above the reset threshold, WDO goes high with no delay.
RESET O
The inverse of RESET, active high. Whenever RESET is high, RESET is low.
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PT0082(10/10) Ver: 7
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Data Sheet
PT7A7511-15/7521-25/7531-35
µP Supervisor Circuits
Functional Description
The PT75xx family can assert reset output during power-up, power-down and brownout conditions for µP system, detect power
failure or low-battery conditions with a 1.25V threshold detector and have watchdog functions. Refer to Function Table of
PT7A75xx Family for their individual features. The typical application see Figure 4.
Reset Output
The supervisory circuits can assert reset for a microprocessor during power-up, power-down and brownout to prevent code
execution errors.
On power-up, once Vcc reaches about 1.2V, RESET is a guaranteed logic low of 0.4V or less. As Vcc rises, RESET stays low.
When Vcc rises above the reset threshold, an internal timer releases RESET after about 200ms. RESET pulses low whenever Vcc
drops below the reset threshold, i.e. brownout condition. If brownout occurs in the middle of a previously initiated reset pulse, the
pulse continues for at least another 140ms. On power-down, once Vcc falls below the reset threshold, RESET stays low and is
guaranteed to be 0.4V or less until Vcc drops below 1.0V.
The PT7A752x and PT7A753x active-high RESET output is simply the inverse of the RESET output, and is guaranteed to be
valid with Vcc down to 1.2V. Some µPs, such as Intel’s 80C51, require an active-high reset pulse.
Watchdog Timer
The watchdog circuit monitors the µP activity. If the µP does not toggle the watchdog input (WDI) within 1.6sec and WDI is not
in high impedance, WDO goes low. As long as RESET is asserted or the WDI input is in high impedance, the watchdog timer will
stay cleared and will not count. As soon as reset is released and WDI is driven high or low, the timer will start counting. Pulses as
short as 50ns can be detected.
Typically, WDO will be connected to the non-maskable interrupt input (NMI) of a µP. When VCC drops below the reset
threshold, WDO will go low whether or not the watchdog timer has timed out yet. Normally this would trigger an NMI interrupt,
but RESET goes low simultaneously, and thus overrides the NMI interrupt. If WDI is left unconnected, WDO can be used as a
low-line output. Since floating WDI disables the internal timer, WDO goes low only when VCC falls below the reset threshold,
thus functioning as a low-line output.
Manual Reset
The manual-reset input (MR) allows reset to be triggered by a push button switch. The switch is effectively debounced by the
140ms minimum reset pulse width. MR is TTL/CMOS logic compatible, so it can be driven by any logic reset output.
Power-Fail Comparator
The power-fail comparator will send out a Low signal once detects a voltage lowered than 1.25V. It can be used for various
purposes because its output and non-inverting input are not internally connected. The inverting input is internally connected to a
1.25V reference..
Typical Application Circuit
DC Linear
Regulator
Vcc
Supervisory
PFI
Circuit
WDI
µ
P
Vcc
RESET
I/O Line
NMI
Interrupt
IN
OUT
RESET
WDO
PFOMR
µ
P
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PT0082(10/10) Ver: 7
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Data Sheet
PT7A7511-15/7521-25/7531-35
µP Supervisor Circuits
Maximum Ratings
Storage Temperature ............................................................-65oC to +150oC
Ambient Temperature with Power Applied.......................... -40oC to +85oC
Supply Voltage to Ground Potential (Vcc to GND) ..............-0.3V to +7.0V
DC Input Voltage (All inputs except Vcc and GND)......-0.3V to VCC+0.3V
DC Output Current (All outputs) ..........................................................20mA
Power Dissipation .......................................... 500mW (Depend on package)
Recommended Operation Conditions
Sym Description Test Conditions Min Typ Max Unit
Supply Voltage for 75x1,75x2 - 4.5 5.0 5.5 V
Supply Voltage for 75x3,75x4 - 3.0 3.3 5.5 V
VCC
Supply Voltage for 75x5 2.7 3.0 5.5
VCC > 4.0V 2.0 2.4 - V
VIH1
MR Input High Voltage VCC ≤ 4.0V 0.7VCC - - V
VIH2 WDI Input High Voltage - 0.7VCC - - V
VCC > 4.0V - - 0.8 V
VIL1
MR Input Low Voltage VCC ≤ 4.0V - - 0.2VCC V
VIL2 WDI Input Low Voltage - - - 0.3VCC V
TA Operating Temperature - -40 - 85
℃
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions above those indicated in the operational sec-
tions of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect reliability.
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PT0082(10/10) Ver: 7
6
Data Sheet
PT7A7511-15/7521-25/7531-35
µP Supervisor Circuits
DC Electrical Characteristics
(VCC = VRN + 5% to 5.5V, TA= -40~85ºC, unless otherwise noted.)(Note 1)
Symbol Description Test Conditions Min Typ Max Unit
ICC Supply Current
75x1/x2 Vcc = 5V,
75x3/x4 Vcc = 3.3V,
75x5 Vcc = 3.0V, Left WDI un-
connected (No output load)
- 30 200 µA
VIH Input High Voltage
Pin: MR, WDI 0.7VCC - - V
VIL Input Low Voltage
Pin: MR, WDI - - 0.3VCC V
TA= 25ºC VRN - 1.5% VRN V
RN + 1.5%
75x1 4.560 4.630 4.699
75x2 4.314 4.380 4.446
75x3 3.034 3.080 3.126
75x4 2.886 2.930 2.974
VRST
Reset Threshold Voltage
(Note 2)
75x5 2.590 2.630 2.669
V
VRTH＋ Reset Threshold Voltage
(Note 2) VCC Varies between VRN - 5% - 70 - mV
Vcc ≥ 4.5V Isource=800µA Vcc-1.5 - -
Vcc ≥ 2.7V Isource=500µA 0.8×Vcc - -
VOH Output High Voltage
Vcc ≥ 1.8V Isource=150µA 0.8×Vcc - -
V
Vcc ≥ 4.5V Isink=3.2mA - - 0.4
Vcc ≥ 2.7V Isink=1.2mA - - 0.3
VOL Output Low Voltage
Vcc ≥ 1.2V Isink=100µA - - 0.3
V
VPFI varies from 1.0V to 1.5V 1.23 1.25 1.27
VPFT PFI Input Threshold VPFI varies from 0V to 1.0V 1.20 1.25 1.30 V
PFI connected to Vcc - - 2.00
IPFI PFI Input Current PFI connected to GND -2.00 - - µA
WDI connected to VCC - 30 100
IWDI Average WDI Input
Current (Note 3) WDI connected to GND -100 -30 - µA
IMR
MR input Current
MR=0, Vcc = 5V -600 -250 -100 µA
Note: 1. Parameters of room temperature guaranteed by production test and parameters of full-temperature guaranteed by design.
2. Valid for both RESET and RESET. VRST is the Reset threshold voltage when VCC from high to low level, VRN is nominal
reset threshold voltage.
3. WDI is internally serviced within the watchdog period if WDI is left unconnected.
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PT0082(10/10) Ver: 7
7
Data Sheet
PT7A7511-15/7521-25/7531-35
µP Supervisor Circuits
AC Electrical Characteristics
Symbol Description Test Conditions Min Typ Max Unit
tRS Reset Pulse Width
MR from low to High, TA=25℃ 160 200 280 ms
tWD Watchdog Timeout Period
WDI, MR tied to Vcc, Vcc>VRN+5% ,
TA=25℃ 1.2 1.6 2.25 s
tMR
MR Pulse Width - 200 - - ns
tMD
MR to RESET Delay Vcc=5V - - 250 ns
tWP WDI Pulse Width - 150 - - ns
Watchdog Timing Diagram
t
WP
t
WD
t
WD
t
WD
t
RS
WDI
WDO
RESET
RESET
5V
0V
5V
0V
5V
0V
5V
0V
Externally
Triggered by MR
Watchdog Timing Diagram
V
RT
t
RS
t
RS
t
MR
t
MD
WDO
RESET
MR
5V
0V
V
RT
V
CC
5V
0V
5V
0V
5V
0V
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PT0082(10/10) Ver: 7
8
Data Sheet
PT7A7511-15/7521-25/7531-35
µP Supervisor Circuits
Mechanical Information
WE (Lead free and Green SOIC-8)
PE (Lead free DIP-8)
X.XX
X.XX DENOTES DIMENSIONS
IN MILLIMETERS
N
ote:
1) Controlling dimensions in inches.
2) Ref: JEDEC MS-001 BA
1
8
.355
.400
9.01
10.16
.240
.280
6.09
7.11
7.62
8.25
.300
.325
.008
.014
0.20
0.35 .430
Max
0O
15o
10.92
2.54
5.33
.210
Max
SEATING
PLANE
.014
.022
.115
.150
.356
.558
2.921
3.81
.100
typical
.015 Min 0.381
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
N
ote:
1) Controlling dimens ions in millimeters .
2) Ref: JEDEC MS-012 A A
SEATING PLANE
1
8
.189
.196 4.80
5.00
.149
.157
3.78
3.99
.016
.026
0.406
0.660
REF
.050
BS
C
1.27
.013
.020
0.330
0.508
.0040
.0098 0.10
0.25
.053
.068 1.35
1.75
.0099
.0196
0.25
0.50 x 45o
0-8o
.016
.050
0.40
1.27
.0075
.0098
0.19
0.25
.2284
.2440
5.80
6.20
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PT0082(10/10) Ver: 7
9
Data Sheet
PT7A7511-15/7521-25/7531-35
µP Supervisor Circuits
Notes
Email: support@pti.com.cn Web Site: www.pti.com.cn, www.pti-ic.com
China: No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China
Tel: (86)-21-6485 0576 Fax: (86)-21-6485 2181
Asia Pacific: Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong
Tel: (852)-2243 3660 Fax: (852)- 2243 3667
U.S.A.: 3545 North First Street, San Jo se, California 95134, USA
Tel: (1)-408-435 0800 Fax: (1)-408-435 1100
Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or
performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of any circuitry described other than the
circuitry embodied in Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other
rights, of Pericom Technology Incorporation.
