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FEATURES
DESCRIPTION/ORDERING INFORMATION
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
TOE
D1
A1
GND
Y1
A2
VCC
D2
A3
GND
Y2
A4
D3
A5
GND
Y3
A6
VCC
D4
A7
GND
A8
Y4
LE
DIR
B1
Q1
GND
B2
Q2
VCC
B3
Q3
GND
B4
Q4
B5
Q5
GND
B6
Q6
VCC
B7
Q7
GND
Q8
B8
LOE
SN74ALVCH169738-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCHWITH FOUR INDEPENDENT BUFFERS
SCES435B – APRIL 2003 – REVISED SEPTEMBER 2004
•Member of the Texas Instruments Widebus™Family
•Bus Hold on Data Inputs Eliminates the Needfor External Pullup/Pulldown Resistors•Latch-Up Performance Exceeds 250 mA PerJESD 17•ESD Protection Exceeds JESD 22– 2000-V Human-Body Model (A114-A)– 200-V Machine Model (A115-A)– 1000-V Charged-Device Model (C101)
This device contains four independent noninvertingbuffers and an 8-bit noninverting bus transceiver andD-type latch, designed for 1.65-V to 3.6-V V
CCoperation.
The SN74ALVCH16973 is particularly suitable fordemultiplexing an address/data bus into a dedicatedaddress bus and dedicated data bus. The device isused where there is asynchronous bidirectionalcommunication between the A and B data bus, andthe address signals are latched and buffered on theQ bus. The control-function implementation minimizesexternal timing requirements.
This device can be used as one 4-bit buffer, one 8-bittransceiver, or one 8-bit latch. It allows datatransmission from the A bus to the B bus or from theB bus to the A bus, depending on the logic level atthe direction-control (DIR) input. The transceiveroutput-enable ( TOE) input can be used to disable thetransceivers so that the A and B buses effectively areisolated.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
Tube SN74ALVCH16973DLSSOP - DL ALVCH16973Tape and reel SN74ALVCH16973DLR-40 °C to 85 °C
TSSOP - DGG Tape and reel SN74ALVCH16973DGGR ALVCH16973TVSOP - DGV Tape and reel SN74ALVCH16973DGVR VH973
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2004, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
SN74ALVCH16973
8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCHWITH FOUR INDEPENDENT BUFFERS
SCES435B – APRIL 2003 – REVISED SEPTEMBER 2004
When the latch-enable (LE) input is high, the Q outputs follow the data (A) inputs. When LE is taken low, the Qoutputs are latched at the levels set up at the A inputs. The latch output-enable ( LOE) input can be used to placethe nine Q outputs in either a normal logic state (high or low logic level) or the high-impedance state. In thehigh-impedance state, the Q outputs neither drive nor load the bus lines significantly. LOE does not affectinternal operations of the latch. Old data can be retained or new data can be entered while the Q outputs are inthe high-impedance state.
To ensure the high-impedance state during power up or power down, LOE and TOE should be tied to V
CCthrough pullup resistors; the minimum values of the resistors are determined by the current-sinking capability ofthe drivers.
The four independent noninverting buffers perform the Boolean function Y = D and are independent of the stateof DIR, TOE, LE, and LOE.
The A and B I/Os and D inputs have bus-hold circuitry. Active bus-hold circuitry holds unused or undriven datainputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
FUNCTION TABLES
INPUTS
OPERATIONTOE DIR
L L B data to A busL H A data to B busA bus and B busH X
isolation
INPUTS
OUTPUT
QLOE LE A
L H H HL H L LL L X Q
0
H X X Z
INPUT OUTPUTD Y
L LH H
2
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LOE
DIR
To Seven Other Channels
Q1
C1
1D
LE
A1
B1
TOE
48
25
24
3
1
46
47
D1 2 5 Y1
One of Eight Channels
One of Four Channels
SN74ALVCH169738-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCHWITH FOUR INDEPENDENT BUFFERS
SCES435B – APRIL 2003 – REVISED SEPTEMBER 2004
LOGIC DIAGRAM (POSITIVE LOGIC)
3
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ABSOLUTE MAXIMUM RATINGS
(1)
RECOMMENDED OPERATING CONDITIONS
(1)
SN74ALVCH16973
8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCHWITH FOUR INDEPENDENT BUFFERS
SCES435B – APRIL 2003 – REVISED SEPTEMBER 2004
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range -0.5 4.6 VExcept I/O and D input ports
(2)
-0.5 4.6V
I
Input voltage range VI/O and D input ports
(2) (3)
-0.5 V
CC
+ 0.5V
O
Output voltage range
(2) (3)
-0.5 V
CC
+ 0.5 VI
IK
Input clamp current V
I
< 0 -50 mAI
OK
Output clamp current V
O
< 0 -50 mAI
O
Continuous output current ±50 mAContinuous current through each V
CC
or GND ±100 mADGG package 70θ
JA
Package thermal impedance
(4)
DGV package 58 °C/WDL package 63T
stg
Storage temperature range -65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3) This value is limited to 4.6 V maximum.(4) The package thermal impedance is calculated in accordance with JESD 51-7.
MIN MAX UNIT
V
CC
Supply voltage 1.65 3.6 VV
CC
= 1.65 V to 1.95 V 0.65 ×V
CC
V
IH
High-level input voltage V
CC
= 2.3 V to 2.7 V 1.7 VV
CC
= 3 V to 3.6 V 2V
CC
= 1.65 V to 1.95 V 0.35 ×V
CC
V
IL
Low-level input voltage V
CC
= 2.3 V to 2.7 V 0.7 VV
CC
= 3 V to 3.6 V 0.8V
I
Input voltage 0 V
CC
VV
O
Output voltage 0 V
CC
VV
CC
= 1.65 V -4V
CC
= 2.3 V -12I
OH
High-level output current mAV
CC
= 2.7 V -12V
CC
= 3 V -24V
CC
= 1.65 V 4V
CC
= 2.3 V 12I
OL
Low-level output current mAV
CC
= 2.7 V 12V
CC
= 3 V 24∆t/ ∆v Input transition rise or fall rate 10 ns/VT
A
Operating free-air temperature -40 85 °C
(1) All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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ELECTRICAL CHARACTERISTICS
SN74ALVCH169738-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCHWITH FOUR INDEPENDENT BUFFERS
SCES435B – APRIL 2003 – REVISED SEPTEMBER 2004
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
I
OH
= -100 µA 1.65 V to 3.6 V V
CC
- 0.2I
OH
= -4 mA 1.65 V 1.2I
OH
= -6 mA 2.3 V 2V
OH
2.3 V 1.7 VI
OH
= -12 mA 2.7 V 2.23 V 2.4I
OH
= -24 mA 3 V 2I
OL
= 100 µA 1.65 V to 3.6 V 0.2I
OL
= 4 mA 1.65 V 0.45I
OL
= 6 mA 2.3 V 0.4V
OL
V2.3 V 0.7I
OL
= 12 mA
2.7 V 0.4I
OL
= 24 mA 3 V 0.55I
I
V
I
= V
CC
or GND 3.6 V ±5µAV
I
= 0.57 V 1.65 V 25I
BHL
(2)
V
I
= 0.7 V 2.3 V 45 µAV
I
= 0.8 V 3 V 75V
I
= 1.07 V 1.65 V -25I
BHH
(3)
V
I
= 1.7 V 2.3 V -45 µAV
I
= 2 V 3 V -751.95 V 200I
BHLO
(4)
V
I
= 0 to V
CC
2.7 V 300 µA3.6 V 5001.95 V -200I
BHHO
(5)
V
I
= 0 to V
CC
2.7 V -300 µA3.6 V -500I
OZ
(6)
V
O
= V
CC
or GND 3.6 V ±10 µAI
CC
V
I
= V
CC
or GND, I
O
= 0 3.6 V 30 µAOne input at V
CC
- 0.6 V,∆I
CC
3 V to 3.6 V 750 µAOther inputs at V
CC
or GNDControl inputs 3C
i
V
I
= V
CC
or GND 3.3 V pFD 4A ports 4.5C
io
V
O
= V
CC
or GND 3.3 V pFB ports 4.5C
o
Q V
O
= V
CC
or GND 3.3 V 3 pF
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25 °C.(2) The bus-hold circuit can sink at least the minimum low sustaining current at V
IL
max. I
BHL
should be measured after lowering V
IN
to GNDand then raising it to V
IL
max.(3) The bus-hold circuit can source at least the minimum high sustaining current at V
IH
min. I
BHH
should be measured after raising V
INto V
CC
and then lowering it to V
IH
min.(4) An external driver must source at least I
BHLO
to switch this node from low to high.(5) An external driver must sink at least I
BHHO
to switch this node from high to low.(6) For I/O ports, the parameter I
OZ
includes the input leakage current.
5
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TIMING REQUIREMENTS
SWITCHING CHARACTERISTICS
SN74ALVCH16973
8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCHWITH FOUR INDEPENDENT BUFFERS
SCES435B – APRIL 2003 – REVISED SEPTEMBER 2004
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
V
CC
= 2.5 V V
CC
= 3.3 VV
CC
= 1.8 V
±0.2 V ±0.3 V
UNITMIN MAX MIN MAX MIN MAX
t
w
Pulse duration, LE high 2 2 2 nst
su
Setup time, data before LE ↓0.9 0.9 0.9 nst
h
Hold time, data after LE ↓0.9 0.9 0.9 ns
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
V
CC
= 2.5 V V
CC
= 3.3 VV
CC
= 1.8 VFROM TO
±0.2 V ±0.3 VPARAMETER UNIT(INPUT) (OUTPUT)
TYP MIN MAX MIN MAX
D Y 2.2 0.5 3.2 0.5 3A 2.2 0.5 3.2 0.5 3t
pd
Q nsLE 2.8 0.5 3.3 0.5 3A or B B or A 2.2 0.5 3.2 0.5 3LOE Q 2.9 0.7 4.9 0.7 4.7t
en
TOE 3 0.7 4.6 0.7 4.4 nsA or BDIR 3.4 0.7 4.9 0.7 4.7LOE Q 2.8 0.5 4.3 0.5 4.1t
dis
TOE 3.2 0.5 4.3 0.5 4.1 nsA or BDIR 3.4 0.5 4.9 0.5 4.7
6
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OPERATING CHARACTERISTICS
(1)
SN74ALVCH169738-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCHWITH FOUR INDEPENDENT BUFFERS
SCES435B – APRIL 2003 – REVISED SEPTEMBER 2004
T
A
= 25 °C
V
CC
= 1.8 V V
CC
= 2.5 V V
CC
= 3.3 VPARAMETER TEST CONDITIONS UNITTYP TYP TYP
One f
A
= 10 MHz,One f
B
= 10 MHz,A outputs enabled,
TOE = GND,Q outputs disabled, 12 14 19LOE = V
CC
,One A output switching
DIR = GND,C
L
= 0 pFOne f
A
= 10 MHz,One f
B
= 10 MHz,B outputs enabled,
TOE = GND,Q outputs disabled, 12 14 21LOE = V
CC
,One B output switching
DIR = GND,C
pd
(2)
Power dissipation
C
L
= 0 pF
pF(each output) capacitance
One f
A
= 10 MHz,One f
LE
= 20 MHz,Q outputs enabled,
One f
Q
= 10 MHz,A and B I/Os isolated, 11 13 19TOE = V
CC
,One Q output switching
LOE = GND,C
L
= 0 pFOne f
D
= 10 MHz,One Y output switching, One f
Y
= 10 MHz,A and B I/Os isolated, TOE = V
CC
, 7 8 12Q outputs disabled LOE = V
CC
,C
L
= 0 pFOne f
A
= 10 MHz,A and B I/Os isolated, One f
LE
= 20 MHz,Power dissipation Q outputs disabled, f
Q
not switching,C
pd (Z)
4 5 11 pFcapacitance One LE and one A data TOE = V
CC
,input switching LOE = V
CC
,C
L
= 0 pFf
A
not switching,
One f
LE
= 20 MHz,A and B I/Os isolated,C
pd
(3)
Power dissipation f
Q
not switching,Q outputs disabled, 6 7 9 pF(each LE) capacitance TOE = V
CC
,One LE input switching
LOE = V
CC
,C
L
= 0 pF
(1) Total device C
pd
for multiple (m) outputs switching and (n) LE inputs switching = [m * C
pd
(each output)] + [n * C
pd
(each LE)].(2) C
pd
(each output) is the C
pd
for each data bit (input and output circuitry) when it operates at 10 MHz (Note: the LE is operating at20 MHz in this test, but its I
CC
component has been subtracted).(3) C
pd
(each LE) is the C
pd
for the clock circuitry only when it operates at 20 MHz.
7
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PARAMETER MEASUREMENT INFORMATION
VM
VM
VM
VM
VM
VM
VM
VM
VOH
VOL
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1 Open
GND
RL
RL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + V∆
VOH − V∆
0 V
VI
0 V
0 V
tw
VIVI
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
0 V
VI
VM
tPHL
VMVM
VI
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VMVM
tPLH
VLOAD
VLOAD/2
1.8 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
1 kΩ
500 Ω
500 Ω
VCC RL
2 × VCC
2 × VCC
6 V
VLOAD CL
30 pF
30 pF
50 pF
0.15 V
0.15 V
0.3 V
V∆
VCC
VCC
2.7 V
VI
VCC/2
VCC/2
1.5 V
VM
tr/tf
≤2 ns
≤2 ns
≤2.5 ns
INPUT
SN74ALVCH16973
8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCHWITH FOUR INDEPENDENT BUFFERS
SCES435B – APRIL 2003 – REVISED SEPTEMBER 2004
Figure 1. Load Circuit and Voltage Waveforms
8
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
74ALVCH16973DGGRE4 ACTIVE TSSOP DGG 48 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74ALVCH16973DGVRE4 ACTIVE TVSOP DGV 48 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74ALVCH16973DLG4 ACTIVE SSOP DL 48 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74ALVCH16973DLRG4 ACTIVE SSOP DL 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALVCH16973DGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALVCH16973DGVR ACTIVE TVSOP DGV 48 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALVCH16973DL ACTIVE SSOP DL 48 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALVCH16973DLR ACTIVE SSOP DL 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Feb-2006
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040048/E 12/01
48 PINS SHOWN
56
0.730
(18,54)
0.720
(18,29)
4828
0.370
(9,40)
(9,65)
0.380
Gage Plane
DIM
0.420 (10,67)
0.395 (10,03)
A MIN
A MAX
0.010 (0,25)
PINS **
0.630
(16,00)
(15,75)
0.620
0.010 (0,25)
Seating Plane
0.020 (0,51)
0.040 (1,02)
25
24
0.008 (0,203)
0.0135 (0,343)
48
1
0.008 (0,20) MIN
A
0.110 (2,79) MAX
0.299 (7,59)
0.291 (7,39)
0.004 (0,10)
M
0.005 (0,13)
0.025 (0,635)
0°–ā8°
0.005 (0,13)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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