CAT1021LE-30TE13 - Catalyst Semiconductor, Inc.

DESCRIPTION

The CAT1021, CAT1022 and CAT1023 are complete

memory and supervisory solutions for microcontroller-

based systems. A 2k-bit serial EEPROM memory and a

system power supervisor with brown-out protection are

integrated together in low power CMOS technology.

Memory interface is via a 400kHz I2C bus.

The CAT1021 and CAT1023 provide a precision VCC

sense circuit and two open drain outputs: one (RESET)

drives high and the other (RESET) drives low whenever

VCC falls below the reset threshold voltage. The CAT1022

has only a RESET output and does not have a Write

Protect input. The CAT1021 also has a Write Protect

input (WP). Write operations are disabled if WP is

connected to a logic high.

All supervisors have a 1.6 second watchdog timer circuit

that resets a system to a known state if software or a

hardware glitch halts or “hangs” the system. For the

CAT1021 and CAT1022, the watchdog timer monitors

the SDA signal. The CAT1023 has a separate watchdog

timer interrupt input pin, WDI.

CAT1021, CAT1022, CAT1023

Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset

and Watchdog Timer

FEATURES

■Precision power supply voltage monitor

— 5V, 3.3V and 3V systems

— Five threshold voltage options

■Watchdog timer

■Active high or low reset

— Valid reset guaranteed at VCC = 1 V

■400kHz I2C bus

■2.7V to 5.5V operation

■Low power CMOS technology

■16-Byte page write buffer

■Built-in inadvertent write protection

— WP pin (CAT1021)

■1,000,000 Program/Erase cycles

■Manual reset input

■100 year data retention

■8-pin DIP, SOIC, TSSOP, MSOP or TDFN

(3 x 4.9 mm & 3 x 3 mm foot-print) packages

— TDFN max height is 0.8mm

■Industrial and extended temperature ranges

Characteristics subject to change without notice Doc No. 3009, Rev. G

The power supply monitor and reset circuit protect memory

and system controllers during power up/down and against

brownout conditions. Five reset threshold voltages support

5V, 3.3V and 3V systems. If power supply voltages are out

of tolerance reset signals become active, preventing the

system microcontroller, ASIC or peripherals from operating.

Reset signals become inactive typically 200 ms after the

supply voltage exceeds the reset threshold level. With both

active high and low reset signals, interface to microcontrollers

and other ICs is simple. In addition, the RESET pin or a

separate input, MR, can be used as an input for push-button

manual reset capability.

The on-chip, 2k-bit EEPROM memory features a 16-byte

page. In addition, hardware data protection is provided by a

VCC sense circuit that prevents writes to memory whenever

VCC falls below the reset threshold or until VCC reaches the

reset threshold during power up.

Available packages include an 8-pin DIP and surface mount

8-pin SO, 8-pin TSSOP, 8-pin TDFN and 8-pin MSOP

packages. The TDFN package thickness is 0.8mm maximum.

TDFN footprint options are 3x3mm or 3x4.9mm (MSOP pad

layout).

Preliminary Information

CAT1021, CAT1022, CAT1023 Preliminary Information

Doc. No. 3009, Rev. G

BLOCK DIAGRAM Part Dash Minimum Maximum

Number Threshold Threshold

-45 4.50 4.75

-42 4.25 4.50

-30 3.00 3.15

-28 2.85 3.00

-25 2.55 2.70

Threshold Voltage Options

PIN CONFIGURATION

(Bottom View)

TDFN Package: 3mm x 4.9mm

0.8mm maximum height - (RD2, ZD2)

(Bottom View)

TDFN Package: 3mm x 3mm

0.8mm maximum height - (RD4, ZD4)

MR VCC

RESET

SCL

SDA

RESET

VSS

CAT1021

MR VCC

SCL

SDA

RESET

VSS

CAT1022

MR VCC

SCL

SDA

RESET

VSS

CAT1023

VCC

WDI

RESET

VCC

RESET

SCL

SDA

RESE

VSS

CAT1021

VCC

SCL

SDA

RESE

VSS

CAT1022

CAT1023

VCC

WDI

SCL

SDA

RESE

VSS

VCC

SCL

SDA

RESE

VSS

CAT1022

VCC

WDI

SCL

SDA

RESE

RESET

VSS

CAT1023

VCC

RESET

SCL

SDA

RESE

VSS

CAT1021

2kbit

DOUT

ACK

SENSE AMPS

SHIFT REGISTERS

CONTROL

LOGIC

WORD ADDRESS

BUFFERS

START/STOP

LOGIC

EEPROM

VCC

EXTERNAL LOAD

COLUMN

DECODERS

XDEC

DATA IN STORAGE

HIGH V OL TAGE/

TIMING CONTROL

VSS

SDA

RESET Controller

Precision

Vcc Monitor

STATE COUNTERS

SLAVE

ADDRESS

COMPARATORS

RESET RESET

(CAT1021)

(CAT1021/23) WDI

(CAT1023)

DIP Package (P, L)

SOIC Package (S, V)

TSSOP Package (U, Y)

MSOP Package (R, Z)

Preliminary Information CAT1021, CAT1022, CAT1023

Doc No. 3009, Rev. G

PIN DESCRIPTION

RESET/RESETRESET

RESETRESET

RESET: RESET OUTPUTS

(RESET CAT1021/23 Only)

These are open drain pins and RESET can be used as a

manual reset trigger input. By forcing a reset condition on

the pin the device will initiate and maintain a reset condition.

The RESET pin must be connected through a pull-down

resistor, and the RESET pin must be connected through a

pull-up resistor.

SDA: SERIAL DATA ADDRESS

The bidirectional serial data/address pin is used to transfer

all data into and out of the device. The SDA pin is an open

drain output and can be wire-ORed with other open drain

or open collector outputs.

SCL: SERIAL CLOCK

Serial clock input.

PIN FUNCTIONS

Pin Name Function

NC No Connect

RESET Active Low Reset Input/Output

VSS Ground

SDA Serial Data/Address

SCL Clock Input

RESET Active High Reset Output (CAT1021/23)

VCC Power Supply

WP Write Protect (CAT1021 only)

MR Manual Reset Input

WDI Watchdog Timer Interrupt (CAT1023)

CAT102X FAMILY OVERVIEW

For supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163

data sheets.

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OPERATING TEMPERATURE RANGE

Industrial -40˚C to 85˚C

Extended -40˚C to 125˚C

MR:MR:

MR: MANUAL RESET INPUT

Manual Reset input is a debounced input that can be

connected to an external source for Manual Reset.

Pulling the MR input low will generate a Reset condition.

Reset outputs are active while MR input is low and for

the reset timeout period after MR returns to high. The

input has an internal pull up resistor.

WP (CAT1021 Only): WRITE PROTECT INPUT

When WP input is tied to VSS or left unconnected write

operations to the entire array are allowed. When tied to

VCC, the entire array is protected. This input has an

internal pull down resistor.

WDI (CAT1023 Only): WATCHDOG TIMER INTERRUPT

Watchdog Timer Interrupt Input is used to reset the

watchdog timer . If a transition from high to low or low to

high does not occur every 1.6 seconds, the RESET

outputs will be driven active.

CAT1021, CAT1022, CAT1023 Preliminary Information

Doc. No. 3009, Rev. G

ABSOLUTE MAXIMUM RATINGS

Temperature Under Bias ................. –55°C to +125°C

Storage Temperature....................... –65°C to +150°C

Voltage on any Pin with

Respect to Ground(1) ........... –2.0 V to VCC + 2.0 V

VCC with Respect to Ground ................ –2.0V to 7.0 V

Package Power Dissipation

Capability (TA = 25°C).................................. 1.0 W

Lead Soldering Temperature (10 secs)............ 300°C

Output Short Circuit Current(2) ........................ 100 mA

Stresses above those listed under “Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions

outside of those listed in the operational sections of this specification

is not implied. Exposure to any absolute maximum rating for extended

periods may affect device performance and reliability.

Note:

(1) The minimum DC input voltage is –0.5V. During transitions,

inputs may undershoot to

–2.0V for periods of less than 20 ns. Maximum DC voltage on

output pins is VCC +0.5V, which may overshoot to VCC +2.0V

for periods of less than 20 ns.

(2) Output shorted for no more than one second. No more than

one output shorted at a time.

Notes:

1. VIL min and VIH max are reference values only and are not tested.

2. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.

DC OPERATING CHARACTERISTICS

VCC = 2.7V to 5.5V and over the recommended temperature conditions unless otherwise specified.

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Preliminary Information CAT1021, CAT1022, CAT1023

Doc No. 3009, Rev. G

CAPACITANCE

TA = 25°C, f = 1.0 MHz, VCC = 5V

Symbol Test Test Conditions Max Units

COUT(1) Output Capacitance VOUT = 0V 8 pF

CIN(1) Input Capacitance VIN = 0V 6 pF

AC CHARACTERISTICS

VCC = 2.7 V to 5.5 V and over the recommended temperature conditions, unless otherwise specified.

Notes:

1. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.

2. Test Conditions according to “AC Test Conditions” table.

3. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the

write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.

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CAT1021, CAT1022, CAT1023 Preliminary Information

Doc. No. 3009, Rev. G

RESET CIRCUIT AC CHARACTERISTICS

Notes:

1. Test Conditions according to “AC Test Conditions” table.

2. Power-up, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table

3. Power-Down, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table

4. VCC Glitch Reference Voltage = VTHmin; Based on characterization data

5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.

6. tPUR and tPUW are the delays required from the time VCC is stable until the specified memory operation can be initiated.

7. Latch-up protection is provided for stresses up to 100 mA on input and output pins from -1 V to VCC + 1 V.

AC TEST CONDITIONS

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RELIABILITY CHARACTERISTICS

Symbol Parameter Reference Test Method Min Max Units

NEND(5) Endurance MIL-STD-883, Test Method 1033 1,000,000 Cycles/Byte

TDR(5) Data Retention MIL-STD-883, Test Method 1008 100 Years

VZAP(5) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts

ILTH(5)(7) Latch-Up JEDEC Standard 17 100 mA

Preliminary Information CAT1021, CAT1022, CAT1023

Doc No. 3009, Rev. G

embedded EEPROM is disabled for all operations,

including write operations. If the Reset output(s) are

active, in progress communications to the EEPROM are

aborted and no new communications are allowed. In this

condition an internal write cycle to the memory can not be

started, but an in progress internal non-volatile memory

write cycle can not be aborted. An internal write cycle

initiated before the Reset condition can be successfully

finished if there is enough time (5ms) before VCC reaches

the minimum value of 2V.

In addition, the CA T1021 includes a Write Protection Input

which when tied to VCC will disable any write operations

to the device.

Watchdog Timer

The Watchdog Timer provides an independent protection

for microcontrollers. During a system failure, CAT1021/

22/23 devices will provide a reset signal after a time-out

interval of 1.6 seconds for a lack of activity. The CAT1023

is designed with the Watchdog timer feature on the WDI

pin. The CAT1021 and CAT1022 monitor the SDA line. If

WDI or SDA does not toggle within a 1.6 second interval,

the reset condition will be generated on the reset outputs.

The watchdog timer is cleared by any transition on a

monitored line.

As long as reset signal is asserted, the watchdog timer

will not count and will stay cleared.

DEVICE OPERATION

Reset Controller Description

The CAT1021/22/23 precision RESET controllers ensure

correct system operation during brownout and power

up/down conditions. They are configured with open

drain RESET outputs.

During power-up, the RESET outputs remain active

until VCC reaches the VTH threshold and will continue

driving the outputs for approximately 200ms (tPURST)

after reaching VTH. After the tPURST timeout interval, the

device will cease to drive the reset outputs. At this point

the reset outputs will be pulled up or down by their

respective pull up/down resistors.

During power-down, the RESET outputs will be active

when VCC falls below VTH. The RESET output will be

valid so long as VCC is >1.0V (VRVALID). The device is

designed to ignore the fast negative going VCC transient

pulses (glitches).

Reset output timing is shown in Figure 1.

Manual Reset Operation

The RESET pin can operate as reset output and manual

reset input. The input is edge triggered; that is, the

RESET input will initiate a reset timeout after detecting

a high to low transition.

When RESET I/O is driven to the active state, the 200

msec timer will begin to time the reset interval. If external

reset is shorter than 200 ms, Reset outputs will remain

active at least 200 ms.

The CAT1021/22/23 also have a separate manual reset

input. Driving the MR input low by connecting a

pushbutton (normally open) from MR pin to GND will

generate a reset condition. The input has an internal pull

up resistor.

Reset remains asserted while MR is low and for the

Reset Timeout period after MR input has gone high.

Glitches shorter than 100 ns on MR input will not

generate a reset pulse. No external debouncing circuits

are required. Manual reset operation using MR input is

shown in Figure 2.

Hardware Data Protection

The CAT1021/22/23 supervisors have been designed

to solve many of the data corruption issues that have

long been associated with serial EEPROMs. Data

corruption occurs when incorrect data is stored in a

memory location which is assumed to hold correct data.

Whenever the device is in a Reset condition, the

CAT1021, CAT1022, CAT1023 Preliminary Information

Doc. No. 3009, Rev. G

Figure 2. MRMR

MRMR

MR Operation and Timing

RESET

tMRD tPURST

tMRW

Figure 1. RESET Output Timing

GLITCH

CC PURST

PURST

RPD

RVALID

RESET

RPD

Preliminary Information CAT1021, CAT1022, CAT1023

Doc No. 3009, Rev. G

EMBEDDED EEPROM OPERATION

The CAT1021/22/23 feature a 2kbit embedded serial

EEPROM that supports the I2C Bus data transmission

protocol. This Inter-Integrated Circuit Bus protocol defines

any device that sends data to the bus to be a transmitter

and any device receiving data to be a receiver. The

transfer is controlled by the Master device which

generates the serial clock and all START and STOP

conditions for bus access. Both the Master device and

Slave device can operate as either transmitter or receiver,

but the Master device controls which mode is activated.

I2C Bus Protocol

The features of the I2C bus protocol are defined as

follows:

(1) Data transfer may be initiated only when the bus is

not busy.

(2) During a data transfer, the data line must remain

stable whenever the clock line is high. Any changes in

the data line while the clock line is high will be interpreted

as a START or STOP condition.

START Condition

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of

SDA when SCL is HIGH. The CAT1021/22/23 monitor

the SDA and SCL lines and will not respond until this

condition is met.

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must end

with a STOP condition.

DEVICE ADDRESSING

The Master begins a transmission by sending a START

condition. The Master sends the address of the particular

slave device it is requesting. The four most significant

bits of the 8-bit slave address are programmable in metal

and the default is 1010.

The last bit of the slave address specifies whether a

Read or Write operation is to be performed. When this bit

is set to 1, a Read operation is selected, and when set

to 0, a Write operation is selected.

After the Master sends a START condition and the slave

address byte, the CAT1021/22/23 monitors the bus and

responds with an acknowledge (on the SDA line) when

its address matches the transmitted slave address. The

CAT1021/22/23 then perform a Read or Write operation

depending on the R/W bit.

tWR

STOP

CONDITION START

CONDITION ADDRESS

ACK8TH BIT

BYTE n

SCL

SDA

Figure 4. Write Cycle Timing

tHIGH

SCL

SDA IN

SDA OUT

tLOW

tFtLOW

tBUF

tSU:STO

tSU:DAT

tHD:DAT

tHD:STA

tSU:STA

tAA tDH

Figure 3. Bus Timing

CAT1021, CAT1022, CAT1023 Preliminary Information

Doc. No. 3009, Rev. G

ACKNOWLEDGE

After a successful data transfer, each receiving device

is required to generate an acknowledge. The

acknowledging device pulls down the SDA line during

the ninth clock cycle, signaling that it received the 8 bits

of data.

All devices respond with an acknowledge after receiving

a START condition and its slave address. If the device

has been selected along with a write operation, it

responds with an acknowledge after receiving each 8-

bit byte.

When a device begins a READ mode it transmits 8 bits

of data, releases the SDA line and monitors the line for

an acknowledge. Once it receives this acknowledge, the

device will continue to transmit data. If no acknowledge

is sent by the Master, the device terminates data

transmission and waits for a STOP condition.

WRITE OPERATIONS

Byte Write

In the Byte Write mode, the Master device sends the

START condition and the slave address information (with

the R/W bit set to zero) to the Slave device. After the Slave

generates an acknowledge, the Master sends a 8-bit

address that is to be written into the address pointers of

the device. After receiving another acknowledge from the

Slave, the Master device transmits the data to be written

into the addressed memory location. The device

acknowledges once more and the Master generates the

STOP condition. At this time, the device begins an

internal programming cycle to non-volatile memory. While

the cycle is in progress, the device will not respond to any

request from the Master device.

Figure 7. Slave Address Bits

CAT

Default Configuration

1010000R/W

START BIT

SDA

STOP BIT

SCL

Figure 5. Start/Stop Timing

ACKNOWLEDGE

START

SCL FROM

MASTER 89

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

Figure 6. Acknowledge Timing

Preliminary Information CAT1021, CAT1022, CAT1023

Doc No. 3009, Rev. G

Page Write

The CAT1021/22/23 writes up to 16 bytes of data in a

single write cycle, using the Page Write operation. The

page write operation is initiated in the same manner as

the byte write operation, however instead of terminating

after the initial byte is transmitted, the Master is allowed

to send up to 15 additional bytes. After each byte has

been transmitted, the CAT1021/22/23 will respond with

an acknowledge and internally increment the lower order

address bits by one. The high order bits remain

unchanged.

If the Master transmits more than 16 bytes before sending

the STOP condition, the address counter ‘wraps around,’

and previously transmitted data will be overwritten.

When all 16 bytes are received, and the STOP condition

has been sent by the Master, the internal programming

cycle begins. At this point, all received data is written to

the CAT1021/22/23 in a single write cycle.

BYTE

ADDRESS

SLAVE

ADDRESS

DATA

BUS ACTIVITY :

MASTER

SDA LINE

Figure 8. Byte Write Timing

Figure 9. Page Write Timing

BUS A CTIVITY :

MASTER

SDA LINE

DATA n+15

BYTE

ADDRESS (n)

DATA n

DATA n+1

SLAVE

ADDRESS

CAT1021, CAT1022, CAT1023 Preliminary Information

Doc. No. 3009, Rev. G

Acknowledge Polling

Disabling of the inputs can be used to take advantage of

the typical write cycle time. Once the stop condition is

issued to indicate the end of the host’s write opration, the

CAT1021/22/23 initiates the internal write cycle. ACK

polling can be initiated immediately. This involves issuing

the start condition followed by the slave address for a

write operation. If the device is still busy with the write

operation, no ACK will be returned. If a write operation

has completed, an ACK will be returned and the host can

then proceed with the next read or write operation.

WRITE PROTECTION PIN (WP)

The Write Protection feature (CAT1021 only) allows the

user to protect against inadvertent memory array

programming. If the WP pin is tied to VCC, the entire

memory array is protected and becomes read only. The

CAT1021 will accept both slave and byte addresses,

but the memory location accessed is protected from

programming by the device’s failure to send an

acknowledge after the first byte of data is received.

Read Operations

The READ operation for the CAT1021/22/23 is initiated

in the same manner as the write operation with one

exception, the R/W bit is set to one. Three different

READ operations are possible: Immediate/Current

Address READ, Selective/Random READ and

Sequential READ.

SCL

SDA 8TH BIT

STOPNO ACKDATA OUT

SLAVE

ADDRESS

KDATA N

BUS ACTIVITY :

MASTER

SDA LINE

Figure 10. Immediate Address Read Timing

Preliminary Information CAT1021, CAT1022, CAT1023

Doc No. 3009, Rev. G

Immediate/Current Address Read

The CAT1021/22/23 address counter contains the

address of the last byte accessed, incremented by one.

In other words, if the last READ or WRITE access was

to address N, the READ immediately following would

access data from address N + 1. For N = E = 255, the

counter will wrap around to zero and continue to clock

out valid data. After the CAT1021/22/23 receives its

slave address information (with the R/W bit set to one),

it issues an acknowledge, then transmits the 8-bit byte

requested. The master device does not send an

acknowledge, but will generate a STOP condition.

Selective/Random Read

Selective/Random READ operations allow the Master

device to select at random any memory location for a

READ operation. The Master device first performs a

‘dummy’ write operation by sending the START condition,

slave address and byte addresses of the location it

wishes to read. After the CAT1021/22/23 acknowledges,

the Master device sends the START condition and the

slave address again, this time with the R/W bit set to one.

The CAT1021/22/23 then responds with its acknowledge

and sends the 8-bit byte requested. The master device

does not send an acknowledge but will generate a

STOP condition.

Sequential Read

The Sequential READ operation can be initiated by

either the Immediate Address READ or Selective READ

operations. After the CAT1021/22/23 sends the inital 8-

bit byte requested, the Master will responds with an

acknowledge which tells the device it requires more

data. The CAT1021/22/23 will continue to output an 8-bit

byte for each acknowledge, thus sending the STOP

condition.

The data being transmitted from the CAT1021/22/23 is

sent sequentially with the data from address N followed

by data from address N + 1. The READ operation

address counter increments all of the CAT1021/22/23

address bits so that the entire memory array can be read

during one operation.

SLAVE

ADDRESS

BUS ACTIVITY :

MASTER

SDA LINE

BYTE

ADDRESS (n)

KDATA n

SLAVE

ADDRESS

Figure 11. Selective Read Timing

BUS ACTIVITY :

MASTER

SDA LINE

DATA n+xDATA n

DATA n+1

DATA n+2

SLAVE

ADDRESS

Figure 12. Sequential Read Timing

CAT1021, CAT1022, CAT1023 Preliminary Information

Doc. No. 3009, Rev. G

d 0.08 c

f 0.10 c

0.10m C A B

0.15

85A

3.00 + 0.15

2.00 + 0.15

0.10

0.15

0.20

0.25

PIN 1 ID

0.60 + 0.10 (8X)

0.15 c

4.90 + 0.10

(5)

PIN 1 INDEX AREA

3.00 + 0.10

(S)

0.30 + 0.05 (8X)

j1.95 REF. (2x)

0.65 TYP. (6x)

0.75 + 0.05

0.0-0.05

8x 0.20 REF.

NOTE:

1. ALL DIMENSION ARE IN mm. ANGLES IN DEGREES.

2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.

COPLANARITY SHALL NOT EXCEED 0.08mm.

3. WARPAGE SHALL NOT EXCEED 0.10mm.

4. PACKAGE LENGTH / PACKAGE WIDTH ARE CONSIDERED AS SPECIAL

CHARACTERISTIC(S).

5. REFER TO JEDEC MO-229, FOOTPRINTS ARE COMPATIBLE TO 8 MSOP.

TDFN 3X4.9 PACKAGE (RD2)

PACKAGE OUTLINES

Preliminary Information CAT1021, CAT1022, CAT1023

Doc No. 3009, Rev. G

3.00 + 0.10

(S)

3.00 + 0.10

(S)

PIN 1 INDEX AREA

0.75 + 0.05

0.0 - 0.05

0.30 + 0.07 (8x)

0.25 min.

0.75 + 0.05

2.30 + 0.10

C0.35

PIN 1 ID

1.50 + 0.10

1.95 REF. (2x)

0.65 TYP. (6x)

0.30 + 0.10 (8x)

0.15

NOTE:

1. ALL DIMENSION ARE IN mm. ANGLES IN DEGREES.

2. COPLANARITY SHALL NOT EXCEED 0.08 mm.

3. WARPAGE SHALL NOT EXCEED 0.10 mm.

4. PACKAGE LENGTH / PACKAGE WIDTH ARE CONSIDERED AS SPECIAL CHARACTERISTIC(S)

5. REFER JEDEC MO-229 / WEEC

TDFN 3X3 PACKAGE (RD4)

CAT1021, CAT1022, CAT1023 Preliminary Information

Doc. No. 3009, Rev. G

Ordering Information

Note:

(1) The device used in the above example is a CAT1021SI-30TE13 (Supervisory circuit with I2C serial 2k CMOS EEPROM, SOIC, Industrial

Temperature, 3.0-3.15V Reset Threshold Voltage, Tape and Reel).

1021

Temperature Range

I = Industrial (-40˚C to 85˚C)

Prefix Device # Suffix

SI TE13

Product

Number

1021: 2K

Tape & Reel

TE13: 2000/Reel

Package

P: PDIP

S: SOIC

R: MSOP

U: TSSOP

RD2: 8-pad TDFN

(3x4.9mm, MSOP Footprint)

RD4: 8-pad TDFN (3x3mm)

L: PDIP (Lead free, Halogen free)

V: SOIC (Lead free, Halogen free)

Y: TSSOP (Lead free, Halogen free)

Z: MSOP (Lead free, Halogen free)

ZD2: TDFN 3x4.9mm (Lead free, Halogen free)

ZD4: TDFN 3x3mm (Lead free, Halogen free)

-30

CAT

Reset Threshold

Voltage

45: 4.5-4.75V

42: 4.25-4.5V

30: 3.0-3.15V

28: 2.85-3.0V

25: 2.55-2.7V

Optional

Company ID

1022: 2K

1023: 2K

E = Extended (-40˚C to +125˚C)

REVISION HISTORY

Date Rev. Reason

9/25/2003 F Added Green Package logo

Updated DC Operating Characteristic notes

Updated Reliability Characteristics notes

11/7/2003 G Eliminated Automotive temperature range

Updated Ordering Information with “Green” package

codes

Updated Reset Circuit AC Characteristics

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Publication #: 3009

Revison: G

Issue date: 11/10/03

Type: Preliminary