SY84113BU
Low Power 2.5V 1.25Gbps Limiting Post
A mplifier with Ultra Wide LOS Range
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (
408
) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
August 11, 2015
Revision 2.0
hbwhelp@micrel.com or (408) 955-1690
General Description
The SY84113BU low power limiting post amplifier is
designed for use in fiber-optic optical modules for
multirate applications up to 1.25Gbps. The device
connects t o a typical transimpedance amplif ier (TIA) and
can produce output signals to CML-level waveforms.
Intended for the GbE and Fibre Channel applications,
the SY84113BU offers a wide loss-of-signal (LOS)
range. It is able to detect input signals for as low as
5mVpp and as high as 100mVpp. The SY84113BU is
intended to be used in AC-coupled input applications.
The SY84113BU generates a LOS open-collector TTL
output. A pro gramm able LOS level set p in (LOSLVL) sets
the sensitivity of the input amplitude detection. LOS
asserts high if the input amplitude falls below the
threshold set by LOSLVL and de-asserts low otherwise.
The enab le input (/EN) d e-asserts the tru e output sig nal
without removing the input signal. The LOS output can
be fed back to the /EN input to implement the squelch
function that maintains output stability under an LOS
condition.
The SY84113BU operates on a single 2.5V power
supply and offers ultra-low power consumption. This
device is perfectly suited to meet the stringent power
requirements of the CSFP/SFP/SFF optical modules.
All support documentation can be found on Micrel’s
website at: www.micrel.com.
Features
Ultra-wide loss-of-signal (LOS) range (5mVpp to
100mVpp)
Single 2.5V power supply
Ultra-low power consumption (55mW typical)
125Mbps to 1.25 Gbps ope rat ion
Low-noise CML data outputs
TTL /EN input
Programmable LOS level (LOSLVL)
Internal 50 termination
Available in a tin y 3mm × 3mm QFN package
Extensive temperature range (40°C to +95°C)
Applications
Gigabit Ether net
Fibre Channel
GEPON
Markets
Datacom/telecom
Compact SFP/SFF opt ical t r ansc eiv er
SFP/SFF optical tran sceiver
_________________________________________________________________________________________________________
Typical Application
Micrel, Inc.
SY84113BU
, 2015 2
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Ordering Information
Part Number Package Type Operating Range Package Marking Lead Finish
SY84113BUMG QFN-16 Industrial 113B with Pb-Free Bar-Line Indicator NiPdAu Pb-Free
SY84113BUMGTR
(1)
QFN-16 Industrial 113B with Pb-Free Bar-Line Indicator NiPdAu Pb-Free
Notes:
1. Tape and Reel.
Pin Configuration
16-Pin (3mm × 3mm) QFN-16
Pin Description
Pin Number Pin Name Type Pin Function
15 /EN TTL Input /Enable: This input enables the outputs when LOW. Internally
connected to a 25kpull-up resistor and will default to a logic HIGH
state if left open.
1, 4 DIN, /DIN Data Input Differential data inputs. Each input is internally terminated to the VREF
pin by a 50Ω resistor.
6 VREF Reference Voltage: Place 0.1uF capacitor to Vcc to help stabilize
LOSLVL.
14 LOSLVL DC Input Loss-of-Signal Level Set. A resistor from this pin to VCC sets the
threshold for the data input amplitude at which LOS will be asserted.
2, 3, 10,
11, ePad GND Ground Device Ground. Ex posed pad (ePad) must be connected t o PCB ground
plane.
7 LOS Open-Collector
TTL Output Loss-of-signal: asserts high when the data input amplitude falls below
the threshold set by LOSLVL.
12, 9 /DOUT, DOUT CML Output Differential data outputs. Unused output should be terminated 50Ω to
VCC.
5, 8, 13, 16 VCC Positive Rail Positive power supply. . Bypass with a 0.1uF || 0.01uF low-ESR
capacitor as close to VCC pin as possible.
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Absolute Maximum Ratings(2)
Supply Voltage (VCC) ....................................... 0V to +4.0V
Input Voltage (DIN, /DIN) ....................................... 0 to VCC
Output Current (IOUT) ............................................... ±25mA
EN Voltage ............................................................. 0 to VCC
VREF Current ......................................... 800µA to +500µA
LOSLVL Voltage ................................................. VREF to VCC
Lead Temperature (soldering, 20s) .......................... 260°C
Storage Temperature (Ts) ....................... 65°C to +150°C
Operating Ratings(3)
Supply Voltage (VCC) ...................... +2.375 to +2.625 V
Ambient Temperature (TA) .................. 40°C to +95°C
Junction Temperature (TJ) ................ 40°C to +120°C
Package Thermal Resistance(4)
(θJA) Still-Air ................................................ 60°C/W
(ψJB) ............................................................ 33°C/W
DC Electrical Characteristics
VCC = 2.5 ±5%; TA = 40°C to +95°C, typical values at VCC = 2.5V, TA = 25°C.
Symbol Parameter Condition Min. Typ. Max. Units
ICC Power Supply Current Outputs terminated 50 to Vcc 22 35 mA
LOSLVL LOSLVL Voltage VREF VCC V
VOH DOUT, /DOUT
HIGH Voltage VCC0.020 VCC0.005 VCC V
VOL DOUT, /DOUT
LOW Voltage VCC0.475 VCC0.400 VCC0.350 V
VREF Reference Voltage Vcc 0.6 V
Z0 Single-Ended
Output Impedance 40 50 60
ZI Single-Ended
Input Impedance 40 50 60
TTL DC Electrical Characteristics
VCC = 2.5 ±5%; TA = 40°C to +95°C, typical values at VCC = 2.5V, TA = 25°C.
Symbol Parameter Condition Min. Typ. Max. Units
VIH /EN Input HIGH Voltage 2.0 Vcc V
VIL /EN Input LO W Voltage 0.8 V
IIH /EN Input HIGH Current VIN = VCC
20 µA
IIL /EN Input LO W Current VIN = 0.5V 0.3 mA
VOH LOS Output HIGH Level Vcc = 2.5V. IOH < 50uA 2 V
VOL LOS Output LOW Level IOL = 2mA 0.5 V
Notes:
2. Permanent device dam age may occur if absolute maximum ratings are exceeded. This is a stress rating only and funct i onal operati on is not
implied at conditions other than those detailed i n the operational sect i ons of this data sheet. E xposure to absolute maximum ratings conditions
for extended periods may affect device reliabil ity.
3. The datasheet lim its are not guaranteed i f t he device is operated beyond the operating ratings.
4. Package Therm al Resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. ψJB uses a
4-layer and θJA in still air unless otherwise stated.
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AC Electrical Characteristics
VCC = 2.5 ±5%; TA = 40°C to +95°C, typical values at VCC = 2.5V, TA = 25°C.; RLoad = 50Ω to VCC;
Symbol Parameter Condition Min. Typ. Max. Units
tr, tf Output Rise/Fal l Time
(20% to 80%) Note 5 150 260 ps
tJITTER Deterministic
Random Note 6
Note 7 15
5 psPP
psRMS
VID Differential Input Voltage Swing 5 1800 mVPP
VOD Differential Output Voltage Swing Note 5 700 800 950 mVPP
TOFF LOS Release Time Note 10 2 10 µS
TON LOS Assert Time Note 10 2 10 µS
LOSAL Low LOS Assert Level RLOSLVL = 10k
(8)
3.9 mVPP
LOSDL Low LOS De-assert Level RLOSLVL = 10k
(8)
5.6 mVPP
HYSL Low LOS Hysteresis RLOSLVL = 10k
(8)
2 3.1 4.5 dB
LOSAM Medium LOS Assert Level RLOSLVL = 5k
(8)
7 9.2 mVPP
LOSDM Medium LOS De-assert Level RLOSLVL = 5k
(8)
13.6 16 mVPP
HYSM Medium LOS Hysteresis RLOSLVL = 5k
(9)
2 3.4 4.5 dB
LOSAH High LOS Assert Level RLOSLVL = 100
(8)
60 73 mVPP
LOSDH High LOS De-assert Level RLOSLVL = 100
(8)
103 130 mVPP
HYSH High LOS Hysteresis RLOSLVL = 100
(9)
2 3.0 4.5 dB
B-3dB 3dB Bandwidth 850 MHz
AV(Diff) Differential Voltage Gain 38 dB
S21 Single-Ended Small-Signal Gain 26 32 dB
Notes:
5. Ampl ifi er i n limiting mode. I nput is a 200MHz square wave.
6. Determini st ic jitter m easured using 1.250 Gbps K28.5 pattern, VID = 60mVPP.
7. Random jitter m easured using 1.250Gbps K28.7 pattern, VID = 60mVPP.
8. See “Typic al Operati ng Charact eristics” for a graph showing how to choose a particular R LOSLVL for a particular LOS assert and its associated
de-assert amplitude.
9. This specification defines electrical hysteresis as 20log (LOS De-Assert/LOS Assert). The ratio between optical hysteresis and electrical
hysteresis is found to vary between 1.5 and 2 depending upon the level of received optical power and ROSA characteristics. Based on that
ratio, the optic al hysteresis corresponding t o the el ect rical hysteresis range 2dB-4.5 dB, shown in the AC characteristics t abl e, will be 1dB-3dB
Optical Hysteresis.
10. In real world applic ations, the LOS Releas e/Assert time can be strongly influenced by the RC time constant of the AC-coupling cap and the
50Ω input termination. To keep this time low, use a decoupling cap with the lowest value that is allowed by the data rate and the number of
consecuti ve identical bits in the applic ation (t ypical val ues are in the range of 0.001µF to 1.0µF).
Micrel, Inc.
SY84113BU
, 2015 5
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Typical Functional Characteristics
VCC = 2.5 ±5%; TA = 40°C to +95°C, typical values at VCC = 2.5V, TA = 25°C.; RLoad = 50Ω to VCC.
Typical Operating Characteristics
VCC = 2.5 ±5%; TA = 40°C to +95°C, typical values at VCC = 2.5V, TA = 25°C.; RLoad = 50Ω to VCC.
LOS Assert /De-Assert Levels
1
10
100
1000
0.1 110
LO SLVL Resi stor (KOhm )
Ampl it ude ( m V)
LOS Hyst eresis
1
2
3
4
5
6
0.1 110
LO SLVL Resi stor (KOhm )
Hysteresis (dB)
Micrel, Inc.
SY84113BU
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Functional Block Diagram
Micrel, Inc.
SY84113BU
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Functional Description
The SY84113BU is a high-sensitivity limiting post
amplifier that operates f r om a single +2.5V power s upply
over temperatures from 40°C to +85°C. Signals with
data rates up to 1.25Gbps, and as sm all as 5mVpp, c an
be amplified. Figure 1 shows the allowed input voltage
swing. The SY84113BU generates a LOS output signal
that can be fed back to /EN for output stability in the
absence of a signal at the input. LOSLVL sets the
sensitivity of the input amplitude detection. SY84113BU
offers ultra wide LOS detection range. This allows the
device to be used in multiple AC-coupled applications.
Input Amplifier/Buffer
Figure 2 shows a simplified schematic of the input
stage. The high-sensitivity of the input amplifier can
detect and amplify AC-coupled signals as small as
5mVpp to f ull CML output level. T he input stage also c an
allow signals as large as 1800mVpp. Input signals are
amplified with a typically 38dB differential voltage gain
until they reach the limiting mode of the amplifier.
SY84113BU outputs in standard 400mV CML output
levels.
Output Buffer
The SY84113BU’s CML output buffer is designed to
drive 50Ω lines and is internally terminated with 50Ω to
VCC. Figure 3 shows a schematic of the output stage.
Loss-of-Signal (LOS)
The SY84113BU generates a chatter-free LOSs-of-
signal (LOS) open-collector TTL output as shown in
Figure 4. LOS is used to determine that the input
amplitude is too sm all to be cons idered as a valid input.
LOS asserts high if the input amplitude falls below the
threshold set by LOSLVL and de-asserts low other wise.
LOS can be fed back to the enable (/EN) input to
maintain output stability under a LOSs of signal
condition. /EN de-asserts low the true output signal
without removing the input signals. Typically, 3dB LOS
hysteresis is provided to prevent chattering.
LOS Level Set
A programmable LOS level set pin (LOSLVL) sets the
threshold of the input amplitude detection. Connecting
an external resistor between VCC and LOSLVL sets the
voltage at LOSLVL. This voltage ranges from VCC to
VREF. The external resistor creates a voltage divider
between VCC and VREF, as shown in Figure 5.
Hysteresis
The SY84113BU provides typically 3dB LOS electrical
hysteresis, which is defined as 20log (VINLOS-Assert /
VINLOS-De-Assert). Because the relationship between the
voltage out of the ROSA to optical power at its input is
linear, the optical hysteresis will be typically half of the
electrical hysteresis reported in the datasheet, but in
practice the ratio between electrical and optical
hysteresis is f oun d t o be within th e r a nge 1. 5 - 1.8. Thus
3dB electrical hysteresis will correspond to an optical
hysteresis within the range 1.7dB - 2dB.
Micrel, Inc.
SY84113BU
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Figure 1. VIS and VID Definition
Figure 2. Input Structure Figure 3. Output Structure
Figure 4. LOS Output Structure Figure 5. LOSLVL Setting Circuit
Note: Recommended value for RLOSLVL is 15kΩ or less.
Micrel, Inc.
SY84113BU
, 2015 9
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Package Information and Recommended Land Pattern(11)
16-Pin (3mm × 3mm) QFN (QFN-16)
Note:
11. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.
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SY84113BU
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Package Information and Recommended Land Pattern(11) (Continued)
Micrel, Inc.
SY84113BU
, 2015 11
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MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel, Inc. is a leading global manufacturer of IC solutions for the worldwide high performance linear and power, LAN, and timing &
communications markets. The Company’s products include advanced mixed
-signal, analog & power semiconductors; high-
performance
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a
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ormation furnished i n this data
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