M1N25664TUH4A2F / M1N51264TUH8A2F 256MB: 32M x 64 / 512MB: 64M x 64 PC2-5300 Unbuffered DDR2 SO-DIMM 200 pin Unbuffered DDR2 SO-DIMM Based on DDR2-667 32Mx16 SDRAM Features * 200-Pin Small Outline Dual In-Line Memory Module (SO-DIMM) * 32Mx64 and 64Mx64 Unbuffered DDR2 SO-DIMM based on * Data is read or written on both clock edges * DRAM DLL aligns DQ and DQS transitions with clock transitions. 32Mx16 DDR2 SDRAM devices. * Performance: * Address and control signals are fully synchronous to positive clock edge * Programmable Operation: - DIMM CAS Latency: 3, 4, 5 PC2-5300 Unit Speed Sort 3C DIMM CAS Latency 5 fCK 333 MHz tCK 3 ns fDQ 667 MHz - Burst Type: Sequential or Interleave - Burst Length: 4, 8 - Operation: Burst Read and Write * Auto Refresh (CBR) and Self Refresh Modes * Automatic and controlled precharge commands * 13/10/1 Addressing (M1N25664TUH4A2F) * Intended for 333MHz applications * Inputs and outputs are SSTL-18 compatible 13/10/2 Addressing (M1N51264TUH8A2F) * 7.8 s Max. Average Periodic Refresh Interval * VDD = VDDQ = 1.8V 0.1V * SDRAMs have 4 internal banks for concurrent operation * Serial Presence Detect * Gold contacts * Module has one physical bank * Differential clock inputs * SDRAMs in 84-ball FBGA Package Description M1N25664TUH4A2F and M1N51264TUH8A2F are unbuffered 200-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Small Outline Dual InLine Memory Module (SO-DIMM), organized as one rank of 32x64 and two ranks of 64x64 high-speed memory array. Modules use four 32Mx16 (M1N25664TUH4A2F) or eight 32Mx16 (M1N51264TUH8A2F) 84-ball FBGA packaged devices. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All Super Elixir DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 2.66" long space-saving footprint. The DIMM is intended for use in applications operating up to 333 MHz clock speeds and achieves high-speed data transfer rates of up to 667MHz . Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. REV 1.0 06/14/2005 1 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N25664TUH4A2F / M1N51264TUH8A2F 256MB: 32M x 64 / 512MB: 64M x 64 PC2-5300 Unbuffered DDR2 SO-DIMM Ordering Information Part Number M1N25664TUH4A2F- 3C Speed DDR2-667 PC2-5300 333MHz (3ns @ CL = 5) Organization Power 32Mx64 1.8V Leads Note Green Gold M1N51264TUH8A2F- 3C REV 1.0 06/14/2005 DDR2-667 PC2-5300 333MHz (3ns @ CL = 5) 64Mx64 Green 2 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N25664TUH4A2F / M1N51264TUH8A2F 256MB: 32M x 64 / 512MB: 64M x 64 PC2-5300 Unbuffered DDR2 SO-DIMM Pin Description CK0, CK0 Differential Clock Inputs CKE0, CKE1 Data input/output DQS0-DQS7 Bidirectional data strobes DQS0-DQS7 Differential data strobes RAS Row Address Strobe CAS Column Address Strobe WE Write Enable CS0, CS1 Chip Selects DM0-DM7 Input Data Masks Power (1.8V) VDD VREF A0-A12 Row Address Inputs A0-A9 Column Address Inputs A10/AP DQ0-DQ63 Clock Enable Ref. Voltage for SSTL_18 inputs VDDSPD Serial EEPROM positive power supply VSS Ground Column Address Input/Auto-precharge SCL Serial Presence Detect Clock Input BA0, BA1 SDRAM Bank Address Inputs SDA Serial Presence Detect Data input/output ODT0, ODT1 Active termination control lines SA0, SA1 NC Serial Presence Detect Address Inputs No Connect Pinout Pin Front Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 VREF Pin Back 2 VSS 51 DQS2 52 DM2 101 A1 102 A0 151 DQ42 152 DQ46 3 VSS 4 DQ4 53 VSS 54 VSS 103 VDD 104 VDD 153 DQ43 154 DQ47 5 DQ0 6 DQ5 55 DQ18 56 DQ22 105 A10/AP 106 BA1 155 VSS 156 VSS 7 DQ1 8 VSS 57 DQ19 58 DQ23 107 BA0 108 RAS 157 DQ48 158 DQ52 9 VSS 10 DM0 59 VSS 60 VSS 109 WE 110 CS0 159 DQ49 160 DQ53 11 DQS0 12 VSS 61 DQ24 62 DQ28 111 VDD 112 VDD 161 VSS 162 VSS 13 DQS0 14 DQ6 63 DQ25 64 DQ29 113 CAS 114 ODT0 163 NC 164 CK1 15 VSS 16 DQ7 65 VSS 66 VSS 115 CS1 116 (A13) 165 VSS 166 CK1 17 DQ2 18 VSS 67 DM3 68 DQS3 117 VDD 118 VDD 167 DQS6 168 VSS 19 DQ3 20 DQ12 69 NC 70 DQS3 119 ODT1 120 NC 169 DQS6 170 DM6 21 VSS 22 DQ13 71 VSS 72 VSS 121 VSS 122 VSS 171 VSS 172 VSS 23 DQ8 24 VSS 73 DQ26 74 DQ30 123 DQ32 124 DQ36 173 DQ50 174 DQ54 25 DQ9 26 DM1 75 DQ27 76 DQ31 125 DQ33 126 DQ37 175 DQ51 176 DQ55 27 VSS 28 VSS 77 VSS 78 VSS 127 VSS 128 VSS 177 VSS 178 VSS 29 DQS1 30 CK0 79 CKE0 80 CKE1 129 DQS4 130 DM4 179 DQ56 180 DQ60 31 DQS1 32 CK0 81 VDD 82 VDD 131 DQS4 132 VSS 181 DQ57 182 DQ61 33 VSS 34 VSS 83 NC 84 (A15) 133 VSS 134 DQ38 183 VSS 184 VSS 35 DQ10 36 DQ14 85 (BA2) 86 (A14) 135 DQ34 136 DQ39 185 DM7 186 DQS7 37 DQ11 38 DQ15 87 VDD 88 VDD 137 DQ35 138 VSS 187 VSS 188 DQS7 39 VSS 40 VSS 89 A12 90 A11 139 VSS 140 DQ44 189 DQ58 190 VSS 41 VSS 42 VSS 91 A9 92 A7 141 DQ40 142 DQ45 191 DQ59 192 DQ62 43 DQ16 44 DQ20 93 A8 94 A6 143 DQ41 144 VSS 193 VSS 194 DQ63 45 DQ17 46 DQ21 95 VDD 96 VDD 145 VSS 146 DQS5 195 SDA 196 VSS 47 VSS 48 VSS 97 A5 98 A4 147 DM5 148 DQS5 197 SCL 198 SA0 49 DQS2 50 NC 99 A3 100 A2 149 VSS 150 VSS 199 VDDSPD 200 SA1 Note: All pin assignments are consistent for all 8-byte unbuffered versions. REV 1.0 06/14/2005 3 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N25664TUH4A2F / M1N51264TUH8A2F 256MB: 32M x 64 / 512MB: 64M x 64 PC2-5300 Unbuffered DDR2 SO-DIMM Input/Output Functional Description Symbol Type Polarity Function CK0 (SSTL) The positive line of the differential pair of system clock inputs which drives the input to Positive the on-DIMM PLL. All the DDR2 SDRAM address and control inputs are sampled on the Edge rising edge of their associated clocks. CK0 (SSTL) Negative The negative line of the differential pair of system clock inputs which drives the input to Edge the on-DIMM PLL. CKE0, CKE1 (SSTL) Active High Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. CS0, CS1 (SSTL) Active Low Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS, CAS, WE (SSTL) Active Low When sampled at the positive rising edge of the clock, RAS, CAS, WE define the operation to be executed by the SDRAM. VREF Supply Reference voltage for SSTL-18 inputs ODT0, ODT1 Input Active High BA0, BA1 (SSTL) - Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9, A11 defines the column address (CA0CA10) when sampled at the rising clock edge. In addition to the column address, AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to precharge. A0 - A9 A10/AP A11, A12 (SSTL) - DQ0 - DQ63 CB0 - CB7 (SSTL) Active High VDD, VSS Supply DQS0 - DQS7 DQS0 - DQS7 (SSTL) DM0 - DM7 Input On-Die Termination control signals Data and Check Bit Input/Output pins. Check bits are only applicable on the x72 DIMM configurations. Power and ground for the DDR2 SDRAM input buffers and core logic Negative and Data strobe for input and output data Positive Edge Active High The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not used on x64 modules. SA0 - SA2 - Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. SDA - This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DD to act as a pull-up. SCL - This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pull-up. VDDSPD REV 1.0 06/14/2005 Supply Serial EEPROM positive power supply. 4 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N25664TUH4A2F / M1N51264TUH8A2F 256MB: 32M x 64 / 512MB: 64M x 64 PC2-5300 Unbuffered DDR2 SO-DIMM Functional Block Diagram (256MB - 1 Rank, 32Mx16 DDR2 SDRAMs) CS0 DQS2 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 LDQS CS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS D1 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 A0-A12 D0 BA0-BA1 : SDRAMs D0-D3 RAS : SDRAMs D0-D3 CAS CAS : SDRAMs D0-D3 CKE0 CKE : SDRAMs D0-D3 WE Notes : 1. 2. 3. 4. LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQS6 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 LDQS CS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS D3 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 SPD D0-D3 D0-D3 D0-D3 D2 CK0 CK0 2 loads CK1 CK1 2 loads Serial PD N.C. WE : SDRAMs D0-D3 CS DQS4 DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 VDDSPD VDD/VDDQ VREF VSS VDDID A0-A12 : SDRAMs D0-D3 RAS CKE1 06/14/2005 CS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 BA0-BA1 REV 1.0 LDQS LDQS DQS0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 SCL WP A0 A1 A2 SA0 SA1 SA2 SDA DQ wiring may differ from that described in this drawing . DQ/DQS/DM/CKE/S relationships are maintained as shown. DQ/DQS/DM/DQS resistors are 22+/- 5% Ohms. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD is not equal to V DDQ. 5 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N25664TUH4A2F / M1N51264TUH8A2F 256MB: 32M x 64 / 512MB: 64M x 64 PC2-5300 Unbuffered DDR2 SO-DIMM Functional Block Diagram (512MB - 2 Ranks, 32Mx16 DDR2 SDRAMs) CS1 CS0 LDQS LDQS DQS2 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 LDQS CS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS D1 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 BA0-BA1 A0-A12 LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CS D4 CS D5 CS DQS4 DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQS6 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 LDQS CS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS D3 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 LDQS CS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 D2 D6 LDQS CS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 D7 BA0-BA1 : SDRAMs D0-D3 A0-A12 : SDRAMs D0-D3 RAS : SDRAMs D0-D3 CAS CAS : SDRAMs D0-D3 CKE0 CKE : SDRAMs D0-D3 CKE1 N.C. CK0 VDDSPD VDD/VDDQ VREF VSS VDDID SPD D0-D3 D0-D3 D0-D3 2 loads CK0 CK1 2 loads CK1 WE : SDRAMs D0-D3 ODT0 ODT : SDRAMs D0-D3 ODT1 ODT : SDRAMs D4-D7 Notes : 1. 2. 3. 4. 06/14/2005 D0 LDQS LDQS RAS WE REV 1.0 CS DQS0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 Serial PD DQ wiring may differ from that described in this drawing. DQ/DQS/DM/CKE/S relationships are maintained as shown. DQ/DQS/DM/DQS resistors are 22+/- 5% Ohms. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD is not equal to V DDQ. SCL WP A0 A1 SA0 SA1 A2 SDA 6 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N25664TUH4A2F / M1N51264TUH8A2F 256MB: 32M x 64 / 512MB: 64M x 64 PC2-5300 Unbuffered DDR2 SO-DIMM Serial Presence Detect (256MB - 1 Rank, 32Mx16 DDR2 SDRAMs) (Part 1 of 2) Byte 0 Description Number of Serial PD Bytes Written during Production 1 Total Number of Bytes in Serial PD device 2 Fundamental Memory Type 3 Number of Row Addresses on Assembly SPD Entry Value Serial PD Data Entry (Hexadecimal) DDR2667 (-3C) DDR2667 (-3C) 128 80 256 08 DDR2-SDRAM 08 13 0D 4 Number of Column Addresses on Assembly 5 Number of DIMM Rank, Package, and Height 10 0A 1 rank, Height=30mm 6 Data Width of this Assembly 60 X64 40 7 Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL_1.8V 05 9 DDR2 SDRAM Device Cycle Time at CL=5 3ns 30 10 DDR2 SDRAM Device Access Time from Clock at CL=5 11 DIMM Configuration Type 12 Refresh Rate/Type 13 Primary DDR2 SDRAM Width X16 10 14 Error Checking DDR2 SDRAM Device Width N/A 00 15 Reserved Undefined 00 16 DDR2 SDRAM Device Attributes: Burst Length Supported 4,8 0C 17 DDR2 SDRAM Device Attributes: Number of Device Banks 4 04 18 DDR2 SDRAM Device Attributes: CAS Latencies Supported 3,4,5 38 0.45ns 45 Non-Parity/ECC 00 7.8s/self 82 19 DIMM Mechanical Characteristics 20 DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes 22 DDR2 SDRAM Device Attributes: General Support weak driver 03 23 Minimum Clock Cycle at CL=4 3.75ns 3D 24 Maximum Data Access Time from Clock at CL=4 0.5ns 50 5ns 50 25 Minimum Clock Cycle Time at CL=3 26 Maximum Data Access Time from Clock at CL=3 27 Minimum Row Precharge Time (tRP) <3.80mm 01 SODIMM (67.6mm) 04 Normal DIMM 00 0.6ns 60 15ns 3C 28 Minimum Row Active to Row Active delay (tRRD) 10ns 28 29 Minimum RAS to CAS delay (tRCD) 15ns 3C 30 Minimum RAS Pulse Width (tRAS) 45ns 2D 256MB 40 31 Module Bank Density per Rank 32 Address and Command Setup Time Before Clock (tIS) 33 Address and Command Hold Time After Clock (tIH) 34 Data Input Setup Time Before Clock (tDS) 35 Data Input Hold Time After Clock (tDH) 36 Write Recovery Time (tWR) 37 Internal Write to Read Command delay (tWTR) 7.5ns 1E 38 Internal Read to Precharge delay (tRTP) 7.5ns 1E REV 1.0 06/14/2005 0.2ns 20 0.275ns 27 0.1ns 10 0.175ns 17 15ns 3C Note 7 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N25664TUH4A2F / M1N51264TUH8A2F 256MB: 32M x 64 / 512MB: 64M x 64 PC2-5300 Unbuffered DDR2 SO-DIMM Serial Presence Detect (256MB - 1 Rank, 32Mx16 DDR2 SDRAMs) Byte 39 Description Reserved (Part 2 of 2) SPD Entry Value Serial PD Data Entry (Hexadecimal) DDR2667 (-3C) DDR2667 (-3C) Undefined 00 The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns 00 40 Extension of Byte 41 tRC and Byte 42 tRFC 41 Minimum Core Cycle Time (tRC) 60ns 3C 42 Min. Auto Refresh Command Cycle Time (tRFC) 105ns 69 43 Maximum Clock Cycle Time (tCK) 8ns 80 44 Max. DQS-DQ Skew Factor (tDQS) 0.24ns 18 45 Read Data Hold Skew Factor (tQHS) 0.34ns 22 46 PLL Relock Time 47 Tcasemax 48 N/A 00 6 55 Thermal Resistance of DRAM Package from Top (Case) to Ambient ( Psi T-A DRAM ) 118 76 49 DRAM Case Temperature Rise from Ambient due to ActivatePrecharge/Mode Bits (DT0/Mode Bits) 36 93 50 DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby(DT2N/DT2Q) 56 38 51 DRAM Case Temperature Rise from Ambient due to Precharge Power-Down(DT2P) 37 25 52 DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) 37 25 53 DRAM Case temperature Rise from Ambient due to Active PowerDown with Fast PDN Exit (DT3Pfast) 43 2B 54 DRAM Case temperature Rise from Ambient due to Active PowerDown with Slow PDN Exit (DT3Pslow) 27 1B 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) 42 54 56 DRAM Case Temperature Rise from Ambient due to Burst Refresh (DT5B) 36 24 57 DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto-Precharge (DT7) 54 36 58 Thermal Resistance of PLL Package from Top (Case) to Ambient ( Psi T-A PLL ) 00 00 59 Thermal Resistance of Register Package from Top (Case) to Ambient ( Psi T-A Register) 00 00 60 PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) 00 00 61 Register Case Temperature Rise from Ambient due to Register Active/Mode Bit (DT Register Active/Mode Bit) 00 00 62 SPD Revision 63 Checksum Data 1.2 12 Checksum Data 19 64-71 Manufacturer's JEDEC ID Code Super Elixir 7F7F7F0B00000000 72-255 Reserved Undefined REV 1.0 06/14/2005 Note 8 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N25664TUH4A2F / M1N51264TUH8A2F 256MB: 32M x 64 / 512MB: 64M x 64 PC2-5300 Unbuffered DDR2 SO-DIMM Serial Presence Detect (512MB - 2 Ranks, 32Mx16 DDR2 SDRAMs) (Part 1 of 2) Byte 0 Description Number of Serial PD Bytes Written during Production 1 Total Number of Bytes in Serial PD device 2 Fundamental Memory Type 3 Number of Row Addresses on Assembly SPD Entry Value Serial PD Data Entry (Hexadecimal) DDR2667 (-3C) DDR2667 (-3C) 128 80 256 08 DDR2-SDRAM 08 13 0D 4 Number of Column Addresses on Assembly 5 Number of DIMM Rank, Package, and Height 10 0A 2 rank, Height=30mm 6 Data Width of this Assembly 61 X64 40 7 Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL_1.8V 05 9 DDR2 SDRAM Device Cycle Time at CL=5 3ns 30 10 DDR2 SDRAM Device Access Time from Clock at CL=5 11 DIMM Configuration Type 12 Refresh Rate/Type 13 Primary DDR2 SDRAM Width X16 10 14 Error Checking DDR2 SDRAM Device Width N/A 00 15 Reserved Undefined 00 16 DDR2 SDRAM Device Attributes: Burst Length Supported 4,8 0C 17 DDR2 SDRAM Device Attributes: Number of Device Banks 4 04 18 DDR2 SDRAM Device Attributes: CAS Latencies Supported 3,4,5 38 0.45ns 45 Non-Parity/ECC 00 7.8s/self 82 19 DIMM Mechanical Characteristics 20 DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes 22 DDR2 SDRAM Device Attributes: General Support weak driver 03 23 Minimum Clock Cycle at CL=4 3.75ns 3D 24 Maximum Data Access Time from Clock at CL=4 0.5ns 50 5ns 50 25 Minimum Clock Cycle Time at CL=3 26 Maximum Data Access Time from Clock at CL=3 27 Minimum Row Precharge Time (tRP) <3.80mm 01 SODIMM (67.6mm) 04 Normal DIMM 00 0.6ns 60 15ns 3C 28 Minimum Row Active to Row Active delay (tRRD) 10ns 28 29 Minimum RAS to CAS delay (tRCD) 15ns 3C 30 Minimum RAS Pulse Width (tRAS) 45ns 2D 256MB 40 31 Module Bank Density per Rank 32 Address and Command Setup Time Before Clock (tIS) 33 Address and Command Hold Time After Clock (tIH) 34 Data Input Setup Time Before Clock (tDS) 35 Data Input Hold Time After Clock (tDH) 36 Write Recovery Time (tWR) 37 Internal Write to Read Command delay (tWTR) 7.5ns 1E 38 Internal Read to Precharge delay (tRTP) 7.5ns 1E REV 1.0 06/14/2005 0.2ns 20 0.275ns 27 0.1ns 10 0.175ns 17 15ns 3C Note 9 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N25664TUH4A2F / M1N51264TUH8A2F 256MB: 32M x 64 / 512MB: 64M x 64 PC2-5300 Unbuffered DDR2 SO-DIMM Serial Presence Detect (512MB - 2 Ranks, 32Mx16 DDR2 SDRAMs) (Part 2 of 2) Byte 39 Description Reserved SPD Entry Value Serial PD Data Entry (Hexadecimal) DDR2667 (-3C) DDR2667 (-3C) Undefined 00 The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns 00 40 Extension of Byte 41 tRC and Byte 42 tRFC 41 Minimum Core Cycle Time (tRC) 60ns 3C 42 Min. Auto Refresh Command Cycle Time (tRFC) 105ns 69 43 Maximum Clock Cycle Time (tCK) 8ns 80 44 Max. DQS-DQ Skew Factor (tDQS) 0.24ns 18 45 Read Data Hold Skew Factor (tQHS) 0.34ns 22 46 PLL Relock Time 47 Tcasemax 48 N/A 00 6 55 Thermal Resistance of DRAM Package from Top (Case) to Ambient ( Psi T-A DRAM ) 118 76 49 DRAM Case Temperature Rise from Ambient due to ActivatePrecharge/Mode Bits (DT0/Mode Bits) 36 93 50 DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby(DT2N/DT2Q) 56 38 51 DRAM Case Temperature Rise from Ambient due to Precharge Power-Down(DT2P) 37 25 52 DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) 37 25 53 DRAM Case temperature Rise from Ambient due to Active PowerDown with Fast PDN Exit (DT3Pfast) 43 2B 54 DRAM Case temperature Rise from Ambient due to Active PowerDown with Slow PDN Exit (DT3Pslow) 27 1B 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) 42 54 56 DRAM Case Temperature Rise from Ambient due to Burst Refresh (DT5B) 36 24 57 DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto-Precharge (DT7) 54 36 58 Thermal Resistance of PLL Package from Top (Case) to Ambient ( Psi T-A PLL ) 00 00 59 Thermal Resistance of Register Package from Top (Case) to Ambient ( Psi T-A Register) 00 00 60 PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) 00 00 61 Register Case Temperature Rise from Ambient due to Register Active/Mode Bit (DT Register Active/Mode Bit) 00 00 62 SPD Revision 63 Checksum Data 1.2 12 Checksum Data 19 64-71 Manufacturer's JEDEC ID Code Super Elixir 7F7F7F0B00000000 72-255 Reserved Undefined Note NOTE: REV 1.0 06/14/2005 Note M1N51264TUH8A2F-3C I 4D314E3531323634545548384132462D33432 10 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N25664TUH4A2F / M1N51264TUH8A2F 256MB: 32M x 64 / 512MB: 64M x 64 PC2-5300 Unbuffered DDR2 SO-DIMM Absolute Maximum DC Ratings Symbol VIN, VOUT Parameter Rating Units Voltage on I/O pins relative to VSS -0.5 to +2.3 V VIN Voltage on Input relative to VSS -0.5 to +2.3 V VDD Voltage on VDD supply relative to VSS -1.0 to +2.3 V VDDQ Voltage on VDDQ supply relative to VSS -0.5 to +2.3 V 0 to +70 C -55 to +100 C TA Operating Temperature (Ambient) TSTG Storage Temperature (Plastic) Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC Electrical Characteristics and Operating Conditions TA = 0 C ~ 70 C; VDDQ = VDD = 1.8V 0.1V Symbol Min Max Units Notes VDD Supply Voltage 1.7 1.9 V 1 VDDQ I/O Supply Voltage 1.7 1.9 V 1 VREF I/O Reference Voltage 0.49 x VDDQ 0.51 x VDDQ V 1, 2 VTT Parameter I/O Termination Voltage (System) VREF - 0.04 VREF + 0.04 V 1, 3 VIH (DC) Input High (Logic1) Voltage VREF + 0.125 VDDQ + 0.3 V 1 VIL (DC) Input Low (Logic0) Voltage -0.3 VREF - 0.125 V 1 -5 5 A 1 -5 5 A 1 Input Leakage Current IIL Any input 0V VIN VDD; All other pins not under test = 0V Output Leakage Current IOL DQs are disabled; 0V Vout VDDQ Note: 1. 2. Inputs are not recognized as valid until VREF stabilizes. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to- 3. peak noise on VREF may not exceed 2% of the DC value. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. REV 1.0 06/14/2005 11 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N25664TUH4A2F / M1N51264TUH8A2F 256MB: 32M x 64 / 512MB: 64M x 64 PC2-5300 Unbuffered DDR2 SO-DIMM Operating, Standby, and Refresh Currents TA = 0 C ~ 70 C; VDDQ = VDD = 1.8V 0.1V (256MB, 1 Rank, 32Mx16 DDR2 SDRAMs) Symbol Parameter/Condition PC2-5300 Unit Notes (-3C) IDD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address 380 mA 440 mA 20 mA 200 mA 160 mA 76 mA 24 mA 200 mA 600 mA 680 mA and control inputs changing once per clock cycle IDD1 Operating Current: one bank; active/read/precharge; Burst = 4; tRC = tRC (MIN); CL= 4; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle IDD2P IDD2N Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle IDD2Q Precharge quiet standby current IDD3PF IDD3PS IDD3N Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); MRS(12)=0 Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); MRS(12)=1 Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; Burst = 4; reads; continuous burst; IDD4R address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 4; tCK = tCK (MIN); IOUT = 0mA Operating Current: one bank; Burst = 4; writes; continuous burst; IDD4W address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL= 4; tCK = tCK (MIN) IDD5 Auto-Refresh Current: tRC = tRFC (MIN) 640 mA IDD6 Self-Refresh Current: CKE 0.2V 20 mA IDD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at 960 mA every transfer; tRC = tRC (min); IOUT = 0mA. Note: Module IDD was calculated from component IDD. It may different from the actual measurement. REV 1.0 06/14/2005 12 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N25664TUH4A2F / M1N51264TUH8A2F 256MB: 32M x 64 / 512MB: 64M x 64 PC2-5300 Unbuffered DDR2 SO-DIMM Operating, Standby, and Refresh Currents TA = 0 C ~ 70 C; VDDQ = VDD = 1.8V 0.1V (512MB, 2 Ranks, 32Mx16 DDR2 SDRAMs) Symbol Parameter/Condition PC2-5300 Unit Notes (-3C) IDD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address 580 mA 640 mA 40 mA 400 mA 320 mA 152 mA 48 mA 400 mA 800 mA 880 mA and control inputs changing once per clock cycle IDD1 Operating Current: one bank; active/read/precharge; Burst = 4; tRC = tRC (MIN); CL= 4; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle IDD2P IDD2N Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle IDD2Q Precharge quiet standby current IDD3PF IDD3PS IDD3N Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); MRS(12)=0 Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); MRS(12)=1 Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; Burst = 4; reads; continuous burst; IDD4R address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 4; tCK = tCK (MIN); IOUT = 0mA Operating Current: one bank; Burst = 4; writes; continuous burst; IDD4W address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL= 4; tCK = tCK (MIN) IDD5 Auto-Refresh Current: tRC = tRFC (MIN) 840 mA IDD6 Self-Refresh Current: CKE 0.2V 40 mA IDD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at 1160 mA every transfer; tRC = tRC (min); IOUT = 0mA. Note: Module IDD was calculated from component IDD. It may different from the actual measurement. REV 1.0 06/14/2005 13 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N25664TUH4A2F / M1N51264TUH8A2F 256MB: 32M x 64 / 512MB: 64M x 64 PC2-5300 Unbuffered DDR2 SO-DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 1 of 2) -3C Symbol Parameter Unit Min. Max. tAC DQ output access time from CK/CK -0.45 +0.45 ns DQS output access time from CK/CK -0.4 +0.4 ns tCH CK high-level width 0.45 0.55 tCK tCL CK low-level width 0.45 0.55 tCK tCH or tCL - tCK 3 8 ns ns tDQSCK tHP Minimum half clk period for any given cycle; defined by clk high (tCH) or clk low (tCL) time tCK Clock cycle time tDH DQ and DM input hold time 0.175 - tDS DQ and DM input setup time 0.1 - ns tIPW Input pulse width 0.6 - tCK tDIPW DQ and DM input pulse width (each input) 0.35 - tCK tHZ Data-out high-impedance time from CK/CK - tAC,MAX ns ns CL=4, 5 tLZ(DQ) DQ low-impedance time from CK/CK 2tAC,MIN tAC,MAX tLZ(DQS) DQS low-impedance time from CK/CK tAC,MIN tAC,MAX ns tDQSQ DQS-DQ skew (DQS & associated DQ signals) - 0.24 ns tQHS Data hold Skew Factor - 0.34 ns tQH Data output hold time from DQS tHP tQHS - tCK WL-0.25 WL+0.25 tCK DQS input low (high) pulse width (write cycle) 0.35 - tCK tDSS DQS falling edge to CK setup time (write cycle) 0.2 - tCK tDSH DQS falling edge hold time from CK (write cycle) 0.2 - tCK tMRD Mode register set command cycle time 2 - tCK tDQSS tDQSL,(H) Write command to 1st DQS latching transition tWPST Write postamble 0.40 0.60 tCK tWPRE Write preamble 0.35 - tCK tIH Address and control input hold time 0.275 - ns tIS Address and control input setup time 0.20 - ns tRPRE Read preamble 0.9 1.1 tCK tRPST Read postamble 0.40 0.60 tCK tRAS Active to Precharge command 39 70,000 ns tRRD Active bank A to Active bank B command 7.5 - ns REV 1.0 06/14/2005 14 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N25664TUH4A2F / M1N51264TUH8A2F 256MB: 32M x 64 / 512MB: 64M x 64 PC2-5300 Unbuffered DDR2 SO-DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 2 of 2) -3C Unit Symbol Parameter Min. Max. tCCD CAS to CAS 2 tWR Write recovery time 15 - tCK ns tDAL Auto precharge write recovery + precharge time tWR + tRP - tCK tWTR Internal write to read command delay 7.5 - tCK tRTP Internal read to precharge command delay 7.5 - ns tXSNR Exit self refresh to a Non-read command tXSRD Exit self refresh to a Read command tRFC+10 - ns 200 - tCK - tCK Exit precharge power down to any Non- read command 2 tXARD Exit active power down to read command 2 - tCK tXARDS Exit active power down to read command (slow exit, lower power) 7-AL - tCK tXP tCKE CKE minimum pulse width 3 - tCK tAOND ODT turn-on delay 2 2 tCK tAC(min) tAC(max) ns tAC(min) +2 2tCK + tAC(max) +1 ns 2.5 2.5 tCK tAC(min) tAC(max) +0.6 ns tAC(min)+2 2.5tCK + tAC(max) +1 ns tAON ODT turn-on tAONPD ODT turn-on (Power down mode) tAOFD ODT turn-off delay tAOF ODT turn-off +0.7 tAOFPD ODT turn-off (Power down mode) tANPD ODT to power down entry latency 3 - tCK tAXPD ODT power down exit latency 8 - tCK 0 12 ns tOIT OCD drive mode output delay tDelay Minimum time clocks remains ON after CKE asynchronously drops Low tRCD Active to Read or Write delay 15 ns tRP Precharge command period 15 ns tREFI Average Periodic Refresh Interval REV 1.0 06/14/2005 tIS + tCK + tIH ns 7.8 s 15 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N25664TUH4A2F / M1N51264TUH8A2F 256MB: 32M x 64 / 512MB: 64M x 64 PC2-5300 Unbuffered DDR2 SO-DIMM Package Dimensions (256MB, 1 Rank, 32Mx16 DDR2 SDRAMs) FRONT 67.60 (2X) 1.80 1 2.15 39 11. 40 41 30.00 20.00 6.00 4.00 63.60 199 Detail A Detail B 4.20 47.40 2.45 2.70 SIDE BACK 3. 80 MAX 1.00+/- 0.1 0.45 2.55 Detail B Detail A 0.25 MAX 4.00+/-0.10 1.00+/- 0.10 0.60 Note: All dimensions are typical with tolerances of+/- 0.15 unless otherwise stated. Units: Millimeters (Inches) REV 1.0 06/14/2005 16 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N25664TUH4A2F / M1N51264TUH8A2F 256MB: 32M x 64 / 512MB: 64M x 64 PC2-5300 Unbuffered DDR2 SO-DIMM Package Dimensions (512MB - 2 Ranks, 32Mx16 DDR2 SDRAMs) FRONT 67.60 20.00 6.00 (2X) 1.80 1 2.15 39 11.40 41 30.00 4.00 63.60 199 Detail A Detail B 4.20 47.40 2.45 2.70 BACK SIDE 3.80 MAX 1.00+/- 0.1 0.45 2.55 Detail B Detail A 0.25 MAX 4.00+/-0.10 1.00+/- 0.10 0.60 Note: All dimensions are typical with tolerances of +/- 0.15 unless otherwise stated. Units: Millimeters (Inches) REV 1.0 06/14/2005 17 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N25664TUH4A2F / M1N51264TUH8A2F 256MB: 32M x 64 / 512MB: 64M x 64 PC2-5300 Unbuffered DDR2 SO-DIMM Revision Log Rev Date 0.1 05/2005 Preliminary. 0.2 06/2005 Add Part number in SPD code. 1.0 06/2005 Official release. REV 1.0 06/14/2005 Modification 18 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice.