128K x 36 Synchronous Flow-Through 3.3V Cache RAM
CY7C1345
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05164 Rev. ** Revised September 18, 2001
345
Features
• Supports 117-MHz microprocessor cache systems with
zero wait states
• 128K by 36 common I/O
• Fast clock-to-output times
—7.5 ns (117-MHz version)
• Two-bit wrap-around counter supporting either
interleaved or linear burst sequence
• Separate processor and controller address strobes
provide direct interface with the processor and external
cache controller
• Synchronous self-timed write
• Asynchronous output enable
• Supports 3.3V & 2.5V I/O levels
• JEDEC-standard pinout
• 100-pin TQFP packaging
• ZZ “sleep” mode
Functional Description
The CY7C1345 is a 3.3V, 128K by 36 synchronous cache
RAM designed to interface with high-speed microprocessors
with minimum glue logic. Maximum access delay from clock
rise is 7. 5 ns (117-MH z ve r s io n). A 2 -bi t o n-c hi p c o un ter c ap -
tures the first address in a burst and increments the address
automatically for the rest of the burst access.
The CY7C1345 allows either interleaved or linear burst se-
quences, selected by the MODE input pin. A HIGH selects an
interlea ved burst sequence, wh ile a LOW selects a linear burst
sequenc e. Burst accesses c an be in itiated wi th the Pro ce ss or
Address Strobe (ADSP) or the cache Controller Address
Strobe (ADSC) inputs. Address advancement is controlled by
the address advancement (ADV) input.
A synchron ous self-time d write mechan ism is provide d to sim-
plify the write interface. A synchronous chip enable input and
an async hron ou s outp ut en abl e inp ut provide easy contro l for
bank selection and output three-state control.
Selection Guide
7C1345-117 7C1345-100 7C1345-90 7C1345-50
Maximum Access Time (ns) 7.5 8.0 8.5 11.0
Maximum Operating Current (mA) 350 325 300 250
Maximum Standby Current (mA) 10.0 10.0 10.0 10.0
Pentium is a registered trademark of Intel Corporation.
CLK
ADV
ADSC
A[16:0]
GW
BWE
BWS0
CE1
CE3
CE2
OE
ZZ
BURST
COUNTER
DQ[31:24],DP3
BYTEWRITE
REGISTERS
ADDRESS
REGISTER
DQ
INPUT
REGISTERS
128K X 36
MEMORY
ARRAY
CLK
Q0
Q1
Q
D
CE
CE
CLR
SLEEP
CONTROL
DQ[23:16],DP2
BYTEWRITE
REGISTERS
DQ
DQ
DQ[15:8],DP1
BYTEWRITE
REGISTERS
DQ[7:0],DP0
BYTEWRITE
REGISTERS
D Q
ENABLE
REGISTER
DQ
CE
CLK
36 36
17
15
15
17
(A0,A1)2
MODE
ADSP
Logic Block Diag ram
DQ[31:0]
BWS1
BWS2
BWS3
DP[3:0]
CY7C1345
Document #: 38-05164 Rev. ** Page 2 of 17
Pin Configuration
100-Lead TQ FP
A
5
A
4
A
3
A
2
A
1
A
0
DNU
DNU
V
SS
V
DD
DNU
A
10
A
11
A
12
A
13
A
14
A
16
DP1
DQ14
VDDQ
VSSQ
DQ13
DQ12
DQ11
DQ10
VSSQ
VDDQ
DQ9
DQ8
VSS
NC
VDD
DQ7
DQ6
VDDQ
VSSQ
DQ5
DQ4
DQ3
DQ2
VSSQ
VDDQ
DQ1
DQ0
DP0
DP2
DQ16
DQ17
VDDQ
VSSQ
DQ18
DQ19
DQ20
DQ21
VSSQ
VDDQ
DQ22
DQ23
VSSQ
VDD
NC
VSS
DQ24
DQ25
VDDQ
VSSQ
DQ26
DQ27
DQ28
DQ29
VSSQ
VDDQ
DQ30
DQ31
DP3
A6
A7
CE
1
CE
2
BWS
3
BWS
2
BWS
1
BWS
0
CE
3
V
DD
V
SS
CLK
GW
BWE
OE
ADSP
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
BYTE0
BYTE2
A
15
ADV
ADSC
ZZ
MODE
DNU
BYTE1
DQ15
BYTE3
V
SS
100-Pin TQFP
CY7C1345
CY7C1345
Document #: 38-05164 Rev. ** Page 3 of 17
Pin Descriptions
Pin Number Name I/O Description
85 ADSC Input-
Synchronous Address Strobe from Controller , sampled on t he rising e dge of CLK. W hen asserte d
LOW, A[15:0] is captured in the address registers. A[1:0] are also loaded into the burst
counte r. When ADSP and ADSC are both asserted, only ADSP is recogniz ed.
84 ADSP Input-
Synchronous Address Strobe from Processor , sampled on the rising edge of CLK. When asserted
LOW, A[15:0] is captured in the address registers. A[1:0] are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP
is ignored when CE1 is deasserted HIGH.
36, 37 A[1:0] Input-
Synchronous A1, A0 A ddress In puts. T hese inputs feed the on- chip b urst c ounter as the LSBs as
well as bei ng use d to acce ss a partic ula r memo ry loc ation in the memo ry array.
49 −44,
81–82,
99–100,
32–35
A[16:2] Input-
Synchronous Address Inputs used in conjunction with A[1:0] to select one of the 64K address
locatio ns. Sampled at the ri sing edge of the CLK, if C E1, CE2, and CE3 are sa mpled
active, and ADSP or ADSC is active LOW.
96–93 BW[3:0] Input-
Synchronous Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes.
Sampled on the ri sing e dge. BW 0 controls DQ[7:0] and DP0, BW1 controls DQ[15:8]
and DP1, BW2 controls DQ[23:16] and DP2, and BW3 controls DQ[31:24] and DP3. See
Write Cycle Description table for further details.
83 ADV Input-
Synchronous Adva nce Input, us ed to advan ce the on-ch ip address counter. When LOW the inter-
nal burst cou nter is a dvanc ed in a bu rst seq uence . The burs t seque nce is select ed
using the MODE input.
87 BWE Input-
Synchronous Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
88 GW Input-
Synchronous Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is
used t o conduct a global writ e, independ ent of th e state of BWE and BW[3:0]. Global
writes override byte writes.
89 CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device.
98 CE1Input-
Synchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjun cti on w ith CE2 and CE3 to select/deselect the device. CE1 gates ADSP.
97 CE2Input-
Synchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjun cti on w ith CE1 and CE3 to select/deselect the device.
92 CE3Input-
Synchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjun cti on w ith CE1 and CE2 to select/deselect the device.
86 OE Input-
Asynchronous Output Enable, asynchronous input, active LOW. Controls the direction of the I/O
pins. Whe n LOW , the I/O pins beha ve as outputs. Wh en deasserted HI GH, I/O pins
are three-stated, and act as input data pi ns.
64 ZZ Input-
Asynchronous Snooze Input. Active HIGH asynchronous. When HIGH, the device enters a
low-power standby mode in which all other inputs are ignored, but the data in the
memory array is maintained.Leaving ZZ floating or NC will default the device into an
active state. ZZ pin has an internal pull-down.
31 MODE -Mode Input. Selects the burst order of the device. T ied HIGH selects the interleaved
burst order. Pulled LOW selects the linear burst order. When left floating or NC,
defaults to interleaved burst order. Mode pin has an internal pull-up.
30–28,
25–22,
19–18,
13–12, 9–6,
3–1, 80–78,
75–72,
69–68,
63–62,
59–56,
53–51
DQ[31:0],
DP[3:0] I/O-
Synchronous Bidire ctional Da ta I/O lines. As inp uts, they feed into a n on-chip data regis ter that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in
the memory location specified by A[16:0] during the previous clock rise of the read
cycle. The direction of the pins is controlled by OE in conjunction with the internal
control lo gic. W hen O E is asse rted LOW, th e pins beha ve as outp uts. W hen HIG H,
DQ[31:0] and DP[3:0] are placed in a thr ee-s tat e co ndi tion. The outputs are au tom at-
ically three-stated when a Write cycle is detected.
15, 41, 65,
91 VDD Power Supply Power su pp ly i npu ts to the co re of the devi ce . Shou ld b e c onn ec ted to 3.3 V pow e r
supply.
CY7C1345
Document #: 38-05164 Rev. ** Page 4 of 17
Functional Overview
All syn chrono us in puts p ass through input regist ers co ntrolle d
by the rising edge of the clock. Maximum access delay from
the clock rise (tCDV) is 7.5 ns (117-MHz device).
The CY7C1345 supports secondary cache in systems utilizing
either a linear or interleaved burst sequence. The interleaved
burst o rder supp orts Pentium an d i 48 6 p roc es so rs. The linear
burst sequence is suited for processors that utilize a linear
burst s equ enc e. The bu rst order is user se lec tab le, and is d e-
termined by sampling the MODE input. Accesses can be initi-
ated with either the Processor Address Strobe (ADSP) or the
Controller Address Strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captu res the first ad-
dress in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byt e Write S elect (BW[3:0]) inputs. A Global Write
Enable (G W) overri des all byte write inp uts and wri tes data to
all four bytes. All writes are simplified with on-chip synchro-
nous self- t imed w rite ci rcu itry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynch ro nous Ou tp ut En able ( O E) provide for easy bank se-
lection and output three-state control. ADSP is ignored if CE1
is HIGH.
Single Read Acce sse s
A single re ad acc ess is ini tiated when the fol lowi ng condit ion s
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all as-
serted active, and (2) ADSP or ADSC is asserted LOW (if the
access is initiated by ADSC, the write inputs must be deassert-
ed during this first cycle). The address presented to the ad-
dress inputs is latched into the address register and the burst
counter/ control logi c and presen ted to the m emory co re. If th e
OE input is asserted LOW , the requested data will be avail able
at the data outputs a maximum to tCDV after clock rise. ADSP
is ignored if CE1 is HIGH.
Single Wr ite Accesses Initia ted by ADSP
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, and (2) ADSP is asserted LOW. The addresses pre-
sented are loaded into the address register and the burst
counter/ control lo gic and d elivered to the RA M core. Th e write
inputs (GW, BWE, and BW[3:0]) are ignored during this first
clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte writes are allowed.
During byte writes, BW0 controls DQ[7:0], BW1 controls
DQ[15:8], BW2 controls DQ[23:16], and BW3 contr o ls DQ [31:24].
All I/Os are three-stated during a byte write. Since this is a
common I/O device, the asynchronous OE input signal must
be deasserted and the I/Os must be three-stated prior to the
presentation of data to DQ[31:0]. As a safety precaution, the
data lines are three-stated once a write cycle is detected, re-
gardless of the state of OE.
Single Write Accesses Initiated by ADSC
This w rite acce ss is i nitiated whe n the f ollowin g condition s are
satis fie d at clo ck ris e : (1) CE1, CE2, and CE3 are al l as se rt ed
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the writ e input si gnals (GW, BWE, and BW[3:0])
indicate a write access. ADSC is ignored if ADSP is active LOW .
The addre sses pre sented are loa ded into th e address register
and the burst counter/control logic and delivered to the RAM
core. The i nfor mation pres ented to DQ[31:0] will be wr itten in to
the speci fied address location. Byte writes are allowed. During
byte wr ites, BW0 contro ls DQ[7:0], BW1 controls DQ[15:8], BW2
controls DQ[23:16], and BWS3 controls DQ[31:24]. All I/Os are
three- stated when a writ e is detected, even a byte write. Since
this is a common I/O device, the asynchronous OE input signal
must be dea sserted and the I/Os must be three-s tated prior to
the presentation of data to DQ[31:0]. As a safety precaution, the
data lines are three-stated once a write cycle is detected, re-
gardless of the state of OE.
Burst Sequences
The CY7C1345 provides an on-chip 2-bit wraparound burst
counter inside the SRAM. The burst counter is fed by A[1:0],
and can follow either a linear or interleaved burst order. The
burst order is determined by the state of the MODE input. A
LOW on MO DE will selec t a linear burst se quence. A HIGH on
MODE will select an interleaved burst order. Leaving MODE
unconnected will cause the device to default to a interleaved
burst sequence.
17, 40, 67,
90 VSS Ground Ground for the I/O circuitry of the device. Should be connected to ground of the
system.
5, 10, 14, 21,
26, 55, 60,
71, 76
VSSQ Ground Ground for the device. Should be connected to ground of the system.
4, 1 1, 20, 27,
54, 61, 70,
77
VDDQ I/O Power
Supply Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.
1, 16, 30,
50–51, 66,
80
NC -No connects.
38, 39, 42,
43 DNU -Do not use pins. Should be left unconnected or tied LOW.
Pin Descriptions (continued)
Pin Number Name I/O Description
CY7C1345
Document #: 38-05164 Rev. ** Page 5 of 17
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ HIGH
places the SRAM in a power conserv ation “sleep” mode. T wo
clock cycles are requ ired to ent er int o or exit from th is “sleep”
mode. While in this mode, data integrity is guaranteed. Access-
es pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be deselec ted p rior to ente ring the “sleep” mode.
CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the
duration of tZZREC after the ZZ input returns LO W . Leaving ZZ
unconnected defaults the device into an active state.
Table 1. Counter Implementation for the Intel
Pentium®/80486 Processor’s Sequence
First
Address Second
Address Third
Address Fourth
Address
AX + 1, AxAX + 1, AxAX + 1, AxAX + 1, Ax
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Table 2. Counter Implementation for a Line ar Sequence
First
Address Second
Address Third
Address Fourth
Address
AX + 1 , AxAX + 1, AxAX + 1, AxAX + 1, Ax
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min. Max. Unit
ICCZZ Snooze mode stand-
by current ZZ > VDD − 0.2V 3 ns
tZZS Device operation to
ZZ ZZ > VDD − 0.2V 2tCYC ns
tZZREC ZZ recovery time ZZ < 0.2V 2tCYC mA
CY7C1345
Document #: 38-05164 Rev. ** Page 6 of 17
Cycle Description Table[1, 2, 3]
Cycle Description ADD
Used CE1CE3CE2ZZ ADSP ADSC ADV WE OE CLK DQ
Deselected Cycle, Power-down None H X X L X L X X X L-H High-Z
Deselected Cycle, Power-down None L X L L L X X X X L-H High-Z
Deselected Cycle, Power-down None L H X L L X X X X L-H High-Z
Deselected Cycle, Power-down None L X L L H L X X X L-H High-Z
Deselected Cycle, Power-down None X X X L H L X X X L-H High-Z
Snooze Mode, Power-down N one X X X H X X X X X X High-Z
Read Cycle, Begin Burst External L L H L L X X X L L-H Q
Read Cycle, Begin Burst External L L H L L X X X H L-H High-Z
Write Cycle, Begin Burst External L L H L H L X L X L-H D
Read Cycle, Begin Burst External L L H L H L X H L L-H Q
Read Cycle, Begin Burst External L L H L H L X H H L-H High-Z
Read Cycle, Continue Burst Next X X X L H H L H L L-H Q
Read Cycle, Continue Burst Next X X X L H H L H H L-H High-Z
Read Cycle, Continue Burst Next H X X L X H L H L L-H Q
Read Cycle, Continue Burst Next H X X L X H L H H L-H High-Z
Write Cycle, Continue Burst Next X X X L H H L L X L-H D
Write Cycle, Continue Burst Next H X X L X H L L X L-H D
Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q
Read Cycle, Suspend Burst Current X X X L H H H H H L-H High-Z
Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q
Read Cycle, Suspend Burst Current H X X L X H H H H L-H High-Z
Write Cycle, Suspend Burst Current X X X L H H H L X L-H D
Write Cycle, Suspend Burst Current H X X L X H H L X L-H D
Notes:
1. X=Don’t Care,” 1=Logic HIGH, 0=Logic LOW.
2. The SRAM always initiates a r ead cycle when ADSP asserted, regardless of the state of GW , BWE, or BWS[3:0]. W rites may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE
is a don't care for the remainder of the write cycle.
3. OE is asynchronous and is not sampled with the clock rise. During a read cycle DQ=High-Z when OE is inact ive, and DQ= da ta when OE is active.
CY7C1345
Document #: 38-05164 Rev. ** Page 7 of 17
Maximum Ratings
(Above w hi ch the useful life may be impaired. For user g uid e-
lines, not tes ted .)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VDD Relative to GND .......–0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State[5]....................................–0.5V to VDD + 0.5V
DC Input Voltage[5]................................–0.5V to VDD + 0.5V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage.......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Notes:
4. When a write cycle is detected, all I/Os are three-stated, even during byte writes.
5. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.
6. TA is the case te mperature.
Wr ite Cycle Descriptions [1, 2, 3, 4 ]
Function GW BWE BW3BW2BW1BW0
Read 11XXXX
Read 101111
Write B yte 0, DP0101110
Write B yte 1, DP1101101
Write Bytes 1, 0, DP0, DP1101100
Write B yte 2, DP2101011
Write Bytes 2, 0, DP2, DP0101010
Write Bytes 2, 1, DP2, DP1101001
Write Bytes 2, 1, 0, DP2, DP1, DP0101000
Write B yte 3, DP3100111
Write Bytes 3, 0, DP3, DP0100110
Write Bytes 3, 1, DP3, DP0100101
Write Bytes 3, 1, 0, DP3, DP1, DP0100100
Write Bytes 3, 2, DP3, DP2100011
Write Bytes 3, 2, 0, DP3, DP2, DP0100010
Write Bytes 3, 2, 1, DP3, DP2, DP1100001
Write All Bytes 1 0 0 0 0 0
Write All Bytes 0 X X X X X
Operating Range
Range Ambient
Temperature[6] VDD VDDQ
Com’l 0°C to +7 0°C 3.135V to 3.6V 2.375V to VDD
CY7C1345
Document #: 38-05164 Rev. ** Page 8 of 17
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA 2.4 V
VDDQ = 2.5V , VDD = Min., IOH = –2.0 mA 2.0 V
VOL Output LOW Voltage VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA 0.4 V
VDDQ = 2.5V , VDD = Min., IOL = 2.0 mA 0.7 V
VIH Input HIGH Voltage VDDQ = 3.3V 2.0 VDD +
0.3V V
VIH Input HIGH Voltage VDDQ = 2.5V 1.7 VDD +
0.3V V
VIL Input LOW Voltage[5] VDDQ = 3.3V –0.3 0.8 V
VIL Input LOW Voltage[5] VDDQ = 2.5V –0.3 0.7 V
IXInput Load Current
(except ZZ and MODE) GND ≤ VI ≤ VDDQ −11µA
Input Current of MODE Input = VSS –30 µA
Input = VDDQ 5µA
Input Current of ZZ Input = VSS –5µA
Input = VDDQ 30 µA
IOZ Output Leakage Current GND ≤ VI ≤ VDD, Output Disabled –55µA
IOS Output Short Circuit Current[7] VDD = Max ., VOUT = GND –300 mA
IDD VDD Operating Supply Current VDD = Ma x., IOUT = 0 mA,
f = fMAX = 1/tCYC 8.5-ns cycle, 117 MHz 350 mA
10-ns cycle, 100 MHz 325 mA
11-ns cycle, 90 MHz 300 mA
20-ns cycle, 50 MHz 250 mA
ISB1 Automatic CE Power-Down
Current—TTL Inputs Max. VDD, Device Dese le ct ed,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC,
inputs switching
8.5-ns cycle, 117 MHz 125 mA
10-ns cycle, 100 MHz 110 mA
11-ns cycle, 90 MHz 100 mA
20-ns cycle, 50 MHz 90 mA
ISB2 Automatic CE Power-Down
Current—CMOS Inputs Max. VDD, Device Deselected,
VIN ≤ 0.3V or VIN > VDDQ – 0.3V ,
f = 0, inputs static
All speeds 10 mA
Max. VDD, Device Deselected,
VIN ≥ VDDQ– 0.3V or VIN ≤ 0.3V,
f = fMAX, inputs switching
ISB3 Automatic CE Power-Down
Current—CMOS Inputs 8.5-ns cycle, 117 MHz 95 mA
10-ns cycle, 100 MHz 85 mA
11-ns cycle, 90 MHz 75 mA
20-ns cycle, 50 MHz 65 mA
ISB4 Automatic CE Power-Down
Current—TTL Inputs Max. VDD, Device Deselected,
VIN ≥ VDD –0.3V or VIN ≤ 0.3V , f = 0,
inputs static
30 mA
Notes:
7. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
CY7C1345
Document #: 38-05164 Rev. ** Page 9 of 17
Capacitance[8]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 2 5°C, f = 1 MHz,
VDD = 5.0V 4.0 pF
CI/O I/O Capacitance 4.0 pF
AC Test Loads and Waveforms
Switching Characteristics Over the Operating Range[9]
Parameter Description -117 -100 -90 -50
Min. Max. Min. Max. Min. Max. Min. Max. Unit
tCYC Clock Cycle Time 8.5 10 11 20 ns
tCH Clock HIGH 3.0 4.0 4.5 4.5 ns
tCL Clock LOW 3.0 4.0 4. 5 4.5 ns
tAS Address Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns
tAH Address Hold After C LK Rise 0.5 0.5 0.5 0.5 ns
tCDV Data Output Valid After CLK Rise 7.5 8.0 8.5 11.0 ns
tDOH Data Output Hold After CLK Rise 2.0 2.0 2.0 2.0 ns
tADS ADSP, ADSC Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns
tADH ADSP, ADSC Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
tWES BWS[1:0], GW,BWE Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns
tWEH BWS[1:0], GW,BWE Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
tADVS ADV Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns
tADVH ADV Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
tDS Data Input Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns
tDH Data Input Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
tCES Chip Enable Set-Up 2.0 2.0 2.0 2.0 ns
tCEH Chip Enable Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
tCHZ Clock to High-Z[10, 11] 3.5 3.5 3.5 3.5 ns
tCLZ Clock to Low-Z[10, 11] 0000ns
tEOHZ OE HIGH to Output High-Z[10, 12] 3.5 3.5 3.5 3.5 ns
tEOLZ OE LOW to Output Low-Z[10, 12 ] 0000ns
tEOV OE LOW to Output Valid 3.5 3.5 3.5 3.5 ns
Notes:
8. Tested initially and after any design or process changes that may affect these parameters.
9. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the spec ified IOL/IOH and load capac itance. Shown i n (a) and (b) of AC t est l oads.
10. tCHZ, tCLZ, tEOHZ, and tEOLZ are specified with a load capac itance of 5 pF as in part (b) of AC Test Loads. T ransi tion is measure d ± 2 00 mV fro m stea dy-st ate vo ltage .
11. At any given voltage and temperature, tCHZ (max) is less than tCLZ (min).
12. This parameter is sampled and not 100% tested.
3.0V
GND
90%
10% 90%
10%
≤3.0 ns ≤3.0 ns
OUTPUT
R1=317Ω
R2=351Ω
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
ALL INPUT PULSES
OUTPUT
RL=50Ω
Z0=50Ω
VL=1.5V
3.3V
CY7C1345
Document #: 38-05164 Rev. ** Page 10 of 17
Timing Diagrams
Writ e Cycle Timing [13, 14]
Notes:
13. WE is the combination of BWE, BW[3:0] and GW to define a write cycle (see Write Cycle Descriptions table).
14. WDx stands for Write Data to Address X.
ADSP
CLK
ADSC
ADV
ADD
CE
1
OE
GW
WE
CE
2
CE
3
1a
Da ta In
t
CYC
t
CH
t
CL
t
ADS
t
ADH
t
ADS
t
ADH
t
ADVS
t
ADVH
WD1 WD2 WD3
t
AH
t
AS
t
WS
t
WH
t
WH
t
WS
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
2b 3a
1a
Single Write Burst Write
Unselected
ADSP ignored with CE
1
inac tive
CE
1
masks ADSP
= DON’T CARE
= UNDEFINED
Pip e lined Write
2a 2c 2d
t
DH
t
DS
High-Z
High-Z
Unselected with CE
2
ADV Mu s t Be Inactive for A DSP Write
ADSC initiated write
CY7C1345
Document #: 38-05164 Rev. ** Page 11 of 17
Read Cycle Timing[13, 15]
Note:
15. RDx stands for Read Data from Address X.
Timing Diagrams (continued)
ADSP
CLK
ADSC
ADV
ADD
CE1
OE
GW
WE
CE2
CE3
2a 2c
1a
Data Out
tCYC tCH
tCL
tADS tADH
tADS
tADH
tADVS
tADVH
RD1 RD2 RD3
tAH
tAS
tWS tWH
tWH
tWS
tCES tCEH
tCES tCEH
tCES tCEH
tCDV
tEOV
2b 2c 2d 3a
1a
tOEHZ tDOH
tCLZ tCHZ
Single Read Burst Read Unselected
ADSP ignored with CE1 inactive
Suspend Burst
CE1 masks ADSP
= DON’T CARE = UNDEFINED
Pipelined Read
ADSC initiated read
Unselected with CE2
CY7C1345
Document #: 38-05164 Rev. ** Page 12 of 17
Timing Diagrams (continued)
In/Out
A
tAH
tAS
= DON’T CARE = UNDEFINED
WE is the combination of BWE, BWS[1:0], and GW to define a write cycle (see Write Cycle Descriptions table).
tCLZ
tCHZ
CE is the combination of CE2 and CE3. All chip selects need to be active in order to select
the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X,
tDOH
CLK
ADD
WE
CE1
Data
BCD
ADSP
ADSC
ADV
CE
OE
Q(A) Q(B) Q
(B+1) Q
(B+2) Q
(B+3) Q(B) D(C) D
(C+1) D
(C+2) D
(C+3) Q(D)
tCYC
tCH tCL
tADS tADH
tADS tADH
tADVH
tADVS
tCEH
tCEH
tCES
tCES
tWEH
tWES
tCDV
Read/Write Timing
Device originally
deselected
ADSP ignored
with CE1 HIGH
tEOHZ
Qx stands for Data-out X.
CY7C1345
Document #: 38-05164 Rev. ** Page 13 of 17
Timing Diagrams (continued)
Pipeline Timing
tAS
= DON’T CARE = UNDEFINED
tCLZ
tCHZ
tDOH
CLK
ADD
WE
CE1
Data In/Out
ADSC
ADSP
ADV
CE
OE
D(C)
tCYC
tCH tCL
tADS tADH
tCEH
tCES
tWEH
tWES
tCDV
ADSP ignored
with CE1 HIGH
RD1 RD2 RD3 RD4 WD1 WD2 WD3 WD4
1a
Out 2a
Out 3a
Out 4a
Out 1a
In 2a
In 3a
In 4a
In
Back to Back Reads
ADSP initiated Reads
ADSC initiated Reads
Back to Back Writes
CY7C1345
Document #: 38-05164 Rev. ** Page 14 of 17
Timing Diagrams (continued)
OE
three-state
I/Os
tEOHZ tEOV
tEOLZ
OE Switching Waveforms
CY7C1345
Document #: 38-05164 Rev. ** Page 15 of 17
Note:
16. Device must be deselected when entering ZZ mode. See Cycle Description Table for all possible signal conditions to deselect the device.
17. I/Os are in three-state when exiting ZZ sleep mode.
Timing Diagrams (continued)
ADSP
CLK
ADSC
CE1
CE3
LOW
HIGH
ZZ tZZS
tZZREC
ICC ICC(active)
Three-state
I/Os
ZZ Mode Timing [16, 17]
CE2
ICCZZ
HIGH
CY7C1345
Document #: 38-05164 Rev. ** Page 16 of 17
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cypress Se miconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
Ordering Information
Speed
(MHz) Ordering Code Package
Name Package Type Operating
Range
117 CY7C1345–117AC A101 100-Lea d Thin Qu ad Fla t Pack Comm erc ial
100 CY7C1345–100AC A101 100-Lead Thin Qu ad Fla t Pack
90 CY7C1345–90AC A101 100-L ea d Thin Qu ad Fla t Pack
50 CY7C1345–50AC A101 100-L ea d Thin Qu ad Fla t Pack
Package Diagram
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
CY7C1345
Document #: 38-05164 Rev. ** Page 17 of 17
Document Title: CY7C1345 128K x 36 Synchronous Flow-Through 3.3V Cache RAM
Document Number: 38-05164
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 110193 12/18/01 SZV Change from Spec number: 38-00725 to 38-05164
