Data Sheet 26185.202 6277 8-BIT SERIAL-INPUT, CONSTANTCURRENT LATCHED LED DRIVER A6277ELW LOGIC GROUND 1 SERIAL DATA IN 2 CLOCK 3 CK LATCH ENABLE 4 L HIGH/LOW (CURRENT) 5 POWER GROUND 6 VDD IO REGULATOR FF OE SUB REGISTER 20 LOGIC SUPPLY 19 REXT 18 SERIAL DATA OUT 1 17 SERIAL DATA OUT 2 16 OUTPUT ENABLE 15 POWER GROUND 14 OUT 7 SUB OUT 0 7 OUT 1 8 13 OUT 6 OUT 2 9 12 OUT 5 OUT 3 10 11 OUT 4 LATCHES Dwg. PP-029-17A Note that the A6277EA (DIP) and the A6277ELW (SOIC) are electrically identical and share a common terminal number assignment. ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD ...................... 7.0 V Output Voltage Range, VO ............................ -0.5 V to +24 V Output Current, IO ....................... 150 mA Input Voltage Range, VI .................... -0.4 V to VDD + 0.4 V Package Power Dissipation, PD ..................................... See Graph Operating Temperature Range, TA Suffix `S-' ................ -20C to +85C Suffix `E-' ................ -40C to +85C Storage Temperature Range, TS ........................... -55C to +150C Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high static electrical charges. The A6277x is specifically designed for LED-display applications. Each BiCMOS device includes an 8-bit CMOS shift register, accompanying data latches, and eight npn constant-current sink drivers. Two package styles and two operating temperature ranges are available. The CMOS shift register and latches allow direct interfacing with microprocessor-based systems. With a 5 V logic supply, typical serial data-input rates are up to 20 MHz. The LED drive current is determined by the user's selection of a single resistor. A CMOS serial data output permits cascade connections in applications requiring additional drive lines. For inter-digit blanking, all output drivers can be disabled with an ENABLE input high. In addition, a HIGH/LOW function enables full selected current with the application of a logic low, or 50% selected current with the application of a logic high. The first character of the part number suffix determines the device operating temperature range. Suffix `E-' is for -40C to +85C, and suffix `S-' is -20C to +85C. Two package styles are provided for through-hole DIP (suffix `-A') or surface-mount SOIC (suffix `-LW') applications. The copper lead frame and low logic-power dissipation allow the dual in-line package to sink 122 mA through all outputs continuously over the operating temperature range (1.0 V drop, +85C). FEATURES To 150 mA Constant-Current Outputs Under-Voltage Lockout Low-Power CMOS Logic and Latches High Data Input Rate Similar to Toshiba TD62715FN High/Low Output Current Function Digital "Dim" Control Always order by complete part number, e.g., A6277EA . ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS 6277 8-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER 2.5 SUFFIX 'A', R JA = 55C/W 2.0 1.5 1.0 0.5 SUFFIX 'LW', R JA = 70C/W 0 25 50 75 100 125 AMBIENT TEMPERATURE IN C 150 Dwg. GP-018-1 FUNCTIONAL BLOCK DIAGRAM V DD UVLO LOGIC SUPPLY CLOCK SERIAL DATA IN SERIAL-PARALLEL SHIFT REGISTER LATCH ENABLE LATCHES SERIAL DATA OUT2 FF SERIAL DATA OUT 1 OUTPUT ENABLE (ACTIVE LOW) LOGIC GROUND MOS BIPOLAR HIGH/LOW (CURRENT) POWER GROUND IO REGULATOR POWER GROUND SUB Dwg. FP-013-7 2 OUT 0 OUT 1 OUT 2 OUT N 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright (c) 2001, Allegro MicroSystems, Inc. R EXT 6277 8-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER VDD VDD IN IN Dwg. EP-010-12 Dwg. EP-010-11 OUTPUT ENABLE (active low) LATCH ENABLE and HIGH/LOW VDD VDD OUT IN Dwg. EP-063-6 Dwg. EP-010-13 CLOCK and SERIAL DATA IN SERIAL DATA OUT TRUTH TABLE Serial Shift Register Contents Data Clock Input Input I1 I2 I3 ... IN-1 IN Serial Latch Data Enable Output Input Latch Contents I1 I2 I3 ... IN-1 IN Output Enable Input Output Contents I1 I2 I3 ... IN-1 IN H H R1 R2 ... RN-2 RN-1 RN-1 L L R1 R2 ... RN-2 RN-1 RN-1 X R1 R2 R3 ... RN-1 RN RN X X X L R1 R2 R3 ... RN-1 RN PN H P1 P2 P3 ... PN-1 PN L P1 P2 P3 ... PN-1 PN X X H H H H ... H X X ... P1 P2 P3 ... L = Low Logic (Voltage) Level www.allegromicro.com X PN-1 PN H = High Logic (Voltage) Level X X ... X = Irrelevant X P = Present State H R = Previous State 3 6277 8-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER ELECTRICAL CHARACTERISTICS at TA = +25C, VH/L = VDD = 5 V (unless otherwise noted). Limits Characteristic Symbol Supply Voltage Range VDD Under-Voltage Lockout VDD(UV) Output Current (any single output) Output Current Matching IO IO (difference between any two outputs at same VCE) Test Conditions Min. Typ. Max. Unit Operating 4.5 5.0 5.5 V VDD = 0 to 5 V 3.4 - 4.0 V VCE = 1.0 V, REXT = 160 100 120 140 mA VCE = 0.4 V, REXT = 470 34 42 48 mA REXT = 160 - 1.5 6.0 % REXT = 470 - 1.5 6.0 % - 1.0 5.0 A 0.4 V VCE(A) = VCE(B) 1.0 V: Output Leakage Current ICEX Logic Input Voltage VIH 0.7VDD - - V VIL - - 0.3VDD V SERIAL DATA OUT Voltage (SDO1 & SDO2) Input Resistance Supply Current VOH = 20 V VOL IOL = 1.0 mA - - 0.4 V VOH IOH = -1.0 mA 4.6 - - V ENABLE input, pull up 150 300 600 k LATCH & HIGH/LOW inputs, pull down 100 270 400 k REXT = open, VOE = 5 V - 0.8 1.6 mA REXT = 470 , VOE = 5 V 3.5 6.5 9.5 mA REXT = 160 , VOE = 5 V 14 17 22 mA REXT = 470 , VOE = 0 V 5.0 10 15 mA REXT = 160 , VOE = 0 V 20 27 40 mA RI IDD(OFF) IDD(ON) Typical Data is at VDD = 5 V and is for design information only. 4 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6277 8-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER SWITCHING CHARACTERISTICS at TA = 25C, VDD = VIH = 5 V, VCE = 0.4 V, VIL = 0 V, REXT = 470 , IO = 40 mA, VL = 3 V, RL = 65 , CL = 10.5 pF. Limits Characteristic Propagation Delay Time Propagation Delay Time Symbol tpHL tpLH Test Conditions Min. Typ. Max. Unit CLOCK-OUTn - 350 1000 ns LATCH-OUTn - 350 1000 ns ENABLE-OUTn - 350 1000 ns CLOCK-SERIAL DATA OUT1 - 40 - ns CLOCK-OUTn - 300 1000 ns LATCH-OUTn - 400 1000 ns ENABLE-OUTn - 380 1000 ns CLOCK-SERIAL DATA OUT2 - 40 - ns Output Fall Time tf 90% to 10% voltage 150 250 1000 ns Output Rise Time tr 10% to 90% voltage 150 250 600 ns Min. Typ. Max. Unit RECOMMENDED OPERATING CONDITIONS Characteristic Symbol Supply Voltage VDD 4.5 5.0 5.5 V Output Voltage VO - 1.0 4.0 V Output Current IO Continuous, any one output - - 150 mA IOH SERIAL DATA OUT - - -1.0 mA IOL SERIAL DATA OUT - - 1.0 mA VIH 0.7VDD - - V VIL - - 0.3VDD V - - 10 MHz Logic Input Voltage Clock Frequency www.allegromicro.com fCK Conditions Cascade operation 5 6277 8-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER TIMING REQUIREMENTS and SPECIFICATIONS (Logic Levels are VDD and Ground) C 50% CLOCK A SERIAL DATA IN B DATA 50% tp SERIAL DATA OUT.1 DATA 50% tp SERIAL DATA OUT.2 DATA 50% D E LATCH ENABLE 50% OUTPUT ENABLE LOW = ALL OUTPUTS ENABLED tp HIGH = OUTPUT OFF DATA 50% OUT N LOW = OUTPUT ON Dwg. WP-029-3 HIGH = ALL OUTPUTS DISABLED (BLANKED) OUTPUT ENABLE 50% t dis(BQ) F t en(BQ) tf tr 90% OUT N DATA 10% Dwg. WP-030-1 A. Data Active Time Before Clock Pulse (Data Set-Up Time), tsu(D) .......................................... 60 ns B. Data Active Time After Clock Pulse (Data Hold Time), th(D) .............................................. 20 ns C. Clock Pulse Width, tw(CK) ............................................... 50 ns D. Time Between Clock Activation and Latch Enable, tsu(L) ............................................ 100 ns E. Latch Enable Pulse Width, tw(L) ................................... 100 ns F. Output Enable Pulse Width, tw(OE) ................................ 4.5 s NOTE - Timing is representative of a 10 MHz clock. Significantly higher speeds are attainable. -- Max. Clock Transition Time, tr or tf .............................. 10 s 6 Information present at any register is transferred to the respective latch when the LATCH ENABLE is high (serial-toparallel conversion). The latches will continue to accept new data as long as the LATCH ENABLE is held high. Applications where the latches are bypassed (LATCH ENABLE tied high) will require that the OUTPUT ENABLE input be high during serial data entry. When the OUTPUT ENABLE input is high, the output source drivers are disabled (OFF). The information stored in the latches is not affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE input low, the outputs are controlled by the state of their respective latches. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6277 8-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE A6277xA A6277xLW VCE = 1 V VCE = 1 V 140 ALLOWABLE OUTPUT CURRENT IN mA/BIT ALLOWABLE OUTPUT CURRENT IN mA/BIT 140 VCE = 2 V 120 VCE = 3 V 100 VCE = 4 V 80 60 40 TA = +25C VDD = 5 V RJA = 55C/W 20 0 VCE = 2 V 120 VCE = 3 V 100 80 VCE = 4 V 60 40 TA = +25C VDD = 5 V RJA = 70C/W 20 0 0 20 40 60 80 100 0 20 DUTY CYCLE IN PER CENT 40 60 80 DUTY CYCLE IN PER CENT Dwg. GP-062-17 Dwg. GP-062-16 VCE = 1 V 140 140 ALLOWABLE OUTPUT CURRENT IN mA/BIT ALLOWABLE OUTPUT CURRENT IN mA/BIT 100 VCE = 2 V 120 VCE = 3 V 100 80 VCE = 4 V 60 40 TA = +50C VDD = 5 V RJA = 55C/W 20 0 VCE = 1 V 120 VCE = 2 V 100 VCE = 3 V 80 VCE = 4 V 60 40 TA = +50C VDD = 5 V RJA = 70C/W 20 0 0 20 40 60 80 100 DUTY CYCLE IN PER CENT 20 40 60 80 100 DUTY CYCLE IN PER CENT Dwg. GP-062-15 www.allegromicro.com 0 Dwg. GP-062-14 7 6277 8-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE (cont.) A6277xA A6277xLW VCE = 0.7 V 140 120 ALLOWABLE OUTPUT CURRENT IN mA/BIT ALLOWABLE OUTPUT CURRENT IN mA/BIT 140 VCE = 1 V 100 VCE = 2 V VCE = 3 V 80 60 VCE = 4 V 40 TA = +85C VDD = 5 V RJA = 55C/W 20 VCE = 0.7 V 120 VCE = 1 V 100 VCE = 2 V 80 VCE = 3 V 60 VCE = 4 V 40 TA = +85C VDD = 5 V RJA = 70C/W 20 0 0 0 20 40 60 80 0 100 20 40 TYPICAL CHARACTERISTICS OUTPUT CURRENT IN mA/BIT 60 40 TA = +25C REXT = 470 20 0 0.5 1.0 1.5 2.0 VCE IN VOLTS Dwg. GP-063-1 8 80 100 Dwg. GP-062-12 Dwg. GP-062-13 0 60 DUTY CYCLE IN PER CENT DUTY CYCLE IN PER CENT 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6277 8-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER TERMINAL DESCRIPTION Terminal No. Terminal Name Function 1 LOGIC GROUND Reference terminal for control logic. 2 SERIAL DATA IN Serial-data input to the shift-register. 3 CLOCK 4 LATCH ENABLE 5 HIGH/LOW (CURRENT) 6 POWER GROUND 7-14 OUT0-7 15 POWER GROUND Ground. 16 OUTPUT ENABLE When (active) low, the output drivers are enabled; when high, all output drivers are turned OFF (blanked). 17 SERIAL OUT2 CMOS serial-data output (on clock falling edge). 18 SERIAL OUT1 CMOS serial-data output (on clock rising edge) to the following shift-registers. 19 REXT 20 LOGIC SUPPLY Clock input terminal for data shift on rising edge. Data strobe input terminal; serial data is latched with high-level input. Logic low for 100% of programmed current level; logic high for 50% of programmed current level. Ground. The eight current-sinking output terminals. An external resistor at this terminal establishes the output current for all sink drivers. (VDD) The logic supply voltage. Typically 5 V. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. www.allegromicro.com 9 6277 8-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER Applications Information The load current per bit (IO) is set by the external resistor (REXT) as shown in the figure below. 140 VCE = 0.7 V 0.7 V per diode) for a group of drivers. If the available voltage source will cause unacceptable dissipation and series resistors or diode(s) are undesirable, a regulator such as the Sanken Series SAI or Series SI can be used to provide supply voltages as low as 3.3 V. OUTPUT CURRENT IN mA/BIT 120 For reference, typical LED forward voltages are: Blue 3.0 - 4.0 V Green 1.8 - 2.2 V Yellow 2.0 - 2.1 V Amber 1.9 - 2.65 V Red 1.6 - 2.25 V Infrared 1.2 - 1.5 V 100 80 60 40 20 0 100 200 300 500 700 1k 2k 3k 5k CURRENT-CONTROL RESISTANCE, REXT IN OHMS Dwg. GP-061-1 Package Power Dissipation (PD). The maximum allowable package power dissipation is determined as PD(max) = (150 - TA)/RJA. The actual package power dissipation is PD(act) = dc(VCE * IO * 8) + (VDD * IDD). When the load supply voltage is greater than 3 V to 5 V, considering the package power dissipating limits of these devices, or if PD(act) > PD(max), an external voltage reducer (VDROP) should be used. Load Supply Voltage (VLED). These devices are designed to operate with driver voltage drops (VCE) of 0.4 V to 0.7 V with LED forward voltages (VF) of 1.2 V to 4.0 V. If higher voltages are dropped across the driver, package power dissipation will be increased significantly. To minimize package power dissipation, it is recommended to use the lowest possible load supply voltage or to set any series dropping voltage (VDROP) as VDROP = VLED - VF - VCE with VDROP = Io * RDROP for a single driver, or a Zener diode (VZ), or a series string of diodes (approximately 10 Pattern Layout. This device has separate logic-ground and power-ground terminals. If ground pattern layout contains large common-mode resistance, and the voltage between the system ground and the LATCH ENABLE or CLOCK terminals exceeds 2.5 V (because of switching noise), these devices may not operate correctly. VLED V DROP VF V CE 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Dwg. EP-064 6277 8-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER A6277EA Dimensions in Inches (controlling dimensions) 0.014 0.008 11 20 0.430 MAX 0.280 0.240 0.300 BSC 1 0.070 0.045 0.100 1.060 0.980 10 0.005 BSC MIN 0.210 MAX 0.150 0.115 0.015 MIN 0.022 0.014 Dwg. MA-001-20 in Dimensions in Millimeters (for reference only) 20 0.355 0.204 11 10.92 MAX 7.11 6.10 7.62 BSC 1 1.77 1.15 2.54 26.92 24.89 10 0.13 BSC MIN 5.33 MAX 3.81 2.93 0.39 MIN 0.558 0.356 NOTES: 1. 2. 3. 4. Dwg. MA-001-20 mm Exact body and lead configuration at vendor's option within limits shown. Lead spacing tolerance is non-cumulative Lead thickness is measured at seating plane or below. Supplied in standard sticks/tubes of 18 devices. www.allegromicro.com 11 6277 8-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER A6277ELW Dimensions in Inches (for reference only) 20 11 0.0125 0.0091 0.419 0.394 0.2992 0.2914 0.050 0.016 0.020 0.013 1 2 0.050 3 0.5118 0.4961 0 TO 8 BSC 0.0926 0.1043 Dwg. MA-008-20 in 0.0040 MIN. Dimensions in Millimeters (controlling dimensions) 20 11 0.32 0.23 10.65 10.00 7.60 7.40 1.27 0.40 0.51 0.33 1 2 1.27 3 13.00 12.60 BSC 0 TO 8 2.65 2.35 0.10 MIN. Dwg. MA-008-20 mm NOTES: 1. Exact body and lead configuration at vendor's option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Supplied in standard sticks/tubes of 37 devices or add "TR" to part number for tape and reel. 12 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000