5 V-Powered
CMOS RS-232 Drivers/Receivers
ADM231L–ADM234L/ADM236L–ADM241L
Rev. C
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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
Single 5 V power supply
Meets all EIA-232-E and V.28 specifications
120 kbps data rate
On-board dc-to-dc converters
±9 V output swing with 5 V supply
Small 1 µF capacitors
Low power shutdown ≤1 µA
±30 V receiver input levels
Latch-up free
APPLICATIONS
Computers
Peripherals
Modems
Printers
Instruments
GENERAL DESCRIPTION
The ADM2xx family of line drivers/receivers is intended for all
EIA-232-E and V.28 communications interfaces, especially in
applications in which 12 V is not available. The ADM236L and
ADM241L feature a low power shutdown mode that reduces
power dissipation to less than 5 µW, making them ideally suited
for battery-powered equipment. The ADM233L does not
require any external components and is particularly useful in
applications where printed circuit board space is critical.
All members of the ADM2xxL family, except the ADM231L and
ADM239L, include two internal charge pump voltage converters
that allow operation from a single 5 V supply. These parts convert
the 5 V input power to the ±10 V required for RS-232 output
ADM236L TYPICAL OPERATING CIRCUIT
T1
IN
T1
OUT
T2
IN
T2
OUT
RS-232
OUTPUTS
T3
IN
T4
IN
R1
OUT
R1
IN
R2
OUT
R2
IN
TTL/CMOS
OUTPUTS
R3
IN
R3
OUT
T3
OUT
T4
OUT
1µF
+6.3V
1µF
+16V
C1+
C1–
C2–
C2+ V– 1µF
+16V
+10V TO –10V
VOLTAGE
INVERTER
1µF
+6.3V 1µF
+6.3V
+5V INPUT
V
CC
+5V TO +10V
VOLTAGE
DOUBLER
T1
T2
T3
T4
R1
R2
R3
V+
SD
ADM236L
GND
00070-0-015
T
TL/CMOS
INPUTS
1
RS-232
INPUTS
2
1
INTERNAL 400kΩPULL-UP RESISTOR ON EACH TTL/CMOS INPUT.
2
INTERNAL 5kΩPULL-DOWN RESISTOR ON EACH RS-232 INPUT.
EN
Figure 1.
levels. The ADM231L and ADM239L are designed to operate
from 5 V and 12 V supplies. An internal +12 V to −12 V charge
pump voltage converter generates the −12 V supply.
The ADM2xxL is an enhanced upgrade to the AD2xx family. It
features lower power consumption, faster slew rate, and the
ability to operate with smaller (1 µF) capacitors.
Table 1. Selection Table
Part
Number Power Supply Voltage
No. of RS-232
Drivers
No. of RS-232
Receivers
External
Capacitors
Low Power
Shutdown (SD)
TTL
Three-State EN
No. of
Pins
ADM231L 5 V and 7.5 V to 13.2 V 2 2 2 No No 14
ADM232L 5 V 2 2 4 No No 16
ADM233L 5 V 2 2 None No No 20
ADM234L 5 V 4 0 4 No No 16
ADM236L 5 V 4 3 4 Yes Yes 24
ADM237L 5 V 5 3 4 No No 24
ADM238L 5 V 4 4 4 No No 24
ADM239L 5 V and 7.5 V to 13.2 V 3 5 2 No Yes 24
ADM241L 5 V 4 5 4 Yes Yes 28
ADM231L–ADM234L/ADM236L–ADM241L
Rev. C | Page 2 of 20
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configurations and Function Descriptions ........................... 5
Typical Performance Characteristics ............................................. 8
Typical Operating Circuits .............................................................. 9
General Information ...................................................................... 12
Circuit Description .................................................................... 12
Application Hints ....................................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 17
REVISION HISTORY
4/05—Rev. B to Rev. C
Updated Format..................................................................Universal
Removed ADM223, ADM230L, and ADM235L............Universal
Changed Hysteresis Level..................................................Universal
Changes to Specifications Table...................................................... 3
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 17
5/01—Rev. A to Rev. B
Edits to Test Conditions/Comments of Specifications................ 2
1/01—Rev. 0 to Rev. A
Removed ESD information from Features section ...................... 1
Changes to Specifications Table...................................................... 2
Removed ESD information from
Absolute Maximum Ratings section .............................................. 2
Revision 0: Initial Version
ADM231L–ADM234L/ADM236L–ADM241L
Rev. C | Page 3 of 20
SPECIFICATIONS
VCC = 5 V ± 10% (ADM231L, ADM232L, ADM234L, ADM236L, ADM238L, ADM239L, ADM241L); VCC = 5 V ± 5% (ADM233L and
ADM237L); V+ = 7.5 V to 13.2 V (ADM231L and ADM239L); C1 to C4 = 1.0 µF ceramic. All specifications TMIN to TMAX, unless
otherwise noted.
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
Output Voltage Swing ±5 ±9 V All transmitter outputs loaded with 3 kΩ to ground
VCC Power Supply Current 2.5 6.0 mA No load, (ADM232L only)
3.5 13 mA No load
V+ Power Supply Current 1.5 4 mA No load, V+ = 12 V (ADM231L and ADM239L only)
Shutdown Supply Current 1 10 µA
Input Logic Threshold Low, VINL 0.8 V TIN, EN, SD, EN, SD
Input Logic Threshold High, VINH 2.0 V TIN, EN, SD, EN, SD
Logic Pull-Up Current 12 25 µA
RS-232 Input Voltage Range1 –30 +30 V TIN = 0 V
RS-232 Input Threshold Low 0.8 1.2 V
RS-232 Input Threshold High 1.6 2.4 V
RS-232 Input Hysteresis 0.65 V
RS-232 Input Resistance 3 5 7 kΩ TA = 0°C to 85°C
TTL/CMOS Output Voltage Low, VOL 0.4 V
TTL/CMOS Output Voltage High, VOH 3.5 V IOUT = −1.0 mA
TTL/CMOS Output Leakage Current +0.05 ±10 µA EN = VCC, 0 V ≤ ROUT ≤ VCC
Output Enable Time (TEN) 250 ns ADM236L, ADM239L, ADM241L (Figure 31, CL = 150 pF)
Output Disable Time (TDIS) 50 ns ADM236L, ADM239L, ADM241L (Figure 31, RL = 1 kΩ)
Propagation Delay 0.3 µs RS-232 to TTL
Transition Region Slew Rate 8 V/µs RL = 3 kΩ, CL = 2500 pF, measured from +3 V to −3 V or −3 V to +3 V
Output Resistance 300 Ω VCC = V+ = V– = 0 V, VOUT = ±2 V
RS-232 Output Short-Circuit Current ±10 mA
1 Guaranteed by design.
ADM231L–ADM234L/ADM236L–ADM241L
Rev. C | Page 4 of 20
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VCC –0.3 V to +6 V
V+ (VCC – 0.3 V) to +14 V
V– +0.3 V to −14 V
Input Voltages
TIN –0.3 V to (VCC + 0.3 V)
RIN ±30 V
Output Voltages
TOUT (V+, +0.3 V) to (V–, –0.3 V)
ROUT –0.3 V to (VCC + 0.3 V)
Short-Circuit Duration
TOUT Continuous
Power Dissipation
N-14 PDIP (Derate 10 mW/°C
above 70°C)
800 mW
N-16 PDIP (Derate 10.5 mW/°C
above 70°C)
840 mW
N-20 PDIP (Derate 11 mW/°C
above 70°C)
890 mW
N-24-1 PDIP (Derate
13.5 mW/°C above 70°C)
1000 mW
R-16 SOIC (Derate 9 mW/°C
above 70°C)
760 mW
R-24 SOIC (Derate 12 mW/°C
above 70°C)
850 mW
R-28 SOIC (Derate 12.5 mW/°C
above 70°C)
900 mW
RS-28 SSOP (Derate 10 mW/°C
above 70°C)
900 mW
Parameter Rating
Q-14 CERDIP (Derate 10 mW/°C
above 70°C)
720 mW
Q-16 CERDIP (Derate 10 mW/°C
above 70•C)
800 mW
Q-24 CERDIP (Derate
12.5 mW/°C above 70°C)
1000 mW
Thermal Impedance, θJA
N-14 PDIP 140°C/W
N-16 PDIP 135°C/W
N-20 PDIP 125°C/W
N-24-1 PDIP 120°C/W
R-16 SOIC 105°C/W
R-24 SOIC 85°C/W
R-28 SOIC 80°C/W
RS-28 SSOP 100°C/W
Q-14 CERDIP 105°C/W
Q-16 CERDIP 100°C/W
Q-24 CERDIP 55°C/W
Operating Temperature Range
Commercial (J Version) 0°C to 70°C
Industrial (A Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature, Soldering 300°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220° C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of
time may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADM231L–ADM234L/ADM236L–ADM241L
Rev. C | Page 5 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
TOP VIEW
(Not to Scale)
ADM231L
T1IN
T2IN
R2IN R1IN
T1OUT
T2OUT
R2OUT R1OUT
V+
V–
VCC
C1+
C1–
GND
00070-0-004
Figure 2. ADM231L PDIP Pin Configuration
NC
NC = NO CONNECT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TOP VIEW
(Not to Scale)
ADM231L
T1
IN
R1
IN
T1
OUT
R1
OUT
V+
V
CC
GND
T2
IN
R2
IN
T2
OUT
R2
OUT
V–
C1+
C1–
NC
00070-0-037
Figure 3. ADM231L SOIC Pin Configuration
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TOP VIEW
(Not to Scale)
ADM232L
T1
IN
R1
IN
T1
OUT
R1
OUT
V+
V
CC
GND
T2
IN
R2
IN
T
2
OUT
R2
OUT
V–
C1+
C1–
C2–
C2+
00070-0-006
Figure 4. ADM232L PDIP/CERDIP/SOIC Pin Configuration
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TOP VIEW
(Not to Scale)
ADM233L
R1
IN
T2
IN
R2
IN
T1
OUT
T2
OUT
R1
OUT
V+
V–
V
CC
C1+
C2– C2+
C1–
GND
GND C2+
C2–
R2
OUT
V–
T1
IN
00070-0-008
Figure 5. ADM233L PDIP Pin Configuration
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TOP VIEW
(Not to Scale)
ADM234L
T1
IN
T3
IN
T3
OUT
V+
V
CC
GND
T2
IN
T4
IN
T
1
OUT
T4
OUT
V–
C1+
C1–
C2–
C2+
T
2
OUT
00070-0-010
Figure 6. ADM234L PDIP/CERDIP/SOIC Pin Configuration
1
2
3
7
24
23
22
18
8
9
10
17
16
15
11
12
14
13
4
5
21
20
619
TOP VIEW
(Not to Scale)
ADM236L
T1IN
T2IN
T1OUT
T2OUT
T3OUT
VCC
GND
SD
EN
R3IN
R1IN
R2IN
R2OUT
R1OUT
R3OUT
T3IN
T4IN
T4OUT
V+
V–
C1+
C1– C2+
C–
00070-0-014
Figure 7. ADM236L PDIP/SOIC Pin Configuration
ADM231L–ADM234L/ADM236L–ADM241L
Rev. C | Page 6 of 20
1
2
3
7
24
23
22
18
8
9
10
17
16
15
11
12
14
13
4
5
21
20
619
TOP VIEW
(Not to Scale)
ADM237L
T1
IN
T2
IN
T1
OUT
T2
OUT
T3
OUT
V
CC
GND
R3
IN
R1
IN
R2
IN
R2
OUT
R1
OUT
R3
OUT
T3
IN
T4
IN
T4
OUT
V+
V–C1+
C1– C2+
C2–
T5
IN
T5
OUT
00070-0-016
Figure 8. ADM237L PDIP/CERDIP/SOIC Pin Configuration
1
2
3
7
24
23
22
18
8
9
10
17
16
15
11
12
14
13
4
5
21
20
619
TOP VIEW
(Not to Scale)
ADM238L
T1
IN
R1
IN
T1
OUT
R2
OUT
T2
OUT
V
CC
GND
R4
IN
R2
IN
R3
IN
R3
OUT
R1
OUT
R4
OUT
T2
IN
T3
IN
T3
OUT
V+
V–C1+
C1– C2+
C2–
T4
IN
T4
OUT
00070-0-018
Figure 9. ADM238L PDIP/CERDIP/SOIC Pin Configuration
1
2
3
7
24
23
22
18
8
9
10
17
16
15
11
12
14
13
4
5
21
20
619
TOP VIEW
(Not to Scale)
ADM239L
R4
IN
R5
IN
R1
IN
R4
OUT
R1
OUT
V
CC
GND
T3
IN
T2
IN
R2
OUT
R5
OUT
R3
OUT
R3
IN
T1
OUT
T1
IN
V+
NC
C+
C–
T3
OUT
R2
IN
T2
OUT
V–
00070-0-020
EN
Figure 10. ADM239L PDIP/CERDIP/SOIC Pin Configuration
1
2
3
7
28
27
26
22
8
9
10
21
20
19
11
12
18
17
4
5
25
24
623
TOP VIEW
(Not to Scale)
13
14
16
15
ADM241L
R2
OUT
R2
R5
IN
T4
IN
R3
IN
T1
OUT
T2
OUT
T3
OUT
T4
OUT
R5
OUT
V+
V–
V
CC
C1+
C1– C2+
C2–
GND
SD
OUT
R3
OUT
T3
IN
R4
IN
R4
OUT
R1
IN
R1
OUT
T1
IN
T2
IN
00070-0-022
EN
Figure 11. ADM241L SOIC/SSOP Pin Configuration
ADM231L–ADM234L/ADM236L–ADM241L
Rev. C | Page 7 of 20
Table 4. Pin Function Descriptions
Mnemonic Function
VCC Power Supply Input. 5 V ± 10% (5 V ± 5% for ADM233L).
V+ Internally Generated Positive Supply (+10 V nominal) on all parts, except ADM231L and ADM239L. ADM231L and ADM239L
require an external 7.5 V to 13.2 V supply.
V− Internally Generated Negative Supply (−10 V nominal).
GND Ground Pin. Must be connected to 0 V.
C+ (ADM231L and ADM239L only) External capacitor (+ terminal) is connected to this pin.
C− (ADM231L and ADM239L only) External capacitor (– terminal) is connected to this pin.
C1+ (ADM232L, ADM234L, ADM236L, ADM237L, ADM238L, and ADM241L) External capacitor (+ terminal) is connected to this
pin. (ADM233L) The capacitor is connected internally and no external connection to this pin is required.
C1− (ADM232L, ADM234L, ADM236L, ADM237L, ADM238L, and ADM241L) External capacitor (− terminal) is connected to this
pin. (ADM233L) The capacitor is connected internally and no external connection to this pin is required.
C2+ (ADM232L, ADM234L, ADM236L, ADM237L, ADM238L, and ADM241L) External capacitor (+ terminal) is connected to this
pin. (ADM233L) Internal capacitor connections, Pin 11 and Pin 15, must be connected together.
C2− (ADM232L, ADM234L, ADM236L, ADM237L, ADM238L, and ADM241L) External capacitor (− terminal) is connected to this
pin. (ADM233L) Internal capacitor connections, Pin 10 and Pin 16, must be connected together.
TIN Transmitter (Driver) Inputs. These inputs accept TTL/CMOS levels. An internal 400 kΩ pull-up resistor to VCC is connected to
each input.
TOUT Transmitter (Driver) Outputs. These are RS-232 levels (typically ±10 V).
RIN Receiver Inputs. These inputs accept RS-232 signal levels. An internal 5 kΩ pull-down resistor to GND is connected on each input.
ROUT Receiver Outputs. These are TTL/CMOS levels.
EN
Enable Input. Active low on ADM236L, ADM239L, and ADM241L. This input is used to enable/disable the receiver outputs.
With EN = low, the receiver outputs are enabled. With EN = high, the outputs are placed in a high impedance state. This
facility is useful for connecting to microprocessor systems.
SD Shutdown Input. Active high on ADM236L and ADM241L. With SD = high on the ADM236L and ADM241L, the charge pump
is disabled, the receiver outputs are placed in a high impedance state, and the driver outputs are turned off.
NC No Connect. No connections are required to this pin.
Table 5. ADM236L and ADM241L Truth Table
SD EN Status Transmitters T1 to T5 Receivers R1 to R5
0 0 Normal Operation Enabled Enabled
0 1 Normal Operation Enabled Disabled
1 0 Shutdown Disabled Disabled
ADM231L–ADM234L/ADM236L–ADM241L
Rev. C | Page 8 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
LOAD CURRENT (mA)
–15 510
V+/V– (V)
V+
15
V–
20
0
–10
–5
0
5
10
15
00070-0-026
Figure 12. Charge Pump V+ and V− vs. Current
LOAD CAPACITANCE (pF)
00 500
SLEW RATE (V/
µ
s)
5
NEGATIVE
SLEW
50
1000
10
15
20
25
30
35
40
45
POSITIVE
SLEW
1500 2000 2500 3000
00070-0-027
Figure 13. Transmitter Slew Rate vs. Load Capacitance
V
CC
(V)
–94.0 4.5
Tx O/P (V)
5.0 5.5 6.0
–7
–5
–3
–1
1
3
5
7
9
Tx O/P HI LOADED
Tx O/P LO LOADED
00070-0-028
Figure 14. Transmitter Output Voltage vs. VCC
LOAD CURRENT (mA)
–15 0
Tx O/P (V)
Tx O/P HI
48
–10
–5
0
5
10
15
Tx O/P LO
10
00070-0-029
62
Figure 15. Transmitter Output Voltage vs. Current
VCC (V)
04.5 4.7
IMPEDANCE (Ω)
200
100
50
V+ IMP
V– IMP
150
250
300
350
4.9 5.1 5.3 5.5
00070-0-030
Figure 16. Charge Pump Impedance vs. VCC
ADM231L–ADM234L/ADM236L–ADM241L
Rev. C | Page 9 of 20
TYPICAL OPERATING CIRCUITS
ADM231L
1µF
+16V
C1+
C1–
T1IN T1 T1OUT
T2IN T2 T2OUT
RS-232
OUTPUTS
R1OUT R1 R1IN
R2OUT R2IN
TTL/CMOS
OUTPUTS R2
V– 1µF
+16V
+12V TO –12V
VOLTAGE
INVERTER
V+
GND
+7.5V TO +13.2V
VCC
1µF
+5V INPUT
00070-0-005
TTL/CMOS
INPUTS1
RS-232
INPUTS2
1INTERNAL 400kΩPULL-UP RESISTOR ON EACH TTL/CMOS INPUT.
2INTERNAL 5kΩPULL-DOWN RESISTOR ON EACH RS-232 INPUT.
1
2
8
7
9
6
12
5
10
4
11
3
13
14
Figure 17. ADM231L Typical Operating Circuit (PDIP Pinout)
ADM232L
1µF
+6.3V
1µF
+16V
C1+
C1–
C2–
C2+
T1
IN
T1 T1
OUT
T2
IN
T2 T2
OUT
RS-232
OUTPUTS
R1
OUT
R1 R1
IN
R2
OUT
R2
IN
T
TL/CMO
S
OUTPUTS R2
V– 1µF
+16V
+10V TO –10V
VOLTAGE
INVERTER
1µF
+6.3V 1µF
+6.3V
5V INPUT
V+
V
CC
+5V TO +10V
VOLTAGE
DOUBLER
GND
00070-0-007
TTL/CMOS
INPUTS
1
RS-232
INPUTS
2
1
INTERNAL 400kΩPULL-UP RESISTOR ON EACH TTL/CMOS INPUT.
2
INTERNAL 5kΩPULL-DOWN RESISTOR ON EACH RS-232 INPUT.
Figure 18. ADM232L Typical Operating Circuit
ADM233L
C1+
C1–
V–
V–
T1
IN
T1 T1
OUT
T2
IN
T2 T2
OUT
RS-232
OUTPUTS
R1
OUT
R1 R1
IN
R2
OUT
R2
IN
TTL/CMOS
OUTPUTS R2
C2–
C2+
V
CC
GND
+5V INPUT
GND
INTERNAL
–10V POWER
SUPPLY
INTERNAL
+10V POWER
SUPPLY V+
C2+
C2–
DO NOT MAKE
CONNECTIONS TO
THESE PINS
00070-0-009
TTL/CMOS
INPUTS
1
RS-232
INPUTS
2
1
INTERNAL 400kΩPULL-UP RESISTOR ON EACH TTL/CMOS INPUT.
2
INTERNAL 5kΩPULL-DOWN RESISTOR ON EACH RS-232 INPUT.
Figure 19. ADM233L Typical Operating Circuit
ADM234L
1µF
+6.3V
1µF
+16V
C1+
C1–
C2–
C2+
T1
IN
T1 T1
OUT
T2
IN
T2 T2
OUT
RS-232
OUTPUTS
V– 1µF
+16V
+10V TO –10V
VOLTAGE
INVERTER
1µF
+6.3V
1µF
+6.3V
5V INPUT
V+
V
CC
+5V TO +10V
VOLTAGE
DOUBLER
T3
T4
T3
IN
T4
IN
GND
T3
OUT
T4
OUT
00070-0-011
T
TL/CMOS
INPUTS
1
1
INTERNAL 400kΩPULL-UP RESISTOR ON EACH TTL/CMOS INPUT.
Figure 20. ADM234L Typical Operating Circuit
ADM231L–ADM234L/ADM236L–ADM241L
Rev. C | Page 10 of 20
T1
IN
T1
OUT
T2
IN
T2
OUT
RS-232
OUTPUTS
T3
IN
T4
IN
R1
OUT
R1
IN
R2
OUT
R2
IN
TTL/CMOS
OUTPUTS
R3
IN
R3
OUT
T3
OUT
T4
OUT
1µF
+6.3V
1µF
+16V
C1+
C1–
C2–
C2+ V– 1µF
+16V
+10V TO –10V
VOLTAGE
INVERTER
1µF
+6.3V 1µF
+6.3V
+5V INPUT
V
CC
+5V TO +10V
VOLTAGE
DOUBLER
T1
T2
T3
T4
R1
R2
R3
V+
SD
ADM236L
GND
00070-0-015
T
TL/CMOS
INPUTS
1
RS-232
INPUTS
2
1
INTERNAL 400kΩPULL-UP RESISTOR ON EACH TTL/CMOS INPUT.
2
INTERNAL 5kΩPULL-DOWN RESISTOR ON EACH RS-232 INPUT.
EN
Figure 21. ADM236L Typical Operating Circuit
T1
IN
T1
OUT
T2
IN
T2
OUT
RS-232
OUTPUTS
T3
IN
T4
IN
T5
IN
R1
OUT
R1
IN
R2
OUT
R2
IN
TTL/CMOS
OUTPUTS
R3
IN
R3
OUT
T3
OUT
T4
OUT
T5
OUT
1µF
+6.3V
1µF
+16V
C1+
C1–
C2–
C2+ V– 1µF
+16V
+10V TO –10V
VOLTAGE
INVERTER
1µF
+6.3V 1µF
+6.3V
+5V INPUT
V
CC
+5V TO +10V
VOLTAGE
DOUBLER
T1
T2
T3
T4
T5
R1
R2
R3
V+
ADM237L
20
GND
00070-0-017
T
TL/CMOS
INPUTS
1
RS-232
INPUTS
2
1
INTERNAL 400kΩPULL-UP RESISTOR ON EACH TTL/CMOS INPUT.
2
INTERNAL 5kΩPULL-DOWN RESISTOR ON EACH RS-232 INPUT.
Figure 22. ADM237L Typical Operating Circuit
ADM238L
T1
IN
T1 T1
OUT
T2
IN
T2 T2
OUT
RS-232
OUTPUTS
T3
T4
T3
IN
T4
IN
R1
OUT
R1 R1
IN
R2
OUT
R2 R2
IN
TTL/CMOS
OUTPUTS R3
IN
R4
IN
R3
OUT
R4
OUT
T3
OUT
T4
OUT
GND
R3
R4
1µF
+6.3V
1µF
+16V
C1+
C1–
C2–
C2+ V– 1µF
+16V
+10V TO –10V
VOLTAGE
INVERTER
1µF
+6.3V 1µF
+6.3V
+5V INPUT
V+
V
CC
+5V TO +10V
VOLTAGE
DOUBLER
00070-0-019
T
TL/CMOS
INPUTS
1
RS-232
INPUTS
2
1
INTERNAL 400kΩPULL-UP RESISTOR ON EACH TTL/CMOS INPUT.
2
INTERNAL 5kΩPULL-DOWN RESISTOR ON EACH RS-232 INPUT.
Figure 23. ADM238L Typical Operating Circuit
ADM231L–ADM234L/ADM236L–ADM241L
Rev. C | Page 11 of 20
ADM239L
T1
IN
T1 T1
OUT
T2
IN
T2 T2
OUT
RS-232
OUTPUTS
T3
T3
IN
R1
OUT
R1
IN
R2
OUT
R2
IN
TTL/CMOS
OUTPUTS R3
IN
R4
IN
R5
IN
R3
OUT
R4
OUT
R5
OUT
T3
OUT
NC
GND
1µF
+16V
C1+
C1– V– 1µF
+16V
+12V TO –12V
VOLTAGE
INVERTER
1µF
V+
V
CC
+7.5V TO +13.2V
INPUT
R1
R2
R3
R4
R5
00070-0-021
T
TL/CMOS
INPUTS
1
RS-232
INPUTS
2
1
INTERNAL 400kΩPULL-UP RESISTOR ON EACH TTL/CMOS INPUT.
2
INTERNAL 5kΩPULL-DOWN RESISTOR ON EACH RS-232 INPUT.
EN
+5V INPUT
Figure 24. ADM239L Typical Operating Circuit
ADM241L
T1
IN
T1 T1
OUT
T2
IN
T2 T2
OUT
RS-232
OUTPUTS
T3
T4
T3
IN
T4
IN
R1
OUT
R1 R1
IN
R2
OUT
R2 R2
IN
TTL/CMOS
OUTPUTS R3
IN
R4
IN
R5
IN
R3
OUT
R4
OUT
R5
OUT
T3
OUT
T4
OUT
SD
GND
R3
R4
R5
1
µ
F
+16V
C1+
C1–
C2–
C2+ V– 1
µ
F
+16V
+10V TO –10V
VOLTAGE
INVERTER
1
µ
F
+6.3V 1
µ
F
+6.3V
+5V INPUT
V+
V
CC
+5V TO +10V
VOLTAGE
DOUBLER
1
µ
F
+16V
00070-0-023
TTL/CMOS
INPUTS
1
RS-232
INPUTS
2
1
INTERNAL 400kΩPULL-UP RESISTOR ON EACH TTL/CMOS INPUT.
2
INTERNAL 5kΩPULL-DOWN RESISTOR ON EACH RS-232 INPUT.
EN
Figure 25. ADM241L Typical Operating Circuit
ADM231L–ADM234L/ADM236L–ADM241L
Rev. C | Page 12 of 20
GENERAL INFORMATION
The ADM231L–ADM234L/ADM236L–ADM241L family of
RS-232 drivers/receivers is designed to solve interface problems
by meeting the EIA-232-E specifications while using a single
digital 5 V supply. The EIA-232-E standard requires that trans-
mitters deliver ±5 V minimum on the transmission channel
and that receivers can accept signal levels down to ±3 V. The
ADM231L–ADM234L/ADM236L–ADM241L meet these
requirements by integrating step-up voltage converters and
level-shifting transmitters and receivers onto the same chip.
CMOS technology is used to keep the power dissipation to
an absolute minimum. A comprehensive range of transmitter/
receiver combinations is available for most communications needs.
The ADM236L and ADM241L are particularly useful in
battery-powered systems because they feature a low power
shutdown mode that reduces power dissipation to less than 5 µW.
The ADM233L is designed for applications in which space
saving is important because the charge pump capacitors are
molded into the package. The ADM231L and ADM239L
include only a negative charge pump converter and are intended
for applications in which +12 V is available.
To facilitate sharing a common line or for connection to a
microprocessor data bus, the ADM236L, ADM239L, and
ADM241L feature an enable (EN, EN) function. When the
receivers are disabled, their outputs are placed in a high
impedance state.
1
CH1
CH3 5.00V
5.00V
BW
CH2 5.00V M50.0
µ
sCH1 3.1V
V+, V– EXITING SD
T
T
T
SD
V+
V–
00070-0-031
Figure 26. Charge Pump V+ and V− Exiting Shutdown
1
CH1 5.00V CH2 5.00V M1.00
µ
s CH1 800mV
TT
Tx OUTPUT
Tx INPUT
2
00070-0-032
Figure 27. Transmitter Output Loaded Slew Rate
1
CH1 5.00V CH2 5.00V M1.00
µ
s CH1 800mV
T
T
Tx OUTPUT
Tx INPUT
2
00070-0-033
Figure 28. Transmitter Output Unloaded Slew Rate
CIRCUIT DESCRIPTION
The internal circuitry in the ADM236L to ADM241L consists of
three main sections: a charge pump voltage converter, RS-232-to-
TTL/CMOS receivers, and TTL/CMOS-to-RS-232 transmitters.
Charge Pump DC-to-DC Voltage Converter
The charge pump voltage converter consists of an oscillator and
a switching matrix. The converter generates a 10 V supply from
the 5 V input. This is done in two stages using a switched
capacitor technique, as illustrated in Figure 29 and Figure 30.
First, the 5 V input supply is doubled to 10 V, using capacitor
C1 as the charge storage element. The 10 V level is then
inverted to generate –10 V, using C2 as the storage element.
S1 S3 V+ = 2V
CC
S2 S4
INTERNAL
OSCILLATOR
C1 C3
V
CC
GND V
CC
00070-0-034
Figure 29. Charge Pump Voltage Doubler
S1 S3
S2 S4
INTERNAL
OSCILLATOR
C2 C4
V
+
GND V– = –(V+)
++GND
FROM
VOLTAGE
DOUBLER
00070-0-035
Figure 30. Charge Pump Voltage Inverter
Capacitors C3 and C4 are used to reduce the output ripple.
Their values are not critical and can be reduced if higher levels
of ripple are acceptable. The charge pump capacitors, C1 and C2,
can be reduced at the expense of higher output impedance on the
V+ and V– supplies, and the V+ and V– supplies can be used to
power external circuitry if the current requirements are small.
ADM231L–ADM234L/ADM236L–ADM241L
Rev. C | Page 13 of 20
Transmitter (Driver) Section
The drivers convert TTL/CMOS input levels into EIA-232-E
output levels. With VCC = +5 V and driving a typical EIA-232-E
load, the output voltage swing is ±9 V. Even under worst-case
conditions, the drivers are guaranteed to meet the ±5 V
EIA-232-E minimum requirement.
The input threshold levels are both TTL- and CMOS-compatible
with the switching threshold set at VCC/4. With a nominal VCC =
5 V, the switching threshold is 1.25 V typical. Unused inputs can
be left unconnected because an internal 400 kΩ pull-up resistor
pulls them high, forcing the outputs into a low state.
As required by the EIA-232-E standard, the slew rate is limited to
less than 30 V/µs without the need for an external slew-limiting
capacitor, and the output impedance in the power-off state is
greater than 300 Ω.
Receiver Section
The receivers are inverting level shifters that accept EIA-232-E
input levels (±5 V to ±15 V) and translate them into 5 V TTL/
CMOS levels. The inputs have internal 5 kΩ pull-down resistors
to ground and are protected against overvoltages of up to ±30 V.
The guaranteed switching thresholds are 0.8 V minimum and
2.4 V maximum, which are well within the ±3 V EIA-232-E
requirement. The low level threshold is deliberately positive
because it ensures that an unconnected input is interpreted as
a low level.
The receivers have Schmitt trigger inputs with a hysteresis level
of 0.65 V. This ensures error-free reception for both noisy inputs
and inputs with slow transition times.
Shutdown (SD)
The ADM236L and ADM241L feature a control input that can
be used to disable the part and reduce the power consumption
to less than 5 µW. This is very useful in battery-operated systems.
During shutdown, the charge pump is turned off, the transmitters
are disabled, and all receivers are put into a high impedance,
disabled state. The shutdown control input is active high on all
parts (see Table 5).
Enable Input
ADM239L and ADM241L feature an enable input used to enable
or disable the receiver outputs. The enable input is active low on
the ADM239L and ADM241L (see Table 5). When the receivers
are disabled, their outputs are placed in a high impedance state.
This function allows the outputs to be connected directly to a
microprocessor data bus. It can also be used to allow receivers
from different devices to share a common data line. The timing
diagram for the enable function is shown in Figure 31.
T
EN
T
DIS
3V
0V
R
OUT
3.5V
0.8V
V
OH
– 0.1V
V
OL
+ 0.1V
00070-0-036
EN
Figure 31. Enable Timing
APPLICATION HINTS
Driving Long Cables
In accordance with the EIA-232-E standard, long cables are per-
missible, provided that the total load capacitance does not exceed
2500 pF. For longer cables that do exceed this, it is possible to trade
off baud rate for cable length. Large load capacitances cause a
reduction in slew rate; therefore, the maximum transmission baud
rate is decreased. The ADM236L to ADM241L are designed to
minimize the slew rate reduction that occurs as load capaci-
tance increases.
For the receivers, it is important that a high level of noise
immunity be built in so that slow rise and fall times do not
cause multiple output transitions as the signal passes slowly
through the transition region. The ADM236L to ADM241L
have 0.65 V of hysteresis to guard against this. This ensures that
even in noisy environments error-free reception can be
achieved.
High Baud Rate Operation
The ADM236L to ADM241L feature high slew rates, permitting
data transmission at rates well in excess of the EIA-232-E
specification. The drivers maintain ±5 V signal levels at data
rates up to 100 kbps under worst-case loading conditions.
ADM231L–ADM234L/ADM236L–ADM241L
Rev. C | Page 14 of 20
OUTLINE DIMENSIONS
14
17
8
0.685 (17.40)
0.665 (16.89)
0.645 (16.38) 0.295 (7.49)
0.285 (7.24)
0.275 (6.99)
0.100 (2.54)
BSC
SEATING
PLANE
0.180 (4.57)
MAX
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 (3.81)
0.130 (3.30)
0.110 (2.79) 0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.015 (0.38)
MIN 0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-095-AB
Figure 32. 14-Lead Plastic Dual In-Line Package [PDIP]
(N-14)
Dimensions shown in inches and (millimeters)
16
18
9
0.295 (7.49)
0.285 (7.24)
0.275 (6.99)
0.100 (2.54)
BSC
SEATING
PLANE
0.015 (0.38)
MIN
0.180 (4.57)
MAX
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 (3.81)
0.130 (3.30)
0.110 (2.79) 0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.785 (19.94)
0.765 (19.43)
0.745 (18.92)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-095AC
Figure 33. 16-Lead Plastic Dual In-Line Package [PDIP]
(N-16)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-013AA
SEATING
PLANE
0.30 (0.0118)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
2.65 (0.1043)
2.35 (0.0925)
1.27 (0.0500)
BSC
16 9
8
1
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
10.50 (0.4134)
10.10 (0.3976)
8°
0°
0.75 (0.0295)
0.25 (0.0098) × 45°
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COPLANARITY
0.10
Figure 34. 16-Lead Standard Small Outline Package [SOIC]
Wide Body (R-16)
Dimensions shown in millimeters and (inches)
14
17
8
0.310 (7.87)
0.220 (5.59)
PIN 1
0.005 (0.13) MIN 0.098 (2.49) MAX
0.100 (2.54) BSC
15°
0°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.200 (5.08)
MAX
0.785 (19.94) MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36) 0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
ONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FO
R
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIG
N
Figure 35. 14-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-14)
Dimensions shown in inches and (millimeters)
ADM231L–ADM234L/ADM236L–ADM241L
Rev. C | Page 15 of 20
16
18
9
0.310 (7.87)
0.220 (5.59)
PIN 1
0.005
(0.13)
MIN
0.098 (2.49)
MAX
15°
0°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.200 (5.08)
MAX 0.840 (21.34) MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 36. 16-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-16)
Dimensions shown in inches and (millimeters)
20
110
11
0.985 (25.02)
0.965 (24.51)
0.945 (24.00) 0.295 (7.49)
0.285 (7.24)
0.275 (6.99)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
SEATING
PLANE
0.015 (0.38) MIN
0.180 (4.57)
MAX
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 (3.81)
0.130 (3.30)
0.110 (2.79) 0.100
(2.54)
BSC
0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-095-AE
Figure 37. 20-Lead Plastic Dual In-Line Package [PDIP]
(N-20)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-013AC
0.75 (0.0295)
0.25 (0.0098)
20 11
10
1
8°
0°
× 45°
1.27 (0.0500)
0.40 (0.0157)
SEATING
PLANE
0.30 (0.0118)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
2.65 (0.1043)
2.35 (0.0925)
0.33 (0.0130)
0.20 (0.0079)
1.27
(0.0500)
BSC
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
13.00 (0.5118)
12.60 (0.4961)
COPLANARITY
0.10
Figure 38. 20-Lead Standard Small Outline Package [SOIC]
Wide Body (R-20)
Dimensions shown in millimeters and (inches)
20
110
11
0.310 (7.87)
0.220 (5.59)
PIN 1
0.005
(0.13)
MIN
0.098 (2.49)
MAX
15°
0°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.200 (5.08)
MAX 1.060 (26.92) MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 39. 20-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-20)
Dimensions shown in inches and (millimeters)
24
112
13
1.185 (30.01)
1.165 (29.59)
1.145 (29.08) 0.295 (7.49)
0.285 (7.24)
0.275 (6.99)
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
SEATING
PLANE
0.015 (0.38) MIN
0.180
(4.57)
MAX
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0
.150 (3.81)
0
.130 (3.30)
0
.110 (2.79) 0.100
(2.54)
BSC
0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-095AG
Figure 40. 24-Lead Plastic Dual In-Line Package [PDIP]
(N-24-1)
Dimensions shown in inches and (millimeters)
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
0.075 (1.91)
0.015 (0.38)
0.225 (5.72)
MAX
0.200 (5.08)
0.120 (3.05) 0.070 (1.78)
0.030 (0.76)
0.150
(3.81)
MIN
1.290 (32.77) MAX
0.100 (2.54)
BSC
24
21
13
0.610 (15.49)
0.500 (12.70)
PIN 1
0.098 (2.49) MAX
0.005 (0.13) MIN
0.620 (15.75)
0.590 (14.99)
0.015 (0.38)
0.008 (0.20)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 41. 24-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]
(D-24-2)
Dimensions shown in inches and (millimeters)
ADM231L–ADM234L/ADM236L–ADM241L
Rev. C | Page 16 of 20
1.290 (32.77)
1.150 (31.57)
0.580 (14.73)
0.485 (12.32)
0.165 (4.19)
0.160 (4.06)
0.155 (3.93)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
0.610 (15.49)
0.600 (15.24)
0.590 (14.99)
0.015 (0.38) MIN
0
.210 (5.34)
MAX
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
0.200 (5.08)
0.115 (2.92)
24
112
13
PIN 1
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-011-AA
Figure 42. 24-Lead Plastic Dual In-Line Package [PDIP]
Wide Body (N-24-2)
Dimensions shown in inches and (millimeters)
24
112
13
0.310 (7.87)
0.220 (5.59)
PIN 1
0.005 (0.13)
MIN 0.098 (2.49)
MAX
15°
0°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.200 (5.08)
MAX 1.280 (32.51) MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 43. 24-Lead Ceramic Dual in-Line Package [CERDIP]
(Q-24)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-013AD
8°
0°
0.75 (0.0295)
0.25 (0.0098) ×45°
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
SEATING
PLANE
0.30 (0.0118)
0.10 (0.0039)
0.51 (0.020)
0.31 (0.012)
2.65 (0.1043)
2.35 (0.0925)
1.27 (0.0500)
BSC
24 13
12
110.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
15.60 (0.6142)
15.20 (0.5984)
COPLANARIT
Y
0.10
Figure 44. 24-Lead Standard Small Outline Package [SOIC]
Wide Body (R-24)
Dimensions shown in millimeters and (inches)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-013AE
0.33 (0.0130)
0.20 (0.0079)
8°
0°
0.75 (0.0295)
0.25 (0.0098) ×45°
1.27 (0.0500)
0.40 (0.0157)
SEATING
PLANE
0.30 (0.0118)
0.10 (0.0039)
0.51 (0.0201)
0.33 (0.0130)
2.65 (0.1043)
2.35 (0.0925)
1.27 (0.0500)
BSC
28 15
14
1
18.10 (0.7126)
17.70 (0.6969)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
COPLANARITY
0.10
Figure 45. 28-Lead Standard Small Outline Package [SOIC]
Wide Body (R-28)
Dimensions shown in millimeters and (inches)
0.25
0.09 0.95
0.75
0.55
8°
4°
0°
0.05 MIN
1.85
1.75
1.65
2.00 MAX
0.38
0.22 SEATING
PLANE
0.65
BSC
COPLANARITY
0.10
28 15
14
1
10.50
10.20
9.90
5.60
5.30
5.00
8.20
7.80
7.40
PIN 1
COMPLIANT TO JEDEC STANDARDS MO-150AH
Figure 46. 28-Lead Shrink Small Outline Package [SSOP]
(RS-28)
Dimensions shown in millimeters
ADM231L–ADM234L/ADM236L–ADM241L
Rev. C | Page 17 of 20
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADM231LJN 0°C to 70°C 14-lead PDIP N-14
ADM231LJR 0°C to 70°C 16-lead SOIC R-16
ADM231LJR-REEL 0°C to 70°C 16-lead SOIC R-16
ADM231LJRZ-REEL1 0°C to 70°C 16-lead SOIC R-16
ADM231LAN –40°C to +85°C 14-lead PDIP N-14
ADM231LAQ –40°C to +85°C 14-lead CERDIP Q-14
ADM231LAR –40°C to +85°C 16-lead SOIC R-16
ADM231LAR-REEL –40°C to +85°C 16-lead SOIC R-16
ADM232LJR 0°C to 70°C 16-lead SOIC R-16
ADM232LJR-REEL 0°C to 70°C 16-lead SOIC R-16
ADM232LJRZ1 0°C to 70°C 16-lead SOIC R-16
ADM232LJRZ-REEL71 0°C to 70°C 16-lead SOIC R-16
ADM232LAN –40°C to +85°C 16-lead PDIP N-16
ADM232LAR –40°C to +85°C 16-lead SOIC R-16
ADM232LAR-REEL –40°C to +85°C 16-lead SOIC R-16
ADM232LARZ1 –40°C to +85°C 16-lead SOIC R-16
ADM232LARZ-REEL1 –40°C to +85°C 16-lead SOIC R-16
ADM232LJN 0°C to 70°C 20-lead PDIP N-16
ADM232LJNZ1 0°C to 70°C 20-lead PDIP N-16
ADM233LJN 0°C to 70°C 20-lead PDIP N-20
ADM233LAN –40°C to +85°C 20-lead PDIP N-20
ADM234LJN 0°C to 70°C 16-lead PDIP N-16
ADM234LJR 0°C to 70°C 16-lead SOIC R-16
ADM234LJR-REEL 0°C to 70°C 16-lead SOIC R-16
ADM234LJRZ1 0°C to 70°C 16-lead SOIC R-16
ADM234LJRZ-REEL1 0°C to 70°C 16-lead SOIC R-16
ADM234LAN –40°C to +85°C 16-lead PDIP N-16
ADM234LAQ –40°C to +85°C 16-lead CERDIP Q-16
ADM234LAR –40°C to +85°C 16-lead SOIC R-16
ADM234LAR-REEL –40°C to +85°C 16-lead SOIC R-16
ADM236LJN 0°C to 70°C 24-lead PDIP N-24-1
ADM236LJR 0°C to 70°C 24-lead SOIC R-24
ADM236LJR-REEL 0°C to 70°C 24-lead SOIC R-24
ADM236LAN –40°C to +85°C 24-lead PDIP N-24-1
ADM236LAR –40°C to +85°C 24-lead SOIC R-24
ADM236LAR-REEL –40°C to +85°C 24-lead SOIC R-24
ADM237LJN 0°C to 70°C 24-lead PDIP N-24-1
ADM237LJR 0°C to 70°C 24-lead SOIC R-24
ADM237LJR-REEL 0°C to 70°C 24-lead SOIC R-24
ADM237LJRZ1 0°C to 70°C 24-lead SOIC R-24
ADM237LJRZ-REEL1 0°C to 70°C 24-lead SOIC R-24
ADM237LAN –40°C to +85°C 24-lead PDIP N-24-1
ADM237LAQ –40°C to +85°C 24-lead CERDIP Q-24
ADM237LAR –40°C to +85°C 24-lead SOIC R-24
ADM237LAR-REEL –40°C to +85°C 24-lead SOIC R-24
ADM238LJN 0°C to 70°C 24-lead PDIP N-24-1
ADM238LJNZ1 0°C to 70°C 24-lead PDIP N-24-1
ADM238LJR 0°C to 70°C 24-lead SOIC R-24
ADM238LJR-REEL 0°C to 70°C 24-lead SOIC R-24
ADM238LJRZ1 0°C to 70°C 24-lead SOIC R-24
ADM238LJRZ-REEL1 0°C to 70°C 24-lead SOIC R-24
ADM231L–ADM234L/ADM236L–ADM241L
Rev. C | Page 18 of 20
Model Temperature Range Package Description Package Option
ADM238LAN –40°C to +85°C 24-lead PDIP N-24-1
ADM238LAQ –40°C to +85°C 24-lead CERDIP Q-24
ADM238LAR –40°C to +85°C 24-lead SOIC R-24
ADM238LAR-REEL –40°C to +85°C 24-lead SOIC R-24
ADM238LARZ1 –40°C to +85°C 24-lead SOIC R-24
ADM238LARZ-REEL1 –40°C to +85°C 24-lead SOIC R-24
ADM239LJN 0°C to 70°C 24-lead PDIP N-24-1
ADM239LJR 0°C to 70°C 24-lead SOIC R-24
ADM239LJR-REEL 0°C to 70°C 24-lead SOIC R-24
ADM239LJRZ1 0°C to 70°C 24-lead SOIC R-24
ADM239LJRZ-REEL1 0°C to 70°C 24-lead SOIC R-24
ADM239LAN –40°C to +85°C 24-lead PDIP N-24-1
ADM239LAQ –40°C to +85°C 24-lead CERDIP Q-24
ADM239LAR –40°C to +85°C 24-lead SOIC R-24
ADM239LAR-REEL –40°C to +85°C 24-lead SOIC R-24
ADM241LJR 0°C to 70°C 28-lead SOIC R-28
ADM241LJR-REEL 0°C to 70°C 28-lead SOIC R-28
ADM241LJRZ1 0°C to 70°C 28-lead SOIC R-28
ADM241LJRZ-REEL1 0°C to 70°C 28-lead SOIC R-28
ADM241LAR –40°C to +85°C 28-lead SOIC R-28
ADM241LAR-REEL –40°C to +85°C 28-lead SOIC R-28
ADM241LJRS 0°C to 70°C 28-lead SSOP RS-28
ADM241LJRS-REEL 0°C to 70°C 28-lead SSOP RS-28
ADM241LARS –40°C to +85°C 28-lead SSOP RS-28
ADM241LARS-REEL –40°C to +85°C 28-lead SSOP RS-28
1 Z = Pb-free part.
ADM231L–ADM234L/ADM236L–ADM241L
Rev. C | Page 19 of 20
NOTES
ADM231L–ADM234L/ADM236L–ADM241L
Rev. C | Page 20 of 20
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00070–0–4/05(C)