FN7969 Rev 1.00 Page 1 of 9
January 15, 2016
FN7969
Rev 1.00
January 15, 2016
ISL80138
40V, Low Quiescent Current, 150mA Linear Regulator
DATASHEET
The ISL80138 is a high voltage, adjustable VOUT low quiescent
current linear regulator ideally suited for “always-on” and
“keep alive” applications. The ISL80138 operates from an
input voltage of +6V to +40V under normal operating
conditions and consumes only 18µA of quiescent current at no
load.
The ISL80138 features an EN pin that can be used to put the
device into a low-quiescent current shutdown mode where it
draws only 2µA of supply current. The device features
over-temperature shutdown and current limit protection.
The ISL80138 is rated to operate across the -40°C to +125°C
temperature range and is available in a 14 lead HTSSOP with
an exposed pad package.
Related Literature
•ISL80136 Datasheet
•AN1784, “ISL80136EVAL1Z, ISL80138EVAL1Z Evaluation
Boards User Guide”
Features
•Wide V
IN range of 6V to 40V
• Adjustable output voltage from 2.5V to 12V
• Guaranteed 150mA output current
• Ultra low 18µA typical quiescent current
• Low 2µA of typical shutdown current
• ±1% accurate voltage reference
• Low dropout voltage of 295mV at 150mA
• 40V tolerant logic level (TTL/CMOS) enable input
• Stable operation with 10µF output capacitor
• 5kV ESD HBM rated
• Thermal shutdown and current limit protection
• Thermally enhanced 14 Ld exposed pad HTSSOP package
Applications
•Industrial
• Telecommunications
TABLE 1. KEY DIFFERENCES IN FAMILY OF 40V LDO PARTS
PART NUMBER MINIMUM IOUT IC PACKAGE
ISL80136 50mA 8 Ld EPSOIC
ISL80138 150mA 14 Ld HTSSOP
FIGURE 1. TYPICAL APPLICATION FIGURE 2. QUIESCENT CURRENT vs TEMPERATURE (AT UNITY
GAIN). VIN = 14V
IN OUT
EN ADJ
GND
CIN
0.1µF COUT
10µF
R1
R2
VIN = 14V VOUT = 12V
EPAD
(GND)
0
5
10
15
20
25
-50 0 50 100 150
TEMPERATURE (°C)
QUIESCENT CURRENT (µA)
ISL80138
FN7969 Rev 1.00 Page 2 of 9
January 15, 2016
Block Diagram
Pin Configuration ISL80138 (14 LD HTSSOP)
TOP VIEW
REFERENCE
+
SOFT-START
CONTROL
LOGIC
THERMAL
SENSOR
-
+EA
VIN
EN
GND
VOUT
FET DRIVER
WITH CURRENT
LIMIT
ADJ
1
2
3
4
14
13
12
11
5
6
7
10
9
8
NC
IN
NC
NC
NC
NC
EN
OUT
NC
ADJ
NC
NC
NC
GND
EPAD
(GND)
Pin Descriptions
PIN NUMBER PIN NAME DESCRIPTION
1, 3, 4, 5, 6, 9,
10, 11, 13
NC Pins have internal termination and can be left unconnected. Connection to ground is optional.
2 IN Input voltage pin. A minimum 0.1µF ceramic capacitor is required for proper operation. Range 6V to 40V.
7 EN Enable pin. High on this pin enables the device. Range 0V to VIN.
8GNDGround pin.
12 ADJ This pin is connected to the external feedback resistor divider which sets the LDO output voltage.
14 OUT Regulated output voltage. A 10µF ceramic capacitor is required for stability. Range 0V to 12V.
- EPAD It is recommended to solder the EPAD to the ground plane.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
ENABLE
PIN
OUTPUT VOLTAGE
(V)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL80138IVEAJZ 80138 IAJZ -40 to +125 Yes ADJ 14 Ld HTSSOP M14.173B
ISL80138EVAL1Z Evaluation Platform
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL80138. For more information on MSL please see techbrief TB363.
ISL80138
FN7969 Rev 1.00 Page 3 of 9
January 15, 2016
Absolute Maximum Ratings Thermal Information
IN Pin to GND Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +45V
OUT Pin to GND Voltage. . . . . . . . . . . . . . . . . . . . . . . . .. . .GND - 0.3V to 16V
ADJ Pin to GND Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .. . .GND - 0.3V to 3V
EN Pin to GND Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to VIN
Output Short-circuit Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Indefinite
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 5kV
Machine Model (Tested per JESD-A115-A) . . . . . . . . . . . . . . . . . . . 200V
Charge Device Model (Tested per JESD22-C101C). . . . . . . . . . . . . 2.2kV
Latch-up (Tested per JESD78B; Class II, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical) JA (°C/W) JC (°C/W)
14 Ld HTSSOP Package (Notes 4, 5). . . . . . 37 5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +175°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . -40°C to +125°C
IN pin to GND Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V to +40V
OUT pin to GND Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.5V to +12V
EN pin to GND Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +40V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended Operating Conditions, unless otherwise noted. VIN = 14V, IOUT = 1mA, TA = TJ = -40°C to
+125°C, unless otherwise noted. Typical specifications are at TA = +25°C. Boldface limits apply across the operating temperature range, -40°C to
+125°C.
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 8)TYP
MAX
(Note 8)UNITS
Input Voltage Range VIN 640V
Guaranteed Output
Current
IOUT VIN = VOUT + VDO 150 mA
ADJ Reference Voltage VOUT EN = High, VIN = 14V, IOUT = 0.1mA to 150mA 1.211 1.223 1.235 V
Line Regulation (VOUT low line - VOUT high
line)/VOUT low line
6V < VIN 40V, IOUT = 1mA 0.04 0.15 %
Load Regulation (VOUT no load - VOUT high
load)/VOUT no load
VIN = 14V, IOUT = 100µA to 150mA 0.3 0.6 %
Dropout Voltage
(Note 6)
VDO IOUT = 1mA, VOUT = 2.5V 7 33 mV
IOUT = 150mA, VOUT = 2.5V 380 571 mV
IOUT = 1mA, VOUT = 5V 7 33 mV
IOUT = 150mA, VOUT = 5V 295 507 mV
Shutdown Current ISHDN EN = LOW 2 3.64 µA
Quiescent Current IQ EN = HIGH, IOUT = 0mA 18 24 µA
EN = HIGH, IOUT = 1mA 22 42 µA
EN = HIGH, IOUT = 10mA 34 60 µA
EN = HIGH, IOUT = 150mA 90 125 µA
Power Supply
Rejection Ratio
PSRR f = 100Hz; VIN_RIPPLE = 500mVP-P; Load = 150mA 66 dB
EN FUNCTION
EN Threshold Voltage VEN_H VOUT = Off to On 1.485 V
VEN_L VOUT = On to Off 0.975 V
EN Pin Current IEN VOUT = 0V 0.026 µA
EN to Regulation Time
(Note 7)
tEN 1.65 1.93 ms
ISL80138
FN7969 Rev 1.00 Page 4 of 9
January 15, 2016
PROTECTION FEATURES
Output Current Limit ILIMIT VOUT = 0V 175 410 mA
Thermal Shutdown TSHDN Junction Temperature Rising +165 °C
Thermal Shutdown
Hysteresis
THYST +20 °C
NOTES:
6. Dropout voltage is defined as (VIN - VOUT) when VOUT is 2% below the value of VOUT.
7. Enable to Regulation is the time the output takes to reach 95% of its final value with VIN = 14V and EN is taken from VIL to VIH in 5ns. For the
adjustable versions, the output voltage is set at 5V.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Electrical Specifications Recommended Operating Conditions, unless otherwise noted. VIN = 14V, IOUT = 1mA, TA = TJ = -40°C to
+125°C, unless otherwise noted. Typical specifications are at TA = +25°C. Boldface limits apply across the operating temperature range, -40°C to
+125°C. (Continued)
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 8)TYP
MAX
(Note 8)UNITS
ISL80138
FN7969 Rev 1.00 Page 5 of 9
January 15, 2016
Typical Performance Curves VIN = 14V, IOUT = 1mA, VOUT = 5V, TJ = +25°C, unless otherwise specified.
FIGURE 3. QUIESCENT CURRENT vs LOAD CURRENT FIGURE 4. QUIESCENT CURRENT vs INPUT VOLTAGE (NO LOAD)
FIGURE 5. SHUTDOWN CURRENT vs TEMPERATURE (EN = 0) FIGURE 6. OUTPUT VOLTAGE vs TEMPERATURE (LOAD = 50mA)
FIGURE 7. OUTPUT VOLTAGE vs LOAD CURRENT FIGURE 8. START-UP WAVEFORM
0
20
40
60
80
100
120
050100150
LOAD CURRENT (mA)
-40°C
+125°C
+25°C
QUIESCENT CURRENT (µA)
0
5
10
15
20
25
30
0 10203040
INPUT VOLTAGE (V)
-40°C
+125°C
+25°C
QUIESCENT CURRENT (µA)
0
0.5
1.0
1.5
2.0
2.5
3.0
-50 0 50 100 150
TEMPERATURE (°C)
VIN = 40V
VIN = 14V
SHUTDOWN CURRENT (µA)
-0.010
-0.005
0
0.005
0.010
-50 0 50 100 150
TEMPERATURE (°C)
OUTPUT VOLTAGE VARIATION (%)
VOUT = 3.3V
VOUT = 5V
4.80
4.85
4.90
4.95
5.00
5.05
5.10
5.15
5.20
0 50 100 150
LOAD CURRENT (mA)
OUTPUT VOLTAGE (V)
+25°C
+125°C
-40°C
TIME = 500µs/DIV
1V/DIV
500mV/DIV
EN
VOUT
ISL80138
FN7969 Rev 1.00 Page 6 of 9
January 15, 2016
FIGURE 9. LOAD TRANSIENT RESPONSE FIGURE 10. PSRR vs FREQUENCY FOR VARIOUS OUTPUT VOLTAGES,
(LOAD = 150mA)
FIGURE 11. PSRR vs FREQUENCY FOR VARIOUS LOAD CURRENTS,
VOUT = 3.3V
FIGURE 12. OUTPUT NOISE SPECTRAL DENSITY, IOUT = 10mA
FIGURE 13. OUTPUT NOISE SPECTRAL DENSITY, IOUT = 150mA
Typical Performance Curves VIN = 14V, IOUT = 1mA, VOUT = 5V, TJ = +25°C, unless otherwise specified. (Continued)
50mA
TIME = 5ms/DIV
100mV/DIV
0mA
IOUT
VOUT
0
10
20
30
40
50
60
70
100 1k 10k 100k 1M
FREQUENCY (Hz)
PSRR (dB)
VOUT = 5V
VOUT = 3.3V
0
10
20
30
40
50
60
70
80
90
100 1k 10k 100k 1M
IOUT = 0A
IOUT = 75mA
IOUT = 150mA
FREQUENCY (Hz)
PSRR (dB)
0.01
0.1
1
10
10
100
1k 10k 100k
NOISE (µV/√Hz)
FREQUENCY (Hz)
BW = 100 < f < 100kHz output noise voltage ~ 26 μVrms
VIN = 14V
VOUT = 3.3V
COUT = 10µF
IOUT = 10mA
0.01
0.1
1
10
10 100 1k 10k 100k
NOISE (µV/√Hz)
FREQUENCY (Hz)
VIN = 14V
VOUT = 3.3V
COUT = 10µF
IOUT = 150mA
BW = 100 < f < 100kHz output noise voltage ~ 38 μVrms
ISL80138
FN7969 Rev 1.00 Page 7 of 9
January 15, 2016
Functional Description
Functional Overview
The ISL80138 is a high performance, high voltage, low-dropout
regulator (LDO) with 150mA sourcing capability. The part is rated
to operate across the -40°C to +125°C temperature range.
Featuring ultra-low quiescent current, it is an ideal choice for
“always-on” applications. It works well under a “load dump
condition” where the input voltage could rise up to 40V. This LDO
device also features current limit and thermal shutdown
protection.
Enable Control
The ISL80138 has an enable pin, which turns the device on when
pulled high. When EN is low, the IC goes into shutdown mode and
draws less than 2µA. In “always-on” applications, EN can be tied
to IN.
Current Limit Protection
The ISL80138 has internal current limiting functionality to
protect the regulator during fault conditions. During current limit,
the output sources a fixed amount of current largely independent
of the output voltage. If the short or overload is removed from
VOUT, the output returns to normal voltage regulation mode.
Thermal Fault Protection
In the event that the die temperature exceeds a typical value of
+165°C, the output of the LDO will shut down until the die
temperature cools down to a typical +145°C. The level of power
dissipated, combined with the ambient temperature and the
thermal impedance of the package, determines if the junction
temperature exceeds the thermal shutdown temperature. See
“Power Dissipation” on page 7 for more details.
Application Information
Input and Output Capacitors
A minimum 0.1µF ceramic capacitor is recommended at the
input for proper operation. For the output, a ceramic capacitor
with a capacitance of 10µF is recommended for the ISL80138 to
maintain stability. The ground connection of the output capacitor
should be routed directly to the GND pin of the device and also
placed close to the IC.
Output Voltage Setting
The ISL80138 output voltage is programmed using an external
resistor divider as shown in Figure 14.
The output voltage is calculated using Equation 1:
Power Dissipation
The junction temperature must not exceed the range specified in
“Recommended Operating Conditions” on page 3. The power
dissipation can be calculated using Equation 2:
The maximum allowable junction temperature, TJ(MAX) and the
maximum expected ambient temperature, TA(MAX) will determine
the maximum allowable junction temperature rise (TJ), as shown
in Equation 3:
To calculate the maximum ambient operating temperature, use
the junction-to-ambient thermal resistance (JA) as shown in
Equation 4:
Board Layout Recommendations
A good PCB layout is important to achieve expected
performance. Consideration should be taken when placing the
components and routing the trace to minimize the ground
impedance and keep the parasitic inductance low. The input and
output capacitors should have a good ground connection and be
placed as close to the IC as possible. The feedback trace in the
adjustable version should be away from other noisy traces. The
14 Ld HTSSOP package uses the copper area on the PCB as a
heat sink. The EPAD of this package must be soldered to the
copper plane (GND plane) for effective heat dissipation.
Figure 15 shows a curve for JA of the package for different
copper area sizes.
IN OUT
EN ADJ
GND
CIN
0.1µF
COUT
10µF
R1
R2
FIGURE 14. OUTPUT VOLTAGE SETTING
VOUT 1.223V
R1
R2
-------1+
=(EQ. 1)
PDVIN VOUT
–IOUT VIN IGND
+=(EQ. 2)
TJTJMAX
TAMAX
–= (EQ. 3)
TJMAX
PDMAX
x JA TA
+= (EQ. 4)
FIGURE 15. JA vs EPAD-MOUNT COPPER LAND AREA ON PCB
38
36
34
32
30
28
260 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160
EPAD-MOUNT COPPER LAND AREA ON PCB, mm2
JA (°C/W)
FN7969 Rev 1.00 Page 8 of 9
January 15, 2016
ISL80138
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
For additional products, see www.intersil.com/en/products.html
© Copyright Intersil Americas LLC 2012-2016. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
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Reliability reports are also available from our website at www.intersil.com/support
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE REVISION CHANGE
January 15, 2016 FN7969.1 Updated entire datasheet applying Intersil’s new standards.
On page 1, updated Key Differences Table, Replaced “ADJ OR FIXED VOUT” Column with “IC PACKAGE” column.
On page 2, updated Block Diagram, removed two resistors and switched polarity of EA.
Onpage 2, removed “Range 0V to 3V.” from the ADJ Pin Description
On page 3, updated Note 4 from
“JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See
Tech Brief TB379 for details.”
to
“JA is measured in free air with the component mounted on a high effective thermal conductivity test board with
“direct attach” features. See Tech Brief TB379.”
On page 3, removed “CIN = 0.1μF, COUT =10μF” from the Electrical Specification heading.
On page 3, updated the Line Regulation
-Symbol, from “VOUT/VIN” to “(VOUT low line - VOUT high line)/VOUT low line”.
-Test Conditions, from “3V ≤ VIN ≤ 40V, IOUT = 1mA” to “6V < VIN 40V, IOUT = 1mA”
On page 3, updated the Load Regulation
-Symbol, from “VOUT/IOUT” to “(VOUT no load - VOUT high load)/VOUT no load”.
-Test Conditions from “VIN = VOUT +VDO” to “VIN = 14V”
On page 3, updated the Dropout Voltage (Two rows only):
-Test Conditions from “VOUT = 3.3V” to “VOUT = 2.5V”
-Changed maximum value for condition, IOUT = 150mA, VOUT = 2.5V, from “525” to “571”
-Changed maximum value for condition, IOUT = 150mA, VOUT = 5V, from “460” to “507”
Updated Note 6 from “Dropout voltage is defined as (VIN - VOUT) when VOUT is 2% below the value of VOUT when
VIN =V
OUT + 3V.” to “Dropout voltage is defined as (VIN - VOUT) when VOUT is 2% below the value of VOUT.”
On page 6, switched Figures 9 and 10 location, then updated title for Figure 10 from “POWER SUPPLY REJECTION
RATIO (LOAD = 150mA)” to “PSRR vs FREQUENCY FOR VARIOUS OUTPUT VOLTAGES (LOAD = 150mA)”
Added Figures 11, 12 and 13 on page 6.
Updated Products verbiage to About Intersil verbiage.
January 11, 2012 FN7969.0 Initial Release.
ISL80138
FN7969 Rev 1.00 Page 9 of 9
January 15, 2016
Package Outline Drawing
M14.173B
14 LEAD HEAT-SINK THIN SHRINK SMALL OUTLINE PACKAGE (HTSSOP)
Rev 1, 1/10
BOTTOM VIEW
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
B
A
17
8
14
C
PLANE
SEATING
0.10 C0.10 CBA
H
PIN #1
I.D. MARK
5.00 ±0.10
4.40 ±0.10
0.25 +0.05/-0.06
6.40
0.20 C B A
0.05
3.10 ±0.10
3.00 ±0.10
0°-8°
GAUGE
PLANE
SEE
0.90 +0.15/-0.10
0.60 ±0.15
0.15 +0.05/-0.06
5
2
31
3
1.00 REF
0.65
1.20 MAX
0.25
0.05 MIN
0.15 MAX
EXPOSED THERMAL PAD
SIDE VIEW
DETAIL "X"
END VIEW
1. Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion.
Allowable protrusion shall be 0.80mm total in excess of dimension at
maximum material condition.
Minimum space between protrusion and adjacent lead is 0.07mm.
6. Dimension in ( ) are for reference only.
7. Conforms to JEDEC MO-153, variation ABT-1.
NOTES:
(1.45)
(5.65)
(0.65 TYP) (0.35 TYP)
(3.10)
(3.00)
