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TMS570LS3135, TMS570LS2135, TMS570LS2125
SPNS164C –APRIL 2012–REVISED APRIL 2015
TMS570LS31x5/21x5 16- and 32-Bit RISC Flash Microcontroller
1 Device Overview
1.1 Features
1
• High-Performance Automotive-Grade • Multiple Communication Interfaces
Microcontroller for Safety-Critical Applications – FlexRay Controller With Two Channels
– Dual CPUs Running in Lockstep • 8KB of Message RAM With Parity Protection
– ECC on Flash and RAM Interfaces • Dedicated Transfer Unit (FTU)
– Built-In Self-Test (BIST) for CPU and On-chip – Three CAN Controllers (DCANs)
RAMs • 64 Mailboxes, Each With Parity Protection
– Error Signaling Module With Error Pin • Compliant to CAN Protocol Version 2.0B
– Voltage and Clock Monitoring – Standard Serial Communication Interface (SCI)
• ARM®Cortex®-R4F 32-Bit RISC CPU – Local Interconnect Network (LIN) Interface
– Efficient 1.66 DMIPS/MHz With 8-Stage Pipeline Controller
– FPU With Single- and Double-Precision • Compliant to LIN Protocol Version 2.1
– 12-Region Memory Protection Unit (MPU) • Can be Configured as a Second SCI
– Open Architecture With Third-Party Support – Inter-Integrated Circuit (I2C)
• Operating Conditions – Three Multibuffered Serial Peripheral Interfaces
– System Clock up to 180 MHz (MibSPIs)
– Core Supply Voltage (VCC): 1.2 V Nominal • 128 Words With Parity Protection Each
– I/O Supply Voltage (VCCIO): 3.3 V Nominal – Two Standard Serial Peripheral Interfaces
(SPIs)
– ADC Supply Voltage (VCCAD): 3.0 to 5.25 V • Two Next Generation High-End Timer (N2HET)
• Integrated Memory Modules
– 3MB of Program Flash With ECC (LS3135) – N2HET1: 32 Programmable Channels
– 2MB of Program Flash With ECC – N2HET2: 18 Programmable Channels
(LS2135/2125) – 160-Word Instruction RAM Each With Parity
– 256KB of RAM With ECC (LS3135/2135) Protection
– 192KB of RAM With ECC (LS2125) – Each N2HET Includes Hardware Angle
– 64KB of Flash With ECC for Emulated Generator
EEPROM – Dedicated High-End Transfer Unit (HTU) With
• 16-Bit External Memory Interface MPU for Each N2HET
• Common Platform Architecture • Two 12-Bit Multibuffered ADC Modules
– Consistent Memory Map Across Family – ADC1: 24 Channels
– Real-Time Interrupt (RTI) Timer OS Timer – ADC2: 16 Channels Shared With ADC1
– 96-Channel Vectored Interrupt Module (VIM) – 64 Result Buffers With Parity Protection Each
– 2-Channel Cyclic Redundancy Checker (CRC) • General-Purpose Input/Output (GPIO) Pins
• Direct Memory Access (DMA) Controller Capable of Generating Interrupts
– 16 Channels and 32 Control Packets – Sixteen Pins on the ZWT Package
– Parity Protection for Control Packet RAM – Four Pins on the PGE Package
– DMA Accesses Protected by Dedicated MPU • IEEE 1149.1 JTAG, Boundary Scan and ARM
• Frequency-Modulated Phase-Locked Loop CoreSight™ Components
(FMPLL) With Built-In Slip Detector • JTAG Security Module
• Separate Nonmodulating PLL for FlexRay™ • Packages
• Trace and Calibration Capabilities – 144-Pin Quad Flatpack (PGE) [Green]
– Embedded Trace Macrocell (ETM-R4) – 337-Ball Grid Array (ZWT) [Green]
– Data Modification Module (DMM)
– RAM Trace Port (RTP)
– Parameter Overlay Module (POM)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMS570LS3135, TMS570LS2135, TMS570LS2125
SPNS164C –APRIL 2012–REVISED APRIL 2015
www.ti.com
1.2 Applications
• Braking Systems (Antilock Brake Systems and • Active Driver Assistance Systems
Electronic Stability Control) • Aerospace and Avionics
• Electric Power Steering • Railway Communications
• HEV and EV Inverter Systems • Off-road Vehicles
• Battery Management Systems
2Device Overview Copyright © 2012–2015, Texas Instruments Incorporated
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SPNS164C –APRIL 2012–REVISED APRIL 2015
1.3 Description
The TMS570LS31x5/21x5 device is a high-performance automotive-grade microcontroller family for safety
systems. The safety architecture includes dual CPUs in lockstep, CPU and memory BIST logic, ECC on
both the flash and the data SRAM, parity on peripheral memories, and loopback capability on peripheral
I/Os.
The TMS570LS31x5/21x5 device integrates the ARM Cortex-R4F Floating-Point CPU. The CPU offers an
efficient 1.66 DMIPS/MHz, and has configurations that can run up to 180 MHz, providing up to 298
DMIPS. The device supports the word-invariant big-endian [BE32] format.
The TMS570LS3135 device has 3MB of integrated flash and 256KB of data RAM. The TMS570LS2135
device has 2MB of integrated flash and 256KB of data RAM. The TMS570LS2125 device has 2MB of
integrated flash and 192KB of data RAM. Both the flash and RAM have single-bit error correction and
double-bit error detection. The flash memory on this device is a nonvolatile, electrically erasable, and
programmable memory implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V
supply input (same level as I/O supply) for all read, program, and erase operations. When in pipeline
mode, the flash operates with a system clock frequency of up to 180 MHz. The SRAM supports single-
cycle read and write accesses in byte, halfword, word, and double-word modes.
The TMS570LS31x5/21x5 device features peripherals for real-time control-based applications, including
two Next Generation High-End Timer (N2HET) timing coprocessors and two 12-bit Analog-to-Digital
Converters (ADCs) supporting up to 24 inputs.
The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time
applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer
micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs,
capture or compare inputs, or GPIO. The N2HET is especially well suited for applications requiring
multiple sensor information and drive actuators with complex and accurate time pulses. A High-End Timer
Transfer Unit (HTU) can perform DMA-type transactions to transfer N2HET data to or from main memory.
A Memory Protection Unit (MPU) is built into the HTU.
The device has two 12-bit-resolution MibADCs with 24 channels and 64 words of parity-protected buffer
RAM each. The MibADC channels can be converted individually or can be grouped by software for
sequential conversion sequences. Sixteen channels are shared between the two MibADCs. There are
three separate groupings. Each sequence can be converted once when triggered or configured for
continuous conversion mode. The MibADC has a 10-bit mode for use when compatibility with older
devices or faster conversion time is desired.
The device has multiple communication interfaces: three MibSPIs, two SPIs, one LIN, one SCI, three
DCANs, one I2C module, and one FlexRay controller. The SPIs provide a convenient method of serial
high-speed communication between similar shift-register type devices. The LIN supports the Local
Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the standard Non-
Return-to-Zero (NRZ) format.
The DCAN supports the CAN 2.0 (A and B) protocol standard and uses a serial, multimaster
communication protocol that efficiently supports distributed real-time control with robust communication
rates of up to 1 Mbps. The DCAN is ideal for systems operating in noisy and harsh environments (for
example, automotive vehicle networking and industrial fieldbus) that require reliable serial communication
or multiplexed wiring.
The FlexRay controller uses a dual-channel serial, fixed time base multimaster communication protocol
with communication rates of 10 Mbps per channel. A FlexRay Transfer Unit (FTU) enables autonomous
transfers of FlexRay data to and from the CPU main memory. Transfers are protected by a dedicated,
built-in MPU.
The I2C module is a multimaster communication module providing an interface between the
microcontroller and an I2C-compatible device through the I2C serial bus. The I2C supports speeds of 100
and 400 Kbps.
Copyright © 2012–2015, Texas Instruments Incorporated Device Overview 3
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The Frequency-Modulated Phase-Locked Loop (FMPLL) clock module is used to multiply the external
frequency reference to a higher frequency for internal use. There are two FMPLL modules on this device.
These modules, when enabled, provide two of the seven possible clock source inputs to the Global Clock
Module (GCM). The GCM manages the mapping between the available clock sources and the device
clock domains.
The device also has an External Clock Prescaler (ECP) module that when enabled, outputs a continuous
external clock on the ECLK pin (or ball). The ECLK frequency is a user-programmable ratio of the
peripheral interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an
indicator of the device operating frequency.
The DMA controller has 16 channels, 32 control packets, and parity protection on its memory. An MPU is
built into the DMA to limit the DMA to prescribed areas of memory and to protect the rest of the memory
system from any malfunction of the DMA.
The Error Signaling Module (ESM) monitors all device errors and determines whether an interrupt is
generated or the external ERROR pin is toggled when a fault is detected. The ERROR pin can be
monitored externally as an indicator of a fault condition in the microcontroller.
The External Memory Interface (EMIF) provides off-chip expansion capability with the ability to interface to
synchronous DRAM (SDRAM) devices, asynchronous memories, peripherals or FPGA devices.
Several interfaces are implemented to enhance the debugging capabilities of application code. In addition
to the built-in ARM Cortex-R4F CoreSight debug features, an External Trace Macrocell (ETM) provides
instruction and data trace of program execution. For instrumentation purposes, a RAM Trace Port (RTP)
module is implemented to support high-speed tracing of RAM and peripheral accesses by the CPU or any
other master. A Data Modification Module (DMM) gives the ability to write external data into the device
memory. Both the RTP and DMM have no or only minimum impact on the program execution time of the
application code. A Parameter Overlay Module (POM) can reroute flash accesses to internal memory or to
the EMIF. This rerouting allows the dynamic calibration against production code of parameters and tables
without rebuilding the code to explicitly access RAM or halting the processor to reprogram the data flash.
With integrated safety features and a wide choice of communication and control peripherals, the
TMS570LS31x5/21x5 device is an ideal solution for high-performance real-time control applications with
safety-critical requirements.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE
TMS570LS2125ZWT NFBGA (337) 16.0 mm × 16.0 mm
TMS570LS2125PGE LQFP (144) 20.0 mm × 20.0 mm
TMS570LS2135ZWT NFBGA (337) 16.0 mm × 16.0 mm
TMS570LS2135PGE LQFP (144) 20.0 mm × 20.0 mm
TMS570LS3135ZWT NFBGA (337) 16.0 mm × 16.0 mm
TMS570LS3135PGE LQFP (144) 20.0 mm × 20.0 mm
(1) For more information, see Section 9,Mechanical Packaging and Orderable Information.
4Device Overview Copyright © 2012–2015, Texas Instruments Incorporated
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DMA POM DMM HTU1 FTU HTU2
Switched Central Resource
Main Cross Bar: Arbitration and Prioritization Control
CRC Switched Central Resource Peripheral Central Resource Bridge
Dual Cortex-R4F
CPUs in Lockstep Switched Central Resource
MibADC1 MibADC2 I2CN2HET1 FlexRay
GION2HET2
64KB Flash
for EEPROM
Emulation
with ECC IOMM
PMM
VIM
RTI
DCC1
DCC2
3MB(B)
Flash
with
ECC ETM-R4
RTP
64K(A)
64K
64K
64K
RTPCLK
RTPnENA
RTPSYNC
RTPDATA[15:0]
TRACECLKIN
TRACECLK
TRACECTL
ETMDATA[31:0]
DMMCLK
DMMnENA
DMMSYNC
DMMDATA[15:0]
256KB
RAM
with
ECC
EMIF
EMIF_CLK
EMIF_CKE
EMIF_nCS[4:2]
EMIF_nCS[0]
EMIF_ADDR[21:0]
EMIF_BA[1:0]
EMIF_DATA[15:0]
EMIF_nDQM[1:0]
EMIF_nOE
EMIF_nWE
EMIF_nRAS
EMIF_nCAS
EMIF_nRW
EMIF_nWAIT
VSSAD
VCCAD
I2C_SCL
I2C_SDA
FRAY_RX1
FRAY_TX1
FRAY_TXEN1
FRAY_RX2
FRAY_TX2
FRAY_TXEN2
GIOB[7:0]
GIOA[7:0]
VCCAD
VSSAD
ADREFHI
ADREFLO
AD1EVT
AD1IN[7:0]
AD1IN[23:8]
AD2IN[15:0]
AD2EVT
ADREFHI
ADREFLO
# 2
# 3
# 4
# 1
# 2
# 1
always on
Core/RAM RAM
Core
# 5
# 3
Color Legend for Power Domains
DCAN1
DCAN2
DCAN3
LIN
SCI
SPI4
MibSPI1
CAN1_RX
CAN1_TX
CAN2_RX
CAN2_TX
CAN3_RX
CAN3_TX
MIBSPI1_CLK
MIBSPI1_SIMO[1:0]
MIBSPI1_SOMI[1:0]
MIBSPI1_nCS[5:0]
MIBSPI1_nENA
SPI2
SPI2_CLK
SPI2_SIMO
SPI2_SOMI
SPI2_nCS[1:0]
SPI2_nENA
MibSPI3
MIBSPI3_CLK
MIBSPI3_SIMO
MIBSPI3_SOMI
MIBSPI3_nCS[5:0]
MIBSPI3_nENA
SPI4_CLK
SPI4_SIMO
SPI4_SOMI
SPI4_nCS0
SPI4_nENA
MibSPI5
LIN_RX
LIN_TX
SCI_RX
SCI_TX
SYS
nPORRST
nRST
ECLK
ESM nERROR
N2HET2[18,16]
N2HET2[15:0]
N2HET1[31:0]
N2HET1_PIN_nDIS
N2HET2_PIN_nDIS
MIBSPI5_SIMO[3:0]
MIBSPI5_SOMI[3:0]
MIBSPI5_nCS[3:0]
MIBSPI5_nENA
MIBSPI5_CLK
TMS570LS3135, TMS570LS2135, TMS570LS2125
www.ti.com
SPNS164C –APRIL 2012–REVISED APRIL 2015
1.4 Functional Block Diagram
A. For devices with 192KB RAM with ECC, the RAM #3 power domain is not supported.
B. The TMS570LS2135 and TMS570LS2125 devices only support 2MB of Flash with ECC.
Figure 1-1. Functional Block Diagram
Copyright © 2012–2015, Texas Instruments Incorporated Device Overview 5
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SPNS164C –APRIL 2012–REVISED APRIL 2015
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Table of Contents
1 Device Overview ......................................... 16.11 Tightly Coupled RAM (TCRAM) Interface Module .. 80
1.1 Features .............................................. 16.12 Parity Protection for Peripheral RAMs .............. 80
1.2 Applications........................................... 26.13 On-Chip SRAM Initialization and Testing ........... 82
1.3 Description............................................ 36.14 External Memory Interface (EMIF) .................. 84
1.4 Functional Block Diagram ............................ 56.15 Vectored Interrupt Manager......................... 91
2 Revision History ......................................... 76.16 DMA Controller...................................... 94
3 Device Comparison ..................................... 96.17 Real Time Interrupt Module ......................... 96
4 Terminal Configuration and Functions ........... 10 6.18 Error Signaling Module.............................. 98
4.1 PGE QFP Package Pinout (144-Pin) ............... 10 6.19 Reset / Abort / Error Sources...................... 102
4.2 ZWT BGA Package Ball-Map (337-Ball Grid Array) 11 6.20 Digital Windowed Watchdog....................... 104
4.3 Terminal Functions ................................. 12 6.21 Debug Subsystem ................................. 105
5 Specifications .......................................... 39 7 Peripheral Information and Electrical
Specifications ......................................... 116
5.1 Absolute Maximum Ratings ........................ 39 7.1 Peripheral Legend ................................. 116
5.2 ESD Ratings ........................................ 39 7.2 Multibuffered 12-Bit Analog-to-Digital Converter .. 116
5.3 Power-On Hours (POH)............................. 39 7.3 General-Purpose Input/Output..................... 127
5.4 Recommended Operating Conditions............... 40 7.4 Enhanced High-End Timer (N2HET) .............. 128
5.5 Switching Characteristics for Clock Domains....... 41 7.5 FlexRay Interface .................................. 133
5.6 Wait States Required ............................... 41 7.6 Controller Area Network (DCAN) .................. 135
5.7 Power Consumption................................. 42 7.7 Local Interconnect Network Interface (LIN)........ 136
5.8 Input/Output Electrical Characteristics.............. 43 7.8 Serial Communication Interface (SCI) ............. 137
5.9 Thermal Resistance Characteristics ................ 44 7.9 Inter-Integrated Circuit (I2C) ....................... 138
5.10 Output Buffer Drive Strengths ...................... 45 7.10 Multibuffered / Standard Serial Peripheral
5.11 Input Timings........................................ 46 Interface............................................ 141
5.12 Output Timings...................................... 46 8 Device and Documentation Support.............. 153
5.13 Low-EMI Output Buffers ............................ 48 8.1 Device Support..................................... 153
6 System Information and Electrical 8.2 Documentation Support............................ 155
Specifications........................................... 50 8.3 Related Links ...................................... 155
6.1 Device Power Domains ............................. 50 8.4 Community Resources............................. 155
6.2 Voltage Monitor Characteristics..................... 51 8.5 Trademarks ........................................ 155
6.3 Power Sequencing and Power On Reset ........... 52 8.6 Electrostatic Discharge Caution ................... 155
6.4 Warm Reset (nRST)................................. 54 8.7 Glossary............................................ 155
6.5 ARM-R4F CPU Information ......................... 55 8.8 Device Identification Code Register ............... 157
6.6 Clocks ............................................... 58 8.9 Die Identification Registers ....................... 158
6.7 Clock Monitoring .................................... 66 8.10 Module Certifications............................... 158
6.8 Glitch Filters......................................... 68 9 Mechanical Packaging and Orderable
6.9 Device Memory Map ................................ 69 Information............................................. 165
6.10 Flash Memory ....................................... 77 9.1 Packaging Information ............................. 165
6Table of Contents Copyright © 2012–2015, Texas Instruments Incorporated
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SPNS164C –APRIL 2012–REVISED APRIL 2015
2 Revision History
This data manual revision history highlights the technical changes made to the SPNS164B device-specific
data manual to make it an SPNS164C revision.
Scope: Applicable updates to the Hercules™ TMS570 MCU device family, specifically relating to the
TMS570LS31x5/21x5 devices, which are now in the production data (PD) stage of development have
been incorporated.
Changes from August 1, 2013 to April 30, 2015 (from B Revision (July 2013) to C Revision) Page
•Section 1 (Device Overview): Updated/Changed section title ................................................................. 1
• Updated/Changed the N2HET feature............................................................................................. 1
• (Device Information): Added table.................................................................................................. 4
• Added Section 3, Device Comparison ............................................................................................. 9
•Section 4 (Terminal Configuration and Functions): Updated/Changed section title........................................ 10
•Table 4-2 (PGE Enhanced High-End Timer Modules (N2HET1, N2HET2)): Updated/Changed N2HET1 time
input capture or output compare pin description................................................................................ 14
•Table 4-2: Added N2HET1_PIN_nDIS signal DESCRIPTION ................................................................ 14
•Table 4-2: Updated/Changed N2HET2 time input capture or output compare pin description ........................... 15
•Table 4-2: Added N2HET2_PIN_nDIS signal DESCRIPTION ................................................................ 15
•Table 4-3 Updated description about using GIOB[2] on pin 55 .............................................................. 15
•Table 4-13 (PGE Test and Debug Modules Interface): Updated/Changed TEST pin description........................ 18
•Table 4-19 (ZWT Enhanced High-End Timer (N2HET) Modules): Updated/Changed N2HET1 time input capture
or output compare pin description ................................................................................................ 22
•Table 4-19 Added alternate terminals for N2HET1 pins 17, 19, 21, 23, 25, 27, 29 and 31............................... 22
•Table 4-19: Added N2HET1_PIN_nDIS signal DESCRIPTION............................................................... 22
•Table 4-19: Updated/Changed N2HET2 time input capture or output compare pin description.......................... 23
•Table 4-19: Added N2HET2_PIN_nDIS signal DESCRIPTION............................................................... 23
•Table 4-20 Updated description about using GIOB[2] on ball V10 ........................................................... 24
•Table 4-28 (External Memory Interface (EMIF)): Global: Deleted EMIF_RNW pin function............................... 28
•Table 4-34 (ZWT Test and Debug Modules Interface): Updated/Changed TEST pin description ....................... 34
•Table 4-36 (No Connects): Deleted NC pins A8, B8, and B9; supported on FlexRay Interface Controller ............. 35
•Section 5 (Specifications): Updated/Changed section title .................................................................... 39
•Section 5.1 (Absolute Maximum Ratings): Reformatted table................................................................. 39
•Section 5.1 (Absolute Maximum Ratings): Updated/Changed VCCAD supply voltage range MAX value from "5.5"
to "6.25" V............................................................................................................................ 39
•Section 5.1: Updated/Changed ADC input pins input voltage range MAX value from "5.5" to "6.25" V................. 39
•Section 5.2 (ESD Ratings): Added table (new).................................................................................. 39
•Section 5.3 (Power-On Hours (POH)): Added table (new) .................................................................... 39
•Section 5.8 (Input/Output Electrical Characteristics): Updated/Changed Input Clamp Current from IIC to IIK........... 43
•Section 5.9 (Thermal Resistance Characteristics): Moved section and updated/changed subsection title. ............ 44
•Table 5-2 (Thermal Resistance Characteristics (PGE Package)): Added test conditions and added ΨJT row for
PGE package........................................................................................................................ 44
•Table 5-3 (Thermal Resistance Characteristics (ZWT Package)): Added test conditions and added ΨJT row for
ZWT package........................................................................................................................ 44
• Clarified impact of SPI2PC9 register on drive strength of SPI2SOMI pin .................................................. 45
• Updated/Changed the MIN value of tv(RST) to 2256tc(OSC) ns .................................................................. 54
•Section 6.6.1 (Clock Sources): Added Table 6-8, Available Clock Source cross-references............................. 58
•Section 6.6.1.1 (Main Oscillator): Added Figure 6-4, Recommended Crystal/Clock Connection cross-reference ..... 58
•Table 6-10 Added limits for HF LPO after software trim ...................................................................... 60
•Table 6-13 (Clock Domain Descriptions): Added missing "1" to the VCLKACON clock source selection register
name for VCLKA3 row.............................................................................................................. 63
•Section 6.9.1 Added addititional device-specific memory map................................................................ 70
•Table 6-20 Corrected size of bank 7 OTP and bank 7 OTP ECC............................................................ 72
•Figure 6-12 (TCRAM Block Diagram): Updated/Changed figure, deleted A TCM.......................................... 80
•Table 6-25 Added table footnotes identifying the address ranges of the ESRAM PBIST groups........................ 82
•Table 6-25 Added RAM power domain information in the table notes....................................................... 82
•Table 6-26(Memory Initialization): Updated/Changed N2HET2 RAM ending address from "0xFF57FFFF" to
"0xFF45FFFF" ....................................................................................................................... 83
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•Table 6-38 Corrected base JTAG ID Base Value From 0xnD8A002F to 0xnB8A002F.................................. 106
•Table 6-38 (JTAG ID Code): Added JTAG Identification Code for Silicon Revision "Rev D" ........................... 106
•Table 7-7 (MibADC Recommended Operating Conditions): Updated/Changed Analog input clamp current from
IAIC to IAIK ............................................................................................................................ 121
• FlexRay Interface, Section 7.5.1 (Features): Updated/Changed "8KB of message ..." bullet for clarification......... 133
• Controller Area Network (DCAN) Section 7.6.1 (Features): Updated/Changed TRM references to the correct
document titles .................................................................................................................... 135
•Table 7-24 (SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO =
output, and SPISOMI = input)): Updated/Changed table footnote to "... CLOCK PHASE bit (SPIFMTx.16) is
cleared" ............................................................................................................................. 145
•Section 8 (Device and Documentation Support): Updated/Changed section to meet new requirements, including
addition of several subsections .................................................................................................. 153
•Section 8.8 (Device Identification Code Register): Added Device ID code value for silicon Rev D .................... 157
•Section 8.9 (Die Identification Registers): Updated/Changed the address of the two die identification registers
(DIEIDL and DIEIDH) to point to the original registers at location 0xFFFFFF7C and 0xFFFFFF80 for this section. 158
•Table 8-3 (Die-ID Registers): Updated/Changed the BIT LOCATION column for all ITEM rows....................... 158
•Section 9 (Mechanical Packaging and Orderable Information): Updated/Changed section title........................ 165
•Section 9.1 (Packaging Information): Updated/Changed the paragraph ................................................... 165
8Revision History Copyright © 2012–2015, Texas Instruments Incorporated
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3 Device Comparison
Table 3-1 lists the features of the TMS570LS2125/LS2135/LS3135 devices.
Table 3-1. TMS570LS2125, LS2135, LS3135 Device Comparison(1)(2)
FEATURES DEVICES
Generic Part TMS570LC4357ZWT(3) TMS570LS3137ZWT(3) TMS570LS3135ZWT TMS570LS3135PGE TMS570LS2135ZWT TMS570LS2135PGE TMS570LS2125ZWT TMS570LS2125PGE TMS570LS1227ZWT(3)
Number
Package 337 BGA 337 BGA 337 BGA 144 QFP 337 BGA 144 QFP 337 BGA 144 QFP 337 BGA
CPU ARM Cortex-R5F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F
Frequency (MHz) 300 180 180 160 180 160 180 160 180
32 I
Cache (KB) – – – – – – – –
32 D
Flash (KB) 4096 3072 3072 3072 2048 2048 2048 2048 1280
RAM (KB) 512 256 256 256 256 256 192 192 192
Data Flash 128 64 64 64 64 64 64 64 64
[EEPROM] (KB)
EMAC 10/100 10/100 – – – – – – 10/100
FlexRay 2-ch 2-ch 2-ch 2-ch 2-ch 2-ch 2-ch 2-ch 2-ch
CAN 4 3 3 3 3 3 3 3 3
MibADC 2 (41ch) 2 (24ch) 2 (24ch) 2 (24ch) 2 (24ch) 2 (24ch) 2 (24ch) 2 (24ch) 2 (24ch)
12-bit (Ch)
N2HET (Ch) 2 (64) 2 (44) 2 (50) 2 (50) 2 (44) 2 (40) 2 (44) 2 (40) 2 (44)
ePWM Channels 14 – – – – – – – 14
eCAP Channels 6 – – – – – – – 6
eQEP Channels 2 – – – – – – – 2
MibSPI (CS) 5 (4 x 6 + 2) 3 (6 + 6 + 4) 3 (6 + 6 + 4) 3 (5 + 6 + 1) 3 (6 + 6 + 4) 3 (5 + 6 + 1) 3 (6 + 6 + 4) 3 (5 + 6 + 1) 3 (6 + 6 + 4)
SPI (CS) – 2 (2 + 1) 2 (2 + 1) 1 (1) 2 (2 + 1) 1 (1) 2 (2 + 1) 1 (1) 2 (2 + 1)
SCI (LIN) 4 (2 with LIN) 2 (1 with LIN) 2 (1 with LIN) 2 (1 with LIN) 2 (1 with LIN) 2 (1 with LIN) 2 (1 with LIN) 2 (1 with LIN) 2 (1 with LIN)
2 1 1 1 1 1 1 1 1
I2C
168 (with 16 interrupt 144 (with 16 interrupt 144 (with 16 interrupt 58 (with 4 interrupt 144 (with 16 interrupt 58 (with 4 interrupt 144 (with 16 interrupt 58 (with 4 interrupt 101 (with 16 interrupt
GPIO (INT)(4) capable) capable) capable) capable) capable) capable) capable) capable) capable)
EMIF 16-bit data 16-bit data 16-bit data – 16-bit data – 16-bit data – 16-bit data
ETM (Trace) 32-bit 32-bit 32-bit – 32-bit – 32-bit – –
RTP/DMM 16/16 16/16 16/16 – 16/16 – 16/16 – –
Operating -40ºC to 125ºC -40ºC to 125ºC -40ºC to 125ºC -40ºC to 125ºC -40ºC to 125ºC -40ºC to 125ºC -40ºC to 125ºC -40ºC to 125ºC -40ºC to 125ºC
Temperature
Core Supply (V) 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V
I/O Supply (V) 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V
(1) For additional device variants, see www.ti.com/tms570
(2) This table reflects the maximum configuration for each peripheral. Some functions are multiplexed and not all pins are available at the same time.
(3) Superset device
(4) Total number of pins that can be used as general-purpose input or output when not used as part of a peripheral
Copyright © 2012–2015, Texas Instruments Incorporated Device Comparison 9
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1108
2
3
4
5
FRAYTXEN2
nTRST 109
144
110
111
112
113
114
115
116
117
118
119
120
121
AD1IN[10]/ AD2IN[10]
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
2323
24
25
26
2727
28
29
30
31
32
33
34
35
36
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
FRAYTX2
FRAYRX2
MIBSPI3NCS[3]
MIBSPI3NCS[2]
N2HET1[11]
FLTP1
FLTP2
GIOA[2]
VCCIO
VSS
CAN3RX
CAN3TX
GIOA[5]
N2HET1[22]
GIOA[6]
VCC
OSCIN
Kelvin_GND
OSCOUT
VSS
GIOA[7]
N2HET1[01]
N2HET1[03]
N2HET1[0]
VCCIO
VSS
VSS
VCC
N2HET1[02]
N2HET1[05]
MIBSPI5NCS[0]
N2HET1[07]
TEST
N2HET1[09]
N2HET1[4]
MIBSPI3NCS[1]
N2HET1[06]
N2HET1[13]
MIBSPI1NCS[2]
N2HET1[15]
VCCIO
VSS
VSS
VCC
nPORRST
VSS
VCC
VCC
VSS
MIBSPI3SOMI
MIBSPI3SIMO
MIBSPI3CLK
MIBSPI3NENA
MIBSPI3NCS[0]
VSS
VCC
AD1IN[16]/ AD2IN[0]
AD1IN[17]/ AD2IN[01]
AD1IN[0]
AD1IN[07]
AD1IN[18]/ AD2IN[02]
AD1IN[19]/ AD2IN[03]
AD1IN[20]/ AD2IN[04]
AD1IN[21]/ AD2IN[05]
ADREFHI
ADREFLO
VSSAD
VCCAD
AD1IN[09]/ AD2IN[09]
AD1IN[01]
AD1IN[02]
AD1IN[03]
AD1IN[11]/ AD2IN[11]
AD1IN[04]
AD1IN[12]/ AD2IN[12]
AD1IN[05]
AD1IN[13]/ AD2IN[13]
AD1IN[06]
AD1IN[22]/ AD2IN[06]
AD1IN[14]/ AD2IN[14]
AD1IN[08]/ AD2IN[08]
AD1IN[23]/ AD2IN[07]
AD1IN[15]/ AD2IN[15]
AD1EVT
VCC
VSS
CAN1TX
CAN1RX
N2HET1[24]
N2HET1[26]
MIBSPI1SIMO
MIBSPI1SOMI
MIBSPI1CLK
MIBSPI1NENA
MIBSPI5NENA
MIBSPI5SOMI[0]
MIBSPI5SIMO[0]
MIBSPI5CLK
VCC
VSS
VSS
VCCIO
N2HET1[08]
N2HET1[28]
TMS
TDI
TDO
TCK
RTCK
VCC
VSS
nRST
nERROR
N2HET1[10]
ECLK
VCCIO
VSS
VSS
VCC
N2HET1[12]
N2HET1[14]
FRAYRX1
N2HET1[30]
CAN2TX
CAN2RX
MIBSPI1NCS[1]
LINRX
LINTX
FRAYTX1
VCCP
VSS
VCCIO
VCC
VSS
N2HET1[16]
N2HET1[18]
N2HET1[20]
FRAYTXEN1
VCC
VSS
MIBSPI1NCS[0]
TMS570LS3135, TMS570LS2135, TMS570LS2125
SPNS164C –APRIL 2012–REVISED APRIL 2015
www.ti.com
4 Terminal Configuration and Functions
4.1 PGE QFP Package Pinout (144-Pin)
A. Pins can have multiplexed functions. Only the default function is depicted in the figure.
Figure 4-1. PGE QFP Package Pinout (144-Pin)(A)
10 Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated
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A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
19
VSS
VSS
TMS
N2HET1
[10]
MIBSPI5
NCS[0]
MIBSPI1
SIMO
MIBSPI1
NENA
MIBSPI5
CLK
MIBSPI5
SIMO[0]
N2HET1
[28]
DMM_
DATA[0]
CAN3RX
AD1EVT
AD1IN[15]
/
AD2IN[15]
AD1IN[22]
/
AD2IN[06]
AD1IN
[06]
AD1IN[11]
/
AD2IN[11]
VSSAD
VSSAD
19
18
VSS
TCK
TDO
nTRST
N2HET1
[08]
MIBSPI1
CLK
MIBSPI1
SOMI
MIBSPI5
NENA
MIBSPI5
SOMI[0]
N2HET1
[0]
DMM_
DATA[1]
CAN3TX
NC
AD1IN[08]
/
AD2IN[08]
AD1IN[14]
/
AD2IN[14]
AD1IN[13]
/
AD2IN[13]
AD1IN
[04]
AD1IN
[02]
VSSAD
18
17
TDI
RST
EMIF_
ADDR[21]
EMIF_
nWE
MIBSPI5
SOMI[1]
DMM_
CLK
MIBSPI5
SIMO[3]
MIBSPI5
SIMO[2]
N2HET1
[31]
EMIF_
nCS[3]
EMIF_
nCS[2]
EMIF_
nCS[4]
EMIF_
nCS[0]
NC
AD1IN
[05]
AD1IN
[03]
AD1IN[10]
/
AD2IN[10]
AD1IN
[01]
AD1IN[09]
/
AD2IN[09]
17
16
RTCK
FRAY
TXEN1
EMIF_
ADDR[20]
EMIF_
BA[1]
MIBSPI5
SIMO[1]
DMM_
NENA
MIBSPI5
SOMI[3]
MIBSPI5
SOMI[2]
DMM_
SYNC
NC
NC
NC
NC
NC
AD1IN[23]
/
AD2IN[07]
AD1IN[12]
/
AD2IN[12]
AD1IN[19]
/
AD2IN[03]
ADREFLO
VSSAD
16
15
FRAY
RX1
FRAY
TX1
EMIF_
ADDR[19]
EMIF_
ADDR[18]
ETM
DATA[06]
ETM
DATA[05]
ETM
DATA[04]
ETM
DATA[03]
ETM
DATA[02]
ETM
DATA[16] /
EMIF_
DATA[0]
ETM
DATA[17] /
EMIF_
DATA[1]
ETM
DATA[18] /
EMIF_
DATA[2]
ETM
DATA[19] /
EMIF_
DATA[3]
NC
NC
AD1IN[21]
/
AD2IN[05]
AD1IN[20]
/
AD2IN[04]
ADREFHI
VCCAD
15
14
N2HET1
[26]
nERROR
EMIF_
ADDR[17]
EMIF_
ADDR[16]
ETM
DATA[07]
VCCIO
VCCIO
VCCIO
VCC
VCC
VCCIO
VCCIO
VCCIO
VCCIO
NC
NC
AD1IN[18]
/
AD2IN[02]
AD1IN
[07]
AD1IN
[0]
14
13
N2HET1
[17]
N2HET1
[19]
EMIF_
ADDR[15]
NC
ETM
DATA[12] /
EMIF_BA[0]
VCCIO
VCCIO
ETM
DATA[01]
NC
AD1IN[17]
/
AD2IN[01]
AD1IN[16]
/
AD2IN[0]
NC
13
12
ECLK
N2HET1
[04]
EMIF_
ADDR[14]
NC
ETM
DATA[13] /
EMIF_nOE
VCCIO
VSS
VSS
VCC
VSS
VSS
VCCIO
ETM
DATA[0]
MIBSPI5
NCS[3]
NC
NC
NC
12
11
N2HET1
[14]
N2HET1
[30]
EMIF_
ADDR[13]
NC
ETM
DATA[14] /
EMIF_
nDQM[1]
VCCIO
VSS
VSS
VSS
VSS
VSS
VCCPLL
ETME
TRACE
CTL
NC
NC
NC
NC
11
10
CAN1TX
CAN1RX
EMIF_
ADDR[12]
NC
ETM
DATA[15] /
EMIF_
nDQM[0]
VCC
VCC
VSS
VSS
VSS
VCC
VCC
ETM
TRACE
CLKOUT
NC
NC
MIBSPI3
NCS[0]
GIOB[3]
10
9
N2HET1
[27]
FRAY
TXEN2
EMIF_
ADDR[11]
NC
ETM
DATA[08] /
EMIF_
ADDR[5]
VCC
VSS
VSS
VSS
VSS
VSS
VCCIO
ETM
TRACE
CLKIN
NC
NC
MIBSPI3
CLK
MIBSPI3
NENA
9
8
FRAY
RX2
FRAY
TX2
EMIF_
ADDR[10]
NC
ETM
DATA[09] /
EMIF_
ADDR[4]
VCCP
VSS
VSS
VCC
VSS
VSS
VCCIO
ETM
DATA[31] /
EMIF_
DATA[15]
NC
NC
MIBSPI3
SOMI
MIBSPI3
SIMO
8
7
LINRX
LINTX
EMIF_
ADDR[9]
NC
ETM
DATA[10] /
EMIF_
ADDR[3]
VCCIO
VCCIO
ETM
DATA[30] /
EMIF_
DATA[14]
NC
NC
N2HET1
[09]
nPORRST
7
6
GIOA[4]
MIBSPI5
NCS[1]
EMIF_
ADDR[8]
NC
ETM
DATA[11] /
EMIF_
ADDR[2]
VCCIO
VCCIO
VCCIO
VCCIO
VCC
VCC
VCCIO
VCCIO
VCCIO
ETM
DATA[29] /
EMIF_
DATA[13]
NC
NC
N2HET1
[05]
MIBSPI5
NCS[2]
6
5
GIOA[0]
GIOA[5]
EMIF_
ADDR[7]
EMIF_
ADDR[1]
ETM
DATA[20] /
EMIF_
DATA[4]
ETM
DATA[21] /
EMIF_
DATA[5]
ETM
DATA[22] /
EMIF_
DATA[6]
FLTP2
FLTP1
ETM
DATA[23] /
EMIF_
DATA[7]
ETM
DATA[24] /
EMIF_
DATA[8]
ETM
DATA[25] /
EMIF_
DATA[9]
ETM
DATA[26] /
EMIF_
DATA[10]
ETM
DATA[27] /
EMIF_
DATA[11]
ETM
DATA[28] /
EMIF_
DATA[12]
NC
NC
MIBSPI3
NCS[1]
N2HET1
[02]
5
4
N2HET1
[16]
N2HET1
[12]
EMIF_
ADDR[6]
EMIF_
ADDR[0]
NC
NC
NC
N2HET1
[21]
N2HET1
[23]
NC
NC
NC
NC
NC
EMIF_
nCAS
NC
NC
NC
NC
4
3
N2HET1
[29]
N2HET1
[22]
MIBSPI3
NCS[3]
SPI2
NENA
N2HET1
[11]
MIBSPI1
NCS[1]
MIBSPI1
NCS[2]
GIOA[6]
MIBSPI1
NCS[3]
EMIF_
CLK
EMIF_
CKE
N2HET1
[25]
SPI2
NCS[0]
EMIF_
nWAIT
EMIF_
nRAS
NC
NC
NC
N2HET1
[06]
3
2
VSS
MIBSPI3
NCS[2]
GIOA[1]
SPI2
SOMI
SPI2 CLK
GIOB[2]
GIOB[5]
CAN2TX
GIOB[6]
GIOB[1]
KELVIN_
GND
GIOB[0]
N2HET1
[13]
N2HET1
[20]
MIBSPI1
NCS[0]
NC
TEST
N2HET1
[01]
VSS
2
1
VSS
VSS
GIOA[2]
SPI2
SIMO
GIOA[3]
GIOB[7]
GIOB[4]
CAN2RX
N2HET1
[18]
OSCIN
OSCOUT
GIOA[7]
N2HET1
[15]
N2HET1
[24]
NC
N2HET1
[07]
N2HET1
[03]
VSS
VSS
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
TMS570LS3135, TMS570LS2135, TMS570LS2125
www.ti.com
SPNS164C –APRIL 2012–REVISED APRIL 2015
4.2 ZWT BGA Package Ball-Map (337-Ball Grid Array)
A. Balls can have multiplexed functions. Only the default function, except for the EMIF signals that are multiplexed with
ETM signals, is depicted in the figure.
Figure 4-2. ZWT Package Pinout. Top View(A)
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4.3 Terminal Functions
Section 4.3.1 and Section 4.3.2 identify the external signal names, the associated pin or ball numbers
along with the mechanical package designator, the pin or ball type (Input, Output, I/O, Power, or Ground),
whether the pin or ball has any internal pullup or pulldown, whether the pin or ball can be configured as a
GPIO, and a functional pin or ball description. The first signal name listed is the primary function for that
terminal. The signal name in bold is the function being described. For information on how to select
between different multiplexed functions, see the TMS570LS31x/21x 16/32-Bit RISC Flash Microcontroller
Technical Reference Manual (SPNU499) .
NOTE
In the Terminal Functions table below, the "Reset Pull State" is the state of the pull applied to
the terminal while nPORRST is low and immediately after nPORRST goes High. The default
pull direction may change when software configures the pin for an alternate function. The
"Pull Type" is the type of pull asserted when the signal name in bold is enabled for the given
terminal by the IOMM control registers.
All I/O signals except nRST are configured as inputs while nPORRST is low and
immediately after nPORRST goes High. While nPORRST is low, the input buffers
are disabled, and the output buffers are disabled with the default pulls enabled.
All output-only signals have the output buffer disabled and the default pull enabled
while nPORRST is low, and are configured as outputs with the pulls disabled
immediately after nPORRST goes High.
4.3.1 PGE Package
4.3.1.1 Multibuffered Analog-to-Digital Converters (MibADCs)
Table 4-1. PGE Multibuffered Analog-to-Digital Converters (MibADC1, MibADC2)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
ADREFHI(1) 66 Input ADC high reference supply
ADREFLO(1) 67 Input ADC low reference supply
N/A None
VCCAD(1) 69 Power Operating supply for ADC
VSSAD(1) 68 Ground
AD1EVT 86 I/O Pulldown Programmable, 20 µA ADC1 event trigger input, or GPIO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS 55 I/O Pullup Programmable, 20 µA ADC2 event trigger input, or GPIO
AD1IN[0] 60
AD1IN[1] 71
AD1IN[2] 73
AD1IN[3] 74 Input N/A None ADC1 analog input
AD1IN[4] 76
AD1IN[5] 78
AD1IN[6] 80
AD1IN[7] 61
(1) The ADREFHI, ADREFLO, VCCAD and VSSAD connections are common for both ADC cores.
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Table 4-1. PGE Multibuffered Analog-to-Digital Converters (MibADC1, MibADC2) (continued)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
AD1IN[8] / AD2IN[8] 83
AD1IN[9] / AD2IN[9] 70
AD1IN[10] / AD2IN[10] 72
AD1IN[11] / AD2IN[11] 75
AD1IN[12] / AD2IN[12] 77
AD1IN[13] / AD2IN[13] 79
AD1IN[14] / AD2IN[14] 82
AD1IN[15] / AD2IN[15] 85 Input N/A None ADC1/ADC2 shared analog inputs
AD1IN[16] / AD2IN[0] 58
AD1IN[17] / AD2IN[1] 59
AD1IN[18] / AD2IN[2] 62
AD1IN[19] / AD2IN[3] 63
AD1IN[20] / AD2IN[4] 64
AD1IN[21] / AD2IN[5] 65
AD1IN[22] / AD2IN[6] 81
AD1IN[23] / AD2IN[7] 84
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4.3.1.2 Enhanced High-End Timer (N2HET) Modules
Table 4-2. PGE Enhanced High-End Timer Modules (N2HET1, N2HET2)
TERMINAL SIGNAL RESET PULL PULL TYPE DESCRIPTION
144 TYPE STATE
SIGNAL NAME PGE
N2HET1[0]/SPI4CLK 25
N2HET1[1]/SPI4NENA/N2HET2[8] 23
N2HET1[2]/SPI4SIMO[0] 30
N2HET1[3]/SPI4NCS[0]/N2HET2[10] 24
N2HET1[4] 36
N2HET1[5]/SPI4SOMI[0]/N2HET2[12] 31
N2HET1[6]/SCIRX 38
N2HET1[7]/N2HET2[14] 33 Programmable,
N2HET1[8]/MIBSPI1SIMO[1] 106 I/O Pulldown 20 µA
N2HET1[9]/N2HET2[16] 35
N2HET1[10] 118
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] 6
N2HET1[12] 124
N2HET1[13]/SCITX 39
N2HET1[14] 125
N2HET1[15]/MIBSPI1NCS[4] 41
N2HET1[16] 139
Programmable,
MIBSPI1NCS[1]/N2HET1[17] 130 I/O Pullup 20 µA N2HET1 timer input capture
Programmable, or output compare, or GIO.
N2HET1[18] 140 I/O Pulldown 20 µA Each terminal has a
Programmable, suppression filter with a
MIBSPI1NCS[2]/N2HET1[19] 40 I/O Pullup 20 µA programmable duration.
Programmable,
N2HET1[20] 141 I/O Pulldown 20 µA
Programmable,
N2HET1[22] 15 I/O Pulldown 20 µA
Programmable,
MIBSPI1NENA/N2HET1[23] 96 I/O Pullup 20 µA
Programmable,
N2HET1[24]/MIBSPI1NCS[5] 91 I/O Pulldown 20 µA
Programmable,
MIBSPI3NCS[1]/N2HET1[25]/MDCLK 37 I/O Pullup 20 µA
Programmable,
N2HET1[26] 92 I/O Pulldown 20 µA
Programmable,
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] 4 I/O Pullup 20 µA
Programmable,
N2HET1[28] 107 I/O Pulldown 20 µA
Programmable,
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] 3 I/O Pullup 20 µA
Programmable,
N2HET1[30] 127 I/O Pulldown 20 µA
Programmable,
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31] 54 I/O Pullup 20 µA
Programmable, Disable selected PWM
GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS 14 I/O Pulldown 20 µA outputs
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Table 4-2. PGE Enhanced High-End Timer Modules (N2HET1, N2HET2) (continued)
TERMINAL SIGNAL RESET PULL PULL TYPE DESCRIPTION
144 TYPE STATE
SIGNAL NAME PGE
GIOA[2]/N2HET2[0] 9
GIOA[6]/N2HET2[4] 16
GIOA[7]/N2HET2[6] 22 N2HET2 time input capture
N2HET1[1]/SPI4NENA/N2HET2[8] 23 or output compare, or GPIO
Programmable,
N2HET1[3]/SPI4NCS[0]/N2HET2[10] 24 I/O Pulldown Each terminal has a
20 µA suppression filter with a
N2HET1[5]/SPI4SOMI[0]/N2HET2[12] 31 programmable duration.
N2HET1[7]/N2HET2[14] 33
N2HET1[9]/N2HET2[16] 35
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] 6
Programmable, Disable selected PWM
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS 55 I/O Pullup 20 µA outputs
4.3.1.3 General-Purpose Input/Output (GPIO)
Table 4-3. PGE General-Purpose Input/Output (GPIO)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
GIOA[2]/N2HET2[0] 9 General-purpose I/O.
GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS 14 All GPIO terminals are
Programmable,
I/O Pulldown capable of generating
20 µA
GIOA[6]/N2HET2[4] 16 interrupts to the CPU on rising
GIOA[7]/N2HET2[6] 22 / falling / both edges.
The application cannot output
a level onto this terminal
when it is configured as
Programmable, GIOB[2]. A pull-up is enabled
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS 55 I/O Pullup 20 µA on this input. This pull cannot
be disabled, and is not
programmable using the GIO
module pull control registers.
4.3.1.4 FlexRay Interface Controller (FlexRay)
Table 4-4. FlexRay Interface Controller (FlexRay)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
Fixed 100 µA
FRAYRX1 126 Input Pullup FlexRay data receive (channel 1)
Pullup
FRAYTX1 133 Output FlexRay data transmit (channel 1)
N/A None
FRAYTXEN1 142 Output FlexRay transmit enable (channel 1)
Fixed 100 µA
FRAYRX2 2 Input Pullup FlexRay data receive (channel 2)
Pullup
FRAYTX2 1 Output FlexRay data transmit (channel 2)
N/A None
FRAYTXEN2 5 Output FlexRay transmit enable (channel 2)
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4.3.1.5 Controller Area Network Controllers (DCANs)
Table 4-5. PGE Controller Area Network Controllers (DCAN)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
CAN1RX 90 CAN1 receive, or GPIO
CAN1TX 89 CAN1 transmit, or GPIO
CAN2RX 129 CAN2 receive, or GPIO
Programmable,
I/O Pullup 20 µA
CAN2TX 128 CAN2 transmit, or GPIO
CAN3RX 12 CAN3 receive, or GPIO
CAN3TX 13 CAN3 transmit, or GPIO
4.3.1.6 Local Interconnect Network Interface Module (LIN)
Table 4-6. PGE Local Interconnect Network Interface Module (LIN)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
LINRX 131 LIN receive, or GPIO
Programmable,
I/O Pullup 20 µA
LINTX 132 LIN transmit, or GPIO
4.3.1.7 Standard Serial Communication Interface (SCI)
Table 4-7. PGE Standard Serial Communication Interface (SCI)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
N2HET1[6]/SCIRX 38 SCI receive, or GPIO
Programmable,
I/O Pulldown 20 µA
N2HET1[13]/SCITX 39 SCI transmit, or GPIO
4.3.1.8 Inter-Integrated Circuit Interface Module (I2C)
Table 4-8. PGE Inter-Integrated Circuit Interface Module (I2C)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] 4 I2C serial data, or GPIO
Programmable,
I/O Pullup 20 µA
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] 3 I2C serial clock, or GPIO
4.3.1.9 Standard Serial Peripheral Interface (SPI)
Table 4-9. PGE Standard Serial Peripheral Interface (SPI)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
N2HET1[0]/SPI4CLK 25 SPI4 clock, or GPIO
N2HET1[3]/SPI4NCS[0]/N2HET2[10] 24 SPI4 chip select, or GPIO
N2HET1[1]/SPI4NENA/N2HET2[8] 23 SPI4 enable, or GPIO
Programmable,
I/O Pulldown 20 µA SPI4 slave-input master-
N2HET1[2]/SPI4SIMO[0] 30 output, or GPIO
SPI4 slave-output master-
N2HET1[5]/SPI4SOMI[0]/N2HET2[12] 31 input, or GPIO
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4.3.1.10 Multibuffered Serial Peripheral Interface Modules (MibSPI)
Table 4-10. PGE Multibuffered Serial Peripheral Interface Modules (MibSPI)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
MIBSPI1CLK 95 MibSPI1 clock, or GPIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1] 105 Programmable,
Pullup 20 µA
MIBSPI1NCS[1]/N2HET1[17] 130 MibSPI1 chip select, or GPIO
MIBSPI1NCS[2]/N2HET1[19] 40
N2HET1[15]/MIBSPI1NCS[4] 41 Programmable,
Pulldown MibSPI1 chip select, or GPIO
20 µA
N2HET1[24]/MIBSPI1NCS[5] 91 I/O
MIBSPI1NENA/N2HET1[23] 96 MibSPI1 enable, or GPIO
Programmable,
Pullup 20 µA
MIBSPI1SIMO[0] 93 MibSPI1 slave-in master-out, or GPIO
Programmable,
N2HET1[8]/MIBSPI1SIMO[1] 106 Pulldown MibSPI1 slave-in master-out, or GPIO
20 µA
MIBSPI1SOMI[0] 94 Programmable,
Pullup MibSPI1 slave-out master-in, or GPIO
20 µA
MIBSPI1NCS[0]/MIBSPI1SOMI[1] 105
MIBSPI3CLK 53 MibSPI3 clock, or GPIO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS 55 Programmable,
MIBSPI3NCS[1]/N2HET1[25]/MDCLK 37 Pullup 20 µA MibSPI3 chip select, or GPIO
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] 4
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] 3 I/O Programmable,
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] 6 Pulldown MibSPI3 chip select, or GPIO
20 µA
MIBSPI3NENA /MIBSPI3NCS[5]/N2HET1[31] 54 MibSPI3 chip select, or GPIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31] 54 MibSPI3 enable, or GPIO
Programmable,
Pullup 20 µA
MIBSPI3SIMO[0] 52 MibSPI3 slave-in master-out, or GPIO
MIBSPI3SOMI[0] 51 MibSPI3 slave-out master-in, or GPIO
MIBSPI5CLK 100 MibSPI5 clock, or GPIO
MIBSPI5NCS[0] 32 MibSPI5 chip select, or GPIO
Programmable,
MIBSPI5NENA 97 I/O Pullup MibSPI5 enable, or GPIO
20 µA
MIBSPI5SIMO[0] 99 MibSPI5 slave-in master-out, or GPIO
MIBSPI5SOMI[0] 98 MibSPI5 slave-out master-in, or GPIO
4.3.1.11 System Module Interface
Table 4-11. PGE System Module Interface
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
Power-on reset, cold reset
External power supply monitor
circuitry must drive nPORRST
Fixed 100 µA low when any of the supplies
nPORRST 46 Input Pulldown Pulldown to the microcontroller fall out
of the specified range. This
terminal has a glitch filter.
See Section 6.8.
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Table 4-11. PGE System Module Interface (continued)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
System reset, warm reset,
bidirectional.
The internal circuitry indicates
any reset condition by driving
nRST low.
The external circuitry can
assert a system reset by
Fixed 100 µA
nRST 116 I/O Pullup driving nRST low. To ensure
Pullup that an external reset is not
arbitrarily generated, TI
recommends that an external
pullup resistor is connected to
this terminal.
This terminal has a glitch
filter. See Section 6.8.
ESM Error Signal
Fixed 20 µA
nERROR 117 I/O Pulldown Indicates error of high
Pulldown severity. See Section 6.18.
4.3.1.12 Clock Inputs and Outputs
Table 4-12. PGE Clock Inputs and Outputs
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
From external
OSCIN 18 Input crystal/resonator, or external
clock input
N/A None
KELVIN_GND 19 Input Kelvin ground for oscillator
OSCOUT 20 Output To external crystal/resonator
Programmable, 20 External prescaled clock
ECLK 119 I/O Pulldown µA output, or GIO.
GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS 14 Input Pulldown 20 µA External clock input #1
4.3.1.13 Test and Debug Modules Interface
Table 4-13. PGE Test and Debug Modules Interface
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
SIGNAL NAME 144 TYPE STATE
PGE
Test enable. This terminal
must be connected to ground
TEST 34 I/O Fixed 100 µA directly or via a pulldown
Pulldown Pulldown resistor.
nTRST 109 Input JTAG test hardware reset
RTCK 113 Output N/A None JTAG return test clock
Fixed 100 µA
TCK 112 Input Pulldown JTAG test clock
Pulldown
Fixed 100 µA
TDI 110 I/O Pullup JTAG test data in
Pullup
100 µA
TDO 111 Output None JTAG test data out
Pulldown
Fixed 100 µA
TMS 108 I/O Pullup JTAG test select
Pullup
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4.3.1.14 Flash Supply and Test Pads
Table 4-14. PGE Flash Supply and Test Pads
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
3.3-V
VCCP 134 N/A None Flash pump supply
Power
FLTP1 7 Flash test pads. These
terminals are reserved for TI
use only. For proper operation
N/A None these terminals must connect
FLTP2 8only to a test pad or not be
connected at all [no connect
(NC)].
4.3.1.15 Supply for Core Logic: 1.2-V Nominal
Table 4-15. PGE Supply for Core Logic: 1.2-V Nominal
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
VCC 17
VCC 29
VCC 45
VCC 48
VCC 49
VCC 57 1.2-V N/A None 1.2-V Core supply
Power
VCC 87
VCC 101
VCC 114
VCC 123
VCC 137
VCC 143
4.3.1.16 Supply for I/O Cells: 3.3-V Nominal
Table 4-16. PGE Supply for I/O Cells: 3.3-V Nominal
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
SIGNAL NAME 144 TYPE STATE
PGE
VCCIO 10
VCCIO 26
VCCIO 42 3.3-V 3.3-V Operating supply for
N/A None
Power I/Os
VCCIO 104
VCCIO 120
VCCIO 136
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4.3.1.17 Ground Reference for All Supplies Except VCCAD
Table 4-17. PGE Ground Reference for All Supplies Except VCCAD
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
VSS 11 Ground reference
VSS 21
VSS 27
VSS 28
VSS 43
VSS 44
VSS 47
VSS 50
VSS 56 Ground N/A None
VSS 88
VSS 102
VSS 103
VSS 115
VSS 121
VSS 122
VSS 135
VSS 138
VSS 144
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4.3.2 ZWT Package
4.3.2.1 Multibuffered Analog-to-Digital Converters (MibADCs)
Table 4-18. ZWT Multibuffered Analog-to-Digital Converters (MibADC1, MibADC2)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
337 TYPE
SIGNAL NAME STATE
ZWT
ADREFHI(1) V15 Input ADC high reference supply
ADREFLO(1) V16 Input N/A None ADC low reference supply
VCCAD(1) W15 Power Operating supply for ADC
VSSAD V19
VSSAD W16 Ground N/A None ADC supply power
VSSAD W18
VSSAD W19
Programmable, ADC1 event trigger input, or
AD1EVT N19 I/O Pulldown 20 µA GPIO
Programmable, ADC2 event trigger input, or
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS V10 I/O Pullup 20 µA GPIO
AD1IN[0] W14
AD1IN[1] V17
AD1IN[2] V18
AD1IN[3] T17 Input N/A None ADC1 analog input
AD1IN[4] U18
AD1IN[5] R17
AD1IN[6] T19
AD1IN[7] V14
AD1IN[8] / AD2IN[8] P18
AD1IN[9] / AD2IN[9] W17
AD1IN[10] / AD2IN[10] U17
AD1IN[11] / AD2IN[11] U19
AD1IN[12] / AD2IN[12] T16
AD1IN[13] / AD2IN[13] T18
AD1IN[14] / AD2IN[14] R18
AD1IN[15] / AD2IN[15] P19 ADC1/ADC2 shared analog
Input N/A None inputs
AD1IN[16] / AD2IN[0] V13
AD1IN[17] / AD2IN[1] U13
AD1IN[18] / AD2IN[2] U14
AD1IN[19] / AD2IN[3] U16
AD1IN[20] / AD2IN[4] U15
AD1IN[21] / AD2IN[5] T15
AD1IN[22] / AD2IN[6] R19
AD1IN[23] / AD2IN[7] R16
(1) The ADREFHI, ADREFLO, VCCAD and VSSAD connections are common for both ADC cores.
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4.3.2.2 Enhanced High-End Timer (N2HET) Modules
Table 4-19. ZWT Enhanced High-End Timer (N2HET) Modules
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
337 TYPE
SIGNAL NAME STATE
ZWT
N2HET1[0]/SPI4CLK K18
N2HET1[1]/SPI4NENA/N2HET2[8] V2
N2HET1[2]/SPI4SIMO[0] W5
N2HET1[3]/SPI4NCS[0]/N2HET2[10] U1
N2HET1[4] B12
N2HET1[5]/SPI4SOMI[0]/N2HET2[12] V6
N2HET1[6]/SCIRX W3
N2HET1[7]/N2HET2[14] T1
N2HET1[8]/MIBSPI1SIMO[1] E18
N2HET1[9]/N2HET2[16] V7
N2HET1[10] D19
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] E3
N2HET1[12] B4
N2HET1[13]/SCITX N2
N2HET1[14] A11
N2HET1[15]/MIBSPI1NCS[4] N1
N2HET1[16] A4
N2HET1[17] A13 N2HET1 time input capture or
MIBSPI1NCS[1]/N2HET1[17] F3 output compare, or GIO.
N2HET1[18] J1 Programmable,
I/O Pulldown Each terminal has a
20 µA
N2HET1[19] B13 suppression filter with a
MIBSPI1NCS[2]/N2HET1[19] G3 programmable duration.
N2HET1[20] P2
N2HET1[21] H4
MIBSPI1NCS[3]/N2HET1[21] J3
N2HET1[22] B3
N2HET1[23] J4
MIBSPI1NENA/N2HET1[23] G19
N2HET1[24]/MIBSPI1NCS[5] P1
N2HET1[25] M3
MIBSPI3NCS[1]/N2HET1[25] V5
N2HET1[26] A14
N2HET1[27] A9
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] B2
N2HET1[28] K19
N2HET1[29] A3
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] C3
N2HET1[30] B11
N2HET1[31] J17
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31] W9
Programmable, Disable selected PWM
GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS B5 I/O Pulldown 20 µA outputs
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Table 4-19. ZWT Enhanced High-End Timer (N2HET) Modules (continued)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
337 TYPE
SIGNAL NAME STATE
ZWT
GIOA[2]/N2HET2[0] C1
EMIF_ADDR[0]/N2HET2[1] D4
GIOA[3]/N2HET2[2] E1
EMIF_ADDR[1]/N2HET2[3] D5
GIOA[6]/N2HET2[4] H3
EMIF_BA[1]/N2HET2[5] D16
GIOA[7]/N2HET2[6] M1 N2HET2 time input capture or
EMIF_nCS[0]/RTP_DATA[15]/N2HET2[7] N17 output compare, or GIO.
N2HET1[1]/SPI4NENA/N2HET2[8] V2 Programmable,
I/O Pulldown Each terminal has a
20 µA
EMIF_nCS[3]/RTP_DATA[14]/N2HET2[9] K17 suppression filter with a
N2HET1[3]/SPI4NCS[0]/N2HET2[10] U1 programmable duration.
EMIF_ADDR[6]/RTP_DATA[13]/N2HET2[11] C4
N2HET1[5]/SPI4SOMI[0]/N2HET2[12] V6
EMIF_ADDR[7]/RTP_DATA[12]/N2HET2[13] C5
N2HET1[7]/N2HET2[14] T1
EMIF_ADDR[8]/RTP_DATA[11]/N2HET2[15] C6
N2HET1[9]/N2HET2[16] V7
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] E3
Programmable, Disable selected PWM
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS V10 I/O Pullup 20 µA outputs
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4.3.2.3 General-Purpose Input/Output (GPIO)
Table 4-20. ZWT General-Purpose Input/Output (GPIO)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
337 TYPE
SIGNAL NAME STATE
ZWT
GIOA[0] A5
GIOA[1] C2
GIOA[2]/N2HET2[0] C1
GIOA[3]/N2HET2[2] E1
GIOA[4] A6
GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS B5
GIOA[6]/N2HET2[4] H3 General-purpose I/O.
All GPIO terminals are
GIOA[7]/N2HET2[6] M1 Programmable,
Pulldown capable of generating
20 µA
GIOB[0] M2 interrupts to the CPU on rising
/ falling / both edges.
GIOB[1] K2
GIOB[2] F2 I/O
GIOB[3] W10
GIOB[4] G1
GIOB[5] G2
GIOB[6] J2
GIOB[7] F1
The application cannot output
a level onto this terminal
when it is configured as
Fixed 20 µA GIOB[2]. A pull-up is enabled
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS V10 Pullup Pulldown on this input. This pull cannot
be disabled, and is not
programmable using the GIO
module pull control registers
4.3.2.4 FlexRay Interface Controller (FlexRay)
Table 4-21. FlexRay Interface Controller (FlexRay)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
337 TYPE
SIGNAL NAME STATE
ZWT
Fixed 100 µA FlexRay data receive
FRAYRX1 A15 Input Pullup Pullup (channel 1)
FlexRay data transmit
FRAYTX1 B15 Output (channel 1)
None None FlexRay transmit enable
FRAYTXEN1 B16 Output (channel 1)
Fixed 100 µA FlexRay data receive
FRAYRX2 A8 Input Pullup Pullup (channel 2)
FlexRay data transmit
FRAYTX2 B8 Output (channel 2)
None None FlexRay transmit enable
FRAYTXEN2 B9 Output (channel 2)
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4.3.2.5 Controller Area Network Controllers (DCANs)
Table 4-22. ZWT Controller Area Network Controllers (DCANs)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
337 TYPE
SIGNAL NAME STATE
ZWT
CAN1RX B10 CAN1 receive, or GPIO
CAN1TX A10 CAN1 transmit, or GPIO
CAN2RX H1 CAN2 receive, or GPIO
Programmable,
I/O Pullup 20 µA
CAN2TX H2 CAN2 transmit, or GPIO
CAN3RX M19 CAN3 receive, or GPIO
CAN3TX M18 CAN3 transmit, or GPIO
4.3.2.6 Local Interconnect Network Interface Module (LIN)
Table 4-23. ZWT Local Interconnect Network Interface Module (LIN)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
337 TYPE
SIGNAL NAME STATE
ZWT
LINRX A7 LIN receive, or GPIO
Programmable,
I/O Pullup 20 µA
LINTX B7 LIN transmit, or GPIO
4.3.2.7 Standard Serial Communication Interface (SCI)
Table 4-24. ZWT Standard Serial Communication Interface (SCI)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
337 TYPE
SIGNAL NAME STATE
ZWT
N2HET1[6]/SCIRX W3 SCI receive, or GPIO
Programmable,
I/O Pulldown 20 µA
N2HET1[13]/SCITX N2 SCI transmit, or GPIO
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4.3.2.8 Inter-Integrated Circuit Interface Module (I2C)
Table 4-25. ZWT Inter-Integrated Circuit Interface Module (I2C)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
337 TYPE
SIGNAL NAME STATE
ZWT
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] B2 I2C serial data, or GPIO
Programmable,
I/O Pullup 20 µA
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] C3 I2C serial clock, or GPIO
4.3.2.9 Standard Serial Peripheral Interface (SPI)
Table 4-26. ZWT Standard Serial Peripheral Interface (SPI)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
337 TYPE
SIGNAL NAME STATE
ZWT
SPI2CLK E2 SPI2 clock, or GPIO
SPI2NCS[0] N3 SPI2 chip select, or GPIO
SPI2NENA/SPI2NCS[1] D3 SPI2 chip select, or GPIO
Programmable,
SPI2NENA/SPI2NCS[1] D3 SPI2 enable, or GPIO
I/O Pullup 20 µA SPI2 slave-input master-
SPI2SIMO[0] D1 output, or GPIO
SPI2 slave-output master-
SPI2SOMI[0] D2 input, or GPIO
N2HET1[0]/SPI4CLK K18 SPI4 clock, or GPIO
N2HET1[3]/SPI4NCS[0]/N2HET2[10] U1 SPI4 chip select, or GPIO
N2HET1[1]/SPI4NENA/N2HET2[8] V2 SPI4 enable, or GPIO
Programmable,
I/O Pulldown 20 µA SPI4 slave-input master-
N2HET1[2]/SPI4SIMO[0] W5 output, or GPIO
SPI4 slave-output master-
N2HET1[5]/SPI4SOMI[0]/N2HET2[12] V6 input, or GPIO
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4.3.2.10 Multibuffered Serial Peripheral Interface Modules (MibSPI)
Table 4-27. ZWT Multibuffered Serial Peripheral Interface Modules (MibSPI)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
337 TYPE
SIGNAL NAME STATE
ZWT
MIBSPI1CLK F18 MibSPI1 clock, or GPIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1] R2 Programmable,
MIBSPI1NCS[1]/N2HET1[17] F3 Pullup 20 µA MibSPI1 chip select, or GPIO
MIBSPI1NCS[2]/N2HET1[19] G3
MIBSPI1NCS[3]/N2HET1[21] J3
N2HET1[15]/MIBSPI1NCS[4] N1 Programmable,
Pulldown MibSPI1 chip select, or GPIO
20 µA
N2HET1[24]/MIBSPI1NCS[5] P1 I/O
MIBSPI1NENA/N2HET1[23] G19 MibSPI1 enable, or GPIO
Programmable,
Pullup MibSPI1 slave-in master-out,
20 µA
MIBSPI1SIMO[0] F19 or GPIO
Programmable, MibSPI1 slave-in master-out,
N2HET1[8]/MIBSPI1SIMO[1] E18 Pulldown 20 µA or GPIO
MIBSPI1SOMI[0] G18 Programmable, MibSPI1 slave-out master-in,
Pullup 20 µA or GPIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1] R2
MIBSPI3CLK V9 MibSPI3 clock, or GPIO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS V10 Programmable,
MIBSPI3NCS[1]/N2HET1[25]/MDCLK V5 Pullup 20 µA MibSPI3 chip select, or GPIO
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] B2
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] C3
Programmable,
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] E3 Pulldown MibSPI3 chip select, or GPIO
I/O 20 µA
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31] W9 MibSPI3 chip select, or GPIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31] W9 MibSPI3 enable, or GPIO
Programmable, MibSPI3 slave-in master-out,
Pullup
MIBSPI3SIMO[0] W8 20 µA or GPIO
MibSPI3 slave-out master-in,
MIBSPI3SOMI[0] V8 or GPIO
MIBSPI5CLK/DMM_DATA[4] H19 MibSPI5 clock, or GPIO
MIBSPI5NCS[0]/DMM_DATA[5] E19
MIBSPI5NCS[1]/DMM_DATA[6] B6 MibSPI5 chip select, or GPIO
MIBSPI5NCS[2]/DMM_DATA[2] W6
MIBSPI5NCS[3]/DMM_DATA[3] T12
MIBSPI5NENA/DMM_DATA[7] H18 MibSPI5 enable, or GPIO
MIBSPI5SIMO[0]/DMM_DATA[8] J19 Programmable,
I/O Pullup 20 µA
MIBSPI5SIMO[1]/DMM_DATA[9] E16
MIBSPI5SIMO[2]/DMM_DATA[10] H17
MIBSPI5SIMO[3]/DMM_DATA[11] G17 MibSPI5 slave-in master-out,
or GPIO
MIBSPI5SOMI[0]/DMM_DATA[12] J18
MIBSPI5SOMI[1]/DMM_DATA[13] E17
MIBSPI5SOMI[2]/DMM_DATA[14] H16
MIBSPI5SOMI[3]/DMM_DATA[15] G16
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4.3.2.11 External Memory Interface (EMIF)
Table 4-28. External Memory Interface (EMIF)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
337 TYPE
SIGNAL NAME STATE
ZWT
EMIF_CKE L3 Output None EMIF Clock Enable
EMIF clock. This is an output
signal in functional mode. It is
Pulldown gated off by default, so that
EMIF_CLK K3 I/O None the signal is tri-stated.
PINMUX29[8] must be
cleared to enable this output.
ETMDATA[13]/EMIF_nOE E12 Pulldown None EMIF Output Enable
Fixed 20 µA
EMIF_nWAIT P3 I/O Pullup EMIF Extended Wait Signal
Pullup
EMIF_nWE D17 Output EMIF Write Enable.
EMIF_nCAS R4 Output Pullup EMIF column address strobe
EMIF_nRAS R3 Output EMIF row address strobe
EMIF_nCS[0]/RTP_DATA[15]/N2HET2[7] N17 Output Pulldown EMIF chip select, SDRAM
EMIF_nCS[2] L17 Output Pullup EMIF chip selects,
asynchronous
EMIF_nCS[3]/RTP_DATA[14]/N2HET2[9] K17 Output Pulldown This applies to chip selects 2,
3, and 4
EMIF_nCS[4]/RTP_DATA[7] M17 Output Pullup
ETMDATA[15]/EMIF_nDQM[0] E10 Output EMIF Data Mask or Write
Strobe.
Data mask for SDRAM
devices, write strobe for
ETMDATA[14]/EMIF_nDQM[1] E11 Output connected asynchronous
devices.
EMIF bank address or
ETMDATA[12]/EMIF_BA[0] E13 Output address line
EMIF bank address or
EMIF_BA[1]/N2HET2[5] D16 Output address line
EMIF_ADDR[0]/N2HET2[1] D4 Output
EMIF_ADDR[1]/N2HET2[3] D5 Output
ETMDATA[11]/EMIF_ADDR[2] E6 Output
ETMDATA[10]/EMIF_ADDR[3] E7 Output None
ETMDATA[9]/EMIF_ADDR[4] E8 Output Pulldown
ETMDATA[8]/EMIF_ADDR[5] E9 Output
EMIF_ADDR[6]/RTP_DATA[13]/N2HET2[11] C4 Output
EMIF_ADDR[7]/RTP_DATA[12]/N2HET2[13] C5 Output
EMIF_ADDR[8]/RTP_DATA[11]/N2HET2[15] C6 Output
EMIF_ADDR[9]/RTP_DATA[10] C7 Output
EMIF_ADDR[10]/RTP_DATA[9] C8 Output EMIF address
EMIF_ADDR[11]/RTP_DATA[8] C9 Output
EMIF_ADDR[12]/RTP_DATA[6] C10 Output
EMIF_ADDR[13]/RTP_DATA[5] C11 Output
EMIF_ADDR[14]/RTP_DATA[4] C12 Output
EMIF_ADDR[15]/RTP_DATA[3] C13 Output
EMIF_ADDR[16]/RTP_DATA[2] D14 Output
EMIF_ADDR[17]/RTP_DATA[1] C14 Output
EMIF_ADDR[18]/RTP_DATA[0] D15 Output
EMIF_ADDR[19]/RTP_nENA C15 Output Pulldown
EMIF_ADDR[20]/RTP_nSYNC C16 Output
EMIF_ADDR[21]/RTP_CLK C17 Output
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Table 4-28. External Memory Interface (EMIF) (continued)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
337 TYPE
SIGNAL NAME STATE
ZWT
ETMDATA[16]/EMIF_DATA[0] K15 I/O
ETMDATA[17]/EMIF_DATA[1] L15 I/O
ETMDATA[18]/EMIF_DATA[2] M15 I/O
ETMDATA[19]/EMIF_DATA[3] N15 I/O
ETMDATA[20]/EMIF_DATA[4] E5 I/O
ETMDATA[21]/EMIF_DATA[5] F5 I/O
ETMDATA[22]/EMIF_DATA[6] G5 I/O
ETMDATA[23]/EMIF_DATA[7] K5 I/O Fixed 20 µA
Pulldown EMIF Data
Pullup
ETMDATA[24]/EMIF_DATA[8] L5 I/O
ETMDATA[25]/EMIF_DATA[9] M5 I/O
ETMDATA[26]/EMIF_DATA[10] N5 I/O
ETMDATA[27]/EMIF_DATA[11] P5 I/O
ETMDATA[28]/EMIF_DATA[12] R5 I/O
ETMDATA[29]/EMIF_DATA[13] R6 I/O
ETMDATA[30]/EMIF_DATA[14] R7 I/O
ETMDATA[31]/EMIF_DATA[15] R8 I/O
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4.3.2.12 Embedded Trace Macrocell for Cortex-R4F CPU (ETM-R4F)
Table 4-29. Embedded Trace Macrocell for Cortex-R4F CPU (ETM-R4F)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
337 TYPE
SIGNAL NAME STATE
ZWT
Fixed 20 µA
ETMTRACECLKIN/EXTCLKIN2 R9 Input Pulldown ETM Trace Clock Input
Pullup
ETMTRACECLKOUT R10 ETM Trace Clock Output
ETMTRACECTL R11 ETM trace control
ETMDATA[0] R12
ETMDATA[1] R13
ETMDATA[2] J15
ETMDATA[3] H15
ETMDATA[4] G15
ETMDATA[5] F15
ETMDATA[6] E15
ETMDATA[7] E14
ETMDATA[8]/EMIF_ADDR[5] E9
ETMDATA[9]/EMIF_ADDR[4] E8
ETMDATA[10]/EMIF_ADDR[3] E7
ETMDATA[11]/EMIF_ADDR[2] E6
ETMDATA[12]/EMIF_BA[0] E13
ETMDATA[13]/EMIF_nOE E12
ETMDATA[14]/EMIF_nDQM[1] E11 Output Pulldown None
ETMDATA[15]/EMIF_nDQM[0] E10 ETM data
ETMDATA[16]/EMIF_DATA[0] K15
ETMDATA[17]/EMIF_DATA[1] L15
ETMDATA[18]/EMIF_DATA[2] M15
ETMDATA[19]/EMIF_DATA[3] N15
ETMDATA[20]/EMIF_DATA[4] E5
ETMDATA[21]/EMIF_DATA[5] F5
ETMDATA[22]/EMIF_DATA[6] G5
ETMDATA[23]/EMIF_DATA[7] K5
ETMDATA[24]/EMIF_DATA[8] L5
ETMDATA[25]/EMIF_DATA[9] M5
ETMDATA[26]/EMIF_DATA[10] N5
ETMDATA[27]/EMIF_DATA[11] P5
ETMDATA[28]/EMIF_DATA[12] R5
ETMDATA[29]/EMIF_DATA[13] R6
ETMDATA[30]/EMIF_DATA[14] R7
ETMDATA[31]/EMIF_DATA[15] R8
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4.3.2.13 RAM Trace Port (RTP)
Table 4-30. RAM Trace Port (RTP)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
337 TYPE
SIGNAL NAME STATE
ZWT
EMIF_ADDR[21]/RTP_CLK C17 I/O RTP packet clock, or GPIO
RTP packet handshake, or
EMIF_ADDR[19]/RTP_nENA C15 I/O GPIO
EMIF_ADDR[20]/RTP_nSYNC C16 I/O RTP synchronization, or GPIO
EMIF_ADDR[18]/RTP_DATA[0] D15 Programmable,
EMIF_ADDR[17]/RTP_DATA[1] C14 Pulldown 20 µA
EMIF_ADDR[16]/RTP_DATA[2] D14
EMIF_ADDR[15]/RTP_DATA[3] C13
EMIF_ADDR[14]/RTP_DATA[4] C12
EMIF_ADDR[13]/RTP_DATA[5] C11
EMIF_ADDR[12]/RTP_DATA[6] C10
Programmable,
EMIF_nCS[4]/RTP_DATA[7] M17 Pullup 20 µA
I/O RTP packet data, or GPIO
EMIF_ADDR[11]/RTP_DATA[8] C9
EMIF_ADDR[10]/RTP_DATA[9] C8
EMIF_ADDR[9]/RTP_DATA[10] C7
EMIF_ADDR[8]/RTP_DATA[11]/N2HET2[15] C6 Programmable,
Pulldown 20 µA
EMIF_ADDR[7]/RTP_DATA[12]/N2HET2[13] C5
EMIF_ADDR[6]/RTP_DATA[13]/N2HET2[11] C4
EMIF_nCS[0]/RTP_DATA[15]/N2HET2[7] N17
EMIF_nCS[3]/RTP_DATA[14]/N2HET2[9] K17
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4.3.2.14 Data Modification Module (DMM)
Table 4-31. Data Modification Module (DMM)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
337 TYPE
SIGNAL NAME STATE
ZWT
DMM_CLK F17 DMM clock, or GPIO
DMM_nENA F16 DMM handshake, or GPIO
DMM synchronization, or
DMM_SYNC J16 GPIO
DMM_DATA[0] L19
DMM_DATA[1] L18
MIBSPI5NCS[2]/DMM_DATA[2] W6
MIBSPI5NCS[3]/DMM_DATA[3] T12
MIBSPI5CLK/DMM_DATA[4] H19
MIBSPI5NCS[0]/DMM_DATA[5] E19 Programmable,
I/O Pullup
MIBSPI5NCS[1]/DMM_DATA[6] B6 20 µA
MIBSPI5NENA/DMM_DATA[7] H18 DMM data, or GPIO
MIBSPI5SIMO[0]/DMM_DATA[8] J19
MIBSPI5SIMO[1]/DMM_DATA[9] E16
MIBSPI5SIMO[2]/DMM_DATA[10] H17
MIBSPI5SIMO[3]/DMM_DATA[11] G17
MIBSPI5SOMI[0]/DMM_DATA[12] J18
MIBSPI5SOMI[1]/DMM_DATA[13] E17
MIBSPI5SOMI[2]/DMM_DATA[14] H16
MIBSPI5SOMI[3]/DMM_DATA[15] G16
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4.3.2.15 System Module Interface
Table 4-32. ZWT System Module Interface
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
337 TYPE
SIGNAL NAME STATE
ZWT
Power-on reset, cold reset
External power supply monitor
circuitry must drive nPORRST
Fixed 100 µA low when any of the supplies
nPORRST W7 Input Pulldown Pulldown to the microcontroller fall out
of the specified range. This
terminal has a glitch filter.
See Section 6.8.
System reset, warm reset,
bidirectional.
The internal circuitry indicates
any reset condition by driving
nRST low.
The external circuitry can
assert a system reset by
Fixed 100 µA
nRST B17 I/O Pullup driving nRST low. To ensure
Pullup that an external reset is not
arbitrarily generated, TI
recommends that an external
pullup resistor is connected to
this terminal.
This terminal has a glitch
filter. See Section 6.8.
ESM Error Signal
Fixed 20 µA
nERROR B14 I/O Pulldown Indicates error of high
Pulldown severity. See Section 6.18.
4.3.2.16 Clock Inputs and Outputs
Table 4-33. ZWT Clock Inputs and Outputs
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
337 TYPE
SIGNAL NAME STATE
ZWT
From external
OSCIN K1 Input crystal/resonator, or external
clock input
N/A None
KELVIN_GND L2 Input Kelvin ground for oscillator
OSCOUT L1 Output To external crystal/resonator
Programmable, External prescaled clock
ECLK A12 I/O Pulldown 20 µA output, or GIO.
GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS B5 Input External clock input #1
Fixed 20 µA
Pulldown Pulldown
ETMTRACECLKIN/EXTCLKIN2 R9 Input External clock input #2
1.2-V Dedicated core supply for
VCCPLL P11 N/A None
Power PLLs
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4.3.2.17 Test and Debug Modules Interface
Table 4-34. ZWT Test and Debug Modules Interface
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
337 TYPE
SIGNAL NAME STATE
ZWT
Test enable. This terminal
must be connected to ground
TEST U2 I/O Fixed 100 µA directly or via a pulldown
Pulldown Pulldown resistor.
nTRST D18 Input JTAG test hardware reset
RTCK A16 Output N/A None JTAG return test clock
Fixed 100 µA
TCK B18 Input Pulldown JTAG test clock
Pulldown
Fixed 100 µA
TDI A17 I/O Pullup JTAG test data in
Pullup
100 µA
TDO C18 Output None JTAG test data out
Pulldown
Fixed 100 µA
TMS C19 I/O Pullup JTAG test select
Pullup
4.3.2.18 Flash Supply and Test Pads
Table 4-35. ZWT Flash Supply and Test Pads
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
337 TYPE
SIGNAL NAME STATE
ZWT
3.3-V
VCCP F8 N/A None Flash pump supply
Power
FLTP1 J5 Flash test pads. These
terminals are reserved for TI
use only. For proper operation
– N/A None these terminals must connect
FLTP2 H5 only to a test pad or not be
connected at all [no connect
(NC)].
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4.3.2.19 No Connects
Table 4-36. No Connects
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
337 TYPE
SIGNAL NAME STATE
ZWT
NC D6 – N/A None
NC D7 – N/A None
NC D8 – N/A None
NC D9 – N/A None
NC D10 – N/A None
NC D11 – N/A None
NC D12 – N/A None
NC D13 – N/A None
NC E4 – N/A None
NC F4 – N/A None
NC G4 – N/A None
NC K4 – N/A None
NC K16 – N/A None
NC L4 – N/A None
NC L16 – N/A None
NC M4 – N/A None
NC M16 – N/A None
NC N4 – N/A None
NC N16 – N/A None No Connects. These balls are
NC N18 – N/A None not connected to any internal
logic and can be connected to
NC P4 – N/A None the PCB ground without
affecting the functionality of
NC P15 – N/A None the device.
NC P16 – N/A None
NC P17 – N/A None
NC R1 – N/A None
NC R14 – N/A None
NC R15 – N/A None
NC T2 – N/A None
NC T3 – N/A None
NC T4 – N/A None
NC T5 – N/A None
NC T6 – N/A None
NC T7 – N/A None
NC T8 – N/A None
NC T9 – N/A None
NC T10 – N/A None
NC T11 – N/A None
NC T13 – N/A None
NC T14 – N/A None
NC U3 – N/A None
NC U4 – N/A None
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Table 4-36. No Connects (continued)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
337 TYPE
SIGNAL NAME STATE
ZWT
NC U5 – N/A None No Connects. These balls are
not connected to any internal
NC U6 – N/A None logic and can be connected to
the PCB ground without
NC U7 – N/A None affecting the functionality of
NC U8 – N/A None the device.
NC U9 – N/A None
NC U10 – N/A None
NC U11 – N/A None
NC U12 – N/A None
NC V3 – N/A None
NC V4 – N/A None
NC V11 – N/A None
NC V12 – N/A None
NC W4 – N/A None
NC W11 – N/A None
NC W12 – N/A None
NC W13 – N/A None
4.3.2.20 Supply for Core Logic: 1.2-V Nominal
Table 4-37. ZWT Supply for Core Logic: 1.2-V Nominal
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
337 TYPE
SIGNAL NAME STATE
ZWT
VCC F9
VCC F10
VCC H10
VCC J14
VCC K6 1.2-V
VCC K8 N/A None Core supply
Power
VCC K12
VCC K14
VCC L6
VCC M10
VCC P10
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4.3.2.21 Supply for I/O Cells: 3.3-V Nominal
Table 4-38. ZWT Supply for I/O Cells: 3.3-V Nominal
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
337 TYPE
SIGNAL NAME STATE
ZWT
VCCIO F6
VCCIO F7
VCCIO F11
VCCIO F12
VCCIO F13
VCCIO F14
VCCIO G6
VCCIO G14
VCCIO H6
VCCIO H14
VCCIO J6 3.3-V
VCCIO L14 N/A None Operating supply for I/Os
Power
VCCIO M6
VCCIO M14
VCCIO N6
VCCIO N14
VCCIO P6
VCCIO P7
VCCIO P8
VCCIO P9
VCCIO P12
VCCIO P13
VCCIO P14
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4.3.2.22 Ground Reference for All Supplies Except VCCAD
Table 4-39. ZWT Ground Reference for All Supplies Except VCCAD
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
337 TYPE
SIGNAL NAME STATE
ZWT
VSS A1
VSS A2
VSS A18
VSS A19
VSS B1
VSS B19
VSS H8
VSS H9
VSS H11
VSS H12
VSS J8
VSS J9
VSS J10
VSS J11
VSS J12 Ground N/A None Ground reference
VSS K9
VSS K10
VSS K11
VSS L8
VSS L9
VSS L10
VSS L11
VSS L12
VSS M8
VSS M9
VSS M11
VSS M12
VSS V1
VSS W1
VSS W2
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5 Specifications
5.1 Absolute Maximum Ratings (1)
Over Operating Free-Air Temperature Range MIN MAX UNIT
VCC(2) –0.3 1.43
Supply voltage VCCIO, VCCP(2) –0.3 4.6 V
VCCAD –0.3 6.25
All input pins –0.3 4.6
Input voltage V
ADC input pins –0.3 6.25
IIK (VI< 0 or VI> VCCIO)–20 20
All pins, except AD1IN[23:0] and AD2IN[15:0] mA
Input clamp current IIK (VI< 0 or VI> VCCAD)–10 10
AD1IN[23:0] and AD2IN[15:0]
Total –40 40 mA
Operating free-air temperature, TA: –40 125 °C
Operating junction temperature, TJ: –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to their associated
grounds.
5.2 ESD Ratings
VALUE UNIT
Human body model (HBM), per AEC Q100-002(1) ±2 kV
All pins ±500
Electrostatic discharge Corner pins on 144-pin PGE
VESD Charged device model (CDM), ±750
(ESD) performance: (1, 36, 37, 72, 73, 108, 109, 144) V
per AEC Q100-011 Corner balls on 337-ball ZWT ±750
(A1, A19, W1, W19)
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS‑001 specification.
5.3 Power-On Hours (POH)(1)(2)
JUNCTION
NOMINAL CORE VOLTAGE (VCC) LIFETIME POH
TEMPERATURE (Tj)
1.2 105ºC 100K
(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms
and conditions for TI semiconductor products.
(2) To avoid significant degradation, the device power-on hours (POH) must be limited to those specified in this table. To convert to
equivalent POH for a specific temperature profile, see the Calculating Equivalent Power-on-Hours for Hercules Safety MCUs Application
Report (SPNA207).
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5.4 Recommended Operating Conditions(1)
MIN NOM MAX UNIT
VCC Digital logic supply voltage (Core) 1.14 1.2 1.32 V
VCCPLL PLL Supply Voltage 1.14 1.2 1.32 V
VCCIO Digital logic supply voltage (I/O) 3 3.3 3.6 V
VCCAD MibADC supply voltage 3 3.3/5.0 5.25 V
VCCP Flash pump supply voltage 3 3.3 3.6 V
VSS Digital logic supply ground 0 V
VSSAD MibADC supply ground –0.1 0.1 V
VADREFHI A-to-D high-voltage reference source VSSAD VCCAD V
VADREFLO A-to-D low-voltage reference source VSSAD VCCAD V
VSLEW Maximum positive slew rate for VCCIO, VCCAD and VCCP supplies 1 V/µs
TAOperating free-air temperature -40 125 °C
TJOperating junction temperature(2) -40 150 °C
(1) All voltages are with respect to VSS, except VCCAD, which is with respect to VSSAD
(2) Reliability data is based upon a temperature profile that is equivalent to 100,000 power-on hours at 105°C junction temperature.
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Address Wait States
Data Wait States
RAM
Address Wait States
Data Wait States
Flash
0MHz
0MHz
0MHz
0MHz
100MHz
0 1 3
0
0
0
150MHz
2
150MHz
1
fHCLK(max)
50MHz
fHCLK(max)
fHCLK(max)
fHCLK(max)
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5.5 Switching Characteristics for Clock Domains
Over Recommended Operating Conditions
Table 5-1. Clock Domain Timing Specifications
PARAMET DESCRIPTION CONDITIONS MIN MAX UNIT
ER
Pipeline mode enabled 160
PGE Pipeline mode disabled 50
fHCLK HCLK - System clock frequency MHz
Pipeline mode enabled 180
ZWT Pipeline mode disabled 50
fGCLK GCLK - CPU clock frequency fHCLK MHz
fVCLK VCLK - Primary peripheral clock frequency 100 MHz
VCLK2 - Secondary peripheral clock
fVCLK2 100 MHz
frequency
VCLK3 - Secondary peripheral clock
fVCLK3 100 MHz
frequency
VCLKA1 - Primary asynchronous peripheral
fVCLKA1 100 MHz
clock frequency
VCLKA2 - Secondary asynchronous
fVCLKA2 100 MHz
peripheral clock frequency
VCLKA4 - Secondary asynchronous
fVCLKA4 50 MHz
peripheral clock frequency
fRTICLK RTICLK - clock frequency fVCLK MHz
5.6 Wait States Required
Figure 5-1. Wait States Scheme
As shown in Figure 5-1, the TCM RAM can support program and data fetches at full CPU speed without any
address or data wait states required.
The TCM flash can support zero address and data wait states up to a CPU speed of 50 MHz in nonpipelined
mode. The flash supports a maximum CPU clock speed of 160 MHz in pipelined mode for the PGE Package and
180 MHz for the ZWT package, with one address wait state and three data wait states.
The flash wrapper defaults to nonpipelined mode with zero address wait state and one random-read data wait
state.
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5.7 Power Consumption
Over Recommended Operating Conditions
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fHCLK = 180 MHz
(ZWT Package only)
VCC Digital supply current (operating 220(1) 440(2)
mode) fVCLK = 90 MHz,
Flash in pipelined mode, VCCmax
LBIST clock rate = 90 MHz
VCC Digital supply current (LBIST mode) 700(3)(4)
(ZWT Package only)
PBIST ROM clock frequency = 90
ICC, ICCPLL mA
VCC Digital supply current (PBIST mode) MHz 700(3)(4)
(ZWT Package only)
fHCLK = 160 MHz
VCC Digital supply current (operating 200(1) 420(2)
fVCLK = 80 MHz,
mode) Flash in pipelined mode, VCCmax
VCC Digital supply current (LBIST mode) LBIST clock rate = 80 MHz 665(3)(4)
PBIST ROM clock
VCC Digital supply current (PBIST mode) 665(3)(4)
frequency = 80 MHz
ICCIO VCCIO supply current (operating mode) No DC load, VCCmax 10 mA
Single ADC operational, VCCADmax 15
ICCAD VCCAD supply current (operating mode) mA
Both ADCs operational, VCCADmax 30
Single ADC operational, ADREFHImax 3
IADREFHI ADREFHI supply current (operating mode) mA
Both ADCs operational, ADREFHImax 6
Read from 1 bank and program or
ICCP VCCP pump supply current 60 mA
erase another bank, VCCPmax
(1) The typical value is the average current for the nominal process corner and junction temperature of 25ºC.
(2) The maximum ICC, value can be derated
• linearly with voltage
• by 1 ma/MHz for lower operating frequency when fHCLK= 2 * fVCLK
• for lower junction temperature by the equation below where TJK is the junction temperature in Kelvin and the result is in milliamperes.
235 - 0.15 e0.0174 TJK
(3) The maximum ICC, value can be derated
• linearly with voltage
• by 1.7 ma/MHz for lower operating frequency when fHCLK= 2 * fVCLK
• for lower junction temperature by the equation below where TJK is the junction temperature in Kelvin and the result is in milliamperes.
235 - 0.15 e0.0174 TJK
(4) LBIST and PBIST currents are for a short duration, typically less than 10 ms. They are usually ignored for thermal calculations for the
device and the voltage regulator
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5.8 Input/Output Electrical Characteristics(1)
Over Recommended Operating Conditions
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
All inputs except
FRAYRX1, 180
FRAYRX2
Vhys Input hysteresis mV
FRAYRX1, 100
FRAYRX2
All inputs(2) (except
FRAYRX1, –0.3 0.8
FRAYRX2)
VIL Low-level input voltage V
FRAYRX1, 0.4 VCCIO
FRAYRX2
All inputs(2) (except
FRAYRX1, 2 VCCIO + 0.3
FRAYRX2)
VIH High-level input voltage V
FRAYRX1, 0.6 VCCIO
FRAYRX2 IOL = IOLmax 0.2 VCCIO
IOL = 50 µA, standard 0.2
output mode
VOL Low-level output voltage V
IOL = 50 µA, low-EMI
output mode (see 0.2 VCCIO
Section 5.13)
IOH = IOHmax 0.8 VCCIO
IOH = 50 µA, standard VCCIO – 0.3
output mode
VOH High-level output voltage V
IOH = 50 µA, low-EMI
output mode (see 0.8 VCCIO
Section 5.13)
VI< VSSIO - 0.3 or VI>
IIK Input clamp current (I/O pins) –3.5 3.5 mA
VCCIO + 0.3
IIH Pulldown 20 µA VI= VCCIO 5 40
IIH Pulldown 100 µA VI= VCCIO 40 195
IIInput current (I/O pins) IIL Pullup 20 µA VI= VSS –40 –5 µA
IIL Pullup 100 µA VI= VSS –195 –40
All other pins No pullup or pulldown –1 1
CIInput capacitance 2 pF
COOutput capacitance 3 pF
(1) Source currents (out of the device) are negative while sink currents (into the device) are positive.
(2) This does not apply to the nPORRST pin.
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5.9 Thermal Resistance Characteristics
Table 5-2 shows the thermal resistance characteristics for the QFP - PGE mechanical package.
Table 5-3 shows the thermal resistance characteristics for the BGA - ZWT mechanical package.
Table 5-2. Thermal Resistance Characteristics (PGE Package)
°C / W
Junction-to-free air thermal resistance, Still air using JEDEC 2S2P test
RΘJA 39
board
RΘJB Junction-to-board thermal resistance 26.3
RΘJC Junction-to-case thermal resistance 6.7
ΨJT Junction-to-package top, Still air 0.10
Table 5-3. Thermal Resistance Characteristics (ZWT Package)
°C / W
Junction-to-free air thermal resistance, Still air (includes 5x5 thermal via
RΘJA 18.8
cluster in 2s2p PCB connected to 1st ground plane)
RΘJB Junction-to-board thermal resistance 14.1
RΘJC Junction-to-case thermal resistance 7.1
Junction-to-package top, Still air (includes 5x5 thermal via cluster in 2s2p
ΨJT 0.33
PCB connected to 1st ground plane)
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5.10 Output Buffer Drive Strengths
Table 5-4. Output Buffer Drive Strengths
LOW-LEVEL OUTPUT CURRENT,
IOL for VI=VOLmax
or SIGNALS
HIGH-LEVEL OUTPUT CURRENT,
IOH for VI=VOHmin
FRAYTX2, FRAYTX1, FRAYTXEN1, FRAYTXEN2,
MIBSPI5CLK, MIBSPI5SOMI[0], MIBSPI5SOMI[1], MIBSPI5SOMI[2], MIBSPI5SOMI[3],
MIBSPI5SIMO[0], MIBSPI5SIMO[1], MIBSPI5SIMO[2], MIBSPI5SIMO[3],
8 mA TMS, TDI, TDO, RTCK,
SPI4CLK, SPI4SIMO, SPI4SOMI, nERROR,
N2HET2[1], N2HET2[3],
All EMIF Outputs and I/Os, All ETM Outputs
MIBSPI3SOMI, MIBSPI3SIMO, MIBSPI3CLK, MIBSPI1SIMO, MIBSPI1SOMI, MIBSPI1CLK,
4 mA nRST
AD1EVT,
CAN1RX, CAN1TX, CAN2RX, CAN2TX, CAN3RX, CAN3TX,
DMM_CLK, DMM_DATA[0], DMM_DATA[1], DMM_nENA, DMM_SYNC,
GIOA[0-7], GIOB[0-7],
LINRX, LINTX,
2 mA zero-dominant MIBSPI1NCS[0], MIBSPI1NCS[1-3], MIBSPI1NENA, MIBSPI3NCS[0-3], MIBSPI3NENA,
MIBSPI5NCS[0-3], MIBSPI5NENA,
N2HET1[0-31], N2HET2[0], N2HET2[2], N2HET2[4], N2HET2[5], N2HET2[6], N2HET2[7],
N2HET2[8], N2HET2[9], N2HET2[10], N2HET2[11], N2HET2[12], N2HET2[13], N2HET2[14],
N2HET2[15], N2HET2[16], N2HET2[18],
SPI2NCS[0], SPI2NENA, SPI4NCS[0], SPI4NENA
ECLK,
selectable 8 mA/2 mA SPI2CLK, SPI2SIMO, SPI2SOMI
The default output buffer drive strength is 8mA for these signals.
Table 5-5. Selectable 8 mA/2 mA Control
SIGNAL CONTROL BIT ADDRESS 8 mA 2 mA
ECLK SYSPC10[0] 0xFFFF FF78 0 1
SPI2CLK SPI2PC9[9](1) 0xFFF7 F668 0 1
SPI2SIMO SPI2PC9[10](1) 0xFFF7 F668 0 1
SPI2SOMI SPI2PC9[11](1) 0xFFF7 F668 0 1
(1) Either SPI2PC9[11] or SPI2PC9[24] can change the output strength of the SPI2SOMI pin. In case of a 32-bit write where these two bits
differ, SPI2PC9[11] determines the drive strength.
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VCCIO
VIH VIH
VIL 0
Input
tpw
VIL
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5.11 Input Timings
Figure 5-2. TTL-Level Inputs
Table 5-6. Timing Requirements for Inputs(1)
MIN MAX UNIT
tpw Input minimum pulse width tc(VCLK) + 10(2) ns
(1) tc(VCLK) = peripheral VBUS clock cycle time = 1 / f(VCLK)
(2) The timing shown in Figure 5-2 is only valid for pins used in GPIO mode.
5.12 Output Timings
Table 5-7. Switching Characteristics for Output Timings versus Load Capacitance (CL)
PARAMETER MIN MAX UNIT
CL = 15 pF 2.5
CL = 50 pF 4
Rise time, trns
CL = 100 pF 7.2
CL = 150 pF 12.5
8 mA low EMI pins
(see Table 5-4)CL = 15 pF 2.5
CL = 50 pF 4
Fall time, tfns
CL = 100 pF 7.2
CL = 150 pF 12.5
CL = 15 pF 5.6
CL = 50 pF 10.4
Rise time, trns
CL = 100 pF 16.8
CL = 150 pF 23.2
4 mA low EMI pins
(see Table 5-4)CL = 15 pF 5.6
CL= 50 pF 10.4
Fall time, tfns
CL = 100 pF 16.8
CL = 150 pF 23.2
2 mA-z low EMI pins CL = 15 pF 8
(see Table 5-4)CL = 50 pF 15
Rise time, trns
CL = 100 pF 23
CL = 150 pF 33
CL = 15 pF 8
CL = 50 pF 15
Fall time, tfns
CL = 100 pF 23
CL = 150 pF 33
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tf
tr
VCCIO
VOH VOH
VOL VOL 0
Output
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Table 5-7. Switching Characteristics for Output Timings versus Load Capacitance (CL) (continued)
PARAMETER MIN MAX UNIT
CL = 15 pF 2.5 ns
CL = 50 pF 4
Rise time, trCL = 100 pF 7.2
CL = 150 pF 12.5
8 mA mode CL = 15 pF 2.5 ns
CL = 50 pF 4
Fall time, tfCL = 100 pF 7.2
Selectable 8 mA/2 mA-z CL = 150 pF 12.5
pins CL = 15 pF 8 ns
(see Table 5-4)CL = 50 pF 15
Rise time, trCL = 100 pF 23
CL = 150 pF 33
2 mA-z mode CL = 15 pF 8 ns
CL = 50 pF 15
Fall time, tfCL = 100 pF 23
CL = 150 pF 33
Figure 5-3. CMOS-Level Outputs
Table 5-8. Timing Requirements for Outputs(1)
MIN MAX UNIT
Delay between low to high, or high to low transition of general-purpose output signals
td(parallel_out) that can be configured by an application in parallel, for example, all signals in a 5 ns
GIOA port, or all N2HET1 signals, and so forth.
(1) This specification does not account for any output buffer drive strength differences or any external capacitive loading differences. Check
Table 5-4 for output buffer drive strength information on each signal.
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5.13 Low-EMI Output Buffers
The low-EMI output buffer has been designed explicitly to address the issue of decoupling sources of
emissions from the pins which they drive. This is accomplished by adaptively controlling the impedance of
the output buffer, and is particularly effective with capacitive loads.
This is not the default mode of operation of the low-EMI output buffers and must be enabled by setting the
system module GPCR1 register for the desired module or signal, as shown in Table 5-9. The adaptive
impedance control circuit monitors the DC bias point of the output signal. The buffer internally generates
two reference levels, VREFLOW and VREFHIGH, which are set to approximately 10% and 90% of
VCCIO, respectively.
Once the output buffer has driven the output to a low level, if the output voltage is below VREFLOW, then
the impedance of the output buffer will increase to Hi-Z. A high degree of decoupling between the internal
ground bus and the output pin will occur with capacitive loads, or any load in which no current is flowing,
for example, the buffer is driving low on a resistive path to ground. Current loads on the buffer which
attempt to pull the output voltage above VREFLOW will be opposed by the impedance of the output buffer
so as to maintain the output voltage at or below VREFLOW.
Conversely, once the output buffer has driven the output to a high level, if the output voltage is above
VREFHIGH then the output buffer’s impedance will again increase to Hi-Z. A high degree of decoupling
between internal power bus ad output pin will occur with capacitive loads or any loads in which no current
is flowing, for example, buffer is driving high on a resistive path to VCCIO. Current loads on the buffer
which attempt to pull the output voltage below VREFHIGH will be opposed by the buffer’s output
impedance so as to maintain the output voltage at or above VREFHIGH.
The bandwidth of the control circuitry is relatively low, so that the output buffer in adaptive impedance
control mode cannot respond to high-frequency noise coupling into the power buses of the buffer. In this
manner, internal bus noise approaching 20% peak-to-peak of VCCIO can be rejected.
Unlike standard output buffers which clamp to the rails, an output buffer in impedance control mode will
allow a positive current load to pull the output voltage up to VCCIO + 0.6 V without opposition. Also, a
negative current load will pull the output voltage down to VSSIO – 0.6 V without opposition. This is not an
issue because the actual clamp current capability is always greater than the IOH / IOL specifications.
The low-EMI output buffers are automatically configured to be in the standard buffer mode when the
device enters a low-power mode.
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Table 5-9. Low-EMI Output Buffer Hookup
CONTROL REGISTER TO
MODULE OR SIGNAL NAME ENABLE LOW-EMI MODE
Module: MibSPI1 GPREG1.0
Module: SPI2 GPREG1.1
Module: MibSPI3 GPREG1.2
Reserved GPREG1.3
Module: MibSPI5 GPREG1.4
Module: FlexRay GPREG1.5
Module: EMIF GPREG1.6
Module: ETM GPREG1.7
Signal: TMS GPREG1.8
Signal: TDI GPREG1.9
Signal: TDO GPREG1.10
Signal: RTCK GPREG1.11
Signal: TEST GPREG1.12
Signal: nERROR GPREG1.13
Reserved GPREG1.14
Module: RTP GPREG1.15
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6 System Information and Electrical Specifications
6.1 Device Power Domains
The device core logic is split up into multiple power domains in order to optimize the power for a given
application use case. There are 8 core power domains in total: PD1, PD2, PD3, PD4, PD5, RAM_PD1,
RAM_PD2 and RAM_PD3.
The actual contents of these power domains are indicated in Section 1.4.
PD1 is an "always-ON" power domain, which cannot be turned off. Each of the other core power domains
can be turned ON/OFF one time during device initialization as per the application requirement. Refer to
the Power Management Module (PMM) chapter of TMS570LS31X/21X Technical Reference Manual
(SPNU499) for more details.
NOTE
The clocks to a module must be turned off before powering down the core domain that
contains the module.
NOTE
The logic in the modules that are powered down lose power completely. Any access to
modules that are powered down results in an abort being generated. When power is
restored, the modules power-up to their default states (after normal power-up). No register or
memory contents are preserved in the core domains that are turned off.
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6.2 Voltage Monitor Characteristics
A voltage monitor is implemented on this device. The purpose of this voltage monitor is to eliminate the
requirement for a specific sequence when powering up the core and I/O voltage supplies.
6.2.1 Important Considerations
• The voltage monitor does not eliminate the need of a voltage supervisor circuit to guarantee that the
device is held in reset when the voltage supplies are out of range.
• The voltage monitor only monitors the core supply (VCC) and the I/O supply (VCCIO). The other
supplies are not monitored by the VMON. For example, if the VCCAD or VCCP are supplied from a
source different from that for VCCIO, then there is no internal voltage monitor for the VCCAD and
VCCP supplies.
6.2.2 Voltage Monitor Operation
The voltage monitor generates the Power Good MCU signal (PGMCU) as well as the I/Os Power Good IO
signal (PGIO) on the device. During power-up or power-down, the PGMCU and PGIO are driven low when
the core or I/O supplies are lower than the specified minimum monitoring thresholds. The PGIO and
PGMCU being low isolates the core logic as well as the I/O controls during the power-up or power-down
of the supplies. This allows the core and I/O supplies to be powered up or down in any order.
When the voltage monitor detects a low voltage on the I/O supply, it will assert a power-on reset. When
the voltage monitor detects an out-of-range voltage on the core supply, it asynchronously makes all output
pins high impedance, and asserts a power-on reset. The voltage monitor is disabled when the device
enters a low power mode.
The VMON also incorporates a glitch filter for the nPORRST input. Refer to Section 6.3.3.1 for the timing
information on this glitch filter.
Table 6-1. Voltage Monitoring Specifications
PARAMETER MIN TYP MAX UNIT
VCC low - VCC level below this threshold is detected as too 0.75 0.9 1.13
low.
Voltage monitoring VCC high - VCC level above this threshold is detected as
VMON 1.40 1.7 2.1 V
thresholds too high.
VCCIO low - VCCIO level below this threshold is detected 1.85 2.4 2.9
as too low.
6.2.3 Supply Filtering
The VMON has the capability to filter glitches on the VCC and VCCIO supplies.
Table 6-2 shows the characteristics of the supply filtering. Glitches in the supply larger than the maximum
specification cannot be filtered.
Table 6-2. VMON Supply Glitch Filtering Capability
PARAMETER MIN MAX UNIT
Width of glitch on VCC that can be filtered 250 1000 ns
Width of glitch on VCCIO that can be filtered 250 1000 ns
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6.3 Power Sequencing and Power On Reset
6.3.1 Power-Up Sequence
There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage. The power-
up sequence starts with the I/O voltage rising above the minimum I/O supply threshold, (see Table 6-4 for
more details), core voltage rising above the minimum core supply threshold and the release of power-on
reset. The high frequency oscillator will start up first and its amplitude will grow to an acceptable level. The
oscillator start up time is dependent on the type of oscillator and is provided by the oscillator vendor. The
different supplies to the device can be powered up in any order.
The device goes through the following sequential phases during power up.
Table 6-3. Power-Up Phases
Oscillator startup and validity check 1032 oscillator cycles
eFuse autoload 1180 oscillator cycles
Flash pump power-up 688 oscillator cycles
Flash bank power-up 617 oscillator cycles
Total 3517 oscillator cycles
The CPU reset is released at the end of the sequence in Table 6-3 and fetches the first instruction from
address 0x00000000.
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3.3 V VCCIOPORH
1.2 V VCCPORH
VCCIOPORL
V (1.2 V)
V / V (3.3 V)
CC
CCIO CCP
nPORRST
8
66
7
7
93
VCCPORL
VIL(PORRST)
V / V
CCIO CCP
VCC
VCCPORL
VIL(PORRST)
VIL VIL VIL
VCCIOPORH
VCCPORH
VCCIOPORL
NOTE: There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage; this is just an exemplary drawing.
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6.3.2 Power-Down Sequence
The different supplies to the device can be powered down in any order.
6.3.3 Power-On Reset: nPORRST
This is the power-on reset. This reset must be asserted by an external circuitry whenever the I/O or core
supplies are outside the specified recommended range. This signal has a glitch filter on it. It also has an
internal pulldown.
6.3.3.1 nPORRST Electrical and Timing Requirements
Table 6-4. Electrical Requirements for nPORRST
NO. PARAMETER MIN MAX UNIT
VCCPORL VCC low supply level when nPORRST must be active during power-up 0.5 V
VCC high supply level when nPORRST must remain active during power-
VCCPORH 1.14 V
up and become active during power down
VCCIO / VCCP low supply level when nPORRST must be active during
VCCIOPORL 1.1 V
power-up
VCCIO / VCCP high supply level when nPORRST must remain active
VCCIOPORH 3.0 V
during power-up and become active during power down
VIL(PORRST) Low-level input voltage of nPORRST VCCIO > 2.5V 0.2 * VCCIO V
Low-level input voltage of nPORRST VCCIO < 2.5V 0.5 V
Setup time, nPORRST active before VCCIO and VCCP > VCCIOPORL during
3 tsu(PORRST) 0 ms
power-up
6 th(PORRST) Hold time, nPORRST active after VCC > VCCPORH 1 ms
7 tsu(PORRST) Setup time, nPORRST active before VCC < VCCPORH during power down 2 µs
8 th(PORRST) Hold time, nPORRST active after VCCIO and VCCP > VCCIOPORH 1 ms
9 th(PORRST) Hold time, nPORRST active after VCC < VCCPORL 0 ms
Filter time nPORRST pin;
tf(nPORRST) 500 2000 ns
pulses less than MIN will be filtered out, pulses greater than MAX will
generate a reset.
Figure 6-1. nPORRST Timing Diagram
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6.4 Warm Reset (nRST)
This is a bidirectional reset signal. The internal circuitry drives the signal low on detecting any device reset
condition. An external circuit can assert a device reset by forcing the signal low. On this terminal, the
output buffer is implemented as an open drain (drives low only). To ensure an external reset is not
arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal.
This terminal has a glitch filter. It also has an internal pullup
6.4.1 Causes of Warm Reset
Table 6-5. Causes of Warm Reset
DEVICE EVENT SYSTEM STATUS FLAG
Power-Up Reset Exception Status Register, bit 15
Oscillator fail Global Status Register, bit 0
PLL slip Global Status Register, bits 8 and 9
Watchdog exception / Debugger reset Exception Status Register, bit 13
CPU Reset (driven by the CPU STC) Exception Status Register, bit 5
Software Reset Exception Status Register, bit 4
External Reset Exception Status Register, bit 3
6.4.2 nRST Timing Requirements
Table 6-6. nRST Timing Requirements
MIN MAX UNIT
tv(RST) Valid time, nRST active after nPORRST inactive 2256tc(OSC)(1) ns
Valid time, nRST active (all other System reset conditions) 32tc(VCLK)
tf(nRST) Filter time nRST pin; pulses less than MIN will be filtered out; pulses greater 475 2000 ns
than MAX will generate a reset. See Section 6.8.
(1) Assumes the oscillator has started up and stabilized before nPORRST is released .
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North Flip West
F
F
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6.5 ARM-R4F CPU Information
6.5.1 Summary of ARM Cortex-R4F CPU Features
The features of the ARM Cortex-R4F CPU include:
• An integer unit with integral EmbeddedICE-RT logic.
• High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible Interfaces (AXI)
for Level two (L2) master and slave interfaces.
• Floating Point Coprocessor
• Dynamic branch prediction with a global history buffer, and a 4-entry return stack
• Low interrupt latency.
• Nonmaskable interrupt.
• A Harvard Level one (L1) memory system with:
– Tightly-Coupled Memory (TCM) interfaces with support for error correction or parity checking
memories
– ARMv7-R architecture Memory Protection Unit (MPU) with 12 regions
• Dual core logic for fault detection in safety-critical applications.
• An L2 memory interface:
– Single 64-bit master AXI interface
– 64-bit slave AXI interface to TCM RAM blocks
• A debug interface to a CoreSight Debug Access Port (DAP).
• A trace interface to a CoreSight ETM-R4.
• A Performance Monitoring Unit (PMU).
• A Vectored Interrupt Controller (VIC) port.
For more information on the ARM Cortex-R4F CPU see www.arm.com.
6.5.2 ARM Cortex-R4F CPU Features Enabled by Software
The following CPU features are disabled on reset and must be enabled by the application if required.
• ECC On Tightly-Coupled Memory (TCM) Accesses
• Hardware Vectored Interrupt (VIC) Port
• Floating Point Coprocessor
• Memory Protection Unit (MPU)
6.5.3 Dual Core Implementation
The device has two Cortex-R4F cores, where the output signals of both CPUs are compared in the CCM-
R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed by two
clock cycles as shown in Figure 6-3.
The CPUs have a diverse CPU placement given by following requirements:
• different orientation; for example, CPU1 = "north" orientation, CPU2 = "flip west" orientation
• dedicated guard ring for each CPU
Figure 6-2. Dual-CPU Orientation
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CPU 1 CPU 2
2cycledelay
2cycledelay
CCM-R4
CCM-R4
compare
CPU1CLK
CPU2CLK
compare
error
Input+Control
Output+Control
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6.5.4 Duplicate Clock Tree After GCLK
The CPU clock domain is split into two clock trees, one for each CPU, with the clock of the second CPU
running at the same frequency and in phase to the clock of CPU1. See Figure 6-3.
6.5.5 ARM Cortex-R4F CPU Compare Module (CCM-R4) for Safety
This device has two ARM Cortex-R4F CPU cores, where the output signals of both CPUs are compared in
the CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed in
a different way as shown in Figure 6-3.
Figure 6-3. Dual Core Implementation
To avoid an erroneous CCM-R4 compare error, the application software must initialize the registers of
both CPUs before the registers are used, including function calls where the register values are pushed
onto the stack.
6.5.6 CPU Self-Test
The CPU STC (Self-Test Controller) is used to test the two Cortex-R4F CPU Cores using the
Deterministic Logic BIST Controller as the test engine.
The main features of the self-test controller are:
• Ability to divide the complete test run into independent test intervals
• Capable of running the complete test as well as running few intervals at a time
• Ability to continue from the last executed interval (test set) as well as ability to restart from the
beginning (First test set)
• Complete isolation of the self-tested CPU core from rest of the system during the self-test run
• Ability to capture the Failure interval number
• Time-out counter for the CPU self-test run as a fail-safe feature
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6.5.6.1 Application Sequence for CPU Self-Test
1. Configure clock domain frequencies.
2. Select number of test intervals to be run.
3. Configure the time-out period for the self-test run.
4. Enable self-test.
5. Wait for CPU reset.
6. In the reset handler, read CPU self-test status to identify any failures.
7. Retrieve CPU state if required.
For more information see the device specific technical reference manual.
6.5.6.2 CPU Self-Test Clock Configuration
The maximum clock rate for the self-test is 90MHz. The STCCLK is divided down from the CPU clock.
This divider is configured by the STCCLKDIV register at address 0xFFFFE108.
For more information see the device specific technical reference manual.
6.5.6.3 CPU Self-Test Coverage
Table 6-7 shows CPU test coverage achieved for each self-test interval. It also lists the cumulative test
cycles. The test time can be calculated by multiplying the number of test cycles with the STC clock period.
Table 6-7. CPU Self-Test Coverage
INTERVALS TEST COVERAGE, % TEST CYCLES
000
1 62.13 1365
2 70.09 2730
3 74.49 4095
4 77.28 5460
5 79.28 6825
6 80.90 8190
7 82.02 9555
8 83.10 10920
9 84.08 12285
10 84.87 13650
11 85.59 15015
12 86.11 16380
13 86.67 17745
14 87.16 19110
15 87.61 20475
16 87.98 21840
17 88.38 23205
18 88.69 24570
19 88.98 25935
20 89.28 27300
21 89.50 28665
22 89.76 30030
23 90.01 31395
24 90.21 32760
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OSCIN OSCOUT
C1
(see Note A)
C2
Crystal
(a)
OSCIN OSCOUT
(b)
External
(toggling 0 V to 3.3 V)
Clock Signal
Note A: The values of C1 and C2 should be provided by the resonator/crystal vendor.
Kelvin_GND
Note B: Kelvin_GND should not be connected to any other GND.
(see Note B)
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6.6 Clocks
6.6.1 Clock Sources
Table 6-8 lists the available clock sources on the device. Each of the clock sources can be enabled or
disabled using the CSDISx registers in the system module. The clock source number in the table
corresponds to the control bit in the CSDISx register for that clock source.
Table 6-8 also shows the default state of each clock source.
Table 6-8. Available Clock Sources
CLOCK DEFAULT
NAME DESCRIPTION
SOURCE # STATE
0 OSCIN Main Oscillator Enabled
1 PLL1 Output From PLL1 Disabled
2 Reserved Reserved Disabled
3 EXTCLKIN1 External Clock Input #1 Disabled
4 CLK80K Low Frequency Output of Internal Reference Oscillator Enabled
5 CLK10M High Frequency Output of Internal Reference Oscillator Enabled
6 PLL2 Output From PLL2 Disabled
7 EXTCLKIN2 External Clock Input #2 Disabled
6.6.1.1 Main Oscillator
The oscillator is enabled by connecting the appropriate fundamental resonator/crystal and load capacitors
across the external OSCIN and OSCOUT pins as shown in Figure 6-4. The oscillator is a single stage
inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test
measurement and low power modes.
TI strongly encourages each customer to submit samples of the device to the resonator/crystal
vendors for validation. The vendors are equipped to determine what load capacitors will best tune
their resonator/crystal to the microcontroller device for optimum startup and operation over
temperature/voltage extremes.
An external oscillator source can be used by connecting a 3.3-V clock signal to the OSCIN pin and leaving
the OSCOUT pin unconnected (open) as shown in Figure 6-4.
Figure 6-4. Recommended Crystal/Clock Connection
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6.6.1.1.1 Timing Requirements for Main Oscillator
Table 6-9. Timing Requirements for Main Oscillator
MIN MAX UNIT
tc(OSC) Cycle time, OSCIN (when using a sine-wave input) 50 200 ns
tc(OSC_SQR) Cycle time, OSCIN, (when input to the OSCIN is a square wave ) 50 200 ns
tw(OSCIL) Pulse duration, OSCIN low (when input to the OSCIN is a square wave) 6 ns
tw(OSCIH) Pulse duration, OSCIN high (when input to the OSCIN is a square wave) 6 ns
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BIAS_EN
Low
Power
Oscillator
LFEN
LF_TRIM
HFEN
HF_TRIM
CLK80K
CLK10M
CLK10M_VALID
nPORRST
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6.6.1.2 Low Power Oscillator
The Low Power Oscillator (LPO) is comprised of two oscillators — HF LPO and LF LPO, in a single
macro.
6.6.1.2.1 Features
The main features of the LPO are:
• Supplies a clock at extremely low power for power-saving modes. This is connected as clock source #
4 of the Global Clock Module.
• Supplies a high-frequency clock for nontiming-critical systems. This is connected as clock source # 5
of the Global Clock Module.
• Provides a comparison clock for the crystal oscillator failure detection circuit.
Figure 6-5. LPO Block Diagram
Figure 6-5 shows a block diagram of the internal reference oscillator. This is a low power oscillator (LPO)
and provides two clock sources: one nominally 80 kHz and one nominally 10 MHz.
6.6.1.2.2 LPO Electrical and Timing Specifications
Table 6-10. LPO Specifications
PARAMETER MIN TYP MAX UNIT
Oscillator fail frequency - lower threshold, using 1.375 2.4 4.875 MHz
untrimmed LPO output
Clock Detection Oscillator fail frequency - higher threshold, using 22 38.4 78 MHz
untrimmed LPO output
Untrimmed frequency 5.5 9 19.5 MHz
Trimmed frequency 8 9.6 11 MHz
LPO - HF oscillator Startup time from STANDBY (LPO BIAS_EN High for
(fHFLPO)10 µs
at least 900µs)
Cold startup time 900 µs
Untrimmed frequency 36 85 180 kHz
LPO - LF oscillator Startup time from STANDBY (LPO BIAS_EN High for 100 µs
(fLFLPO) at least 900µs)
cold startup time 2000 µs
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/NR
/1 to /64
OSCIN
PLL
INTCLK /OD
/1 to /8
VCOCLK /R
/1 to /32
post_ODCLK
/NF
/1 to /256
PLLCLK
/NR2
/1 to /64
OSCIN
PLL#2
INTCLK2 /OD2
/1 to /8
VCOCLK2 /R2
/1 to /32
post_ODCLK2
/NF2
/1 to /256
PLL2CLK
fPLLCLK = (fOSCIN / NR) * NF / (OD * R)
fPLL2CLK = (fOSCIN / NR2) * NF2 / (OD2 * R2)
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6.6.1.3 Phase Locked Loop (PLL) Clock Modules
The PLL is used to multiply the input frequency to some higher frequency.
The main features of the PLL are:
• Frequency modulation can be optionally superimposed on the synthesized frequency of PLL1. The
frequency modulation capability of PLL2 is permanently disabled.
• Configurable frequency multipliers and dividers.
• Built-in PLL Slip monitoring circuit.
• Option to reset the device on a PLL slip detection.
6.6.1.3.1 Block Diagram
Figure 6-6 shows a high-level block diagram of the two PLL macros on this microcontroller. PLLCTL1 and
PLLCTL2 are used to configure the multiplier and dividers for the PLL1. PLLCTL3 is used to configure the
multiplier and dividers for PLL2.
Figure 6-6. ZWT PLLx Block Diagram
6.6.1.3.2 PLL Timing Specifications
Table 6-11. PLL Timing Specifications
PARAMETER MIN MAX UNIT
fINTCLK PLL1 Reference Clock frequency 1 20 MHz
fpost_ODCLK Post-ODCLK – PLL1 Post-divider input clock frequency 400 MHz
fVCOCLK VCOCLK – PLL1 Output Divider (OD) input clock frequency 150 550 MHz
fINTCLK2 PLL2 Reference Clock frequency 1 20 MHz
fpost_ODCLK2 Post-ODCLK – PLL2 Post-divider input clock frequency 400 MHz
fVCOCLK2 VCOCLK – PLL2 Output Divider (OD) input clock frequency 150 550 MHz
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6.6.1.4 External Clock Inputs
The device supports up to two external clock inputs. This clock input must be a square wave input. The
electrical and timing requirements for these clock inputs are specified in Table 6-12. The external clock
sources are not checked for validity. They are assumed valid when enabled.
Table 6-12. External Clock Timing and Electrical Specifications
PARAMETER DESCRIPTION MIN MAX UNIT
fEXTCLKx External clock input frequency 80 MHz
tw(EXTCLKIN)H EXTCLK high-pulse duration 6 ns
tw(EXTCLKIN)L EXTCLK low-pulse duration 6 ns
viL(EXTCLKIN) Low-level input voltage -0.3 0.8 V
viH(EXTCLKIN) High-level input voltage 2 VCCIO + 0.3 V
6.6.2 Clock Domains
6.6.2.1 Clock Domain Descriptions
Table 6-13 lists the device clock domains and their default clock sources. The table also shows the
system module control register that is used to select an available clock source for each clock domain.
Table 6-13. Clock Domain Descriptions
CLOCK SOURCE
CLOCK DOMAIN DEFAULT CLOCK SELECTION DESCRIPTION
NAME SOURCE REGISTER
HCLK OSCIN GHVSRC • Is disabled via the CDDISx registers bit 1
• Used for all system modules including DMA, ESM
GCLK OSCIN GHVSRC • Always the same frequency as HCLK
• In phase with HCLK
• Is disabled separately from HCLK via the CDDISx registers bit 0
• Can be divided by 1up to 8 when running CPU self-test (LBIST)
using the CLKDIV field of the STCCLKDIV register at address
0xFFFFE108
GCLK2 OSCIN GHVSRC • Always the same frequency as GCLK
• 2 cycles delayed from GCLK
• Is disabled along with GCLK
• Gets divided by the same divider setting as that for GCLK when
running CPU self-test (LBIST)
VCLK OSCIN GHVSRC • Divided down from HCLK
• Can be HCLK/1, HCLK/2, ... or HCLK/16
• Is disabled separately from HCLK via the CDDISx registers bit 2
VCLK2 OSCIN GHVSRC • Divided down from HCLK
• Can be HCLK/1, HCLK/2, ... or HCLK/16
• Frequency must be an integer multiple of VCLK frequency
• Is disabled separately from HCLK via the CDDISx registers bit 3
VCLK3 OSCIN GHVSRC • Divided down from HCLK
• Can be HCLK/1, HCLK/2, ... or HCLK/16
• Is disabled separately from HCLK via the CDDISx registers bit 8
VCLKA1 VCLK VCLKASRC • Defaults to VCLK as the source
• Is disabled via the CDDISx registers bit 4
VCLKA2 VCLK VCLKASRC • Defaults to VCLK as the source
• Is disabled via the CDDISx registers bit 5
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Table 6-13. Clock Domain Descriptions (continued)
CLOCK SOURCE
CLOCK DOMAIN DEFAULT CLOCK SELECTION DESCRIPTION
NAME SOURCE REGISTER
VCLKA3 VCLK VCLKACON1 • Defaults to VCLK as the source
• Frequency can be as fast as HCLK frequency.
• Is disabled via the CDDISx registers bit 10
VCLKA3_DIVR VCLK VCLKACON1 • Divided down from the VCLKA3 using the VCLKA3R field of the
VCLKACON1 register at address 0xFFFFE140
• Frequency can be VCLKA3/1, VCLKA3/2, ..., or VCLKA3/8
• Default frequency is VCLKA3/2
• Is disabled separately via the VCLKACON1 register
VCLKA3_DIV_CDDIS bit only if the VCLKA3 clock is not
disabled
VCLKA4 VCLK VCLKACON1 • Defaults to VCLK as the source
• Is disabled via the CDDISx registers bit 11
RTICLK VCLK RCLKSRC • Defaults to VCLK as the source
• If a clock source other than VCLK is selected for RTICLK, then
the RTICLK frequency must be less than or equal to VCLK/3
– Application can ensure this by programming the RTI1DIV
field of the RCLKSRC register, if necessary
• Is disabled via the CDDISx registers bit 6
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HCLK (to SYSTEM)
GCLK, GCLK2 (to CPU)
GCM
VCLK_peri (VCLK to peripherals on PCR1)
VCLKA1 (to DCANx)
0
/1..16
/1..16
RTICLK (to RTI, DWWD)
/1, 2, 4, or 8
VCLK
OSCIN
Low Power
Oscillator 10MHz
80kHz
FMzPLL
1
0
4
5
/1..64 X1..256 /1..8 /1..32
6
PLL # 2
*
VCLK
/1,2,..1024
Phase_seg2
CAN Baud Rate
Phase_seg1
VCLKA1
/1,2,..256
SPIx,MibSPIx
/2,3..224
LIN, SCI
SPI LIN / SCI
/1,2..32
MibADCx
ADCLK
/1,2..65536
External Clock
ECLK
VCLK2
N2HETx
HRP
/1..64
LRP
/20..25
Loop
Resolution Clock
High
Baud Rate Baud Rate
N2HETx
TU
VCLK2
(SSPLL)
(SSPLL)
/1..64 X1..256 /1..8 /1..32 *
1
4
5
6
VCLK
EXTCLKIN1
EXTCLKIN2
3
7
3
7
0
1
4
5
6
3
7
VCLK3
EMIF
VCLK3 (to EMIF)
/1..16
VCLK_sys (VCLK to system modules)
* the frequency at this node must not
exceed the maximum HCLK specifiation.
/1,2..256
I2C
I2C baud
rate
VCLKA2 (to FlexRay)
0
1
4
5
6
VCLK
3
7
/1,2,..4
VCLKA2
GTUC1,2
NTU[1]
NTU[0]
NTU[2]
NTU[3]
RTI
Macro Tick
Start of cycle
PLL#2 output
EXTCLKIN1
VCLKA2
Prop_seg
DCANx
FlexRay
Baud
Rate
FlexRay
TU
FlexRay
VCLK2 (to N2HETx and HTUx)
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6.6.2.2 Mapping of Clock Domains to Device Modules
Each clock domain has a dedicated functionality as shown in Figure 6-7.
Figure 6-7. Device Clock Domains
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6.6.3 Clock Test Mode
The TMS570 platform architecture defines a special mode that allows various clock signals to be brought
out on to the ECLK pin and N2HET1[12] device outputs. This mode is called the Clock Test mode. It is
very useful for debugging purposes and can be configured via the CLKTEST register in the system
module.
Table 6-14. Clock Test Mode Options
SEL_ECP_PIN SEL_GIO_PIN
= SIGNAL ON ECLK = SIGNAL ON N2HET1[12]
CLKTEST[3-0] CLKTEST[11-8]
0000 Oscillator 0000 Oscillator Valid Status
0001 Main PLL free-running clock output 0001 Main PLL Valid status
0010 Reserved 0010 Reserved
0011 EXTCLKIN1 0011 Reserved
0100 CLK80K 0100 Reserved
0101 CLK10M 0101 CLK10M Valid status
0110 Secondary PLL free-running clock output 0110 Secondary PLL Valid Status
0111 EXTCLKIN2 0111 Reserved
1000 GCLK 1000 CLK80K
1001 RTI Base 1001 Reserved
1010 Reserved 1010 Reserved
1011 VCLKA1 1011 Reserved
1100 VCLKA2 1100 Reserved
1101 Reserved 1101 Reserved
1110 VCLKA4 1110 Reserved
1111 Reserved 1111 Reserved
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f[MHz]
1.375 4.875 22 78
fail lower
threshold pass upper
threshold fail
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6.7 Clock Monitoring
The LPO Clock Detect (LPOCLKDET) module consists of a clock monitor (CLKDET) and an internal low
power oscillator (LPO).
The LPO provides two different clock sources – a low frequency (LFLPO) and a high frequency (HFLPO).
The CLKDET is a supervisor circuit for an externally supplied clock signal (OSCIN). In case the OSCIN
frequency falls out of a frequency window, the CLKDET flags this condition in the global status register
(GLBSTAT bit 0: OSC FAIL) and switches all clock domains sourced by OSCIN to the HFLPO clock (limp
mode clock).
The valid OSCIN frequency range is defined as: fHFLPO / 4 < fOSCIN < fHFLPO * 4.
6.7.1 Clock Monitor Timings
For more information on LPO and Clock detection, refer to Table 6-10.
Figure 6-8. LPO and Clock Detection, Untrimmed HFLPO
6.7.2 External Clock (ECLK) Output Functionality
The ECLK pin can be configured to output a prescaled clock signal indicative of an internal device clock.
This output can be externally monitored as a safety diagnostic.
6.7.3 Dual Clock Comparators
The Dual Clock Comparator (DCC) module determines the accuracy of selectable clock sources by
counting the pulses of two independent clock sources (counter 0 and counter 1). If one clock is out of
spec, an error signal is generated. For example, the DCC1 can be configured to use CLK10M as the
reference clock (for counter 0) and VCLK as the "clock under test" (for counter 1). This configuration
allows the DCC1 to monitor the PLL output clock when VCLK is using the PLL output as its source.
An additional use of this module is to measure the frequency of a selectable clock source, using the input
clock as a reference, by counting the pulses of two independent clock sources. Counter 0 generates a
fixed-width counting window after a preprogrammed number of pulses. Counter 1 generates a fixed-width
pulse (1 cycle) after a preprogrammed number of pulses. This pulse sets as an error signal if counter 1
does not reach 0 within the counting window generated by counter 0.
6.7.3.1 Features
• Takes two different clock sources as input to two independent counter blocks.
• One of the clock sources is the known-good, or reference clock; the second clock source is the "clock under test."
• Each counter block is programmable with initial, or seed values.
• The counter blocks start counting down from their seed values at the same time; a mismatch from the expected
frequency for the clock under test generates an error signal which is used to interrupt the CPU.
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6.7.3.2 Mapping of DCC Clock Source Inputs
Table 6-15. DCC1 Counter 0 Clock Sources
CLOCK SOURCE [3:0] CLOCK NAME
others oscillator (OSCIN)
0x5 high frequency LPO
0xA test clock (TCK)
Table 6-16. DCC1 Counter 1 Clock Sources
KEY [3:0] CLOCK SOURCE [3:0] CLOCK NAME
others - N2HET1[31]
0x0 Main PLL free-running clock output
0x1 PLL #2 free-running clock output
0x2 low frequency LPO
0xA 0x3 high frequency LPO
0x4 flash HD pump oscillator
0x5 EXTCLKIN1
0x6 EXTCLKIN2
0x7 ring oscillator
0x8 - 0xF VCLK
Table 6-17. DCC2 Counter 0 Clock Sources
CLOCK SOURCE [3:0] CLOCK NAME
others oscillator (OSCIN)
0xA test clock (TCK)
Table 6-18. DCC2 Counter 1 Clock Sources
KEY [3:0] CLOCK SOURCE [3:0] CLOCK NAME
others - N2HET2[0]
0xA 00x0 - 0x7 Reserved
0x8 - 0xF VCLK
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6.8 Glitch Filters
A glitch filter is present on the following signals.
Table 6-19. Glitch Filter Timing Specifications
PIN PARAMETER MIN MAX UNIT
Filter time nPORRST pin;
nPORRST tf(nPORRST) 475 2000 ns
pulses less than MIN will be filtered out, pulses greater than
MAX will generate a reset(1)
Filter time nRST pin;
nRST tf(nRST) 475 2000 ns
pulses less than MIN will be filtered out, pulses greater than
MAX will generate a reset
Filter time TEST pin;
TEST tf(TEST) 475 2000 ns
pulses less than MIN will be filtered out, pulses greater than
MAX will pass through
(1) The glitch filter design on the nPORRST signal is designed such that no size pulse will reset any part of the microcontroller (flash pump,
I/O pins, and so forth) without also generating a valid reset signal to the CPU.
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Flash(3MB)
RAM(256KB)
0x00000000
0x002FFFFF
0x08000000
0x0803FFFF
CRC
0xFE000000
Peripherals -Frame1
0xFF000000
SYSTEMModules
0xFFFFFFFF
0xF07FFFFF
RAM-ECC
0x08400000
0x0843FFFF
RESERVED
RESERVED
RESERVED
0xF0000000
EMIF(16MB *3)
0x60000000
0x6FFFFFFF
RESERVED
Flash(3MB)(MirroredImage)
0x20000000
0x202FFFFF
RESERVED
RESERVED
Peripherals -Frame2
0xFC000000
0xFCFFFFFF
0xFFF80000
EMIF(128MB)
0x80000000
0x87FFFFFF
CS0
RESERVED
reserved
AsyncRAM
SDRAM
0x64000000
0x68000000
0x6C000000
FlashModuleBus2Interface
RESERVED
(FlashECC,OTP andEEPROMaccesses)
CS4
CS3
CS2
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6.9 Device Memory Map
6.9.1 Memory Map Diagram
The figures below show the device memory maps.
Figure 6-9. TMS570LS3135 Memory Map
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Flash (2MB)
RAM (256KB)
0x00000000
0x001FFFFF
0x08000000
0x0803FFFF
CRC
0xFE000000
Peripherals - Frame 1
0xFF000000
SYSTEM Modules
0xFFFFFFFF
0xF07FFFFF
RAM - ECC
0x08400000
0x0843FFFF
RESERVED
RESERVED
RESERVED
0xF0000000
EMIF (16MB * 3)
0x60000000
0x6FFFFFFF
RESERVED
Flash (2MB) (Mirrored Image)
0x20000000
0x201FFFFF
RESERVED
RESERVED
Peripherals - Frame 2
0xFC000000
0xFCFFFFFF
0xFFF80000
EMIF (128MB)
0x80000000
0x87FFFFFF
CS0
RESERVED
reserved
Async RAM
SDRAM
0x64000000
0x68000000
0x6C000000
Flash Module Bus2 Interface
RESERVED
(Flash ECC, OTP and EEPROM accesses)
CS4
CS3
CS2
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Figure 6-10. TMS570LS2135 Memory Map
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Flash (2MB)
RAM (192KB)
0x00000000
0x001FFFFF
0x08000000
0x0802FFFF
CRC
0xFE000000
Peripherals - Frame 1
0xFF000000
SYSTEM Modules
0xFFFFFFFF
0xF07FFFFF
RAM - ECC
0x08400000
0x0842FFFF
RESERVED
RESERVED
RESERVED
0xF0000000
EMIF (16MB * 3)
0x60000000
0x6FFFFFFF
RESERVED
Flash (2MB) (Mirrored Image)
0x20000000
0x201FFFFF
RESERVED
RESERVED
Peripherals - Frame 2
0xFC000000
0xFCFFFFFF
0xFFF80000
EMIF (128MB)
0x80000000
0x87FFFFFF
CS0
RESERVED
reserved
Async RAM
SDRAM
0x64000000
0x68000000
0x6C000000
Flash Module Bus2 Interface
RESERVED
(Flash ECC, OTP and EEPROM accesses)
CS4
CS3
CS2
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Figure 6-11. TMS570LS2125 Memory Map
The Flash memory is mirrored to support ECC logic testing. The base address of the mirrored Flash
image is 0x2000 0000.
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6.9.2 Memory Map Table
Table 6-20. Device Memory Map
FRAME ADDRESS RANGE RESPONSE FOR ACCESS TO
FRAME CHIP FRAME ACTUAL
MODULE NAME UNIMPLEMENTED LOCATIONS IN
SELECT SIZE SIZE
START END FRAME
MEMORIES TIGHTLY COUPLED TO THE ARM CORTEX-R4F CPU
TCM Flash CS0 0x00000000 0x00FFFFFF 16MB 3MB(1)
TCM RAM + RAM CSRAM0 0x08000000 0x0BFFFFFF 64MB 256KB(2) Abort
ECC
Mirrored Flash Flash mirror frame 0x20000000 0x20FFFFFF 16MB 3MB(1)
EXTERNAL MEMORY ACCESSES
EMIF Chip Select 2 EMIF select 2 0x60000000 0x63FFFFFF 64MB 16MB
(asynchronous)
EMIF Chip Select 3 EMIF select 3 0x64000000 0x67FFFFFF 64MB 16MB
(asynchronous) Access to "Reserved" space will generate
Abort
EMIF Chip Select 4 EMIF select 4 0x68000000 0x6BFFFFFF 64MB 16MB
(asynchronous)
EMIF Chip Select 0 EMIF select 0 0x80000000 0x87FFFFFF 128MB 128MB
(synchronous)
FLASH MODULE BUS2 INTERFACE
Customer OTP, 0xF0000000 0xF0001FFF 8KB 4KB
TCM Flash Bank 0
Customer OTP, 0xF0002000 0xF0003FFF 8KB 4KB
TCM Flash Bank 1
Customer OTP, 0xF000E000 0xF000FFFF 8KB 2KB
EEPROM Bank 7
Customer
OTP–ECC, TCM 0xF0040000 0xF00403FF 1KB 512B
Flash Bank 0
Customer
OTP–ECC, TCM 0xF0040400 0xF00407FF 1KB 512B
Flash Bank 1
Customer
OTP–ECC, 0xF0041C00 0xF0041FFF 1KB 256B
EEPROM Bank 7
TI OTP, TCM Flash 0xF0080000 0xF0081FFF 8KB 4KB
Bank 0 Abort
TI OTP, TCM Flash 0xF0082000 0xF0083FFF 8KB 4KB
Bank 1
TI OTP, EEPROM 0xF008E000 0xF008FFFF 8KB 2KB
Bank 7
TI OTP–ECC, TCM 0xF00C0000 0xF00C03FF 1KB 512B
Flash Bank 0
TI OTP–ECC, TCM 0xF00C0400 0xF00C07FF 1KB 512B
Flash Bank 1
TI OTP–ECC, 0xF00C1C00 0xF00C1FFF 1KB 256B
EEPROM Bank 7
EEPROM 0xF0100000 0xF013FFFF 256KB 8KB
Bank–ECC
EEPROM Bank 0xF0200000 0xF03FFFFF 2MB 64KB
Flash Data Space 0xF0400000 0xF04FFFFF 1MB 384KB
ECC
EMIF SLAVE INTERFACES
EMIF Registers 0xFCFFE800 0xFCFFE8FF 256B 256B Abort
CYCLIC REDUNDANCY CHECKER (CRC) MODULE REGISTERS
CRC CRC frame 0xFE000000 0xFEFFFFFF 16MB 512B Accesses above 0x200 generate abort.
PERIPHERAL MEMORIES
MIBSPI5 RAM PCS[5] 0xFF0A0000 0xFF0BFFFF 128KB 2KB Abort for accesses above 2KB
MIBSPI3 RAM PCS[6] 0xFF0C0000 0xFF0DFFFF 128KB 2KB Abort for accesses above 2KB
(1) The TMS570LS2135 and TMS570LS2125 devices only have 2MB of Flash
(2) The TMS570LS2125 device has only 192KB of RAM.
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Table 6-20. Device Memory Map (continued)
FRAME ADDRESS RANGE RESPONSE FOR ACCESS TO
FRAME CHIP FRAME ACTUAL
MODULE NAME UNIMPLEMENTED LOCATIONS IN
SELECT SIZE SIZE
START END FRAME
MIBSPI1 RAM PCS[7] 0xFF0E0000 0xFF0FFFFF 128KB 2KB Abort for accesses above 2KB
Wrap around for accesses to
unimplemented address offsets lower than
DCAN3 RAM PCS[13] 0xFF1A0000 0xFF1BFFFF 128KB 2KB 0x7FF. Abort generated for accesses
beyond offset 0x800.
Wrap around for accesses to
unimplemented address offsets lower than
DCAN2 RAM PCS[14] 0xFF1C0000 0xFF1DFFFF 128KB 2KB 0x7FF. Abort generated for accesses
beyond offset 0x800.
Wrap around for accesses to
unimplemented address offsets lower than
DCAN1 RAM PCS[15] 0xFF1E0000 0xFF1FFFFF 128KB 2KB 0x7FF. Abort generated for accesses
beyond offset 0x800.
Wrap around for accesses to
unimplemented address offsets lower than
MIBADC2 RAM PCS[29] 0xFF3A0000 0xFF3BFFFF 128KB 8KB 0x1FFF. Abort generated for accesses
beyond 0x1FFF.
Wrap around for accesses to
unimplemented address offsets lower than
MIBADC1 RAM PCS[31] 0xFF3E0000 0xFF3FFFFF 128KB 8KB 0x1FFF. Abort generated for accesses
beyond 0x1FFF.
Wrap around for accesses to
unimplemented address offsets lower than
N2HET2 RAM PCS[34] 0xFF440000 0xFF45FFFF 128KB 16KB 0x3FFF. Abort generated for accesses
beyond 0x3FFF.
Wrap around for accesses to
unimplemented address offsets lower than
N2HET1 RAM PCS[35] 0xFF460000 0xFF47FFFF 128KB 16KB 0x3FFF. Abort generated for accesses
beyond 0x3FFF.
HTU2 RAM PCS[38] 0xFF4C0000 0xFF4DFFFF 128KB 1KB Abort
HTU1 RAM PCS[39] 0xFF4E0000 0xFF4FFFFF 128KB 1KB Abort
FTU RAM PCS[40] 0xFF500000 0xFF51FFFF 128KB 1KB Abort
DEBUG COMPONENTS
CoreSight Debug CSCS0 0xFFA00000 0xFFA00FFF 4KB 4KB Reads: 0, writes: no effect
ROM
Cortex-R4F Debug CSCS1 0xFFA01000 0xFFA01FFF 4KB 4KB Reads: 0, writes: no effect
ETM-R4 CSCS2 0xFFA02000 0xFFA02FFF 4KB 4KB Reads: 0, writes: no effect
CoreSight TPIU CSCS3 0xFFA03000 0xFFA03FFF 4KB 4KB Reads: 0, writes: no effect
POM CSCS4 0xFFA04000 0xFFA04FFF 4KB 4KB Abort
PERIPHERAL CONTROL REGISTERS
FTU PS[23] 0xFFF7A000 0xFFF7A1FF 512B 512B Reads: 0, writes: no effect
HTU1 PS[22] 0xFFF7A400 0xFFF7A4FF 256B 256B Reads: 0, writes: no effect
HTU2 PS[22] 0xFFF7A500 0xFFF7A5FF 256B 256B Reads: 0, writes: no effect
N2HET1 PS[17] 0xFFF7B800 0xFFF7B8FF 256B 256B Reads: 0, writes: no effect
N2HET2 PS[17] 0xFFF7B900 0xFFF7B9FF 256B 256B Reads: 0, writes: no effect
GPIO PS[16] 0xFFF7BC00 0xFFF7BCFF 256B 256B Reads: 0, writes: no effect
MIBADC1 PS[15] 0xFFF7C000 0xFFF7C1FF 512B 512B Reads: 0, writes: no effect
MIBADC2 PS[15] 0xFFF7C200 0xFFF7C3FF 512B 512B Reads: 0, writes: no effect
FlexRay PS[12]+PS[13] 0xFFF7C800 0xFFF7CFFF 2KB 2KB Reads: 0, writes: no effect
I2C PS[10] 0xFFF7D400 0xFFF7D4FF 256B 256B Reads: 0, writes: no effect
DCAN1 PS[8] 0xFFF7DC00 0xFFF7DDFF 512B 512B Reads: 0, writes: no effect
DCAN2 PS[8] 0xFFF7DE00 0xFFF7DFFF 512B 512B Reads: 0, writes: no effect
DCAN3 PS[7] 0xFFF7E000 0xFFF7E1FF 512B 512B Reads: 0, writes: no effect
LIN PS[6] 0xFFF7E400 0xFFF7E4FF 256B 256B Reads: 0, writes: no effect
SCI PS[6] 0xFFF7E500 0xFFF7E5FF 256B 256B Reads: 0, writes: no effect
MibSPI1 PS[2] 0xFFF7F400 0xFFF7F5FF 512B 512B Reads: 0, writes: no effect
SPI2 PS[2] 0xFFF7F600 0xFFF7F7FF 512B 512B Reads: 0, writes: no effect
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Table 6-20. Device Memory Map (continued)
FRAME ADDRESS RANGE RESPONSE FOR ACCESS TO
FRAME CHIP FRAME ACTUAL
MODULE NAME UNIMPLEMENTED LOCATIONS IN
SELECT SIZE SIZE
START END FRAME
MibSPI3 PS[1] 0xFFF7F800 0xFFF7F9FF 512B 512B Reads: 0, writes: no effect
SPI4 PS[1] 0xFFF7FA00 0xFFF7FBFF 512B 512B Reads: 0, writes: no effect
MibSPI5 PS[0] 0xFFF7FC00 0xFFF7FDFF 512B 512B Reads: 0, writes: no effect
SYSTEM MODULES CONTROL REGISTERS AND MEMORIES
DMA RAM PPCS0 0xFFF80000 0xFFF80FFF 4KB 4KB Abort
Wrap around for accesses to
VIM RAM PPCS2 0xFFF82000 0xFFF82FFF 4KB 1KB unimplemented address offsets between
1kB and 4kB.
RTP RAM PPCS3 0xFFF83000 0xFFF83FFF 4KB 4KB Abort
Flash Module PPCS7 0xFFF87000 0xFFF87FFF 4KB 4KB Abort
eFuse Controller PPCS12 0xFFF8C000 0xFFF8CFFF 4KB 4KB Abort
Power Management PPSE0 0xFFFF0000 0xFFFF01FF 512B 512B Abort
Module (PMM)
Test Controller PPSE1 0xFFFF0400 0xFFFF07FF 1KB 1KB Reads: 0, writes: no effect
(FMTM)
PCR registers PPS0 0xFFFFE000 0xFFFFE0FF 256B 256B Reads: 0, writes: no effect
System Module -
Frame 2 (see device PPS0 0xFFFFE100 0xFFFFE1FF 256B 256B Reads: 0, writes: no effect
TRM)
PBIST PPS1 0xFFFFE400 0xFFFFE5FF 512B 512B Reads: 0, writes: no effect
Generates address error interrupt, if
STC PPS1 0xFFFFE600 0xFFFFE6FF 256B 256B enabled
IOMM Multiplexing PPS2 0xFFFFEA00 0xFFFFEBFF 512B 512B Reads: 0, writes: no effect
Control Module
DCC1 PPS3 0xFFFFEC00 0xFFFFECFF 256B 256B Reads: 0, writes: no effect
DMA PPS4 0xFFFFF000 0xFFFFF3FF 1KB 1KB Reads: 0, writes: no effect
DCC2 PPS5 0xFFFFF400 0xFFFFF4FF 256B 256B Reads: 0, writes: no effect
ESM PPS5 0xFFFFF500 0xFFFFF5FF 256B 256B Reads: 0, writes: no effect
CCMR4 PPS5 0xFFFFF600 0xFFFFF6FF 256B 256B Reads: 0, writes: no effect
DMM PPS5 0xFFFFF700 0xFFFFF7FF 256B 256B Reads: 0, writes: no effect
RAM ECC even PPS6 0xFFFFF800 0xFFFFF8FF 256B 256B Reads: 0, writes: no effect
RAM ECC odd PPS6 0xFFFFF900 0xFFFFF9FF 256B 256B Reads: 0, writes: no effect
RTP PPS6 0xFFFFFA00 0xFFFFFAFF 256B 256B Reads: 0, writes: no effect
RTI + DWWD PPS7 0xFFFFFC00 0xFFFFFCFF 256B 256B Reads: 0, writes: no effect
VIM Parity PPS7 0xFFFFFD00 0xFFFFFDFF 256B 256B Reads: 0, writes: no effect
VIM PPS7 0xFFFFFE00 0xFFFFFEFF 256B 256B Reads: 0, writes: no effect
System Module -
Frame 1 (see device PPS7 0xFFFFFF00 0xFFFFFFFF 256B 256B Reads: 0, writes: no effect
TRM)
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6.9.3 Master/Slave Access Privileges
Table 6-21 lists the access permissions for each bus master on the device. A bus master is a module that
can initiate a read or a write transaction on the device.
Each slave module on the main interconnect is listed in the table. A "Yes" indicates that the module listed
in the "MASTERS" column can access that slave module.
Table 6-21. Master / Slave Access Matrix
MASTERS ACCESS MODE SLAVES ON MAIN SCR
Flash Module Non-CPU CRC EMIF Slave Peripheral
Bus2 Interface: Accesses to Interfaces Control
OTP, ECC, Program Flash Registers, All
EEPROM Bank and CPU Data Peripheral
RAM Memories, And
All System
Module Control
Registers And
Memories
CPU READ User/Privilege Yes Yes Yes Yes Yes
CPU WRITE User/Privilege No Yes Yes Yes Yes
DMA User Yes Yes Yes Yes Yes
POM User Yes Yes Yes Yes Yes
DMM User Yes Yes Yes Yes Yes
DAP Privilege Yes Yes Yes Yes Yes
HTU1 Privilege No Yes Yes Yes Yes
HTU2 Privilege No Yes Yes Yes Yes
FTU User No Yes Yes Yes Yes
6.9.3.1 Special Notes on Accesses to Certain Slaves
Write accesses to the Power Domain Management Module (PMM) control registers are limited to the CPU
(master id = 1). The other masters can only read from these registers.
A debugger can also write to the PMM registers. The master-id check is disabled in debug mode.
The device contains dedicated logic to generate a bus error response on any access to a module that is in
a power domain that has been turned OFF.
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6.9.4 POM Overlay Considerations
• The POM overlay can map onto up to 8MB of the internal or external memory space. The starting
address and the size of the memory overlay are configurable via the POM module control registers.
Care must be taken to ensure that the overlay is mapped on to available memory.
• ECC must be disabled by software via CP15 in case POM overlay is enabled; otherwise ECC errors
will be generated.
• POM overlay must not be enabled when the flash and internal RAM memories are swapped via the
MEM SWAP field of the Bus Matrix Module Control Register 1 (BMMCR1).
• When POM is used to overlay the flash onto internal or external RAM, there is a bus contention
possibility when another master accesses the TCM flash. This results in a system hang.
– The POM module implements a time-out feature to detect this exact scenario. The time-out needs
to be enabled whenever POM overlay is enabled.
– The time-out can be enabled by writing 1010 to the Enable TimeOut (ETO) field of the POM Global
Control register (POMGLBCTRL, address = 0xFFA04000).
– In case a read request by the POM cannot be completed within 32 HCLK cycles, the time-out (TO)
flag is set in the POM Flag register (POMFLG, address = 0xFFA0400C). Also, an abort is
generated to the CPU. This can be a prefetch abort for an instruction fetch or a data abort for a
data fetch.
– The prefetch- and data-abort handlers must be modified to check if the TO flag in the POM module
is set. If so, then the application can assume that the time-out is caused by a bus contention
between the POM transaction and another master accessing the same memory region. The abort
handlers need to clear the TO flag, so that any further aborts are not misinterpreted as having been
caused due to a time-out from the POM.
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6.10 Flash Memory
6.10.1 Flash Memory Configuration
Flash Bank: A separate block of logic consisting of 1 to 16 sectors. Each flash bank normally has a
customer-OTP and a TI-OTP area. These flash sectors share input/output buffers, data paths, sense
amplifiers, and control logic.
Flash Sector: A contiguous region of flash memory which must be erased simultaneously due to physical
construction constraints.
Flash Pump: A charge pump which generates all the voltages required for reading, programming, or
erasing the flash banks.
Flash Module: Interface circuitry required between the host CPU and the flash banks and pump module.
Table 6-22. Flash Memory Banks and Sectors
SECTOR SEGMENT
MEMORY ARRAYS (OR BANKS)(1) LOW ADDRESS HIGH ADDRESS
NO. (BYTES)
BANK0 (1.5MB) 0 32KB 0x0000_0000 0x0000_7FFF
1 32KB 0x0000_8000 0x0000_FFFF
2 32KB 0x0001_0000 0x0001_7FFF
3 32KB 0x0001_8000 0x0001_FFFF
4 128KB 0x0002_0000 0x0003_FFFF
5 128KB 0x0004_0000 0x0005_FFFF
6 128KB 0x0006_0000 0x0007_FFFF
7 128KB 0x0008_0000 0x0009_FFFF
8 128KB 0x000A_0000 0x000B_FFFF
9 128KB 0x000C_0000 0x000D_FFFF
10 128KB 0x000E_0000 0x000F_FFFF
11 128KB 0x0010_0000 0x0011_FFFF
12 128KB 0x0012_0000 0x0013_FFFF
13 128KB 0x0014_0000 0x0015_FFFF
14 128KB 0x0016_0000 0x0017_FFFF
BANK1 (1.5MB) 0 128KB 0x0018_0000 0x0019_FFFF
1 128KB 0x001A_0000 0x001B_FFFF
2 128KB 0x001C_0000 0x001D_FFFF
3 128KB 0x001E_0000 0x001F_FFFF
(3MB devices only) 4 128KB 0x0020_0000 0x0021_FFFF
5 128KB 0x0022_0000 0x0023_FFFF
6 128KB 0x0024_0000 0x0025_FFFF
7 128KB 0x0026_0000 0x0027_FFFF
8 128KB 0x0028_0000 0x0029_FFFF
9 128KB 0x002A_0000 0x002B_FFFF
10 128KB 0x002C_0000 0x002D_FFFF
11 128KB 0x002E_0000 0x002F_FFFF
BANK7 (64KB) for EEPROM emulation(2)(3) 0 16KB 0xF020_0000 0xF020_3FFF
1 16KB 0xF020_4000 0xF020_7FFF
2 16KB 0xF020_8000 0xF020_BFFF
3 16KB 0xF020_C000 0xF020_FFFF
(1) The Flash banks are 144-bit-wide bank with ECC support.
(2) The flash bank7 can be programmed while executing code from flash bank0 or bank1.
(3) Code execution is not allowed from flash bank7.
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6.10.2 Main Features of Flash Module
• Support for multiple flash banks for program and/or data storage
• Simultaneous read access on a bank while performing program or erase operation on any other bank
• Integrated state machines to automate flash erase and program operations
• Software interface for flash program and erase operations
• Pipelined mode operation to improve instruction access interface bandwidth
• Support for Single Error Correction Double Error Detection (SECDED) block inside Cortex-R4F CPU
– Error address is captured for host system debugging
• Support for a rich set of diagnostic features
6.10.3 ECC Protection for Flash Accesses
All accesses to the program flash memory are protected by Single Error Correction Double Error Detection
(SECDED) logic embedded inside the CPU. The flash module provides 8 bits of ECC code for 64 bits of
instructions or data fetched from the flash memory. The CPU calculates the expected ECC code based on
the 64 bits received and compares it with the ECC code returned by the flash module. A single-bit error is
corrected and flagged by the CPU, while a multibit error is only flagged. The CPU signals an ECC error
via its Event bus. This signaling mechanism is not enabled by default and must be enabled by setting the
'X' bit of the Performance Monitor Control Register, c9.
MRC p15,#0,r1,c9,c12,#0 ;Enabling Event monitor states
ORR r1, r1, #0x00000010
MCR p15,#0,r1,c9,c12,#0 ;Set 4th bit (‘X’) of PMNC register
MRC p15,#0,r1,c9,c12,#0
The application must also explicitly enable the CPU's ECC checking for accesses on the CPU's ATCM
and BTCM interfaces. These are connected to the program flash and data RAM respectively. ECC
checking for these interfaces can be done by setting the B1TCMPCEN, B0TCMPCEN and ATCMPCEN
bits of the System Control coprocessor's Auxiliary Control Register, c1.
MRC p15, #0, r1, c1, c0, #1
ORR r1, r1, #0x0e000000 ;Enable ECC checking for ATCM and BTCMs
DMB
MCR p15, #0, r1, c1, c0, #1
6.10.4 Flash Access Speeds
For information on flash memory access speeds and the relevant wait states required, refer to Section 5.6.
6.10.5 Flash Program and Erase Timings for Program Flash
Table 6-23. Timing Specifications for Program Flash
PARAMETER MIN NOM MAX UNIT
tprog (144bit) Wide Word (144bit) programming 40 300 µs
time
tprog (Total) 3-MB programming time(1) -40°C to 125°C 32 s
0°C to 60°C, for first 8 16 s
25 cycles
terase Sector/Bank erase time(2) -40°C to 125°C 0.03 4 s
0°C to 60°C, for first 16 100 ms
25 cycles
twec Write/erase cycles with 15-year -40°C to 125°C 1000 cycles
Data Retention requirement
(1) This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes
programming 144 bits at a time at the maximum specified operating frequency.
(2) During bank erase, the selected sectors are erased simultaneously. The time to erase the bank is specified as equal to the time to erase
a sector.
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6.10.6 Flash Program and Erase Timings for Data Flash
Table 6-24. Timing Specifications for Data Flash
PARAMETER MIN NOM MAX UNIT
Wide Word (144bit) programming
tprog (144bit) 40 300 µs
time -40°C to 125°C 660 ms
tprog (Total) 64-KB programming time(1) 0°C to 60°C, for first 165 330 ms
25 cycles
-40°C to 125°C 0.2 8 s
terase Sector/Bank erase time(2) 0°C to 60°C, for first 14 100 ms
25 cycles
Write/erase cycles with 15-year
twec -40°C to 125°C 100000 cycles
Data Retention requirement
(1) This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes
programming 144 bits at a time at the maximum specified operating frequency.
(2) During bank erase, the selected sectors are erased simultaneously. The time to erase the bank is specified as equal to the time to erase
a sector.
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TCM BUS
TCM BUS
72 Bit data + ECC
72 Bit data + ECC
Upper 32 bits data &
4 ECC bits
Lower 32 bits data &
4 ECC bits
36 Bit
wide
RAM
36 Bit
wide
RAM
36 Bit
wide
RAM
36 Bit
wide
RAM
36 Bit
wide
RAM
36 Bit
wide
RAM
Upper 32 bits data &
4 ECC bits
Lower 32 bits data &
4 ECC bits
36 Bit
wide
RAM
36 Bit
wide
RAM
36 Bit
wide
RAM
36 Bit
wide
RAM
36 Bit
wide
RAM
36 Bit
wide
RAM
TCRAM
Interface 1
Cortex-R4F
B0
TCM
B1
TCM
TCRAM
Interface 2
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6.11 Tightly Coupled RAM (TCRAM) Interface Module
Figure 6-12 illustrates the connection of the Tightly Coupled RAM (TCRAM) to the Cortex-R4F CPU.
Figure 6-12. TCRAM Block Diagram
6.11.1 Features
The features of the TCRAM Module are:
• Acts as slave to the Cortex-R4F CPU's BTCM interface
• Supports CPU's internal ECC scheme by providing 64-bit data and 8-bit ECC code
• Monitors CPU Event Bus and generates single or multibit error interrupts
• Stores addresses for single and multibit errors
• Supports RAM trace module
• Provides CPU address bus integrity checking by supporting parity checking on the address bus
• Performs redundant address decoding for the RAM bank chip select and ECC select generation logic
• Provides enhanced safety for the RAM addressing by implementing two 36-bit wide byte-interleaved RAM banks
and generating independent RAM access control signals to the two banks
• Supports auto-initialization of the RAM banks along with the ECC bits
• No support for bit-wise RAM accesses
6.11.2 TCRAM Interface ECC Support
The TCRAM interface passes on the ECC code for each data read by the Cortex-R4F CPU from the RAM.
It also stores the CPU's ECC port contents in the ECC RAM when the CPU does a write to the RAM. The
TCRAM interface monitors the CPU's event bus and provides registers for indicating singlebit or multibit
errors and also for identifying the address that caused the single or multibit error. The event signaling and
the ECC checking for the RAM accesses must be enabled inside the CPU.
For more information see the device specific technical reference manual.
6.12 Parity Protection for Peripheral RAMs
Most peripheral RAMs are protected by odd/even parity checking. During a read access the parity is
calculated based on the data read from the peripheral RAM and compared with the good parity value
stored in the parity RAM for that peripheral. If any word fails the parity check, the module generates a
parity error signal that is mapped to the Error Signaling Module. The module also captures the peripheral
RAM address that caused the parity error.
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The parity protection for peripheral RAMs is not enabled by default and must be enabled by the
application. Each individual peripheral contains control registers to enable the parity protection for
accesses to its RAM.
NOTE
The CPU read access gets the actual data from the peripheral. The application can choose
to generate an interrupt whenever a peripheral RAM parity error is detected.
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6.13 On-Chip SRAM Initialization and Testing
6.13.1 On-Chip SRAM Self-Test Using PBIST
6.13.1.1 Features
• Extensive instruction set to support various memory test algorithms
• ROM-based algorithms allow application to run TI production-level memory tests
• Independent testing of all on-chip SRAM
6.13.1.2 PBIST RAM Groups
Table 6-25. PBIST RAM Grouping
TEST PATTERN (ALGORITHM)
MARCH 13N(1) MARCH 13N(1)
TRIPLE READ TRIPLE READ TWO PORT SINGLE PORT
MEMORY RAM GROUP TEST CLOCK MEM TYPE SLOW READ FAST READ (CYCLES) (CYCLES)
ALGO MASK ALGO MASK ALGO MASK ALGO MASK
0x1 0x2 0x4 0x8
PBIST_ROM 1 ROM CLK ROM 24578 8194
STC_ROM 2 ROM CLK ROM 19586 6530
DCAN1 3 VCLK Dual Port 25200
DCAN2 4 VCLK Dual Port 25200
DCAN3 5 VCLK Dual Port 25200
ESRAM1(2) 6 HCLK Single Port 266280
MIBSPI1 7 VCLK Dual Port 33440
MIBSPI3 8 VCLK Dual Port 33440
MIBSPI5 9 VCLK Dual Port 33440
VIM 10 VCLK Dual Port 12560
MIBADC1 11 VCLK Dual Port 4200
DMA 12 HCLK Dual Port 18960
N2HET1 13 VCLK Dual Port 31680
HTU1 14 VCLK Dual Port 6480
RTP 15 HCLK Dual Port 37800
16 VCLK Dual Port 75400
FLEXRAY 17 Single Port 133160
MIBADC2 18 VCLK Dual Port 4200
N2HET2 19 VCLK Dual Port 31680
HTU2 20 VCLK Dual Port 6480
ESRAM5(3) 21 HCLK Single Port 266280
ESRAM6(4) 22 HCLK Single Port 266280
ESRAM8(5) 28 HCLK Single Port 266280
(1) There are several memory testing algorithms stored in the PBIST ROM. However, TI recommends the March13N algorithm for
application testing.
(2) ESRAM1: Address 0x08000000 - 0x0800FFFF (Always on power domain)
(3) ESRAM5: Address 0x08010000 - 0x0801FFFF (RAM power domain 1)
(4) ESRAM6: Address 0x08020000 - 0x0802FFFF (RAM power domain 2)
(5) ESRAM8: Address 0x08030000 - 0x0803FFFF (RAM power domain 3) Not available on theTMS570LS2125 device.
The PBIST ROM clock frequency is limited to 90 MHz, if 90 MHz < HCLK <= HCLKmax, or HCLK, if
HCLK <= 90 MHz.
The PBIST ROM clock is divided down from HCLK. The divider is selected by programming the ROM_DIV
field of the Memory Self-Test Global Control Register (MSTGCR) at address 0xFFFFFF58.
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6.13.2 On-Chip SRAM Auto Initialization
This microcontroller allows some of the on-chip memories to be initialized to zero via the Memory
Hardware Initialization mechanism in the System module. This hardware mechanism allows an application
to program the memory arrays with error detection capability to a known state based on their error
detection scheme (odd/even parity or ECC).
The MINITGCR register enables the memory initialization sequence, and the MSINENA register selects
the memories that are to be initialized.
For more information on these registers see the device specific technical reference manual.
The mapping of the different on-chip memories to the specific bits of the MSINENA registers is shown in
Table 6-26.
Table 6-26. Memory Initialization
ADDRESS RANGE
CONNECTING MODULE MSINENA REGISTER BIT #
BASE ADDRESS ENDING ADDRESS
RAM (PD#1) 0x08000000 0x0800FFFF 0(1)
RAM (RAM_PD#1) 0x08010000 0x0801FFFF 0(1)
RAM (RAM_PD#2) 0x08020000 0x0802FFFF 0(1)
RAM (RAM_PD#3)(2) 0x08030000 0x0803FFFF 0(1)
MIBSPI5 RAM 0xFF0A0000 0xFF0BFFFF 12(3)
MIBSPI3 RAM 0xFF0C0000 0xFF0DFFFF 11(3)
MIBSPI1 RAM 0xFF0E0000 0xFF0FFFFF 7(3)
DCAN3 RAM 0xFF1A0000 0xFF1BFFFF 10
DCAN2 RAM 0xFF1C0000 0xFF1DFFFF 6
DCAN1 RAM 0xFF1E0000 0xFF1FFFFF 5
FlexRay RAM RAM is not CPU-Addressable n/a(4)
MIBADC2 RAM 0xFF3A0000 0xFF3BFFFF 14
MIBADC1 RAM 0xFF3E0000 0xFF3FFFFF 8
N2HET2 RAM 0xFF440000 0xFF45FFFF 15
N2HET1 RAM 0xFF460000 0xFF47FFFF 3
HTU2 RAM 0xFF4C0000 0xFF4DFFFF 16
HTU1 RAM 0xFF4E0000 0xFF4FFFFF 4
DMA RAM 0xFFF80000 0xFFF80FFF 1
VIM RAM 0xFFF82000 0xFFF82FFF 2
RTP RAM 0xFFF83000 0xFFF83FFF n/a
FTU RAM 0xFF500000 0xFF51FFFF 13
Reserved 0xFC520000 0xFC521FFF n/a
(1) The TCM RAM wrapper has separate control bits to select the RAM power domain that is to be auto-initialized.
(2) Not available on theTMS570LS2125 device.
(3) The MibSPIx modules perform an initialization of the transmit and receive RAMs as soon as the module is released from its local reset
via the SPIGCR0 register. This is independent of whether the application chooses to initialize the MibSPIx RAMs using the system
module auto-initialization method. Before the MibSPI RAM can be initialized using the system module auto-initialization method: (I) The
module must be released from its local reset, AND (ii) The application must poll for the "BUF INIT ACTIVE" status flag in the SPIFLG
register to become cleared (zero)
(4) Reserved only. The FlexRay RAM has its own initialization mechanism.
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EMIF_nCS[3:2]
EMIF_BA[1:0]
13
12
EMIF_ADDR[21:0]
EMIF_nOE
EMIF_DATA[15:0]
EMIF_nWE
10
5
9
7
4
8
6
3
1
EMIF_nDQM[1:0]
30
29
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6.14 External Memory Interface (EMIF)
6.14.1 Features
The EMIF includes many features to enhance the ease and flexibility of connecting to external
asynchronous memories or SDRAM devices. The EMIF features includes support for:
• 3 addressable chip select for asynchronous memories of up to 16MB each
• 1 addressable chip select space for SDRAMs up to 128MB
• 8- or 16-bit data bus width
• Programmable cycle timings such as setup, strobe, and hold times as well as turnaround time
• Select strobe mode
• Extended Wait mode
• Data bus parking
6.14.2 Electrical and Timing Specifications
6.14.2.1 Asynchronous RAM
Figure 6-13. Asynchronous Memory Read Timing
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EMIF_nCS[3:2]
EMIF_BA[1:0]
EMIF_ADDR[21:0]
EMIF_nWE
EMIF_DATA[15:0]
EMIF_nOE
15
1
16
18
20
22 24
17
19
21
23
26
27
EMIF_nDQM[1:0]
EMIF_nCS[3:2]
11
Asserted Deasserted
2
2
EMIF_BA[1:0]
EMIF_ADDR[21:0]
EMIF_DATA[15:0]
EMIF_nOE
EMIF_WAIT
SETUP Extended Due to EMIF_WAIT STROBE HOLD
14
STROBE
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Figure 6-14. EMIFnWAIT Read Timing Requirements
Figure 6-15. Asynchronous Memory Write Timing
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EMIF_nCS[3:2]
25
Asserted
2
2
EMIF_BA[1:0]
EMIF_ADDR[21:0]
EMIF_DATA[15:0]
EMIF_nWE
EMIF_WAIT
SETUP Extended Due to EMIF_WAIT
28
Deasserted
STROBE STROBE HOLD
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Figure 6-16. EMIFnWAIT Write Timing Requirements
Table 6-27. EMIF Asynchronous Memory Timing Requirements
NO. MIN NOM MAX UNIT
Reads and Writes
E EMIF clock period 11 ns
2 tw(EM_WAIT) Pulse duration, EMIFnWAIT 2E ns
assertion and deassertion
Reads
12 tsu(EMDV-EMOEH) Setup time, EMIFDATA[15:0] 30 ns
valid before EMIFnOE high
13 th(EMOEH-EMDIV) Hold time, EMIFDATA[15:0] valid 0.5 ns
after EMIFnOE high
14 tsu(EMOEL-EMWAIT) Setup Time, EMIFnWAIT 4E+30 ns
asserted before end of Strobe
Phase(1)
Writes
28 tsu(EMWEL-EMWAIT) Setup Time, EMIFnWAIT 4E+30 ns
asserted before end of Strobe
Phase(1)
(1) Setup before end of STROBE phase (if no extended wait states are inserted) by which EMIFnWAIT must be asserted to add extended
wait states. Figure Figure 6-14 and Figure Figure 6-16 describe EMIF transactions that include extended wait states inserted during the
STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start
of where the HOLD phase would begin if there were no extended wait cycles.
Table 6-28. EMIF Asynchronous Memory Switching Characteristics(1)(2)(3)
NO. PARAMETER MIN NOM MAX UNIT
Reads and Writes
1 td(TURNAROUND) Turn around time (TA)*E - 4 (TA)*E (TA)*E + 3 ns
Reads
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle
Configuration Registers. These support the following ranges of values: TA[4–1], RS[16–1], RST[64–1], RH[8–1], WS[16–1], WST[64–1],
WH[8–1], and MEWC[1–256]. See the TMS570LS31X/21X Technical Reference Manual (SPNU499) for more information.
(2) E = EMIF_CLK period in ns.
(3) EWC = external wait cycles determined by EMIFnWAIT input signal. EWC supports the following range of values. EWC[256–1]. Note
that the maximum wait time before time-out is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See
the TMS570LS31X/21X Technical Reference Manual (SPNU499) for more information.
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Table 6-28. EMIF Asynchronous Memory Switching Characteristics(1)(2)(3) (continued)
NO. PARAMETER MIN NOM MAX UNIT
3 tc(EMRCYCLE) EMIF read cycle time (EW = 0) (RS+RST+RH)* (RS+RST+RH)* (RS+RST+RH)* ns
E -3 E E + 3
EMIF read cycle time (EW = 1) (RS+RST+RH+( (RS+RST+RH+( (RS+RST+RH+( ns
EWC*16))*E -3 EWC*16))*E EWC*16))*E + 3
4 tsu(EMCEL-EMOEL) Output setup time, EMIFnCS[4:2] ns
(RS)*E-4 (RS)*E (RS)*E+3
low to EMIFnOE low (SS = 0)
Output setup time, EMIFnCS[4:2] ns
-3 0 +3
low to EMIFnOE low (SS = 1)
5 th(EMOEH-EMCEH) Output hold time, EMIFnOE high ns
(RH)*E -4 (RH)*E (RH)*E + 3
to EMIFnCS[4:2] high (SS = 0)
Output hold time, EMIFnOE high ns
-3 0 +3
to EMIFnCS[4:2] high (SS = 1)
6 tsu(EMBAV-EMOEL) Output setup time, EMIFBA[1:0] ns
(RS)*E-4 (RS)*E (RS)*E+3
valid to EMIFnOE low
7 th(EMOEH-EMBAIV) Output hold time, EMIFnOE high ns
(RH)*E-4 (RH)*E (RH)*E+3
to EMIFBA[1:0] invalid
8 tsu(EMAV-EMOEL) Output setup time, ns
EMIFADDR[21:0] valid to (RS)*E-4 (RS)*E (RS)*E+3
EMIFnOE low
9 th(EMOEH-EMAIV) Output hold time, EMIFnOE high ns
(RH)*E-4 (RH)*E (RH)*E+3
to EMIFADDR[21:0] invalid
10 tw(EMOEL) EMIFnOE active low width (EW ns
(RST)*E-3 (RST)*E (RST)*E+3
= 0)
EMIFnOE active low width (EW (RST+(EWC*16 (RST+(EWC*16 (RST+(EWC*16 ns
= 1) )) *E-3 ))*E )) *E+3
11 td(EMWAITH-EMOEH) Delay time from EMIFnWAIT ns
3E-3 4E 4E+30
deasserted to EMIFnOE high
29 tsu(EMDQMV-EMOEL) Output setup time, ns
EMIFnDQM[1:0] valid to (RS)*E-4 (RS)*E (RS)*E+3
EMIFnOE low
30 th(EMOEH-EMDQMIV) Output hold time, EMIFnOE high ns
(RH)*E-4 (RH)*E (RH)*E+3
to EMIFnDQM[1:0] invalid
Writes
15 tc(EMWCYCLE) EMIF write cycle time (EW = 0) (WS+WST+WH) (WS+WST+WH) (WS+WST+WH) ns
* E-3 *E * E+3
EMIF write cycle time (EW = 1) (WS+WST+WH (WS+WST+WH ns
(WS+WST+WH
+( EWC*16))*E +( EWC*16))*E
+(E WC*16))*E
-3 + 3
16 tsu(EMCEL-EMWEL) Output setup time, EMIFnCS[4:2] ns
(WS)*E -4 (WS)*E (WS)*E + 3
low to EMIFnWE low (SS = 0)
Output setup time, EMIFnCS[4:2] ns
-4 0 +3
low to EMIFnWE low (SS = 1)
17 th(EMWEH-EMCEH) Output hold time, EMIFnWE high ns
(WH)*E-4 (WH)*E (WH)*E+3
to EMIFnCS[4:2] high (SS = 0)
Output hold time, EMIFnWE high ns
-4 0 +3
to EMIFCS[4:2] high (SS = 1)
18 tsu(EMDQMV-EMWEL) Output setup time, EMIFBA[1:0] ns
(WS)*E-4 (WS)*E (WS)*E+3
valid to EMIFnWE low
19 th(EMWEH-EMDQMIV) Output hold time, EMIFnWE high ns
(WH)*E-4 (WH)*E (WH)*E+3
to EMIFBA[1:0] invalid
20 tsu(EMBAV-EMWEL) Output setup time, EMIFBA[1:0] ns
(WS)*E-4 (WS)*E (WS)*E+3
valid to EMIFnWE low
21 th(EMWEH-EMBAIV) Output hold time, EMIFnWE high ns
(WH)*E-4 (WH)*E (WH)*E+3
to EMIFBA[1:0] invalid
22 tsu(EMAV-EMWEL) Output setup time, ns
EMIFADDR[21:0] valid to (WS)*E-4 (WS)*E (WS)*E+3
EMIFnWE low
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EMIF_CLK
EMIF_BA[1:0]
EMIF_ADDR[21:0]
EMIF_DATA[15:0]
1
2 2
4
6
8
8
12
14
19
20
3
5
7
7
11
13
17 18
2 EM_CLK Delay
BASIC SDRAM
READ OPERATION
EMIF_nCS[0]
EMIF_nDQM[1:0]
EMIF_nRAS
EMIF_nCAS
EMIF_nWE
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Table 6-28. EMIF Asynchronous Memory Switching Characteristics(1)(2)(3) (continued)
NO. PARAMETER MIN NOM MAX UNIT
23 th(EMWEH-EMAIV) Output hold time, EMIFnWE high ns
(WH)*E-4 (WH)*E (WH)*E+3
to EMIFADDR[21:0] invalid
24 tw(EMWEL) EMIFnWE active low width (EW ns
(WST)*E-3 (WST)*E (WST)*E+3
= 0)
EMIFnWE active low width (EW (WST+(EWC*16 (WST+(EWC*16 (WST+(EWC*16 ns
= 1) )) *E-3 ))*E )) *E+3
25 td(EMWAITH-EMWEH) Delay time from EMIFnWAIT ns
3E-4 4E 4E+30
deasserted to EMIFnWE high
26 tsu(EMDV-EMWEL) Output setup time, ns
EMIFDATA[15:0] valid to (WS)*E-4 (WS)*E (WS)*E+3
EMIFnWE low
27 th(EMWEH-EMDIV) Output hold time, EMIFnWE high ns
(WH)*E-4 (WH)*E (WH)*E+3
to EMIFDATA[15:0] invalid
31 tsu(EMDQMV-EMWEL) Output setup time, ns
EMIFnDQM[1:0] valid to (WH)*E-4 (WH)*E (WH)*E+3
EMIFnWE low
32 th(EMWEH-EMDQMIV) Output hold time, EMIFnWE high ns
(WH)*E-4 (WH)*E (WH)*E+3
to EMIFnDQM[1:0] invalid
6.14.2.2 Synchronous Timing
Figure 6-17. Basic SDRAM Read Operation
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EMIF_CLK
EMIF_BA[1:0]
EMIF_ADDR[21:0]
EMIF_DATA[15:0]
1
2 2
4
6
8
8
12
10
16
3
5
7
7
11
13
15
9
BASIC SDRAM
WRITE OPERATION
EMIF_CS[0]
EMIF_DQM[1:0]
EMIF_nRAS
EMIF_nCAS
EMIF_nWE
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Figure 6-18. Basic SDRAM Write Operation
Table 6-29. EMIF Synchronous Memory Timing Requirements
NO. MIN MAX UNIT
Input setup time, read data valid on
19 tsu(EMIFDV-EM_CLKH) 2 ns
EMIFDATA[15:0] before EMIF_CLK rising
Input hold time, read data valid on
20 th(CLKH-DIV) 1.5 ns
EMIFDATA[15:0] after EMIF_CLK rising
Table 6-30. EMIF Synchronous Memory Switching Characteristics
NO. PARAMETER MIN MAX UNIT
1 tc(CLK) Cycle time, EMIF clock EMIF_CLK 20 ns
2 tw(CLK) Pulse width, EMIF clock EMIF_CLK high or low 5 ns
3 td(CLKH-CSV) Delay time, EMIF_CLK rising to EMIFnCS[0] valid 13 ns
Output hold time, EMIF_CLK rising to EMIFnCS[0]
4 toh(CLKH-CSIV) 1 ns
invalid
Delay time, EMIF_CLK rising to EMIFnDQM[1:0]
5 td(CLKH-DQMV) 13 ns
valid
Output hold time, EMIF_CLK rising to
6 toh(CLKH-DQMIV) 1 ns
EMIFnDQM[1:0] invalid
Delay time, EMIF_CLK rising to EMIFADDR[21:0]
7 td(CLKH-AV) 13 ns
and EMIFBA[1:0] valid
Output hold time, EMIF_CLK rising to
8 toh(CLKH-AIV) 1 ns
EMIFADDR[21:0] and EMIFBA[1:0] invalid
Delay time, EMIF_CLK rising to EMIFDATA[15:0]
9 td(CLKH-DV) 13 ns
valid
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Table 6-30. EMIF Synchronous Memory Switching Characteristics (continued)
NO. PARAMETER MIN MAX UNIT
Output hold time, EMIF_CLK rising to
10 toh(CLKH-DIV) 1 ns
EMIFDATA[15:0] invalid
11 td(CLKH-RASV) Delay time, EMIF_CLK rising to EMIFnRAS valid 13 ns
Output hold time, EMIF_CLK rising to EMIFnRAS
12 toh(CLKH-RASIV) 1 ns
invalid
13 td(CLKH-CASV) Delay time, EMIF_CLK rising to EMIFnCAS valid 13 ns
Output hold time, EMIF_CLK rising to EMIFnCAS
14 toh(CLKH-CASIV) 1 ns
invalid
15 td(CLKH-WEV) Delay time, EMIF_CLK rising to EMIFnWE valid 13 ns
Output hold time, EMIF_CLK rising to EMIFnWE
16 toh(CLKH-WEIV) 1 ns
invalid
Delay time, EMIF_CLK rising to EMIFDATA[15:0]
17 tdis(CLKH-DHZ) 7 ns
tri-stated
Output hold time, EMIF_CLK rising to
18 tena(CLKH-DLZ) 1 ns
EMIFDATA[15:0] driving
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6.15 Vectored Interrupt Manager
The vectored interrupt manager (VIM) provides hardware assistance for prioritizing and controlling the
many interrupt sources present on this device. Interrupts are caused by events outside of the normal flow
of program execution. Normally, these events require a timely response from the central processing unit
(CPU); therefore, when an interrupt occurs, the CPU switches execution from the normal program flow to
an interrupt service routine (ISR).
6.15.1 VIM Features
The VIM module has the following features:
• Supports 96 interrupt channels.
– Provides programmable priority and enable for interrupt request lines.
• Provides a direct hardware dispatch mechanism for fastest IRQ dispatch.
• Provides two software dispatch mechanisms when the CPU VIC port is not used.
– Index interrupt
– Register vectored interrupt
• Parity protected vector interrupt table
6.15.2 Interrupt Request Assignments
Table 6-31. Interrupt Request Assignments
DEFAULT VIM
MODULES INTERRUPT SOURCES INTERRUPT CHANNEL
ESM ESM High level interrupt (NMI) 0
Reserved Reserved 1
RTI RTI compare interrupt 0 2
RTI RTI compare interrupt 1 3
RTI RTI compare interrupt 2 4
RTI RTI compare interrupt 3 5
RTI RTI overflow interrupt 0 6
RTI RTI overflow interrupt 1 7
RTI RTI timebase interrupt 8
GPIO GPIO interrupt A 9
N2HET1 N2HET1 level 0 interrupt 10
HTU1 HTU1 level 0 interrupt 11
MIBSPI1 MIBSPI1 level 0 interrupt 12
LIN LIN level 0 interrupt 13
MIBADC1 MIBADC1 event group interrupt 14
MIBADC1 MIBADC1 sw group 1 interrupt 15
DCAN1 DCAN1 level 0 interrupt 16
SPI2 SPI2 level 0 interrupt 17
FlexRay FlexRay level 0 interrupt 18
CRC CRC Interrupt 19
ESM ESM Low level interrupt 20
SYSTEM Software interrupt (SSI) 21
CPU PMU Interrupt 22
GPIO GPIO interrupt B 23
N2HET1 N2HET1 level 1 interrupt 24
HTU1 HTU1 level 1 interrupt 25
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Table 6-31. Interrupt Request Assignments (continued)
DEFAULT VIM
MODULES INTERRUPT SOURCES INTERRUPT CHANNEL
MIBSPI1 MIBSPI1 level 1 interrupt 26
LIN LIN level 1 interrupt 27
MIBADC1 MIBADC1 sw group 2 interrupt 28
DCAN1 DCAN1 level 1 interrupt 29
SPI2 SPI2 level 1 interrupt 30
MIBADC1 MIBADC1 magnitude compare interrupt 31
FlexRay FlexRay level 1 interrupt 32
DMA FTCA interrupt 33
DMA LFSA interrupt 34
DCAN2 DCAN2 level 0 interrupt 35
DMM DMM level 0 interrupt 36
MIBSPI3 MIBSPI3 level 0 interrupt 37
MIBSPI3 MIBSPI3 level 1 interrupt 38
DMA HBCA interrupt 39
DMA BTCA interrupt 40
EMIF AEMIFINT3 41
DCAN2 DCAN2 level 1 interrupt 42
DMM DMM level 1 interrupt 43
DCAN1 DCAN1 IF3 interrupt 44
DCAN3 DCAN3 level 0 interrupt 45
DCAN2 DCAN2 IF3 interrupt 46
FPU "OR" of the six Cortex R4F FPU Exceptions 47
FTU FTU Transfer Status interrupt 48
SPI4 SPI4 level 0 interrupt 49
MIBADC2 MibADC2 event group interrupt 50
MIBADC2 MibADC2 sw group1 interrupt 51
FlexRay FlexRay T0C interrupt 52
MIBSPI5 MIBSPI5 level 0 interrupt 53
SPI4 SPI4 level 1 interrupt 54
DCAN3 DCAN3 level 1 interrupt 55
MIBSPI5 MIBSPI5 level 1 interrupt 56
MIBADC2 MibADC2 sw group2 interrupt 57
FTU FTU Error interrupt 58
MIBADC2 MibADC2 magnitude compare interrupt 59
DCAN3 DCAN3 IF3 interrupt 60
FMC FSM_DONE interrupt 61
FlexRay FlexRay T1C interrupt 62
N2HET2 N2HET2 level 0 interrupt 63
SCI SCI level 0 interrupt 64
HTU2 HTU2 level 0 interrupt 65
I2C I2C level 0 interrupt 66
Reserved Reserved 67-72
N2HET2 N2HET2 level 1 interrupt 73
SCI SCI level 1 interrupt 74
HTU2 HTU2 level 1 interrupt 75
Reserved Reserved 76-79
HWAG1 HWA_INT_REQ_H 80
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Table 6-31. Interrupt Request Assignments (continued)
DEFAULT VIM
MODULES INTERRUPT SOURCES INTERRUPT CHANNEL
HWAG2 HWA_INT_REQ_H 81
DCC1 DCC1 done interrupt 82
DCC2 DCC2 done interrupt 83
Reserved Reserved 84
PBIST PBIST_DONE 85
Reserved Reserved 86
Reserved Reserved 87
HWAG1 HWA_INT_REQ_L 88
HWAG2 HWA_INT_REQ_L 89
Reserved Reserved 90-95
NOTE
Address location 0x00000000 in the VIM RAM is reserved for the phantom interrupt ISR
entry; therefore only request channels 0..94 can be used and are offset by 1 address in the
VIM RAM.
NOTE
The EMIF_nWAIT signal has a pullup on it. The EMIF module generates a "Wait Rise"
interrupt whenever it detects a rising edge on the EMIF_nWAIT signal. This interrupt
condition is indicated as soon as the device is powered up. This can be ignored if the
EMIF_nWAIT signal is not used in the application. If the EMIF_nWAIT signal is actually used
in the application, then the external slave memory must always drive the EMIF_nWAIT signal
such that an interrupt is not caused due to the default pullup on this signal.
NOTE
The lower-order interrupt channels are higher priority channels than the higher-order interrupt
channels.
NOTE
The application can change the mapping of interrupt sources to the interrupt channels via the
interrupt channel control registers (CHANCTRLx) inside the VIM module.
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6.16 DMA Controller
The DMA controller is used to transfer data between two locations in the memory map in the background
of CPU operations. Typically, the DMA is used to:
• Transfer blocks of data between external and internal data memories
• Restructure portions of internal data memory
• Continually service a peripheral
6.16.1 DMA Features
• CPU independent data transfer
• One master port - PortB (64 bits wide) that interfaces to the TMS570 Memory System.
• FIFO buffer(4 entries deep and each 64 bits wide)
• Channel control information is stored in RAM protected by parity
• 16 channels with individual enable
• Channel chaining capability
• 32 peripheral DMA requests
• Hardware and Software DMA requests
• 8-, 16-, 32-, or 64-bit transactions supported
• Multiple addressing modes for source/destination (fixed, increment, offset)
• Auto-initiation
• Power-management mode
• Memory Protection with four configurable memory regions
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6.16.2 Default DMA Request Map
The DMA module on this microcontroller has 16 channels and up to 32 hardware DMA requests. The
module contains DREQASIx registers which are used to map the DMA requests to the DMA channels. By
default, channel 0 is mapped to request 0, channel 1 to request 1, and so on.
Some DMA requests have multiple sources, as shown in Table 6-32. The application must ensure that
only one of these DMA request sources is enabled at any time.
Table 6-32. DMA Request Line Connection
Modules DMA Request Sources DMA Request
MIBSPI1 MIBSPI1[1](1) DMAREQ[0]
MIBSPI1 MIBSPI1[0](2) DMAREQ[1]
SPI2 SPI2 receive DMAREQ[2]
SPI2 SPI2 transmit DMAREQ[3]
MIBSPI1 / MIBSPI3 / DCAN2 MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3 DMAREQ[4]
MIBSPI1 / MIBSPI3 / DCAN2 MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2 DMAREQ[5]
DCAN1 / MIBSPI5 DCAN1 IF2 / MIBSPI5[2] DMAREQ[6]
MIBADC1 / MIBSPI5 MIBADC1 event / MIBSPI5[3] DMAREQ[7]
MIBSPI1 / MIBSPI3 / DCAN1 MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1 DMAREQ[8]
MIBSPI1 / MIBSPI3 / DCAN2 MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1 DMAREQ[9]
MIBADC1 / I2C / MIBSPI5 MIBADC1 G1 / I2C receive / MIBSPI5[4] DMAREQ[10]
MIBADC1 / I2C / MIBSPI5 MIBADC1 G2 / I2C transmit / MIBSPI5[5] DMAREQ[11]
RTI / MIBSPI1 / MIBSPI3 RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6] DMAREQ[12]
RTI / MIBSPI1 / MIBSPI3 RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7] DMAREQ[13]
MIBSPI3 / MibADC2 / MIBSPI5 MIBSPI3[1](1) / MibADC2 event / MIBSPI5[6] DMAREQ[14]
MIBSPI3 / MIBSPI5 MIBSPI3[0](2) / MIBSPI5[7] DMAREQ[15]
MIBSPI1 / MIBSPI3 / DCAN1 / MibADC2 MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1 DMAREQ[16]
MIBSPI1 / MIBSPI3 / DCAN3 / MibADC2 MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2 DMAREQ[17]
RTI / MIBSPI5 RTI DMAREQ2 / MIBSPI5[8] DMAREQ[18]
RTI / MIBSPI5 RTI DMAREQ3 / MIBSPI5[9] DMAREQ[19]
N2HET1 / N2HET2 / DCAN3 N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3 DMAREQ[20]
IF2
N2HET1 / N2HET2 / DCAN3 N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3 DMAREQ[21]
IF3
MIBSPI1 / MIBSPI3 / MIBSPI5 MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10] DMAREQ[22]
MIBSPI1 / MIBSPI3 / MIBSPI5 MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11] DMAREQ[23]
N2HET1 / N2HET2 / SPI4 / MIBSPI5 N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 DMAREQ[24]
receive / MIBSPI5[12]
N2HET1 / N2HET2 / SPI4 / MIBSPI5 N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 DMAREQ[25]
transmit / MIBSPI5[13]
CRC / MIBSPI1 / MIBSPI3 CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12] DMAREQ[26]
CRC / MIBSPI1 / MIBSPI3 CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13] DMAREQ[27]
LIN / MIBSPI5 LIN receive / MIBSPI5[14] DMAREQ[28]
LIN / MIBSPI5 LIN transmit / MIBSPI5[15] DMAREQ[29]
MIBSPI1 / MIBSPI3 / SCI / MIBSPI5 MIBSPI1[14] / MIBSPI3[14] / SCI receive / DMAREQ[30]
MIBSPI5[1](1)
MIBSPI1 / MIBSPI3 / SCI / MIBSPI5 MIBSPI1[15] / MIBSPI3[15] / SCI transmit / DMAREQ[31]
MIBSPI5[0](2)
(1) SPI1, SPI3, SPI5 receive in compatibility mode
(2) SPI1, SPI3, SPI5 transmit in compatibility mode
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310
310
RTICLK
310
310
310
External
control
CAP eventsource0
CAP eventsource1
=
Upcounter
Capture
upcounter
Compare
upcounter
Freerunningcounter
Capture
RTIFRCx
freerunningcounter
RTICAFRCx
OVLINTx
RTICPUCx
RTIUCx
RTICAUCx
ToCompare
Unit
NTU0
NTU1
NTU2
NTU3
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6.17 Real Time Interrupt Module
The real-time interrupt (RTI) module provides timer functionality for operating systems and for
benchmarking code. The RTI module can incorporate several counters that define the timebases needed
for scheduling an operating system.
The timers also allow you to benchmark certain areas of code by reading the values of the counters at the
beginning and the end of the desired code range and calculating the difference between the values.
In addition the RTI provides a mechanism to synchronize the operating system to the FlexRay
communication cycle. Clock supervision can detect issues on the FlexRay bus with an automatic switch to
an internally generated timebase.
6.17.1 Features
The RTI module has the following features:
• Two independent 64 bit counter blocks
• Four configurable compares for generating operating system ticks or DMA requests. Each event can
be driven by either counter block 0 or counter block 1.
• One counter block usable for application synchronization to FlexRay network including clock
supervision
• Fast enabling/disabling of events
• Two time-stamp (capture) functions for system or peripheral interrupts, one for each counter block
6.17.2 Block Diagrams
Figure 6-19 shows a high-level block diagram for one of the two 64-bit counter blocks inside the RTI
module. Both the counter blocks are identical except the Network Time Unit (NTUx) inputs are only
available as time base inputs for the counter block 0.
Figure 6-19. Counter Block Diagram
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31 0
Compare
control
INTy
DMAREQy
Compare
Update
compare
From counter
block 0
From counter
block 1
RTIUDCPy
RTICOMPy
31 0
=
+
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Figure 6-20. Compare Block Diagram
6.17.3 Clock Source Options
The RTI module uses the RTI1CLK clock domain for generating the RTI time bases.
The application can select the clock source for the RTI1CLK by configuring the RCLKSRC register in the
System module at address 0xFFFFFF50. The default source for RTI1CLK is VCLK.
For more information on clock sources refer to Table 6-8 and Table 6-13.
6.17.4 Network Time Synchronization Inputs
The RTI module supports 4 Network Time Unit (NTU) inputs that signal internal system events, and which
can be used to synchronize the time base used by the RTI module. On this device, these NTU inputs are
connected as shown in Table 6-33.
Table 6-33. Network Time Synchronization Inputs
NTU Input Source
0 Macrotick
1 Start of Cycle
2 PLL2 Clock output
3 EXTCLKIN1 clock input
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6.18 Error Signaling Module
The Error Signaling Module (ESM) manages the various error conditions on the TMS570 microcontroller.
The error condition is handled based on a fixed severity level assigned to it. Any severe error condition
can be configured to drive a low level on a dedicated device terminal called nERROR. This can be used
as an indicator to an external monitor circuit to put the system into a safe state.
6.18.1 Features
The features of the Error Signaling Module are:
• 128 interrupt/error channels are supported, divided into 3 different groups
– 64 channels with maskable interrupt and configurable error pin behavior
– 32 error channels with nonmaskable interrupt and predefined error pin behavior
– 32 channels with predefined error pin behavior only
• Error pin to signal severe device failure
• Configurable timebase for error signal
• Error forcing capability
6.18.2 ESM Channel Assignments
The Error Signaling Module (ESM) integrates all the device error conditions and groups them in the order
of severity. Group1 is used for errors of the lowest severity while Group3 is used for errors of the highest
severity. The device response to each error is determined by the severity group it is connected to.
Table 6-35 shows the channel assignment for each group.
Table 6-34. ESM Groups
ERROR GROUP INTERRUPT CHARACTERISTICS INFLUENCE ON ERROR PIN
Group1 maskable, low or high priority configurable
Group2 nonmaskable, high priority fixed
Group3 no interrupt generated fixed
Table 6-35. ESM Channel Assignments
ERROR SOURCES GROUP CHANNELS
Reserved Group1 0
MibADC2 - parity Group1 1
DMA - MPU Group1 2
DMA - parity Group1 3
Reserved Group1 4
DMA/DMM - imprecise read error Group1 5
FMC - correctable error: bus1 and bus2 interfaces Group1 6
(does not include accesses to EEPROM bank)
N2HET1/N2HET2 - parity Group1 7
HTU1/HTU2 - parity Group1 8
HTU1/HTU2 - MPU Group1 9
PLL - Slip Group1 10
Clock Monitor - interrupt Group1 11
FlexRay - parity Group1 12
DMA/DMM - imprecise write error Group1 13
FTU - parity Group1 14
VIM RAM - parity Group1 15
FTU - MPU Group1 16
MibSPI1 - parity Group1 17
MibSPI3 - parity Group1 18
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Table 6-35. ESM Channel Assignments (continued)
ERROR SOURCES GROUP CHANNELS
MibADC1 - parity Group1 19
Reserved Group1 20
DCAN1 - parity Group1 21
DCAN3 - parity Group1 22
DCAN2 - parity Group1 23
MibSPI5 - parity Group1 24
Reserved Group1 25
RAM even bank (B0TCM) - correctable error Group1 26
CPU - selftest Group1 27
RAM odd bank (B1TCM) - correctable error Group1 28
Reserved Group1 29
DCC1 - error Group1 30
CCM-R4 - selftest Group1 31
Reserved Group1 32
Reserved Group1 33
Reserved Group1 34
FMC - correctable error (EEPROM bank access) Group1 35
FMC - uncorrectable error (EEPROM bank access) Group1 36
IOMM - Mux configuration error Group1 37
Power domain controller compare error Group1 38
Power domain controller self-test error Group1 39
eFuse Controller Error – this error signal is generated when any bit in the eFuse
controller error status register is set. The application can choose to generate an Group1 40
interrupt whenever this bit is set to service any eFuse controller error conditions.
eFuse Controller - Self Test Error. This error signal is generated only when a self
test on the eFuse controller generates an error condition. When an ECC self test Group1 41
error is detected, group 1 channel 40 error signal will also be set.
PLL2 - Slip Group1 42
Reserved Group1 43
Reserved Group1 44
Reserved Group1 45
Reserved Group1 46
Reserved Group1 47
Reserved Group1 48
Reserved Group1 49
Reserved Group1 50
Reserved Group1 51
Reserved Group1 52
Reserved Group1 53
Reserved Group1 54
Reserved Group1 55
Reserved Group1 56
Reserved Group1 57
Reserved Group1 58
Reserved Group1 59
Reserved Group1 60
Reserved Group1 61
DCC2 - error Group1 62
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Table 6-35. ESM Channel Assignments (continued)
ERROR SOURCES GROUP CHANNELS
Reserved Group1 63
GROUP 2
Reserved Group2 0
Reserved Group2 1
CCMR4 - compare Group2 2
Reserved Group2 3
FMC - uncorrectable error (address parity on bus1 accesses) Group2 4
Reserved Group2 5
RAM even bank (B0TCM) - uncorrectable error Group2 6
Reserved Group2 7
RAM odd bank (B1TCM) - uncorrectable error Group2 8
Reserved Group2 9
RAM even bank (B0TCM) - address bus parity error Group2 10
Reserved Group2 11
RAM odd bank (B1TCM) - address bus parity error Group2 12
Reserved Group2 13
Reserved Group2 14
Reserved Group2 15
TCM - ECC live lock detect Group2 16
Reserved Group2 17
Reserved Group2 18
Reserved Group2 19
Reserved Group2 20
Reserved Group2 21
Reserved Group2 22
Reserved Group2 23
RTI_WWD_NMI Group2 24
Reserved Group2 25
Reserved Group2 26
Reserved Group2 27
Reserved Group2 28
Reserved Group2 29
Reserved Group2 30
Reserved Group2 31
GROUP 3
Reserved Group3 0
eFuse Controller - autoload error Group3 1
Reserved Group3 2
RAM even bank (B0TCM) - ECC uncorrectable error Group3 3
Reserved Group3 4
RAM odd bank (B1TCM) - ECC uncorrectable error Group3 5
Reserved Group3 6
FMC - uncorrectable error: bus1 and bus2 interfaces Group3 7
(does not include address parity error and errors on accesses to EEPROM bank)
Reserved Group3 8
Reserved Group3 9
Reserved Group3 10
Reserved Group3 11
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Table 6-35. ESM Channel Assignments (continued)
ERROR SOURCES GROUP CHANNELS
Reserved Group3 12
Reserved Group3 13
Reserved Group3 14
Reserved Group3 15
Reserved Group3 16
Reserved Group3 17
Reserved Group3 18
Reserved Group3 19
Reserved Group3 20
Reserved Group3 21
Reserved Group3 22
Reserved Group3 23
Reserved Group3 24
Reserved Group3 25
Reserved Group3 26
Reserved Group3 27
Reserved Group3 28
Reserved Group3 29
Reserved Group3 30
Reserved Group3 31
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6.19 Reset / Abort / Error Sources
Table 6-36. Reset/Abort/Error Sources
ESM HOOKUP
ERROR SOURCE SYSTEM MODE ERROR RESPONSE group.channel
CPU TRANSACTIONS
Precise write error (NCNB/Strongly Ordered) User/Privilege Precise Abort (CPU) n/a
Precise read error (NCB/Device or Normal) User/Privilege Precise Abort (CPU) n/a
Imprecise write error (NCB/Device or Normal) User/Privilege Imprecise Abort (CPU) n/a
Undefined Instruction Trap
Illegal instruction User/Privilege n/a
(CPU)(1)
MPU access violation User/Privilege Abort (CPU) n/a
SRAM
B0 TCM (even) ECC single error (correctable) User/Privilege ESM 1.26
Abort (CPU), ESM =>
B0 TCM (even) ECC double error (noncorrectable) User/Privilege 3.3
nERROR
B0 TCM (even) uncorrectable error (for example, redundant User/Privilege ESM => NMI => nERROR 2.6
address decode)
B0 TCM (even) address bus parity error User/Privilege ESM => NMI => nERROR 2.10
B1 TCM (odd) ECC single error (correctable) User/Privilege ESM 1.28
Abort (CPU), ESM =>
B1 TCM (odd) ECC double error (noncorrectable) User/Privilege 3.5
nERROR
B1 TCM (odd) uncorrectable error (for example, redundant User/Privilege ESM => NMI => nERROR 2.8
address decode)
B1 TCM (odd) address bus parity error User/Privilege ESM => NMI => nERROR 2.12
FLASH
FMC correctable error - Bus1 and Bus2 interfaces (does not User/Privilege ESM 1.6
include accesses to EEPROM bank)
FMC uncorrectable error - Bus1 accesses Abort (CPU), ESM =>
User/Privilege 3.7
(does not include address parity error) nERROR
FMC uncorrectable error - Bus2 accesses
(does not include address parity error and EEPROM bank User/Privilege ESM => nERROR 3.7
accesses)
FMC uncorrectable error - address parity error on Bus1 User/Privilege ESM => NMI => nERROR 2.4
accesses
FMC correctable error - Accesses to EEPROM bank User/Privilege ESM 1.35
FMC uncorrectable error - Accesses to EEPROM bank User/Privilege ESM 1.36
DMA TRANSACTIONS
External imprecise error on read (Illegal transaction with ok User/Privilege ESM 1.5
response)
External imprecise error on write (Illegal transaction with ok User/Privilege ESM 1.13
response)
Memory access permission violation User/Privilege ESM 1.2
Memory parity error User/Privilege ESM 1.3
DMM TRANSACTIONS
External imprecise error on read (Illegal transaction with ok User/Privilege ESM 1.5
response)
External imprecise error on write (Illegal transaction with ok User/Privilege ESM 1.13
response)
HTU1
NCNB (Strongly Ordered) transaction with slave error response User/Privilege Interrupt => VIM n/a
External imprecise error (Illegal transaction with ok response) User/Privilege Interrupt => VIM n/a
Memory access permission violation User/Privilege ESM 1.9
(1) The Undefined Instruction TRAP is NOT detectable outside the CPU. The trap is taken only if the instruction reaches the execute stage
of the CPU.
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Table 6-36. Reset/Abort/Error Sources (continued)
ESM HOOKUP
ERROR SOURCE SYSTEM MODE ERROR RESPONSE group.channel
Memory parity error User/Privilege ESM 1.8
HTU2
NCNB (Strongly Ordered) transaction with slave error response User/Privilege Interrupt => VIM n/a
External imprecise error (Illegal transaction with ok response) User/Privilege Interrupt => VIM n/a
Memory access permission violation User/Privilege ESM 1.9
Memory parity error User/Privilege ESM 1.8
N2HET1
Memory parity error User/Privilege ESM 1.7
N2HET2
Memory parity error User/Privilege ESM 1.7
FLEXRAY
Memory parity error User/Privilege ESM 1.12
FTU
NCNB (Strongly Ordered) transaction with slave error response User/Privilege Interrupt => VIM n/a
External imprecise error (Illegal transaction with ok response) User/Privilege Interrupt => VIM n/a
Memory access permission violation User/Privilege ESM 1.16
Memory parity error User/Privilege ESM 1.14
MIBSPI
MibSPI1 memory parity error User/Privilege ESM 1.17
MibSPI3 memory parity error User/Privilege ESM 1.18
MibSPI5 memory parity error User/Privilege ESM 1.24
MIBADC
MibADC1 Memory parity error User/Privilege ESM 1.19
MibADC2 Memory parity error User/Privilege ESM 1.1
DCAN
DCAN1 memory parity error User/Privilege ESM 1.21
DCAN2 memory parity error User/Privilege ESM 1.23
DCAN3 memory parity error User/Privilege ESM 1.22
PLL
PLL slip error User/Privilege ESM 1.10
PLL #2 slip error User/Privilege ESM 1.42
CLOCK MONITOR
Clock monitor interrupt User/Privilege ESM 1.11
DCC
DCC1 error User/Privilege ESM 1.30
DCC2 error User/Privilege ESM 1.62
CCM-R4
Self test failure User/Privilege ESM 1.31
Compare failure User/Privilege ESM => NMI => nERROR 2.2
VIM
Memory parity error User/Privilege ESM 1.15
VOLTAGE MONITOR
VMON out of voltage range n/a Reset n/a
CPU SELFTEST (LBIST)
CPU Selftest (LBIST) error User/Privilege ESM 1.27
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Table 6-36. Reset/Abort/Error Sources (continued)
ESM HOOKUP
ERROR SOURCE SYSTEM MODE ERROR RESPONSE group.channel
PIN MULTIPLEXING CONTROL
Mux configuration error User/Privilege ESM 1.37
POWER DOMAIN CONTROL
PSCON compare error User/Privilege ESM 1.38
PSCON self-test error User/Privilege ESM 1.39
eFuse CONTROLLER
eFuse Controller Autoload error User/Privilege ESM => nERROR 3.1
eFuse Controller - Any bit set in the error status register User/Privilege ESM 1.40
eFuse Controller self-test error User/Privilege ESM 1.41
WINDOWED WATCHDOG
WWD Nonmaskable Interrupt exception n/a ESM => NMI => nERROR 2.24
ERRORS REFLECTED IN THE SYSESR REGISTER
Power-Up Reset n/a Reset n/a
Oscillator fail / PLL slip(2) n/a Reset n/a
Watchdog exception n/a Reset n/a
CPU Reset (driven by the CPU STC) n/a Reset n/a
Software Reset n/a Reset n/a
External Reset n/a Reset n/a
(2) Oscillator fail/PLL slip can be configured in the system register (SYS.PLLCTL1) to generate a reset.
6.20 Digital Windowed Watchdog
This device includes a digital windowed watchdog (DWWD) module that protects against runaway code
execution.
The DWWD module allows the application to configure the time window within which the DWWD module
expects the application to service the watchdog. A watchdog violation occurs if the application services the
watchdog outside of this window, or fails to service the watchdog at all. The application can choose to
generate a system reset or a nonmaskable interrupt to the CPU in case of a watchdog violation.
The watchdog is disabled by default and must be enabled by the application. Once enabled, the watchdog
can only be disabled upon a system reset.
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TRST
TMS
TCK
TDI
TDO
RTCK
ICEPICK_C
BoundaryScan
BSR/BSDL
BoundaryScanI/F
SecondaryTap0 DAP
Debug APB
Debug
ROM1
APBslave
Cortex
R4F
APBMux
AHB-AP
POM ETM TPIU
toSCR1via A2A from
PCR1/Bridge
SecondaryTap1
DMM
RTP
TAP 0
TAP 1
SecondaryTap2 AJSM
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6.21 Debug Subsystem
6.21.1 Block Diagram
The device contains an ICEPICK module to allow JTAG access to the scan chains.
Figure 6-21. Debug Subsystem Block Diagram
NOTE
The ETM, RTP and DMM exist in silicon, but are not supported in the PGE package.
6.21.2 Debug Components Memory Map
Table 6-37. Debug Components Memory Map
FRAME ADDRESS RANGE RESPONSE FOR ACCESS TO
FRAME CHIP FRAME ACTUAL
MODULE NAME UNIMPLEMENTED LOCATIONS IN
SELECT SIZE SIZE
START END FRAME
CoreSight Debug CSCS0 0xFFA00000 0xFFA00FFF 4KB 4KB Reads: 0, writes: no effect
ROM
Cortex-R4F CSCS1 0xFFA01000 0xFFA01FFF 4KB 4KB Reads: 0, writes: no effect
Debug
ETM-R4 CSCS2 0xFFA02000 0xFFA02FFF 4KB 4KB Reads: 0, writes: no effect
CoreSight TPIU CSCS3 0xFFA03000 0xFFA03FFF 4KB 4KB Reads: 0, writes: no effect
6.21.3 JTAG Identification Code
The JTAG ID code for this device is the same as the device ICEPick Identification Code.
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Table 6-38. JTAG ID Code
SILICON REVISION ID
Rev A 0x0B8A002F
Rev B 0x2B8A002F
Rev C 0x3B8A002F
Rev D 0x4B8A002F
6.21.4 Debug ROM
The Debug ROM stores the location of the components on the Debug APB bus:
Table 6-39. Debug ROM table
ADDRESS DESCRIPTION VALUE
0x000 pointer to Cortex-R4F 0x00001003
0x001 ETM-R4 0x00002003
0x002 TPIU 0x00003003
0x003 POM 0x00004003
0x004 end of table 0x00000000
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11
2
3
4
5
TMS
TDI
TDO
RTCK
TCK
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6.21.5 JTAG Scan Interface Timings
Table 6-40. JTAG Scan Interface Timing(1)
NO. PARAMETER MIN MAX UNIT
fTCK TCK frequency (at HCLKmax) 12 MHz
fRTCK RTCK frequency (at TCKmax and HCLKmax) 10 MHz
1 td(TCK -RTCK) Delay time, TCK to RTCK 24 ns
2 tsu(TDI/TMS - RTCKr) Setup time, TDI, TMS before RTCK rise (RTCKr) 26 ns
3 th(RTCKr -TDI/TMS) Hold time, TDI, TMS after RTCKr 0 ns
4 th(RTCKr -TDO) Hold time, TDO after RTCKf 0 ns
5 td(TCKf -TDO) Delay time, TDO valid after RTCK fall (RTCKf) 12 ns
(1) Timings for TDO are specified for a maximum of 50pF load on TDO
Figure 6-22. JTAG Timing
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H L H L H L L H
...
...
128-bitcomparator
H L L H H L L H
UNLOCK
FlashModuleOutput
OTP Contents
UnlockByScan
Register
InternalTie-Offs
(exampleonly)
(example)
LH H L L
InternalTie-Offs
(exampleonly)
L H H
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6.21.6 Advanced JTAG Security Module
This device includes an Advanced JTAG Security Module (AJSM) which provides maximum security to the
memory content of the device by letting users secure the device after programming.
Figure 6-23. AJSM Unlock
The device is unsecure by default by virtue of a 128-bit visible unlock code programmed in the OTP
address 0xF0000000.The OTP contents are XOR-ed with the "Unlock By Scan" register contents. The
outputs of these XOR gates are again combined with a set of secret internal tie-offs. The output of this
combinational logic is compared against a secret hard-wired 128-bit value. A match results in the
UNLOCK signal being asserted, so that the device is now unsecure.
A user can secure the device by changing at least one bit in the visible unlock code from 1 to 0. Changing
a 0 to 1 is not possible because the visible unlock code is stored in the One Time Programmable (OTP)
flash region. Also, changing all the 128 bits to zeros is not a valid condition and will permanently secure
the device.
Once secured, a user can unsecure the device by scanning an appropriate value into the "Unlock By
Scan" register of the AJSM module. The value to be scanned is such that the XOR of the OTP contents
and the Unlock-By-Scan register contents results in the original visible unlock code.
The Unlock-By-Scan register is reset only upon asserting power-on reset (nPORRST).
A secure device only permits JTAG accesses to the AJSM scan chain via the Secondary Tap # 2 of the
ICEPick module. All other secondary taps, test taps and the boundary scan interface are not accessible in
this state.
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tr(ETM)
th(ETM)
tl(ETM)
tf(ETM)
tcyc(ETM)
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6.21.7 Embedded Trace Macrocell (ETM-R4)
The device contains a ETM-R4 module with a 32-bit internal data port. The ETM-R4 module is connected
to a TPIU with a 32-bit data bus; the TPIU provides a 35-bit (32-bit data, 3-bit control) external interface
for trace. The ETM-R4 is CoreSight compliant and follows the ETM v3 specification; for more details see
ARM CoreSight ETM-R4 TRM specification.
6.21.7.1 ETM TRACECLKIN Selection
The ETM clock source can be selected as either VCLK or the external ETMTRACECLKIN pin. The
selection is done by the EXTCTLOUT[1:0] control bits of the TPIU; the default is '00'. The address of this
register is TPIU base address + 0x404.
Before you begin accessing TPIU registers, TPIU should be unlocked via coresight key and 1 or 2 should
be written to this register.
Table 6-41. TPIU / TRACECLKIN Selection
EXTCTLOUT[1:0] TPIU/TRACECLKIN
00 tied-zero
01 VCLK
10 ETMTRACECLKIN
11 tied-zero
6.21.7.2 Timing Specifications
Figure 6-24. ETMTRACECLKOUT Timing
Table 6-42. ETMTRACECLK Timing
PARAMETER MIN MAX UNIT
tcyc(ETM) Clock period t(HCLK) * 4 ns
tl(ETM) Low pulse width 20 ns
th(ETM) High pulse width 20 ns
tr(ETM) Clock and data rise time 3 ns
tf(ETM) Clock and data fall time 3 ns
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Figure 6-25. ETMDATA Timing
Table 6-43. ETMDATA Timing
PARAMETER MIN MAX UNIT
Delay time, ETM trace clock high to ETM
td(ETMTRACECLKH-ETMDATAV) 1.5 7 ns
data valid
Delay time, ETM trace clock low to ETM
td(ETMTRACECLKl-ETMDATAV) 1.5 7 ns
data valid
NOTE
The ETMTRACECLK and ETMDATA timing is based on a 15-pF load and for ambient
temperature lower than 85°C.
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tcyc(RTP)
trtf
th(RTP)
tl(RTP)
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6.21.8 RAM Trace Port (RTP)
The RTP provides the ability to datalog the RAM contents of the TMS570 devices or accesses to
peripherals without program intrusion. It can trace all data write or read accesses to internal RAM. In
addition, it provides the capability to directly transfer data to a FIFO to support a CPU-controlled
transmission of the data. The trace data is transmitted over a dedicated external interface.
6.21.8.1 Features
The RTP offers the following features:
• Two modes of operation - Trace Mode and Direct Data Mode
– Trace Mode
• Nonintrusive data trace on write or read operation
• Visibility of RAM content at any time on external capture hardware
• Trace of peripheral accesses
• 2 configurable trace regions for each RAM module to limit amount of data to be traced
• FIFO to store data and address of data of multiple read/write operations
• Trace of CPU and/or DMA accesses with indication of the master in the transmitted data packet
– Direct Data Mode
• Directly write data with the CPU or trace read operations to a FIFO, without transmitting header
and address information
• Dedicated synchronous interface to transmit data to external devices
• Free-running clock generation or clock stop mode between transmissions
• Up to 100 Mbps/pin transfer rate for transmitting data
• Pins not used in functional mode can be used as GIOs
6.21.8.2 Timing Specifications
Figure 6-26. RTPCLK Timing
Table 6-44. RTPCLK Timing
PARAMETER MIN MAX UNIT
Clock period, prescaled from HCLK; must not be
tcyc(RTP) 11 (= 90 MHz) ns
faster than HCLK / 2
th(RTP) High pulse width ((tcyc(RTP))/2) - ((tr+tf)/2) ns
tl(RTP) Low pulse width ((tcyc(RTP))/2) - ((tr+tf)/2) ns
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HCLK
RTPCLK
RTPENA
RTPSYNC
RTPDATA
HCLK
RTPCLK
RTPENA
RTPSYNC
RTPDATA
tena(RTP)
tdis(RTP)
HCLK
RTPCLK
RTPnENA
RTPSYNC
RTPDATA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
d1 d2 d3 d4 d5 d6 d7 d8
Divide by 1
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Figure 6-27. RTPDATA Timing
Table 6-45. RTPDATA Timing
PARAMETER MIN MAX UNIT
td(RTPCLKH-RTPSYNCV) Delay time, RTPCLK high to RTPSYNC valid –5 4 ns
td(RTPCLKH-RTPDATAV) Delay time, RTPCLK high to RTPDATA valid –5 4 ns
Figure 6-28. RTPnENA Timing
Table 6-46. RTPnENA Timing
PARAMETER MIN MAX UNIT
time RTPnENA must go high before what would
tdis(RTP) be the next RTPSYNC, to ensure delaying the 3tc(HCLK) + tr(RTPSYNC) + 12 ns
next packet
time after RTPnENA goes low before a packet that
tena(RTP) 4tc(HCLK) + tr(RTPSYNC) 5tc(HCLK) + tr(RTPSYNC) + 12 ns
has been halted, resumes
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DMMSYNC
DMMCLK
DMMDATA
tssu(DMM) tsh(DMM)
tdsu(DMM) tdh(DMM)
tcyc(DMM)
trtf
th(DMM)
tl(DMM)
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6.21.9 Data Modification Module (DMM)
The Data Modification Module (DMM) provides the capability to modify data in the entire 4-GB address
space of the TMS570 devices from an external peripheral, with minimal interruption of the application.
6.21.9.1 Features
The DMM module has the following features:
• Acts as a bus master, thus enabling direct writes to the 4-GB address space without CPU intervention
• Writes to memory locations specified in the received packet (leverages packets defined by trace mode
of the RAM trace port (RTP) module
• Writes received data to consecutive addresses, which are specified by the DMM module (leverages
packets defined by direct data mode of RTP module)
• Configurable port width (1, 2, 4, 8, 16 pins)
• Up to 100 Mbit/s pin data rate
• Unused pins configurable as GPIO pins
6.21.9.2 Timing Specifications
Figure 6-29. DMMCLK Timing
Table 6-47. Timing Requirements for DMMCLK
MIN MAX UNIT
tcyc(DMM) Cycle time, DMMCLK period tc(HCLK) * 2 ns
th(DMM) Pulse duration, DMMCLK high ((tcyc(DMM))/2) - ((tr+tf)/2) ns
tl(DMM) Pulse duration, DMMCLK low ((tcyc(DMM))/2) - ((tr+tf)/2) ns
Figure 6-30. DMMDATA Timing
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HCLK
DMMCLK
DMMSYNC
DMMDATA
DMMnENA
D00 D01 D10 D11 D20 D21 D30 D31 D40 D41 D50
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Table 6-48. Timing Requirements for DMMDATA
MIN MAX UNIT
tssu(DMM) SYNC active to clk falling edge setup time 2 ns
tsh(DMM) clk falling edge to SYNC inactive hold time 3 ns
tdsu(DMM) DATA to clk falling edge setup time 2 ns
tdh(DMM) clk falling edge to DATA hold time 3 ns
Figure 6-31. DMMnENA Timing
Figure 6-31 shows a case with 1 DMM packet per 2 DMMCLK cycles (Mode = Direct Data Mode, data
width = 8, port width = 4) where none of the packets received by the DMM are sent out, leading to filling
up of the internal buffers. The DMMnENA signal is shown asserted, after the first two packets have been
received and synchronized to the HCLK domain. Here, the DMM has the capacity to accept packets D4x,
D5x, D6x, D7x. Packet D8 would result in an overflow. Once DMMnENA is asserted, the DMM expects to
stop receiving packets after 4 HCLK cycles; once DMMnENA is deasserted, the DMM can handle packets
immediately (after 0 HCLK cycles).
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TRST
TMS
TCK
TDI
TDO
RTCK
IC E PICK
Boundary
BSDL
Boundary Scan Interface Scan
Device Pins (conceptual)
TDI
TDO
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6.21.10 Boundary Scan Chain
The device supports IEEE1149.1-compliant boundary scan for testing pin-to-pin compatibility. The
boundary scan chain is connected to the Boundary Scan Interface of the ICEPICK module.
Figure 6-32. Boundary Scan Implementation (Conceptual Diagram)
Data is serially shifted into all boundary-scan buffers via TDI, and out via TDO.
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7 Peripheral Information and Electrical Specifications
7.1 Peripheral Legend
Table 7-1. Peripheral Legend
ABBREVIATION FULL NAME
MibADC Analog To Digital Converter
CCM-R4F CPU Compare Module - CortexR4F
CRC Cyclic Redundancy Check
DCAN Controller Area Network
DCC Dual Clock Comparator
DMA Direct Memory Access
DMM Data Modification Module
EMIF External Memory Interface
ESM Error Signaling Module
ETM-R4F Embedded Trace Macrocell - CortexR4F
FTU FlexRay Transfer Unit
GPIO General-Purpose Input/Output
HTU High End Timer Transfer Unit
I2C Inter-Integrated Circuit
LIN Local Interconnect Network
MIBSPI Multibuffer Serial Peripheral Interface
N2HET Platform High-End Timer
POM Parameter Overlay Module
RTI Real-Time Interrupt Module
RTP RAM Trace Port
SCI Serial Communications Interface
SPI Serial Peripheral Interface
VIM Vectored Interrupt Manager
7.2 Multibuffered 12-Bit Analog-to-Digital Converter
The multibuffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that
enhances the A-to-D performance by preventing digital switching noise on the logic circuitry which could
be present on VSS and VCC from coupling into the A-to-D analog stage. All A-to-D specifications are given
with respect to ADREFLO unless otherwise noted.
Table 7-2. MibADC Overview
DESCRIPTION VALUE
Resolution 12 bits
Monotonic Assured
Output conversion code 00h to FFFh [00 for VAI ≤ADREFLO; FFF for VAI ≥ADREFHI]
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7.2.1 Features
• 10-/12-bit resolution
• ADREFHI and ADREFLO pins (high and low reference voltages)
• Total Sample/Hold/Convert time: 600 ns Typical Minimum at 30 MHz ADCLK
• One memory region per conversion group is available (event, group 1, group 2)
• Allocation of channels to conversion groups is completely programmable
• Memory regions are serviced either by interrupt or by DMA
• Programmable interrupt threshold counter is available for each group
• Programmable magnitude threshold interrupt for each group for any one channel
• Option to read either 8-bit, 10-bit or 12-bit values from memory regions
• Single or continuous conversion modes
• Embedded self-test
• Embedded calibration logic
• Enhanced power-down mode
– Optional feature to automatically power down ADC core when no conversion is in progress
• External event pin (ADEVT) programmable as general-purpose I/O
7.2.2 Event Trigger Options
The ADC module supports 3 conversion groups: Event Group, Group1 and Group2. Each of these 3
groups can be configured to be hardware event-triggered. In that case, the application can select from
among 8 event sources to be the trigger for a group's conversions.
7.2.2.1 Default MIBADC1 Event Trigger Hookup
Table 7-3. MIBADC1 Event Trigger Hookup
Event # Source Select Bits For G1, G2 Or Event Trigger
(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])
1 000 ADEVT
2 001 N2HET1[8]
3 010 N2HET1[10]
4 011 RTI compare 0 interrupt
5 100 N2HET1[12]
6 101 N2HET1[14]
7 110 GIOB[0]
8 111 GIOB[1]
NOTE
For ADEVT, N2HET1 and GIOB trigger sources, the connection to the MibADC1 module
trigger input is made from the output side of the input buffer. This way, a trigger condition
can be generated either by configuring the function as output onto the pad (via the mux
control), or by driving the function from an external trigger source as input. If the mux control
module is used to select different functionality instead of the ADEVT, N2HET1[x] or GIOB[x]
signals, then care must be taken to disable these signals from triggering conversions; there
is no multiplexing on the input connections.
NOTE
For the RTI compare 0 interrupt source, the connection is made directly from the output of
the RTI module. That is, the interrupt condition can be used as a trigger source even if the
actual interrupt is not signaled to the CPU.
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7.2.2.2 Alternate MIBADC1 Event Trigger Hookup
Table 7-4. Alternate MIBADC1 Event Trigger Hookup
SOURCE SELECT BITS FOR G1, G2 OR EVENT
EVENT # TRIGGER
(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])
1 000 ADEVT
2 001 N2HET2[5]
3 010 N2HET1[27]
4 011 RTI compare 0 interrupt
5 100 N2HET1[17]
6 101 N2HET1[19]
7 110 N2HET1[11]
8 111 N2HET2[13]
The selection between the default MIBADC1 event trigger hook-up versus the alternate event trigger hook-
up is done by multiplexing control module register 30 bits 0 and 1.
If 30[0] = 1, then the default MibADC1 event trigger hook-up is used.
If 30[0] = 0 and 30[1] = 1, then the alternate MibADC1 event trigger hook-up is used.
NOTE
For ADEVT trigger source, the connection to the MibADC1 module trigger input is made from
the output side of the input buffer. This way, a trigger condition can be generated either by
configuring ADEVT as an output function on to the pad (via the mux control), or by driving
the ADEVT signal from an external trigger source as input. If the mux control module is used
to select different functionality instead of the ADEVT signal, then care must be taken to
disable ADEVT from triggering conversions; there is no multiplexing on the input connection.
NOTE
For N2HETx trigger sources, the connection to the MibADC1 module trigger input is made
from the input side of the output buffer (at the N2HETx module boundary). This way, a
trigger condition can be generated even if the N2HETx signal is not selected to be output on
the pad.
NOTE
For the RTI compare 0 interrupt source, the connection is made directly from the output of
the RTI module. That is, the interrupt condition can be used as a trigger source even if the
actual interrupt is not signaled to the CPU.
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7.2.2.3 Default MIBADC2 Event Trigger Hookup
Table 7-5. MIBADC2 Event Trigger Hookup
SOURCE SELECT BITS FOR G1, G2 OR EVENT
EVENT # TRIGGER
(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])
1 000 AD2EVT
2 001 N2HET1[8]
3 010 N2HET1[10]
4 011 RTI compare 0
5 100 N2HET1[12]
6 101 N2HET1[14]
7 110 GIOB[0]
8 111 GIOB[1]
NOTE
For AD2EVT, N2HET1 and GIOB trigger sources, the connection to the MibADC2 module
trigger input is made from the output side of the input buffer. This way, a trigger condition
can be generated either by configuring the function as output onto the pad (via the mux
control), or by driving the function from an external trigger source as input. If the mux control
module is used to select different functionality instead of the AD2EVT, N2HET1[x] or GIOB[x]
signals, then care must be taken to disable these signals from triggering conversions; there
is no multiplexing on the input connections.
NOTE
For the RTI compare 0 interrupt source, the connection is made directly from the output of
the RTI module. That is, the interrupt condition can be used as a trigger source even if the
actual interrupt is not signaled to the CPU.
7.2.2.4 Alternate MIBADC2 Event Trigger Hookup
Table 7-6. Alternate MIBADC2 Event Trigger Hookup
SOURCE SELECT BITS FOR G1, G2 OR EVENT
EVENT # TRIGGER
(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])
1 000 AD2EVT
2 001 N2HET2[5]
3 010 N2HET1[27]
4 011 RTI compare 0
5 100 N2HET1[17]
6 101 N2HET1[19]
7 110 N2HET1[11]
8 111 N2HET2[13]
The selection between the default MIBADC2 event trigger hook-up versus the alternate event trigger hook-
up is done by multiplexing control module register 30 bits 0 and 1.
If 30[0] = 1, then the default MibADC2 event trigger hook-up is used.
If 30[0] = 0 and 30[1] = 1, then the alternate MibADC2 event trigger hook-up is used.
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NOTE
For AD2EVT trigger source, the connection to the MibADC2 module trigger input is made
from the output side of the input buffer. This way, a trigger condition can be generated either
by configuring AD2EVT as an output function on to the pad (via the mux control), or by
driving the AD2EVT signal from an external trigger source as input. If the mux control module
is used to select different functionality instead of the AD2EVT signal, then care must be
taken to disable AD2EVT from triggering conversions; there is no multiplexing on the input
connections.
NOTE
For N2HETx trigger sources, the connection to the MibADC2 module trigger input is made
from the input side of the output buffer (at the N2HETx module boundary). This way, a
trigger condition can be generated even if the N2HETx signal is not selected to be output on
the pad.
NOTE
For the RTI compare 0 interrupt source, the connection is made directly from the output of
the RTI module. That is, the interrupt condition can be used as a trigger source even if the
actual interrupt is not signaled to the CPU.
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7.2.3 ADC Electrical and Timing Specifications
Table 7-7. MibADC Recommended Operating Conditions
PARAMETER MIN MAX UNIT
ADREFHI A-to-D high-voltage reference source ADREFLO VCCAD(1) V
ADREFLO A-to-D low-voltage reference source VSSAD(1) ADREFHI V
VAI Analog input voltage ADREFLO ADREFHI V
Analog input clamp current(2)
IAIK - 2 2 mA
(VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3)
(1) For VCCAD and VSSAD recommended operating conditions, see Section 5.4.
(2) Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.
Table 7-8. MibADC Electrical Characteristics Over Full Ranges of Recommended Operating Conditions
PARAMETER DESCRIPTION/CONDITIONS MIN MAX UNIT
Analog input mux on-
Rmux See Figure 7-1 250 Ω
resistance
ADC sample switch on-
Rsamp See Figure 7-1 250 Ω
resistance
Cmux Input mux capacitance See Figure 7-1 16 pF
Csamp ADC sample capacitance See Figure 7-1 13 pF
VSSAD ≤VIN < VSSAD + 100 mV –300 200
Analog off-state input leakage VCCAD = 3.6 V
IAIL VSSAD + 100 mV ≤VIN ≤VCCAD - 200 mV –200 200 nA
current maximum VCCAD - 200 mV < VIN ≤VCCAD –200 500
VSSAD ≤VIN < VSSAD + 300 mV –1000 250
Analog off-state input leakage VCCAD = 5.5 V
IAIL VSSAD + 300 mV ≤VIN ≤VCCAD - 300 mV –250 250 nA
current maximum VCCAD - 300 mV < VIN ≤VCCAD –250 1000
VSSAD ≤VIN < VSSAD + 100 mV –8 2
ADC1 Analog on-state input VCCAD = 3.6 V
IAOSB1(1) VSSAD + 100 mV < VIN < VCCAD - 200 mV –4 2 µA
bias current maximum VCCAD - 200 mV < VIN < VCCAD –4 12
VSSAD ≤VIN < VSSAD + 100 mV –7 2
ADC2 Analog on-state input VCCAD = 3.6 V
IAOSB2(1) VSSAD + 100 mV ≤VIN ≤VCCAD - 200 mV –4 2 µA
bias current maximum VCCAD - 200 mV < VIN ≤VCCAD –4 10
VSSAD ≤VIN < VSSAD + 300 mV –10 3
ADC1 Analog on-state input VCCAD = 5.5 V
IAOSB1(1) VSSAD + 300 mV ≤VIN ≤VCCAD - 300 mV –5 3 µA
bias current maximum VCCAD - 300 mV < VIN ≤VCCAD –5 14
VSSAD ≤VIN < VSSAD + 300 mV –8 3
ADC2 Analog on-state input VCCAD = 5.5 V
IAOSB2(1) VSSAD + 300 mV ≤VIN ≤VCCAD - 300 mV –5 3 µA
bias current maximum VCCAD - 300 mV < VIN ≤VCCAD –5 12
IADREFHI ADREFHI input current ADREFHI = VCCAD, ADREFLO = VSSAD 3 mA
Normal operating mode 15 mA
ICCAD Static supply current ADC core in power down mode 5 µA
(1) If a shared channel is being converted by both ADC converters at the same time, the on-state leakage is equal to IAOSL1 + IAOSL2
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VS1
On-State
Bias Current
Off-State
Leakages
VS2
VS24
IAOSB
IAIL
IAIL
Rext
Rext
Rext
Pin Smux Rmux
Pin Smux Rmux
Pin Smux Rmux Ssamp Rsamp
Csamp
Cext IAIL
IAIL IAIL
IAIL
Cmux
Cext
Cext
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Figure 7-1. MibADC Input Equivalent Circuit
Table 7-9. MibADC Timing Specifications
PARAMETER MIN NOM MAX UNIT
tc(ADCLK)(1) Cycle time, MibADC clock 0.033 µs
td(SH)(2) Delay time, sample and hold time 0.2 µs
td(PU-ADV) Delay time from ADC power on until first input can be sampled 1 µs
12-BIT MODE
td(c) Delay time, conversion time 0.4 µs
td(SHC)(3) Delay time, total sample/hold and conversion time 0.6 µs
10-BIT MODE
td(c) Delay time, conversion time 0.33 µs
td(SHC)(3) Delay time, total sample/hold and conversion time 0.53 µs
(1) The MibADC clock is the ADCLK, generated by dividing down the VCLK by a prescale factor defined by the ADCLOCKCR register bits
4:0.
(2) The sample and hold time for the ADC conversions is defined by the ADCLK frequency and the AD<GP>SAMP register for each
conversion group. The sample time needs to be determined by accounting for the external impedance connected to the input channel as
well as the ADC’s internal impedance.
(3) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors, for
example, the prescale settings.
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Table 7-10. MibADC Operating Characteristics Over Full Ranges of Recommended Operating Conditions
PARAMETER DESCRIPTION/CONDITIONS MIN NOM MAX UNIT
CR Conversion range over ADREFHI - ADREFLO
which specified accuracy is 3 5.5 V
maintained
ZSET Zero Scale Offset Difference between the first ideal transition 10-bit mode 1 LSB(1)
(from code 000h to 001h) and the actual 12-bit mode 2 LSB(2)
transition
FSET Full Scale Offset Difference between the range of the 10-bit mode 2 LSB
measured code transitions (from first to last) 12-bit mode 3 LSB
and the range of the ideal code transitions
EDNL Differential nonlinearity Difference between the actual step width and 10-bit mode ± 1.5 LSB
error the ideal value. (See Figure 76) 12-bit mode ± 2 LSB
EINL Integral nonlinearity error Maximum deviation from the best straight line 10-bit mode ± 2 LSB
through the MibADC. MibADC transfer
characteristics, excluding the quantization 12-bit mode ± 2 LSB
error.
ETOT Total unadjusted error Maximum value of the difference between an 10-bit mode ± 2 LSB
analog value and the ideal midstep value. 12-bit mode ± 4 LSB
(1) 1 LSB = (ADREFHI – ADREFLO)/ 210 for 10-bit mode
(2) 1 LSB = (ADREFHI – ADREFLO)/ 212 for 12-bit mode
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Differential Linearity
Error (–½ LSB)
1 LSB
1 LSB
Differential Linearity
Error (–½ LSB)
0 ... 110
0 ... 101
0 ... 100
0 ... 011
0 ... 010
0 ... 001
0 ... 000
01 2 345
Digital Output Code
Analog Input Value (LSB)
NOTE A: 1 LSB = (AD – AD )/2
REFHI REFLO
12
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7.2.4 Performance (Accuracy) Specifications
7.2.4.1 MibADC Nonlinearity Errors
The differential nonlinearity error shown in Figure 7-2 (sometimes referred to as differential linearity) is the
difference between an actual step width and the ideal value of 1 LSB.
Figure 7-2. Differential Nonlinearity (DNL) Error
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0 ... 111
0 ... 101
0 ... 100
0 ... 011
0 ... 010
0 ... 001
0 ... 000
01 2 345
Digital Output Code
Analog Input Value (LSB)
0 ... 110
67
At Transition
011/100
(–½ LSB)
At Transition
001/010 (–1/4 LSB)
Actual
Transition
Ideal
Transition
End-Point Lin. Error
NOTE A: 1 LSB = (AD – AD )/2
REFHI REFLO
12
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The integral nonlinearity error shown in Figure 7-3 (sometimes referred to as linearity error) is the
deviation of the values on the actual transfer function from a straight line.
Figure 7-3. Integral Nonlinearity (INL) Error
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0 ... 111
0 ... 101
0 ... 100
0 ... 011
0 ... 010
0 ... 001
0 ... 000
01 2 345
Digital Output Code
Analog Input Value (LSB)
0 ... 110
67
Total Error
At Step
0 ... 001 (1/2 LSB)
Total Error
At Step 0 ... 101
(–1 1/4 LSB)
NOTE A: 1 LSB = (AD – AD )/2
REFHI REFLO
12
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7.2.4.2 MibADC Total Error
The absolute accuracy or total error of an MibADC as shown in Figure 7-4 is the maximum value of the
difference between an analog value and the ideal midstep value.
Figure 7-4. Absolute Accuracy (Total) Error
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7.3 General-Purpose Input/Output
The GPIO module on this device supports two ports, GIOA and GIOB. The I/O pins are bidirectional and
bit-programmable. Both GIOA and GIOB support external interrupt capability.
7.3.1 Features
The GPIO module has the following features:
• Each IO pin can be configured as:
– Input
– Output
– Open Drain
• The interrupts have the following characteristics:
– Programmable interrupt detection either on both edges or on a single edge (set in GIOINTDET)
– Programmable edge-detection polarity, either rising or falling edge (set in GIOPOL register)
– Individual interrupt flags (set in GIOFLG register)
– Individual interrupt enables, set and cleared through GIOENASET and GIOENACLR registers
respectively
– Programmable interrupt priority, set through GIOLVLSET and GIOLVLCLR registers
• Internal pullup/pulldown allows unused I/O pins to be left unconnected
For information on input and output timings see Section 5.11 and Section 5.12
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N2HETx
3
4
2
1
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7.4 Enhanced High-End Timer (N2HET)
The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time
applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer
micromachine and an attached I/O port. The N2HET can be used for pulse width modulated outputs,
capture or compare inputs, or general-purpose I/O. It is especially well suited for applications requiring
multiple sensor information and drive actuators with complex and accurate time pulses.
7.4.1 Features
The N2HET module has the following features:
• Programmable timer for input and output timing functions
• Reduced instruction set (30 instructions) for dedicated time and angle functions
• 160 words of instruction RAM protected by parity
• User defined number of 25-bit virtual counters for timer, event counters and angle counters
• 7-bit hardware counters for some pins allow up to 32-bit resolution in conjunction with the 25-bit virtual
counters
• Up to 32 pins usable for input signal measurements or output signal generation
• Programmable suppression filter for each input pin with adjustable limiting frequency
• Low CPU overhead and interrupt load
• Efficient data transfer to or from the CPU memory with dedicated High-End-Timer Transfer Unit (HTU)
or DMA
• Diagnostic capabilities with different loopback mechanisms and pin status readback functionality
7.4.2 N2HET RAM Organization
The timer RAM uses 4 RAM banks, where each bank has two port access capability. This means that one
RAM address may be written while another address is read. The RAM words are 96 bits wide, which are
split into three 32-bit fields (program, control, and data).
7.4.3 Input Timing Specifications
The N2HET instructions PCNT and WCAP impose some timing constraints on the input signals.
Figure 7-5. N2HET Input Capture Timings
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Table 7-11. Input Timing Requirements for the N2HET Input Capture Functionality
NO. MIN(1) (2) MAX(1) (2) UNIT
Input signal period, PCNT or WCAP for rising edge to rising
1 2 (hr) (lr) tc(VCLK2) + 2 225 (hr) (lr) tc(VCLK2) - 2 ns
edge
Input signal period, PCNT or WCAP for falling edge to falling
2 2 (hr) (lr) tc(VCLK2) + 2 225 (hr) (lr) tc(VCLK2) - 2 ns
edge
Input signal high phase, PCNT or WCAP for rising edge to
3 (hr) (lr) tc(VCLK2) + 2 225 (hr) (lr) tc(VCLK2) - 2 ns
falling edge
Input signal low phase, PCNT or WCAP for falling edge to
4 (hr) (lr) tc(VCLK2) + 2 225 (hr) (lr) tc(VCLK2) - 2 ns
rising edge
(1) hr = High-resolution prescaler, configured using the HRPFC field of the Prescale Factor Register (HETPFR).
(2) lr = Loop-resolution prescaler, configured using the LFPRC field of the Prescale Factor Register (HETPFR).
Both N2HET1 and N2HET2 have channels that are enhanced to be able to capture inputs with smaller
pulse widths than that specified in Table 7-11. See Table 7-13 for a list of which pins support small pulse
capture.
The input capture capability for these channels is specified in Table 7-12.
Table 7-12. Input Timing Requirements for N2HET Channels with Enhanced Pulse Capture
NO. MIN MAX UNIT
Input signal period, PCNT or WCAP for rising edge to rising
1 (hr) (lr) tc(VCLK2) + 2 225 (hr) (lr) tc(VCLK2) - 2 ns
edge
Input signal period, PCNT or WCAP for falling edge to falling
2 (hr) (lr) tc(VCLK2) + 2 225 (hr) (lr) tc(VCLK2) - 2 ns
edge
Input signal high phase, PCNT or WCAP for rising edge to
3 2 (hr) tc(VCLK2) + 2 225 (hr) (lr) tc(VCLK2) - 2 ns
falling edge
Input signal low phase, PCNT or WCAP for falling edge to
4 2 (hr) tc(VCLK2) + 2 225 (hr) (lr) tc(VCLK2) - 2 ns
rising edge
Table 7-13. Input Capture Pin Capability
CHANNEL SUPPORTS 32-BIT CAPTURE ENHANCED PULSE CAPTURE
N2HET1[00] Yes No
N2HET1[01] Yes No
N2HET1[02] Yes No
N2HET1[03] Yes No
N2HET1[04] Yes No
N2HET1[05] Yes No
N2HET1[06] Yes No
N2HET1[07] Yes No
N2HET1[08] Yes No
N2HET1[09] Yes No
N2HET1[10] Yes No
N2HET1[11] Yes No
N2HET1[12] Yes No
N2HET1[13] Yes No
N2HET1[14] Yes No
N2HET1[15] Yes Yes
N2HET1[16] Yes No
N2HET1[17] Yes No
N2HET1[18] Yes No
N2HET1[19] Yes No
N2HET1[20] Yes Yes
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NHET_LOOP_SYNC EXT_LOOP_SYNC
EXT_LOOP_SYNC NHET_LOOP_SYNC
N2HET1 N2HET2
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Table 7-13. Input Capture Pin Capability (continued)
CHANNEL SUPPORTS 32-BIT CAPTURE ENHANCED PULSE CAPTURE
N2HET1[21] Yes No
N2HET1[22] Yes No
N2HET1[23] Yes No
N2HET1[24] Yes No
N2HET1[25] Yes No
N2HET1[26] Yes No
N2HET1[27] Yes No
N2HET1[28] Yes No
N2HET1[29] Yes No
N2HET1[30] Yes No
N2HET1[31] Yes Yes
N2HET2[00] Yes No
N2HET2[01] No No
N2HET2[02] No No
N2HET2[03] No No
N2HET2[04] Yes No
N2HET2[05] No No
N2HET2[06] Yes No
N2HET2[07] No No
N2HET2[08] No No
N2HET2[09] No No
N2HET2[10] No No
N2HET2[11] No No
N2HET2[12] Yes Yes
N2HET2[13] No No
N2HET2[14] Yes Yes
N2HET2[15] No No
N2HET2[16] Yes Yes
N2HET2[18] No No
7.4.4 N2HET1-N2HET2 Interconnections
In some applications the N2HET resolutions must be synchronized. Some other applications require a
single time base to be used for all PWM outputs and input timing captures.
The N2HET provides such a synchronization mechanism. The Clk_master/slave (HETGCR.16) configures
the N2HET in master or slave mode (default is slave mode). A N2HET in master mode provides a signal
to synchronize the prescalers of the slave N2HET. The slave N2HET synchronizes its loop resolution to
the loop resolution signal sent by the master. The slave does not require this signal after it receives the
first synchronization signal. However, anytime the slave receives the resynchronization signal from the
master, the slave must synchronize itself again..
Figure 7-6. N2HET1 – N2HET2 Synchronization Hookup
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N2HET2
IOMMmuxcontrolsignalx
N2HET1[1,3,5,7,9,11]/N2HET2[8,10,12,14,16,18]
N2HET1[1,3,5,7,9,11]
N2HET2[8,10,12,14,16,18]
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7.4.5 N2HET Checking
7.4.5.1 Internal Monitoring
To assure correctness of the high-end timer operation and output signals, the two N2HET modules can be
used to monitor each other’s signals as shown in Figure 7-7. The direction of the monitoring is controlled
by the I/O multiplexing control module.
Figure 7-7. N2HET Monitoring
7.4.5.2 Output Monitoring Using Dual Clock Comparator (DCC)
N2HET1[31] is connected as a clock source for counter 1 in DCC1. This allows the application to measure
the frequency of the pulse-width modulated (PWM) signal on N2HET1[31].
Similarly, N2HET2[0] is connected as a clock source for counter 1 in DCC2. This allows the application to
measure the frequency of the pulse-width modulated (PWM) signal on N2HET2[0].
Both N2HET1[31] and N2HET2[0] can be configured to be internal-only channels. That is, the connection
to the DCC module is made directly from the output of the N2HETx module (from the input of the output
buffer).
For more information on DCC see Section 6.7.3.
7.4.6 Disabling N2HET Outputs
Some applications require the N2HET outputs to be disabled under some fault condition. The N2HET
module provides this capability via the "Pin Disable" input signal. This signal, when driven low, causes the
N2HET outputs identified by a programmable register (HETPINDIS) to be tri-stated. See the device
specific technical reference manual for more details on the "N2HET Pin Disable" feature.
GIOA[5] is connected to the "Pin Disable" input for N2HET1, and GIOB[2] is connected to the "Pin
Disable" input for N2HET2.
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7.4.7 High-End Timer Transfer Unit (HTU)
A High End Timer Transfer Unit (HTU) can perform DMA type transactions to transfer N2HET data to or
from main memory. A Memory Protection Unit (MPU) is built into the HTU.
7.4.7.1 Features
• CPU and DMA independent
• Master Port to access system memory
• 8 control packets supporting dual buffer configuration
• Control packet information is stored in RAM protected by parity
• Event synchronization (HET transfer requests)
• Supports 32- or 64-bit transactions
• Addressing modes for HET address (8 byte or 16 byte) and system memory address (fixed, 32 bit or 64 bit)
• One shot, circular and auto switch buffer transfer modes
• Request lost detection
7.4.7.2 Trigger Connections
Table 7-14. HTU1 Request Line Connection
MODULES REQUEST SOURCE HTU1 REQUEST
N2HET1 HTUREQ[0] HTU1 DCP[0]
N2HET1 HTUREQ[1] HTU1 DCP[1]
N2HET1 HTUREQ[2] HTU1 DCP[2]
N2HET1 HTUREQ[3] HTU1 DCP[3]
N2HET1 HTUREQ[4] HTU1 DCP[4]
N2HET1 HTUREQ[5] HTU1 DCP[5]
N2HET1 HTUREQ[6] HTU1 DCP[6]
N2HET1 HTUREQ[7] HTU1 DCP[7]
Table 7-15. HTU2 Request Line Connection
MODULES REQUEST SOURCE HTU2 REQUEST
N2HET2 HTUREQ[0] HTU2 DCP[0]
N2HET2 HTUREQ[1] HTU2 DCP[1]
N2HET2 HTUREQ[2] HTU2 DCP[2]
N2HET2 HTUREQ[3] HTU2 DCP[3]
N2HET2 HTUREQ[4] HTU2 DCP[4]
N2HET2 HTUREQ[5] HTU2 DCP[5]
N2HET2 HTUREQ[6] HTU2 DCP[6]
N2HET2 HTUREQ[7] HTU2 DCP[7]
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VCCIO
0.6*VCCIO
0.4*VCCIO
0
Input
tpw
0.6*VCCIO
0.4*VCCIO
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7.5 FlexRay Interface
The FlexRay module performs communication according to the FlexRay protocol specification v2.1. The
sample clock bit rate can be programmed to values up to 10 Mbps. Additional bus driver (BD) hardware is
required for connection to the physical layer.
For communication on a FlexRay network, individual message buffers with up to 254 data bytes are
configurable. The message storage consists of a single-ported message RAM that holds up to 128
message buffers. All functions concerning the handling of messages are implemented in the message
handler. Those functions are the acceptance filtering, the transfer of messages between the two FlexRay
Channel Protocol Controllers and the message RAM, maintaining the transmission schedule, as well as
providing message status information.
The register set of the FlexRay module can be accessed directly by the CPU through the VBUS interface.
These registers are used to control, configure, and monitor the FlexRay channel protocol controllers,
message handler, global time unit, system universal control, frame/symbol processing, network
management, interrupt control, and to access the message RAM through the I/O buffer.
7.5.1 Features
The FlexRay module has the following features:
• Conformance with FlexRay protocol specification v2.1
• Data rates of up to 10 Mbps on each channel
• Up to 128 message buffers
• 8KB of message RAM for storage (for example, 128 message buffers with maximum of 48-byte data
section or up to 30 message buffers with 254-byte data section)
• Configuration of message buffers with different payload lengths
• One configurable receive FIFO
• Each message buffer can be configured as receive buffer, as transmit buffer or as part of the receive
FIFO.
• CPU access to message buffers through input and output buffer
• FlexRay Transfer Unit (FTU) for automatic data transfer between data memory and message buffers
without CPU interaction
• Filtering for slot counter, cycle counter, and channel ID
• Maskable module interrupts
• Supports Network Management
7.5.2 Electrical and Timing Specifications
Table 7-16. Timing Requirements for FlexRay Inputs
MIN MAX UNIT
Input minimum pulse width to meet the FlexRay sampling
tpw tc(AVCLK2) + 2.5(1) ns
requirement
(1) tRxAsymDelay parameter
Figure 7-8. FlexRay Inputs
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Table 7-17. FlexRay Jitter Timing
PARAMETER MIN MAX UNIT
tTx1bit Clock jitter and signal symmetry 98 102 ns
tTx10bit FlexRay BSS (byte start sequence) to BSS 999 1001 ns
tTx10bitAvg Average over 10,000 samples 999.5 1000.5 ns
Delay difference between rise and fall from Rx pin to sample
tRxAsymDelay – 2.5 ns
point in FlexRay core
tjit(SCLK) Jitter for the 80-MHz Sample Clock generated by the PLL – 0.5 ns
7.5.3 FlexRay Transfer Unit
The FTU can transfer data between the input buffer (IBF) and output buffer (OBF) of the communication
controller and the system memory without CPU interaction.
Because the FlexRay module is accessed through the FTU, the FTU must be powered up by setting bit 23
in the Peripheral Power Down Registers of the System Module before accessing any FlexRay module
register.
For more information on the FTU, see the TMS570LS31x/TMS570LS21x 16/32-Bit RISC Flash
Microcontroller Technical Reference Manual (SPNU499).
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7.6 Controller Area Network (DCAN)
The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication
protocol that efficiently supports distributed real-time control with robust communication rates of up to 1
Mbps. The DCAN is ideal for applications operating in noisy and harsh environments (for example,
automotive and industrial fields) that require reliable serial communication or multiplexed wiring.
7.6.1 Features
Features of the DCAN module include:
• Supports CAN protocol version 2.0 part A, B
• Bit rates up to 1 Mbps
• The CAN kernel can be clocked by the oscillator for baud-rate generation.
• 64 mailboxes on each DCAN
• Individual identifier mask for each message object
• Programmable FIFO mode for message objects
• Programmable loop-back modes for self-test operation
• Automatic bus on after Bus-Off state by a programmable 32-bit timer
• Message RAM protected by parity
• Direct access to Message RAM during test mode
• CAN Rx / Tx pins configurable as general purpose IO pins
• Message RAM Auto Initialization
• DMA support
For more information on the DCAN, see the TMS570LS31x/21x 16/32-Bit RISC Flash Microcontroller
Technical Reference Manual (SPNU499).
7.6.2 Electrical and Timing Specifications
Table 7-18. Dynamic Characteristics for the DCANx TX and RX Pins
PARAMETER MIN MAX UNIT
td(CANnTX) Delay time, transmit shift register to CANnTX pin(1) 15 ns
td(CANnRX) Delay time, CANnRX pin to receive shift register 5 ns
(1) These values do not include rise/fall times of the output buffer.
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7.7 Local Interconnect Network Interface (LIN)
The SCI/LIN module can be programmed to work either as an SCI or as a LIN. The core of the module is
an SCI. The hardware features of the SCI are augmented to achieve LIN compatibility.
The SCI module is a universal asynchronous receiver-transmitter that implements the standard nonreturn
to zero format. The SCI can be used to communicate, for example, through an RS-232 port or over a K-
line.
The LIN standard is based on the SCI (UART) serial data link format. The communication concept is
single-master/multiple-slave with a message identification for multicast transmission between any network
nodes.
7.7.1 LIN Features
The following are features of the LIN module:
• Compatible to LIN 1.3, 2.0, and 2.1 protocols
• Multibuffered receive and transmit units DMA capability for minimal CPU intervention
• Identification masks for message filtering
• Automatic Master Header Generation
– Programmable Synch Break Field
– Synch Field
– Identifier Field
• Slave Automatic Synchronization
– Synch break detection
– Optional baudrate update
– Synchronization Validation
• 231 programmable transmission rates with 7 fractional bits
• Error detection
• 2 Interrupt lines with priority encoding
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7.8 Serial Communication Interface (SCI)
7.8.1 Features
• Standard universal asynchronous receiver-transmitter (UART) communication
• Supports full- or half-duplex operation
• Standard nonreturn to zero (NRZ) format
• Double-buffered receive and transmit functions
• Configurable frame format of 3 to 13 bits per character based on the following:
– Data word length programmable from 1 to 8 bits
– Additional address bit in address-bit mode
– Parity programmable for zero or 1 parity bit, odd or even parity
– Stop programmable for 1 or 2 stop bits
• Asynchronous or isosynchronous communication modes
• Two multiprocessor communication formats allow communication between more than two devices.
• Sleep mode is available to free CPU resources during multiprocessor communication.
• The 24-bit programmable baud rate supports 224 different baud rates provide high accuracy baud rate selection.
• Four error flags and five status flags provide detailed information regarding SCI events.
• Capability to use DMA for transmit and receive data.
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7.9 Inter-Integrated Circuit (I2C)
The inter-integrated circuit (I2C) module is a multimaster communication module providing an interface
between the TMS570 microcontroller and devices compliant with Philips Semiconductor I2C-bus
specification version 2.1 and connected by an I2C-bus™. This module will support any slave or master I2C
compatible device.
7.9.1 Features
The I2C has the following features:
• Compliance to the Philips I2C-bus specification, v2.1 (The I2C Specification, Philips document number
9398 393 40011)
– Bit/Byte format transfer
– 7-bit and 10-bit device addressing modes
– General call
– START byte
– Multimaster transmitter/ slave receiver mode
– Multimaster receiver/ slave transmitter mode
– Combined master transmit/receive and receive/transmit mode
– Transfer rates of 10 kbps up to 400 kbps (Phillips fast-mode rate)
• Free data format
• Two DMA events (transmit and receive)
• DMA event enable/disable capability
• Seven interrupts that can be used by the CPU
• Module enable/disable capability
• The SDA and SCL are optionally configurable as general-purpose I/O
• Slew rate control of the outputs
• Open-drain control of the outputs
• Programmable pullup/pulldown capability on the inputs
• Supports Ignore NACK mode
NOTE
This I2C module does not support:
• High-speed (HS) mode
• C-bus compatibility mode
• The combined format in 10-bit address mode (the I2C module sends the slave address
second byte every time it sends the slave address first byte)
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SDA
SCL
tw(SDAH)
tw(SCLL)
tw(SCLH)
tw(SP)
th(SCLL-SDAL)
th(SDA-SCLL)
th(SCLL-SDAL)
tsu(SCLH-SDAL)
tf(SCL)
tc(SCL)
tr(SCL)
tsu(SCLH-SDAH)
Stop Start Repeated Start Stop
tsu(SDA-SCLH)
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7.9.2 I2C I/O Timing Specifications
Table 7-19. I2C Signals (SDA and SCL) Switching Characteristics(1)
STANDARD MODE FAST MODE
PARAMETER UNIT
MIN MAX MIN MAX
Cycle time, Internal Module clock for I2C,
tc(I2CCLK) 75.2 149 75.2 149 ns
prescaled from VCLK
f(SCL) SCL Clock frequency 0 100 0 400 kHz
tc(SCL) Cycle time, SCL 10 2.5 µs
Setup time, SCL high before SDA low (for a
tsu(SCLH-SDAL) 4.7 0.6 µs
repeated START condition)
Hold time, SCL low after SDA low (for a repeated
th(SCLL-SDAL) 4 0.6 µs
START condition)
tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs
tw(SCLH) Pulse duration, SCL high 4 0.6 µs
tsu(SDA-SCLH) Setup time, SDA valid before SCL high 250 100 ns
Hold time, SDA valid after SCL low (for I2C bus
th(SDA-SCLL) 0 3.45(2) 0 0.9 µs
devices)
Pulse duration, SDA high between STOP and
tw(SDAH) 4.7 1.3 µs
START conditions
Setup time, SCL high before SDA high (for STOP
tsu(SCLH-SDAH) 4.0 0.6 µs
condition)
tw(SP) Pulse duration, spike (must be suppressed) 0 50 ns
Cb(3) Capacitive load for each bus line 400 400 pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) The maximum th(SDA-SCLL) for I2C bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the SCL
signal.
(3) Cb= The total capacitance of one bus line in pF.
Figure 7-9. I2C Timings
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NOTE
• A device must internally provide a hold time of at least 300 ns for the SDA signal
(referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling
edge of SCL.
• The maximum th(SDA-SCLL) has only to be met if the device does not stretch the LOW
period (tw(SCLL)) of the SCL signal.
• A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the
requirement tsu(SDA-SCLH) ≥250 ns must then be met. This will automatically be the case if
the device does not stretch the LOW period of the SCL signal. If such a device does
stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
tr max + tsu(SDA-SCLH).
• Cb= total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-
times are allowed.
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7.10 Multibuffered / Standard Serial Peripheral Interface
The MibSPI is a high-speed synchronous serial input/output port that allows a serial bit stream of
programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate.
Typical applications for the SPI include interfacing to external peripherals, such as I/Os, memories, display
drivers, and analog-to-digital converters.
7.10.1 Features
Both Standard and MibSPI modules have the following features:
• 16-bit shift register
• Receive buffer register
• 5-bit baud clock generator
• SPICLK can be internally-generated (master mode) or received from an external clock source (slave
mode)
• Each word transferred can have a unique format
• SPI I/Os not used in the communication can be used as digital input/output signals
Table 7-20. MibSPI/SPI Configurations
MibSPIx/SPIx I/Os
MibSPI1 MIBSPI1SIMO[1:0], MIBSPI1SOMI[1:0], MIBSPI1CLK, MIBSPI1nCS[5:0], MIBSPI1nENA
MibSPI3 MIBSPI3SIMO, MIBSPI3SOMI, MIBSPI3CLK, MIBSPI3nCS[5:0], MIBSPI3nENA
MibSPI5 MIBSPI5SIMO[3:0], MIBSPI5SOMI[3:0], MIBSPI5CLK, MIBSPI5nCS[3:0], MIBSPI5nENA
SPI2 SPI2SIMO, SPI2SOMI, SPI2CLK, SPI2nCS[1:0], SPI2nENA
SPI4 SPI4SIMO, SPI4SOMI, SPI4CLK, SPI4nCS[0], SPI4nENA
7.10.2 MibSPI Transmit and Receive RAM Organization
The Multibuffer RAM is comprised of 128 buffers. Each entry in the Multibuffer RAM consists of 4 parts: a
16-bit transmit field, a 16-bit receive field, a 16-bit control field and a 16-bit status field. The Multibuffer
RAM can be partitioned into multiple transfer group with variable number of buffers each.
7.10.3 MibSPI Transmit Trigger Events
Each of the transfer groups can be configured individually. For each of the transfer groups a trigger event
and a trigger source can be chosen. A trigger event can be for example a rising edge or a permanent low
level at a selectable trigger source. For example, up to 15 trigger sources are available which can be used
by each transfer group. These trigger options are listed in Table 7-21 for MIBSPI1, Section 7.10.3.2 for
MIBSPI3 and Section 7.10.3.3 for MibSPI5.
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7.10.3.1 MIBSPI1 Event Trigger Hookup
Table 7-21. MIBSPI1 Event Trigger Hookup
EVENT # TGxCTRL TRIGSRC[3:0] TRIGGER
Disabled 0000 No trigger source
EVENT0 0001 GIOA[0]
EVENT1 0010 GIOA[1]
EVENT2 0011 GIOA[2]
EVENT3 0100 GIOA[3]
EVENT4 0101 GIOA[4]
EVENT5 0110 GIOA[5]
EVENT6 0111 GIOA[6]
EVENT7 1000 GIOA[7]
EVENT8 1001 N2HET1[8]
EVENT9 1010 N2HET1[10]
EVENT10 1011 N2HET1[12]
EVENT11 1100 N2HET1[14]
EVENT12 1101 N2HET1[16]
EVENT13 1110 N2HET1[18]
EVENT14 1111 Internal Tick counter
NOTE
For N2HET1 trigger sources, the connection to the MibSPI1 module trigger input is made
from the input side of the output buffer (at the N2HET1 module boundary). This way, a
trigger condition can be generated even if the N2HET1 signal is not selected to be output on
the pad.
NOTE
For GIOx trigger sources, the connection to the MibSPI1 module trigger input is made from
the output side of the input buffer. This way, a trigger condition can be generated either by
selecting the GIOx pin as an output pin plus selecting the pin to be a GIOx pin, or by driving
the GIOx pin from an external trigger source. If the mux control module is used to select
different functionality instead of the GIOx signal, then care must be taken to disable GIOx
from triggering MibSPI1 transfers; there is no multiplexing on the input connections.
7.10.3.2 MIBSPI3 Event Trigger Hookup
Table 7-22. MIBSPI3 Event Trigger Hookup
EVENT # TGxCTRL TRIGSRC[3:0] TRIGGER
Disabled 0000 No trigger source
EVENT0 0001 GIOA[0]
EVENT1 0010 GIOA[1]
EVENT2 0011 GIOA[2]
EVENT3 0100 GIOA[3]
EVENT4 0101 GIOA[4]
EVENT5 0110 GIOA[5]
EVENT6 0111 GIOA[6]
EVENT7 1000 GIOA[7]
EVENT8 1001 HET[8]
EVENT9 1010 N2HET1[10]
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Table 7-22. MIBSPI3 Event Trigger Hookup (continued)
EVENT # TGxCTRL TRIGSRC[3:0] TRIGGER
EVENT10 1011 N2HET1[12]
EVENT11 1100 N2HET1[14]
EVENT12 1101 N2HET1[16]
EVENT13 1110 N2HET1[18]
EVENT14 1111 Internal Tick counter
NOTE
For N2HET1 trigger sources, the connection to the MibSPI3 module trigger input is made
from the input side of the output buffer (at the N2HET1 module boundary). This way, a
trigger condition can be generated even if the N2HET1 signal is not selected to be output on
the pad.
NOTE
For GIOx trigger sources, the connection to the MibSPI3 module trigger input is made from
the output side of the input buffer. This way, a trigger condition can be generated either by
selecting the GIOx pin as an output pin plus selecting the pin to be a GIOx pin, or by driving
the GIOx pin from an external trigger source. If the mux control module is used to select
different functionality instead of the GIOx signal, then care must be taken to disable GIOx
from triggering MibSPI3 transfers; there is no multiplexing on the input connections.
7.10.3.3 MIBSPI5 Event Trigger Hookup
Table 7-23. MIBSPI5 Event Trigger Hookup
EVENT # TGxCTRL TRIGSRC[3:0] TRIGGER
Disabled 0000 No trigger source
EVENT0 0001 GIOA[0]
EVENT1 0010 GIOA[1]
EVENT2 0011 GIOA[2]
EVENT3 0100 GIOA[3]
EVENT4 0101 GIOA[4]
EVENT5 0110 GIOA[5]
EVENT6 0111 GIOA[6]
EVENT7 1000 GIOA[7]
EVENT8 1001 N2HET1[8]
EVENT9 1010 N2HET1[10]
EVENT10 1011 N2HET1[12]
EVENT11 1100 N2HET1[14]
EVENT12 1101 N2HET1[16]
EVENT13 1110 N2HET1[18]
EVENT14 1111 Internal Tick counter
NOTE
For N2HET1 trigger sources, the connection to the MibSPI5 module trigger input is made
from the input side of the output buffer (at the N2HET1 module boundary). This way, a
trigger condition can be generated even if the N2HET1 signal is not selected to be output on
the pad.
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NOTE
For GIOx trigger sources, the connection to the MibSPI5 module trigger input is made from
the output side of the input buffer. This way, a trigger condition can be generated either by
selecting the GIOx pin as an output pin + selecting the pin to be a GIOx pin, or by driving the
GIOx pin from an external trigger source. If the mux control module is used to select different
functionality instead of the GIOx signal, then care must be taken to disable GIOx from
triggering MibSPI5 transfers; there is no multiplexing on the input connections.
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7.10.4 MibSPI/SPI Master Mode I/O Timing Specifications
Table 7-24. SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO
= output, and SPISOMI = input)(1)(2)(3)
NO. PARAMETER MIN MAX UNIT
1 tc(SPC)M Cycle time, SPICLK(4) 40 256tc(VCLK) ns
Pulse duration, SPICLK high (clock
tw(SPCH)M 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3
polarity = 0)
2(5) ns
Pulse duration, SPICLK low (clock
tw(SPCL)M 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3
polarity = 1)
Pulse duration, SPICLK low (clock
tw(SPCL)M 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3
polarity = 0)
3(5) ns
Pulse duration, SPICLK high (clock
tw(SPCH)M 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3
polarity = 1)
Delay time, SPISIMO valid before
td(SPCH-SIMO)M 0.5tc(SPC)M – 6
SPICLK low (clock polarity = 0)
4(5) ns
Delay time, SPISIMO valid before
td(SPCL-SIMO)M 0.5tc(SPC)M – 6
SPICLK high (clock polarity = 1)
Valid time, SPISIMO data valid after
tv(SPCL-SIMO)M 0.5tc(SPC)M – tf(SPC) – 4
SPICLK low (clock polarity = 0)
5(5) ns
Valid time, SPISIMO data valid after
tv(SPCH-SIMO)M 0.5tc(SPC)M – tr(SPC) – 4
SPICLK high (clock polarity = 1)
Setup time, SPISOMI before SPICLK
tsu(SOMI-SPCL)M tf(SPC) + 2.2
low (clock polarity = 0)
6(5) ns
Setup time, SPISOMI before SPICLK
tsu(SOMI-SPCH)M tr(SPC) + 2.2
high (clock polarity = 1)
Hold time, SPISOMI data valid after
th(SPCL-SOMI)M 10
SPICLK low (clock polarity = 0)
7(5) ns
Hold time, SPISOMI data valid after
th(SPCH-SOMI)M 10
SPICLK high (clock polarity = 1) C2TDELAY*tc(VCLK) + 2*tc(VCLK) (C2TDELAY+2) * tc(VCLK) -
CSHOLD = 0
Setup time CS active - tf(SPICS) + tr(SPC) – 7 tf(SPICS) + tr(SPC) + 5.5
until SPICLK high C2TDELAY*tc(VCLK) + 3*tc(VCLK) (C2TDELAY+3) * tc(VCLK) -
(clock polarity = 0) CSHOLD = 1 - tf(SPICS) + tr(SPC) – 7 tf(SPICS) + tr(SPC) + 5.5
8(6) tC2TDELAY ns
C2TDELAY*tc(VCLK) + 2*tc(VCLK) (C2TDELAY+2) * tc(VCLK) -
CSHOLD = 0
Setup time CS active - tf(SPICS) + tf(SPC) – 7 tf(SPICS) + tf(SPC) + 5.5
until SPICLK low C2TDELAY*tc(VCLK) + 3*tc(VCLK) (C2TDELAY+3) * tc(VCLK) -
(clock polarity = 1) CSHOLD = 1 - tf(SPICS) + tf(SPC) – 7 tf(SPICS) + tf(SPC) + 5.5
0.5*tc(SPC)M + 0.5*tc(SPC)M +
Hold time SPICLK low until CS inactive T2CDELAY*tc(VCLK) + tc(VCLK) - T2CDELAY*tc(VCLK) + tc(VCLK) -
(clock polarity = 0) tf(SPC) + tr(SPICS) - 7 tf(SPC) + tr(SPICS) + 11
9(6) tT2CDELAY ns
0.5*tc(SPC)M + 0.5*tc(SPC)M +
Hold time SPICLK high until CS T2CDELAY*tc(VCLK) + tc(VCLK) - T2CDELAY*tc(VCLK) + tc(VCLK) -
inactive (clock polarity = 1) tr(SPC) + tr(SPICS) - 7 tr(SPC) + tr(SPICS) + 11
(C2TDELAY+1) * tc(VCLK) - ns
10 tSPIENA SPIENAn Sample point (C2TDELAY+1)*tc(VCLK)
tf(SPICS) – 29
SPIENAn Sample point from write to ns
11 tSPIENAW (C2TDELAY+2)*tc(VCLK)
buffer
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared.
(2) tc(VCLK) = interface clock cycle time = 1 / f(VCLK)
(3) For rise and fall timings, see Table 5-7.
(4) When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M ≥(PS +1)tc(VCLK) ≥40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥40ns.
The external load on the SPICLK pin must be less than 60pF.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
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SPICLK
(clock polarity=0)
SPISIMO
SPICSn
Master Out Data Is Valid
9
SPICLK
(clock polarity=1)
SPIENAn
10
Write to buffer
11
8
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Master In Data
Must Be Valid
Master Out Data Is Valid
3
2
1
54
66
7
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Figure 7-10. SPI Master Mode External Timing (CLOCK PHASE = 0)
Figure 7-11. SPI Master Mode Chip Select Timing (CLOCK PHASE = 0)
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Table 7-25. SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO
= output, and SPISOMI = input)(1)(2)(3)
NO. PARAMETER MIN MAX UNIT
1 tc(SPC)M Cycle time, SPICLK (4) 40 256tc(VCLK) ns
Pulse duration, SPICLK high (clock
tw(SPCH)M 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3
polarity = 0)
2(5) ns
Pulse duration, SPICLK low (clock
tw(SPCL)M 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3
polarity = 1)
Pulse duration, SPICLK low (clock
tw(SPCL)M 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3
polarity = 0)
3(5) ns
Pulse duration, SPICLK high (clock
tw(SPCH)M 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3
polarity = 1)
Valid time, SPICLK high after
tv(SIMO-SPCH)M SPISIMO data valid (clock polarity = 0.5tc(SPC)M – 6
0)
4(5) ns
Valid time, SPICLK low after
tv(SIMO-SPCL)M SPISIMO data valid (clock polarity = 0.5tc(SPC)M – 6
1)
Valid time, SPISIMO data valid after
tv(SPCH-SIMO)M 0.5tc(SPC)M – tr(SPC) – 4
SPICLK high (clock polarity = 0)
5(5) ns
Valid time, SPISIMO data valid after
tv(SPCL-SIMO)M 0.5tc(SPC)M – tf(SPC) – 4
SPICLK low (clock polarity = 1)
Setup time, SPISOMI before
tsu(SOMI-SPCH)M tr(SPC) + 2.2
SPICLK high (clock polarity = 0)
6(5) ns
Setup time, SPISOMI before
tsu(SOMI-SPCL)M tf(SPC) + 2.2
SPICLK low (clock polarity = 1)
Valid time, SPISOMI data valid after
tv(SPCH-SOMI)M 10
SPICLK high (clock polarity = 0)
7(5) ns
Valid time, SPISOMI data valid after
tv(SPCL-SOMI)M 10
SPICLK low (clock polarity = 1) 0.5*tc(SPC)M + 0.5*tc(SPC)M +
CSHOLD = 0 (C2TDELAY+2) * tc(VCLK) - (C2TDELAY+2) * tc(VCLK) -
Setup time CS tf(SPICS) + tr(SPC) – 7 tf(SPICS) + tr(SPC) + 5.5
active until SPICLK
high (clock polarity = 0.5*tc(SPC)M + 0.5*tc(SPC)M +
0) CSHOLD = 1 (C2TDELAY+3) * tc(VCLK) - (C2TDELAY+3) * tc(VCLK) -
tf(SPICS) + tr(SPC) – 7 tf(SPICS) + tr(SPC) + 5.5
8(6) tC2TDELAY ns
0.5*tc(SPC)M + 0.5*tc(SPC)M +
CSHOLD = 0 (C2TDELAY+2) * tc(VCLK) - (C2TDELAY+2) * tc(VCLK) -
Setup time CS tf(SPICS) + tf(SPC) – 7 tf(SPICS) + tf(SPC) + 5.5
active until SPICLK
low (clock polarity = 0.5*tc(SPC)M + 0.5*tc(SPC)M +
1) CSHOLD = 1 (C2TDELAY+3) * tc(VCLK) - (C2TDELAY+3) * tc(VCLK) -
tf(SPICS) + tf(SPC) – 7 tf(SPICS) + tf(SPC) + 5.5
T2CDELAY*tc(VCLK) + T2CDELAY*tc(VCLK) +
Hold time SPICLK low until CS tc(VCLK) - tf(SPC) + tr(SPICS) - tc(VCLK) - tf(SPC) + tr(SPICS) +
inactive (clock polarity = 0) 7 11
9(6) tT2CDELAY ns
T2CDELAY*tc(VCLK) + T2CDELAY*tc(VCLK) +
Hold time SPICLK high until CS tc(VCLK) - tr(SPC) + tr(SPICS) - tc(VCLK) - tr(SPC) + tr(SPICS) +
inactive (clock polarity = 1) 7 11
(C2TDELAY+1)* tc(VCLK) - ns
10 tSPIENA SPIENAn Sample Point (C2TDELAY+1)*tc(VCLK)
tf(SPICS) – 29
SPIENAn Sample point from write to ns
11 tSPIENAW (C2TDELAY+2)*tc(VCLK)
buffer
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) tc(VCLK) = interface clock cycle time = 1 / f(VCLK)
(3) For rise and fall timings, see the Table 5-7.
(4) When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M ≥(PS +1)tc(VCLK) ≥40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥40ns.
The external load on the SPICLK pin must be less than 60pF.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
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SPICLK
(clock polarity=0)
SPISIMO
SPICSn
Master Out Data Is Valid
9
SPICLK
(clock polarity=1)
SPIENAn
10
Write to buffer
11
8
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Data Valid
Master In Data
Must Be Valid
Master Out Data Is Valid
3
2
1
5
4
7
6
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Figure 7-12. SPI Master Mode External Timing (CLOCK PHASE = 1)
Figure 7-13. SPI Master Mode Chip Select Timing (CLOCK PHASE = 1)
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7.10.5 SPI Slave Mode I/O Timings
Table 7-26. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input, SPISIMO =
input, and SPISOMI = output)(1)(2)(3)(4)
NO. PARAMETER MIN MAX UNIT
1 tc(SPC)S Cycle time, SPICLK(5) 40 ns
2(6) tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 14 ns
tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 14
3(6) tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 14 ns
tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 14
4(6) Delay time, SPISOMI valid after SPICLK high (clock
td(SPCH-SOMI)S trf(SOMI) + 20
polarity = 0) ns
Delay time, SPISOMI valid after SPICLK low (clock polarity
td(SPCL-SOMI)S trf(SOMI) + 20
= 1)
5(6) Hold time, SPISOMI data valid after SPICLK high (clock
th(SPCH-SOMI)S 2
polarity =0) ns
Hold time, SPISOMI data valid after SPICLK low (clock
th(SPCL-SOMI)S 2
polarity =1)
6(6) Setup time, SPISIMO before SPICLK low (clock polarity =
tsu(SIMO-SPCL)S 4
0) ns
Setup time, SPISIMO before SPICLK high (clock polarity =
tsu(SIMO-SPCH)S 4
1)
Hold time, SPISIMO data valid after SPICLK low (clock
th(SPCL-SIMO)S 2
polarity = 0)
7(6) ns
Hold time, SPISIMO data valid after S PICLK high (clock
th(SPCH-SIMO)S 2
polarity = 1)
Delay time, SPIENAn high after last SPICLK low (clock 2.5tc(VCLK)+tr(ENAn)+
td(SPCL-SENAH)S 1.5tc(VCLK)
polarity = 0) 22
8 ns
Delay time, SPIENAn high after last SPICLK high (clock 2.5tc(VCLK)+ tr(ENAn) +
td(SPCH-SENAH)S 1.5tc(VCLK)
polarity = 1) 22
Delay time, SPIENAn low after SPICSn low (if new data
9 td(SCSL-SENAL)S tf(ENAn) tc(VCLK)+tf(ENAn)+27 ns
has been written to the SPI buffer)
(1) The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is cleared.
(2) If the SPI is in slave mode, the following must be true: tc(SPC)S ≥(PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].
(3) For rise and fall timings, see Table 5-7.
(4) tc(VCLK) = interface clock cycle time = 1 /f(VCLK)
(5) When the SPI is in Slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S ≥(PS +1)tc(VCLK) ≥40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)S = 2tc(VCLK) ≥40ns.
(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
Copyright © 2012–2015, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 149
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SPICLK
(clock polarity=0)
SPICSn
8
SPICLK
(clock polarity=1)
SPIENAn
9
SPISOMI
SPICLK
(clockpolarity=1)
SPICLK
(clockpolarity=0)
3
2
1
5
4
7
SPISIMOData
MustBeValid
SPISOMIDataIsValid
666
SPISIMO
TMS570LS3135, TMS570LS2135, TMS570LS2125
SPNS164C –APRIL 2012–REVISED APRIL 2015
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Figure 7-14. SPI Slave Mode External Timing (CLOCK PHASE = 0)
Figure 7-15. SPI Slave Mode Enable Timing (CLOCK PHASE = 0)
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Table 7-27. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input, SPISIMO =
input, and SPISOMI = output)(1)(2)(3)(4)
NO. PARAMETER MIN MAX UNIT
1 tc(SPC)S Cycle time, SPICLK(5) 40 ns
tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 14
2(6) ns
tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 14
tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 14
3(6) ns
tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 14
Dealy time, SPISOMI data valid after SPICLK low
td(SOMI-SPCL)S trf(SOMI) + 20
(clock polarity = 0)
4(6) ns
Delay time, SPISOMI data valid after SPICLK high
td(SOMI-SPCH)S trf(SOMI) + 20
(clock polarity = 1)
Hold time, SPISOMI data valid after SPICLK high
th(SPCL-SOMI)S 2
(clock polarity =0)
5(6) ns
Hold time, SPISOMI data valid after SPICLK low (clock
th(SPCH-SOMI)S 2
polarity =1)
Setup time, SPISIMO before SPICLK high (clock
tsu(SIMO-SPCH)S 4
polarity = 0)
6(6) ns
Setup time, SPISIMO before SPICLK low (clock polarity
tsu(SIMO-SPCL)S 4
= 1)
High time, SPISIMO data valid after SPICLK high
tv(SPCH-SIMO)S 2
(clock polarity = 0)
7(6) ns
High time, SPISIMO data valid after SPICLK low (clock
tv(SPCL-SIMO)S 2
polarity = 1)
Delay time, SPIENAn high after last SPICLK high
td(SPCH-SENAH)S 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn) + 22
(clock polarity = 0)
8 ns
Delay time, SPIENAn high after last SPICLK low (clock
td(SPCL-SENAH)S 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn) + 22
polarity = 1)
Delay time, SPIENAn low after SPICSn low (if new data
9 td(SCSL-SENAL)S tf(ENAn) tc(VCLK)+tf(ENAn)+ 27 ns
has been written to the SPI buffer)
Delay time, SOMI valid after SPICSn low (if new data
10 td(SCSL-SOMI)S tc(VCLK) 2tc(VCLK)+trf(SOMI)+ 28 ns
has been written to the SPI buffer)
(1) The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) If the SPI is in slave mode, the following must be true: tc(SPC)S ≤(PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].
(3) For rise and fall timings, see Table 5-7.
(4) tc(VCLK) = interface clock cycle time = 1 /f(VCLK)
(5) When the SPI is in Slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S ≥(PS +1)tc(VCLK) ≥40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)S = 2tc(VCLK) ≥40ns.
(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
Copyright © 2012–2015, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 151
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SPISOMI Slave Out Data Is Valid
SPICLK
(clock polarity=0)
SPICSn
8
SPICLK
(clock polarity=1)
SPIENAn
9
10
SPISIMO
SPISOMI
5
7
SPISIMO Data
Must Be Valid
SPISOMI Data Is Valid
666
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
3
2
1
4
TMS570LS3135, TMS570LS2135, TMS570LS2125
SPNS164C –APRIL 2012–REVISED APRIL 2015
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Figure 7-16. SPI Slave Mode External Timing (CLOCK PHASE = 1)
Figure 7-17. SPI Slave Mode Enable Timing (CLOCK PHASE = 1)
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8 Device and Documentation Support
8.1 Device Support
8.1.1 Development Support
Texas Instruments (TI) offers an extensive line of development tools for the TMS570LSxRM48Lx family of
MCUs, including tools to evaluate the performance of the processors, generate code, develop algorithm
implementations, and fully integrate and debug software and hardware modules.
The following products support development:
Software Development Tools
• Code Composer Studio™ (CCS) Integrated Development Environment (IDE)–
– C/C++ Compiler
– Code generation tools
– Assembler/Linker
– FPU Optimized Libraries
• Application algorithms
• Sample applications code
Hardware Development Tools
• Development and evaluation boards
• JTAG-based emulators - XDS510™ class, XDS560™ emulator, XDS100v2, XDS110, XDS200
• Flash programming tools
For a complete listing of development-support tools, visit the Texas Instruments website at www.ti.com.
8.1.2 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
devices. Each commercial family member has one of three prefixes: TMX, TMP, or TMS (for example,
TMS570LS3137). These prefixes represent evolutionary stages of product development from engineering
prototypes (TMX) through fully qualified production devices (TMS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device's electrical specifications.
TMP Final silicon die that conforms to the device's electrical specifications but has not completed quality and
reliability verification.
TMS Fully-qualified production device.
TMX and TMP devices are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices have been characterized fully, and the quality and reliability of the device have been
demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
Figure 8-1 shows the numbering and symbol nomenclature for the TMS570LS31x5/21x5 .
For additional information on the device nomenclature markings, see the device-specific silicon errata
document listed in Section 8.2.1,Related Documentation from Texas Instruments.
Copyright © 2012–2015, Texas Instruments Incorporated Device and Documentation Support 153
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Full Part # TMS 570 LS 31 3 5 D ZWT Q Q1 R
Orderable Part # TMS 570 31 3 5 D ZWT Q Q1 R
Prefix: TM
TMS = Fully Qualified
TMP = Prototype
TMX = Samples
Core Technology:
570 = Cortex R4F
Architecture:
LS = Dual CPUs in Lockstep
(not included in orderable part #)
Flash Memory Size:
31 = 3MB
21 = 2MB
RAM Memory Size:
3 = 256kB
2 = 192kB
Peripheral Set:
5 = FlexRay, no Ethernet
Die Revision:
Blank = Initial Die
A = 1st Die Revision
B = 2nd Die Revision
C = 3rd Die Revision
D = 4th Die Revision
Package Type:
ZWT = 337 BGA Package
PGE = 144 Pin Package
Temperature Range:
Q = -40...+125 C
o
Quality Designator:
Q1 = Automotive
Shipping Options:
R = Tape and Reel
TMS570LS3135, TMS570LS2135, TMS570LS2125
SPNS164C –APRIL 2012–REVISED APRIL 2015
www.ti.com
Figure 8-1. TMS570LS31x5/21x5 Device Numbering Conventions
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8.2 Documentation Support
8.2.1 Related Documentation from Texas Instruments
The following documents describe the TMS570LS31x5/21x5 microcontroller..
SPNU499 TMS570LS31x/21x 16/32-Bit RISC Flash Microcontroller Technical Reference Manual details the
integration, the environment, the functional description, and the programming models for each
peripheral and subsystem in the device.
SPNZ195 TMS570LS31x/21x Microcontroller, Silicon Revision C, Silicon Errata describes the usage notes
and known exceptions to the functional specifications for the device silicon revision C.
SPNZ222 TMS570LS31x/21x Microcontroller, Silicon Revision D, Silicon Errata describes the usage notes
and known exceptions to the functional specifications for the device silicon revision D.
SPNA207 Calculating Equivalent Power-on-Hours for Hercules™ Safety MCUs details how to use the
spreadsheet to calculate the aging effect of temperature on Texas Instruments Hercules Safety MCUs.
8.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 8-1. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
TMS570LS2125 Click here Click here Click here Click here Click here
TMS570LS2135 Click here Click here Click here Click here Click here
TMS570LS3135 Click here Click here Click here Click here Click here
8.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among
engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve
problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help developers
get started with Embedded Processors from Texas Instruments and to foster innovation and growth of
general knowledge about the hardware and software surrounding these devices.
8.5 Trademarks
Code Composer Studio, XDS510, XDS560, E2E are trademarks of Texas Instruments.
CoreSight is a trademark of ARM Limited.
ARM, Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere.
All rights reserved.
I2C-bus is a trademark of NXP Semiconductors N. V.
All other trademarks are the property of their respective owners.
8.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.7 Glossary
SLYZ022 —TI Glossary.
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8.8 Device Identification Code Register
The device identification code register identifies several aspects of the device including the silicon version.
The details of the device identification code register are shown in Table 8-2. The device identification code
register value for this device is:
• Rev A = 0x802AAD05
• Rev B = 0x802AAD15
• Rev C = 0x802AAD1D
• Rev D = 0x802AAD25
Figure 8-2. Device ID Bit Allocation Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CP-15 UNIQUE ID TECH
R-1 R-00000000010101 R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TECH I/O PERIPH FLASH ECC RAM VERSION 1 0 1
VOLT PARITY ECC
AGE
R-101 R-0 R-1 R-10 R-1 R-00000 R-1 R-0 R-1
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset
Table 8-2. Device ID Bit Allocation Register Field Descriptions
BIT FIELD VALUE DESCRIPTION
31 CP15 Indicates the presence of coprocessor 15
1 CP15 present
30-17 UNIQUE ID 10101 Silicon version (revision) bits.
This bit field holds a unique number for a dedicated device configuration (die).
16-13 TECH Process technology on which the device is manufactured.
0101 F021
12 I/O VOLTAGE I/O voltage of the device.
0 I/O are 3.3 V
11 PERIPHERAL Peripheral Parity
PARITY 1 Parity on peripheral memories
10-9 FLASH ECC Flash ECC
10 Program memory with ECC
8 RAM ECC Indicates if RAM memory ECC is present.
1 ECC implemented
7-3 REVISION Revision of the device.
2-0 101 The platform family ID is always 0b101
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8.9 Die Identification Registers
The two die ID registers at addresses 0xFFFFFF7C and 0xFFFFFF80 form a 64-bit die ID with the
information as shown in Table 8-3.
Table 8-3. Die-ID Registers
ITEM NUMBER OF BITS BIT LOCATION
X Coord. on Wafer 12 0xFFFFFF7C[11:0]
Y Coord. on Wafer 12 0xFFFFFF7C[23:12]
Wafer # 8 0xFFFFFF7C[31:24]
Lot # 24 0xFFFFFF80[23:0]
Reserved 8 0xFFFFFF80[31:24]
8.10 Module Certifications
The following communications modules have received certification of adherence to a standard.
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8.10.3.2 LIN Slave Mode - Fixed Baud Rate
Figure 8-7. LIN Certification - Slave Mode - Fixed Baud Rate
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8.10.3.3 LIN Slave Mode - Adaptive Baud Rate
Figure 8-8. LIN Certification - Slave Mode - Adaptive Baud Rate
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9 Mechanical Packaging and Orderable Information
9.1 Packaging Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
without revision of this document. For browser-based versions of this data sheet, refer to the left-hand
navigation.
Copyright © 2012–2015, Texas Instruments Incorporated Mechanical Packaging and Orderable Information 165
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PACKAGE OPTION ADDENDUM
www.ti.com 27-Jul-2018
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TMS5702125DPGEQQ1 ACTIVE LQFP PGE 144 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 TMS570LS
2125DPGEQQ1
TMS5702135DPGEQQ1 ACTIVE LQFP PGE 144 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 TMS570LS
2135DPGEQQ1
TMS5702135DZWTQQ1 ACTIVE NFBGA ZWT 337 90 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 125 TMS570LS
2135DZWTQQ1
TMS5703135DPGEQQ1 ACTIVE LQFP PGE 144 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 TMS570LS
3135DPGEQQ1
TMS5703135DZWTQQ1 ACTIVE NFBGA ZWT 337 90 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 125 TMS570LS
3135DZWTQQ1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
www.ti.com 27-Jul-2018
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
www.ti.com
PACKAGE OUTLINE
C
1.4 MAX
TYP
0.45
0.35
14.4
TYP
14.4 TYP
0.8 TYP
0.8 TYP
337X 0.55
0.45
B16.1
15.9 A
16.1
15.9
(0.8) TYP
(0.8) TYP
NFBGA - 1.4 mm max heightZWT0337A
PLASTIC BALL GRID ARRAY
4223381/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
13 14 15 16 17 18 19
BALL A1 CORNER
SEATING PLANE
BALL TYP 0.12 C
0.15 C A B
0.05 C
SYMM
SYMM
BALL A1 CORNER
W
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
12 3 45678910 11
A
B
12
SCALE 0.950
www.ti.com
EXAMPLE BOARD LAYOUT
337X ( 0.4) (0.8) TYP
(0.8) TYP
( 0.4)
METAL 0.05 MAX
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
( 0.4)
SOLDER MASK
OPENING
0.05 MIN
NFBGA - 1.4 mm max heightZWT0337A
PLASTIC BALL GRID ARRAY
4223381/A 02/2017
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
SYMM
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:7X
1234567 8 910 11
B
A
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
12 13 14 15 16 17 18 19
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
EXPOSED METAL
SOLDER MASK
DEFINED
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(0.8) TYP
(0.8) TYP ( 0.4) TYP
NFBGA - 1.4 mm max heightZWT0337A
PLASTIC BALL GRID ARRAY
4223381/A 02/2017
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE:7X
SYMM
SYMM
1234567 8 910 11
B
A
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
12 13 14 15 16 17 18 19
MECHANICAL DATA
MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK
4040147/C 10/96
0,27
72
0,17
37
73
0,13 NOM
0,25
0,75
0,45
0,05 MIN
36
Seating Plane
Gage Plane
108
109
144
SQ
SQ
22,20
21,80
1
19,80
17,50 TYP
20,20
1,35
1,45
1,60 MAX
M
0,08
0°–7°
0,08
0,50
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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