EP1400SJETPDC-1.8432M EP14 00 SJ ET RoHS PD C -1.8432M Series RoHS Compliant 5.0V Plastic J-Lead SMD HCMOS/TTL Programmable Oscillator Nominal Frequency 1.8432MHz Output Logic Type CMOS Frequency Tolerance/Stability 100ppm Maximum Pin 1 Connection Power Down (Disable Output: Logic Low) Package Operating Temperature Range -40C to +85C Duty Cycle 50 10(%) ELECTRICAL SPECIFICATIONS Nominal Frequency 1.8432MHz Frequency Tolerance/Stability 100ppm Maximum (Inclusive of all conditions: Calibration Tolerance at 25C, Frequency Stability over the Operating Temperature Range,Supply Voltage Change, Output Load Change, First Year Aging at 25C, Shock, and Vibration) Aging at 25C 5ppm/year Maximum Operating Temperature Range -40C to +85C Supply Voltage 5.0Vdc 10% Input Current 45mA Maximum (Unloaded) Output Voltage Logic High (Voh) Vdd-0.4Vdc Minimum (IOH = -16mA) Output Voltage Logic Low (Vol) 0.4Vdc Maximum (IOL = +16mA) Rise/Fall Time 4nSec Maximum (Measured at 20% to 80% of waveform) Duty Cycle 50 10(%) (Measured at 1.4Vdc with TTL Load; Measured at 50% of waveform with HCMOS Load) Load Drive Capability 50pF HCMOS Load Maximum Output Logic Type CMOS Pin 1 Connection Power Down (Disable Output: Logic Low) Tri-State Input Voltage (Vih and Vil) +2.0Vdc Minimum to enable output, +0.8Vdc Max, to disable output, No Connect to enable output. Standby Current 50A Maximum (Pin 1 = Ground) Disable Current 30mA Maximum (Pin 1 = Ground) Absolute Clock Jitter 250pSec Maximum, 100pSec Typical One Sigma Clock Period Jitter 50pSec Maximum Start Up Time 10mSec Maximum Storage Temperature Range -55C to +125C ENVIRONMENTAL & MECHANICAL SPECIFICATIONS Fine Leak Test MIL-STD-883, Method 1014, Condition A Gross Leak Test MIL-STD-883, Method 1014, Condition C Mechanical Shock MIL-STD-202, Method 213, Condition C Resistance to Soldering Heat MIL-STD-202, Method 210 Resistance to Solvents MIL-STD-202, Method 215 Solderability MIL-STD-883, Method 2003 Temperature Cycling MIL-STD-883, Method 1010 Vibration MIL-STD-883, Method 2007, Condition A www.ecliptek.com | Specification Subject to Change Without Notice | Rev D 8/12/2010 | Page 1 of 5 EP1400SJETPDC-1.8432M MECHANICAL DIMENSIONS (all dimensions in millimeters) 5.080 0.203 0.25 MIN 3 4 9.8 MAX 7.620 0.203 4.7 MAX 0.510 0.203 MARKING ORIENTATION 1 2 14.0 MAX PIN CONNECTION 1 Power Down (Logic Low) 2 Ground 3 Output 4 Supply Voltage LINE MARKING 1 ECLIPTEK 2 1.8432M 3 PXXYZZ P=Configuration Designator XX=Ecliptek Manufacturing Code Y=Last Digit of the Year ZZ=Week of the Year Suggested Solder Pad Layout All Dimensions in Millimeters 1.27 (X4) 3.0 (X4) Solder Land (X4) 5.8 3.81 All Tolerances are 0.1 www.ecliptek.com | Specification Subject to Change Without Notice | Rev D 8/12/2010 | Page 2 of 5 EP1400SJETPDC-1.8432M CLOCK OUTPUT POWER DOWN INPUT OUTPUT WAVEFORM & TIMING DIAGRAM VIH VIL VOH 80% or 2.0VDC OUTPUT DISABLE (LOGIC LOW) 50% or 1.4VDC 20% or 0.8VDC VOL tPLZ Fall Time Rise Time tPZL TW T Duty Cycle (%) = TW/T x 100 Test Circuit for TTL Output Output Load Drive Capability RL Value (Ohms) CL Value (pF) 10TTL 5TTL 2TTL 10LSTTL 1TTL 390 780 1100 2000 2200 15 15 6 15 3 Oscilloscope Table 1: RL Resistance Value and CL Capacitance Value Vs. Output Load Drive Capability + + Power Supply _ Current Meter _ Supply Voltage (VDD) Frequency Counter Probe (Note 2) RL (Note 4) Output + Voltage Meter _ + 0.01F (Note 1) 0.1F (Note 1) Ground CL (Note 3) Power Supply _ No Connect or Tri-State Note 1: An external 0.1F low frequency tantalum bypass capacitor in parallel with a 0.01F high frequency ceramic bypass capacitor close to the package ground and VDD pin is required. Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance (>10Mohms), and high bandwidth (>300MHz) passive probe is recommended. Note 3: Capacitance value CL includes sum of all probe and fixture capacitance. Note 4: Resistance value RL is shown in Table 1. See applicable specification sheet for 'Load Drive Capability'. Note 5: All diodes are MMBD7000, MMBD914, or equivalent. www.ecliptek.com | Specification Subject to Change Without Notice | Rev D 8/12/2010 | Page 3 of 5 EP1400SJETPDC-1.8432M Test Circuit for CMOS Output Frequency Counter Oscilloscope + + Power Supply _ Current Meter _ Supply Voltage (VDD) Probe (Note 2) Output + Voltage Meter _ 0.01F (Note 1) 0.1F (Note 1) Ground CL (Note 3) No Connect or Tri-State Note 1: An external 0.1F low frequency tantalum bypass capacitor in parallel with a 0.01F high frequency ceramic bypass capacitor close to the package ground and VDD pin is required. Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance (>10Mohms), and high bandwidth (>300MHz) passive probe is recommended. Note 3: Capacitance value CL includes sum of all probe and fixture capacitance. www.ecliptek.com | Specification Subject to Change Without Notice | Rev D 8/12/2010 | Page 4 of 5 EP1400SJETPDC-1.8432M Recommended Solder Reflow Methods Critical Zone TL to T P Temperature (T) TP Ramp-up Ramp-down TL TS Max TS Min tL t S Preheat t 25C to Peak tP Time (t) Low Temperature Infrared/Convection 240C TS MAX to TL (Ramp-up Rate) Preheat - Temperature Minimum (TS MIN) - Temperature Typical (TS TYP) - Temperature Maximum (TS MAX) - Time (tS MIN) Ramp-up Rate (TL to TP) Time Maintained Above: - Temperature (TL) - Time (tL) Peak Temperature (TP) Target Peak Temperature (TP Target) Time within 5C of actual peak (tp) Ramp-down Rate Time 25C to Peak Temperature (t) Moisture Sensitivity Level 5C/second Maximum N/A 150C N/A 60 - 120 Seconds 5C/second Maximum 150C 200 Seconds Maximum 240C Maximum 240C Maximum 1 Time / 230C Maximum 2 Times 10 seconds Maximum 2 Times / 80 seconds Maximum 1 Time 5C/second Maximum N/A Level 1 Low Temperature Manual Soldering 185C Maximum for 10 seconds Maximum, 2 times Maximum. High Temperature Manual Soldering 260C Maximum for 5 seconds Maximum, 2 times Maximum. www.ecliptek.com | Specification Subject to Change Without Notice | Rev D 8/12/2010 | Page 5 of 5