Rev. 1.4 12/17 Copyright © 2017 by Silico n Laboratories Si826x
Si826x
5KV LED EMULATOR INPUT, 4.0 A ISOLATED GATE DRIVERS
Features
Applications
Safety Regulatory Approvals
Description
The Si826x isolators are pin-compatible, drop-in upgrades for popular opto-
coupled gate drivers, such as 0.6 A ACPL-0302/3020, 2.5 A HCPL-3120/ACPL-
3130, HCNW3120/3130, and similar opto-drivers. The devices are ideal for driving
power MOSFETs and IGBTs used in a wide variety of inverter and motor control
applications. The Si826x isolated gate drivers utilize Silicon Laboratories'
proprietary silicon isolation technology, supporting up to 5.0 kVRMS withstand
voltage per UL1577 and 10kV surge protection per VDE 0884-10. This technology
enables higher-performan ce, reduced variation with tempe rature and age, tighter
part-to-part matching, and superior common-mode rejection compared to opto-
coupled gate drivers. While the input ci rcuit mimics the characteristics of an LED,
less drive current is required, resulting in higher efficiency. Propagation delay time
is independent of input drive current, resulting in consistently short propagation
times, tighter unit-to- unit variation, and greater input circuit design flexibility. As a
result, the Si826x series offers longer service life and dramatically higher reliability
compared to opto-coupled gate drivers.
Pin-compatible, drop-in upgrades for
popular high speed opto-coupled
gate drivers
Low power diode emulator simplifies
design-in process
0.6 and 4.0 Amp peak output drive
current
Rail-to-rail output voltage
Performance and reliability
advantages vs. opto-drivers
Resistant to temperature and age
10x lower FIT rate for longer
service life
14x tighter part-to-part matching
Higher common-mode transient
immunity: >50 kV/µs typical
Robust protection features
Multiple UVLO ordering options
(5, 8, and 12 V) with hysteresis
60 ns propagation delay,
independent of input drive current
Wide VDD range: 6.5 to 30 V
Up to 5000 VRMS isolation
10 kV surge withstand capability
AEC-Q100 qualified
Wide operating temperature range
–40 to +125 °C
RoHS-compliant packages
SOIC-8 (Narrow body)
DIP8 (Gull-wing)
SDIP6 (Stretched SO-6)
IGBT/ MOSFET gate drives
Industrial, HEV and renewable
energy inverters
AC, Brushless, and DC motor
controls and drives
Variable speed motor control in
consumer w hi t e goods
Isolated switch mode and UPS
power supplies
UL 1577 recognized
Up to 5000 Vrms for 1 minute
CSA component notice 5A approval
IEC 60950-1, 60601-1
(reinforced insulation)
VDE certification conformity
VDE0884-10
(basic/reinforced insulation)
CQC certification approval
GB4943.1
Patent pending
Pin Assignments:
See page 23
1
2
3
4
8
7
6
5
ANODE
CATHODE
NC
VDD
VO
VO
SOIC-8, DIP8
Industry Standard Pinout
GND
UVLO
1
3
6
5
4
ANODE
CATHODE
VDD
VO
GND
SDIP6
Industry Standard Pinout
2
NC
UVLO
e
e
Si826x
2 Rev. 1.4
Functional Block Diagram
Diode
Emulator
IF
A1
OUT
VDD
XMIT
GND
REC
C1
Output Driver
Si826x
Rev. 1.4 3
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Regulatory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4. Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.1. Device Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.2. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.3. Under Voltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
5. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5.1. Input Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5.2. Output Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.3. Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.4. Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
6. Pin Descriptions (SOIC-8, DIP8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
7. Pin Descriptions (SDIP6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
9. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
10. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
11. Package Outline: DIP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
12. Land Pattern: DIP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
13. Package Outline: SDIP6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
14. Land Pattern: SDIP6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
15. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
15.1. Si826x Top Marking (Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
15.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
15.3. Si826x Top Marking (DIP8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
15.4. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
15.5. Si826x Top Marking (SDIP6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
15.6. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Si826x
4 Rev. 1.4
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Symbol Min Typ Max Unit
Supply Voltage VDD 6.5 — 30 V
Input Current IF(ON)
(see Figure 1) 6—30mA
Operating Temperature (Ambient) TA–40 — 125 °C
Table 2. Electrical Characteristics 1
VDD =15V or 30V, GND=0V, I
F=6mA, T
A= –40 to +125 °C; typical spe cs at 25 °C; TJ= –40 to +140 °C
Parameter Symbol Test Condition Min Typ Max Unit
DC Parameters
Supply Voltage2VDD (VDD – GND) 6.5 — 30 V
Supply Current (Output High) IDD
IF=10mA
VDD =15V
VDD =30V —
—1.8
2.0 2.4
2.7 mA
mA
Supply Current (Output Low) IDD
VF=0V; I
F=0mA
VDD =15V
VDD =30V —
—1.5
1.7 2.1
2.4 mA
mA
Input Current Threshold IF(TH) ——3.6mA
Input Current Hysteresis IHYS —0.34—mA
Input Forwar d Voltage (OFF ) VF(OFF) Measured at ANODE with
respect to CATHODE. ——1V
Input Forwar d Voltage (ON) VF(ON) Measured at ANODE with
respect to CATHODE. 1.6 — 2.8 V
Input Capacitance CIf=100kHz,
VF=0V,
VF=2V —
—15
15 —
—pF
Output Resistance High
(Source)3ROH Si826xAxx devices — 15 —
Si826xBxx devices (IOH =-1A) — 2.6 5.1
Output Resistance Low (Sink)3ROL Si826xAxx devices — 5 —
Si826xBxx devices (IOL =2A) — 0.8 2.0
Notes:
1. See "8.Ordering Guide" on page 24 for more information.
2. Minimum value of (VDD - GND) decoupling capacitor is 1 µF.
3. Both VO pins are required to be shorted together for 4.0 A compliance.
4. When performing this test, it is recommended that the DUT be soldered down to the PCB to reduce parasitic
inductances, which may cause over-stress conditions due to excessive ringing.
5. Guaranteed by characterization.
Si826x
Rev. 1.4 5
Output High Current (Source)3,4 IOH
Si826xAxx devices (IF=0),
(tPW_IOH < 250 ns)
(see Figure 3) —0.4—
A
Si826xBxx devices (IF=0),
(tPW_IOH < 250 ns),
(VDD –V
O=7.5V)
(see Figure 3) 0.5 1.8 —
Output Low Current (Sink)3,4 IOL
Si826xAxx devices
(IF=10mA),
(tPW_IOL <250 ns)
(see Figure 2)
—0.6—
A
Si826xBxx devices
(IF=10mA),
(tPW_IOL <250 ns),
(VO-GND=4.2V)
(see Figure 2)
1.2 4.0 —
High-Level Output Voltage VOH
Si826xAxx devices
(I OUT = –100 mA) —VDD–
0.4 —
V
Si826xBxx devices
(I OUT = –100 mA) VDD–
0.5 VDD–
0.25 —
Si826xBxx devices
(I OUT =0mA),
(IF=0mA) —V
DD —
Low-Level Output Voltage VOL
Si826xAxx devices
(I OUT = 100 mA),
(IF=10mA) —320 —
mV
Si826xBxx devices
(I OUT = 100 mA),
(IF=10mA) —80 200
UVLO Threshold +
(Si826xxAx mode) VDDUV+ See Figure 10 on page 17.
VDD rising 55.66.3V
UVLO Threshold –
(Si826xxAx mode) VDDUV– See Figure 10 on p age 17.
VDD falling 4.7 5.3 6.0 V
Table 2. Electrical Characteristics (Continued)1
VDD =15V or 30V, GND=0V, I
F=6mA, T
A= –40 to +125 °C; typical spe cs at 25 °C; TJ= –40 to +140 °C
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. See "8.Ordering Guide" on page 24 for more information.
2. Minimum value of (VDD - GND) decoupling capacitor is 1 µF.
3. Both VO pins are required to be shorted together for 4.0 A compliance.
4. When performing this test, it is recommended that the DUT be soldered down to the PCB to reduce parasitic
inductances, which may cause over-stress conditions due to excessive ringing.
5. Guaranteed by characterization.
Si826x
6 Rev. 1.4
UVLO lockout hysteresis
(Si826xxAx mode) VDDHYS —300—mV
UVLO Threshold +
(Si826xxBx mode) VDDUV+ See Figure 11 on page 17.
VDD rising 7.5 8.4 9.4 V
UVLO Threshold –
(Si826xxBx mode) VDDUV– See Figure 11 on page 17.
VDD falling 6.9 7.9 8.9 V
UVLO lockout hysteresis
(Si826xxBx mode) VDDHYS —500—mV
UVLO Threshold +
(Si826xxCx mode) VDDUV+ See Figure 12 on page 17.
VDD rising 10.5 12 13.5 V
UVLO Threshold –
(Si826xxCx mode) VDDUV– See Figure 12 on page 17.
VDD falling 9.4 10.7 12.2 V
UVLO lockout hysteresis
(Si826xxCx mode) VDDHYS —1.3—V
AC Switching Parameters
Input noise filter cut-off pulse
width tNFC — — 15 ns
Minimum pulse width tPMIN —30—ns
Propagation delay (Low-to-High) tPLH CL= 200 pF 20 40 60 ns
Propaga tion delay (High-to-Low) tPHL CL= 200 pF 10 30 50 ns
Pulse Width Distortion PWD |tPLH –t
PHL| — 17 28 ns
Propaga tion Delay Difference5PDD tPHLMAX –t
PLHMIN -1 — 25 ns
Rise time tRCL= 200 pF — 5.5 15 ns
Fall time tFCL= 200 pF — 8.5 20 ns
Device Startup Time tSTART —1630µs
Common Mode
Transient Immunity CMTI Output = low or high
(VCM = 1500 V), (IF>6mA)
(See Figure 4)
35 50 — kV/µs
Table 2. Electrical Characteristics (Continued)1
VDD =15V or 30V, GND=0V, I
F=6mA, T
A= –40 to +125 °C; typical spe cs at 25 °C; TJ= –40 to +140 °C
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. See "8.Ordering Guide" on page 24 for more information.
2. Minimum value of (VDD - GND) decoupling capacitor is 1 µF.
3. Both VO pins are required to be shorted together for 4.0 A compliance.
4. When performing this test, it is recommended that the DUT be soldered down to the PCB to reduce parasitic
inductances, which may cause over-stress conditions due to excessive ringing.
5. Guaranteed by characterization.
Si826x
Rev. 1.4 7
Figure 1. Diode Emulator Model and I-V Curve
Figure 2. IOL Sink Current Test Circuit
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0 5 10 15 20 25 30
AnodetoCathodeVoltage[V]
DiodeEmulatorInputCurrent[mA]
700
2.2 V
10
Anode
Cathode
ESD
Anode
Cathode
e
INPUT 1 µF 100 µF
10
RSNS
0.1
Si826x
1 µF
CER 10 µF
EL
VDD = 1 5 V
IN OUT
GND
VDD
SCHOTTKY
50 ns
200 ns
Measure
I NPUT WAVEFO RM
GND
I
F
9 V +
_
Si826x
8 Rev. 1.4
Figure 3. IOH Source Current Test Circuit
Figure 4. Common Mode Transient Immunity Characterization Circuit
INPUT
1 µF 100 µF
10
RSNS
0.1
Si826x
1 µF
CER 10 µF
EL
VDD = 15 V
IN OUT
VSS
VDD
50 ns
200 ns
Measure
I NPUT W AVEFORM
GND
I
F
SCHOTTKY 5.5 V +
_
Oscilloscope
5 V
Isolated
Supply VO
15 V
Supply
High Voltage
Surge Generator
Vcm Surge
Output
High Voltage
Diffe re n tia l
Probe
GNDCathode
Anode
Inpu t Signa l
Switch
Input Output
Isolated
Ground
267 Si826x
VDD
Si826x
Rev. 1.4 9
2. Regulatory Information
Table 3. Regulatory Information*
CSA
The Si826x is certified under CSA Component Acceptance Notice 5A. For more details, see Master Contract
Number 232873.
60950-1: Up to 1000 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working
voltage.
60601-1: Up to 250 VRMS working voltage and 2 MOPP (Means of Patient Protection).
VDE
The Si826x is certified according to VDE0884-10. For more details, see certificate 40037 51 9 .
VDE0884 Part 10: Up to 1414 Vpeak for reinforced insulation working voltage.
UL
The Si826x is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage for basic protection.
CQC
The Si826x is certified under GB4943.1-2011. For more details, see certificates CQC15001121282 and
CQC15001121283.
Rated up to 1000 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
*Note: Regulatory Certifications apply to 3.75 kVRMS rated devices which are production tested to 4.5 kVRMS fo r 1 sec.
Regulatory Certifications apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.
For more information, see "8.Orde ring Guide" on page 24.
Table 4. Insulation and Safety-Related Specifications
Parameter Symbol Test Condition Value Unit
SOIC-8 DIP8 SDIP6
Nominal External Air Gap
(Clearance) CLR 4.7 min 7.2 min 9.6 min mm
Nominal External Tracking
(Creepage) CPG 3.9 min 7.0 min 8.3 min mm
Minimum Internal Gap
(Internal Clearance) DTI 0.016 0.016 0.016 mm
Tracking Resistance CTI or
PTI IEC60112 600 600 600 V
Erosion Depth ED 0.031 0.031 0.057 mm
Resistance (Input-Output)* RIO 1012 1012 1012
Capacitance (Input-Output)* CIO f=1MHz 1 1 1 pF
*Note: To determine resistance and capacit ance, the Si826x is converted into a 2-terminal device. Pins 1–4 (1–3, SDIP6) are
shorted together to form the first terminal, and pins 5–8 (4–6, SDIP6) are shorted together to form the second terminal.
The parameters are then measured between these two terminals.
Si826x
10 Rev. 1.4
Table 5. IEC 60664-1 Ratings
Parameter Test Conditions Specification
SOIC-8 DIP8 SDIP6
Basic Isolation Group Material Group I I I
Installation
Classification
Rated Mains Voltages <
150 VRMS I-IV I-IV I-IV
Rated Mains Voltages <
300 VRMS I-IV I-IV I-IV
Rated Mains Voltages <
450 VRMS I-III I-III I-IV
Rated Mains Voltages <
600 VRMS I-III I-III I-IV
Rated Mains Voltages <
1000 VRMS I-II I-II I-III
Table 6. VDE 0884-10 Insulation Characteristics*
Parameter Symbol Test Condition Characteristic Unit
SOIC-8 DIP8 SDIP6
Maximum Working
Insulation Voltage VIORM 630 8 91 1140 V peak
Input to Output Test
Voltage VPR
Method b1
(VIORM x 1.875 = VPR, 100%
Production Test, tm= 1 sec,
Partial Discharge < 5 pC)
1181 1671 2138 V peak
Transient Overvoltage VIOTM t = 60 sec 6000 6000 8000 V peak
Surge Voltage VIOSM
Tested per IEC 60065 with
surge voltage of 1.2 μs/50 μs
Si826x tested with magnitude
6250 V x 1.6 = 10 kV
6250 6250 6250 V peak
Pollution Degree
(DIN VDE 0110, Table 1) 222
Insulation Resistance at
TS, VIO =500V RS>109>109>109
*Note: This isolator is suitable for reinforced electrical isola tion only within the sa fety limit data. Maintenance of the safety
data is ensured by protective circuits. The Si826x provides a climat e classification of 40/ 125/21.
Si826x
Rev. 1.4 11
Table 7. IEC Safety Limiting Values*
Parameter Symbol Test Condition Max Unit
SOIC-8 DIP8 SDIP6
Case Temperature TS140 140 140 °C
Input Current IS
JA = 110 °C/W (SOIC-8),
110 °C/W (DIP8),
105 °C/W (SDIP6),
VF= 2.8 V, TJ=140°C,
TA=25°C
370 370 390 mA
Output Power PS111W
*Note: Maximum value allowed in the event of a failure; also see the thermal derating curve in Figures 5, 6, 7, and 8.
Si826x
12 Rev. 1.4
Figure 5. (SOIC-8) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per VDE0884-10
Figure 6. (DIP8) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per VDE0884-10
Table 8. Thermal Characteristics
Parameter Symbol Typ Unit
SOIC-8 DIP8 SDIP6
IC Junction-to- Air The rm a l
Resistance JA 110 110 105 ºC/W
400
600
800
1000
1200
owerͲ Ps,InputCurrentͲ Is
Ps(mW)
Is(mA)
0
200
0 20406080100120140
OutputPo
TsͲ CaseTemperature(°C)
400
600
800
1000
1200
owerͲ Ps,InputCurrentͲ Is
Ps(mW)
Is(mA)
0
200
0 20406080100120140
OutputPo
TsͲ CaseTemperature(°C)
Si826x
Rev. 1.4 13
Figure 7. (SDIP6) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per VDE0884-10
400
600
800
1000
1200
owerͲ Ps,InputCurrentͲ Is
Ps(mW)
Is(mA)
0
200
0 20406080100120140
OutputPo
TsͲ CaseTemperature(°C)
Si826x
14 Rev. 1.4
Table 9. Absolute Maximum Ratings*
Parameter Symbol Min Max Unit
Storage Temperature TSTG –65 +150 °C
Operating Temperature TA–40 +125 °C
Junction Temperature TJ—+140°C
Average Forward Input Current IF(AVG) —30mA
Peak Transient Input Current
(< 1 µs pulse width, 300 ps) IFTR —1A
Reverse Input Voltage VR—0.3V
Supply Voltage VDD –0.5 36 V
Output Voltage VOUT –0.5 36 V
Peak Output Current (tPW = 10 µs, duty cycle = 0.2%)
(0.6 Amp versions) IOPK —0.6A
Peak Output Current (tPW = 10 µs, duty cycle = 0.2%)
(4.0 Amp versions) IOPK —4.0A
Input Power Dissipation PI—75mW
Output Power Dissipation PO—225mW
To tal Power Dissipation
(all packages limited by thermal derating curve) PT—300mW
Lead Solder Temper at ur e (1 0 s) — 260 °C
HBM Rating ESD 4 — kV
Machine Model ESD 300 — V
CDM 2000 — V
Maximum Isolation Voltage (1 s) SOIC-8 — 4500 VRMS
Maximum Isolation Voltage (1 s) DIP8 — 6500 VRMS
Maximum Isolation Voltage (1 s) SDIP6 — 6500 VRMS
*Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions specified in the operational sections of this data sheet.
Si826x
Rev. 1.4 15
3. Functional Description
3.1. Theory of Operation
The Si826x is a functional upgrade for popular opto-isolated drivers, such as the Avago HPCL-3120, HPCL-0302,
Toshiba TLP350, and others. The operatio n of an Si826x chann el is analogous to that of an opto coupler, except an
RF carrier is modulated instead of light. This simple architecture provides a robust isolated data path and requires
no special considerations or initialization at start-up. The Si826x also includes a noise filter that suppresses
propagation of any pulse narrower th an 15 ns. A simplified block diagram for the Si826x is shown in Figure 8.
Figure 8. Simplified Channel Diagram
RF
OSCILLATOR
MODULATOR DEMODULATOR
+
NOISE FILTER
AB
Semiconductor-
Based Isolation
Barrier
Transmitter Receiver
LED
Emulator 0.6 to 4.0 A
peak
Gnd
VDD
Si826x
16 Rev. 1.4
4. Technical Description
4.1. Device Behavior
Truth tables for the Si826x are summarized in Table 10.
4.2. Device Startup
Output VO is held low during power-up until VDD rises above the UVLO+ threshold for a minimum time period of
tSTART. Following this, the output is high when the curren t flowing from anode to cath ode is > IF(ON). Device startup,
normal operation, and shutdown behavior is shown in Figure 9.
Figure 9. Si826x Operating Behavior (IF > IF(MIN) when VF > VF(MIN))
Table 10. Si826x Truth Table Summary*
Input VDD VO
OFF > UVLO LOW
OFF < UVLO LOW
ON > UVLO HIGH
ON < UVLO LOW
*Note: This truth table assumes VDD is powered. If VDD is below UVLO, see "4.3.Under Voltage
Lockout (UVLO)" on page 17 for more information.
I
F
V
O
V
DD
t
START
t
START
V
DDHYS
t
PHL
t
PLH
I
F(ON)
UVLO+
UVLO-
I
HYS
Si826x
Rev. 1.4 17
4.3. Under Voltage Lockout (UVLO)
The UVLO circuit unconditionally drives VO low when VDD is below the lockout threshold. Referring to Figures 10
through 12, upon power up, th e Si826x is maint ained in UVLO until VDD rises above VDDUV+. During power down,
the Si826x enters UVLO when VDD falls below the UVLO threshold plus hysteresis (i.e., VDD < VDDUV+ –
VDDHYS).
Figure 10. Si826xxAx UVLO Response (5 V)
Figure 11. Si826xxBX UVLO Response (8 V)
Figure 12. Si826xxCx UVLO Response (12 V)
3.5
VDDUV+ (Typ)
Output Voltage (VO)
4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5
S u p p ly V o lta ge (V DD - GND) (V)
6.0
VDDUV+ (Typ)
Output Voltage (VO)
6.57.07.58.08.59.09.510.0
Supply Voltage (VDD - GND ) (V )
9.5
VDDUV+ (Typ)
Output Voltage (VO)
10.0 10.5 11.0 11.5 12.0 12.5 13.0
Supply Voltage (VDD - GND) (V )
Si826x
18 Rev. 1.4
5. Applications
The following sections detail the input and output circuits necessary for proper operation. Power dissipation and
layout conside ratio ns ar e also dis c us se d.
5.1. Input Circuit Design
Opto driver manufacturers typically recommend the circuits shown in Figures 13 and 14. These circuits are
specifically designed to improve opto-coupler input common-mode rejection and increase noise immunity.
Figure 13. Si826x Input Circuit
Figure 14. High CMR Si826x Input Circuit
The optically-coupled driver circuit of Figure 13 turns the LED on when the control inpu t is high. H owever, internal
capacitive coupling from the LED to the power and ground conductors can momentarily force the LED into its off
state when the anode and cathode inputs are subjected to a high common-mode transient. The circuit shown in
Figure 14 addres ses th is issu e by u sing a value o f R 1 sufficiently low to overdrive the LED, ens uring it re mains on
during an input common-mode transient. Q1 shorts the LED off in the low output state, again increasing common-
mode transient immunity.
Some opto driver applications re comme nd reve rse-bia sing the LED whe n the control input is off to prevent coupled
noise from energizing the LED. The Si826x input circuit requires less current and has twice the off-state noise
margin compared to opto couplers. However, high CMR opto coupler designs that overdrive the LED (see
Figure 14) may require increasing the value of R1 to limit input current IF to its maximum rating when using the
Si826x. In addition, there is no benefit in driving the Si826x input diode into reverse bias when in the off state.
R1 1
2
3
4
Si826x
Vext
Op en Drain or
C o lle c to r
Control
Input
ANODE
CATHODE
N/C
N/C
R1
1
2
3
4
Si826x
Vext
Control
Input
ANODE
CATHODE
N/C
N/C
Q1
Si826x
Rev. 1.4 19
Consequently, opto coupler circuits using this technique should eith er leave the n egative b ias cir cuitry un populated
or modify the circuitry (e.g., add a clamp diode or current limiting resistor) to ensure that the anode pin of the
Si826x is no more than –0.3 V with respect to the ca th od e wh en rev er se -b ias ed .
New designs should consider the input circuit configurations of Figure 15, which are more efficient than those of
Figures 13 and 14. As shown, S1 and S2 represent any suitable switch, such as a BJT or MOSFET, analog
transmission ga te, pr ocessor I/O, et c. Also, note that the Si826x input can be driven from the I/O port of any MCU
or FPGA capable of sourcing a minimum of 6 mA (see Figure 15C). Additionally, note that the Si826x propagation
delay and output drive do not significantly change for values of IF between IF(MIN) and IF(MAX).
Figure 15. Si826x Other Input Circuit Configurations
5.2. Output Circuit Design
GND can be biased at, above, or below ground as long as the voltage on VDD with res pect to GND is a maximum
of 30 V. VDD decoupling capacitors should be placed as close to the package pins as possible. The optimum
values for these capacitors depend on load current and the distance between the chip and its power source. It is
recommended that 0.1 and 10 µF bypass capacitors be used to reduce high-frequency noise and maximize
performance.
5.3. Layout Considerations
It is most important to minimize ringing in the drive path and noise on the VDD lines. Care must be taken to
minimize parasitic inductance in these paths by locating the Si826x as close as possible to the device it is driving.
In addition, the VDD supply and ground trace paths must be kept short. For this reason, the use of power and
ground planes is highly recommended. A split ground plane system having separate ground and VDD planes for
power devices and small signal components provides the best overall noise performance.
Control
Input
Vext
R1
S1
N/C
ANODE
CATHODE
N/C
See Text
Si826x
A
4
3
2
1
Si826x
1
2
3
4
Vext
Control
Input
S1 N/C
ANODE
CATHODE
N/C
B
R1
S2
Si826x
C
4N/C
3CATHODE
2
MCU I/O
Port pin ANODE
R1
1N/C
Si826x
20 Rev. 1.4
5.4. Power Dissipation Considerations
Proper system design must assure that the Si8 26x oper ates within safe thermal limits across the entire load r ange.
The Si826x total power dissipation is the sum of the power dissipated by bias supply current, internal switching
losses, and power delivered to the load, as shown in Equation 1.
Equation 1.
The maximum allowable power dissipation for the Si826x is a function of the package thermal resistance, ambient
temperature, and maximum allowable junction temperature, as shown in Equation 2.
Equation 2.
Substituting values for PDmax Tjmax, TA, and ja into Equation 2 results in a maximum allowable total power
dissipation of 1.0 W. Note that the maximum allowable load is found by substituting this limit and the appropriate
datasheet values from Table 2 on page 4 into Equation 1 and simplifying. Graphs are shown in Figures 16 and 18.
All points along the load lines in these graphs represent the package dissipation-limited value of CL for the
correspond in g switc hin g freq ue n cy.
PDIFVF
DCVDD
+IDDQ QdCL
+VDD
+f
where: PD is the total device power dissipation (W)
IF is the diode current (30 mA max)
VF is the diode anode to cathode voltage (2.8 V max)
DC is duty cycle (0.5 typical)
VDD is the driver-side supply voltage (30 V max)
IDDQ is the driver maximum bias current (2.5 mA)
Qd is 3 nC
CL is the load capacitance
f is the switching frequency (Hz)
=
PDmax Tjmax TA
–
ja
---------------------------
where:
PDmax is the maximum allowable power dissipation (W)
Tjmax is the maximum junction temperature (140 °C)
TA is the ambient temperature (°C)
ja is the package junction-to-air thermal resistance (110 °C/W)
Si826x
Rev. 1.4 21
Figure 16. (SOIC-8, DIP8, SDIP6) Maximum Load vs. Switching Frequency (25 °C)
0.1
1.0
10.0
100.0
1000.0
10000.0
10 100 1000
MaxLoad(nF)
Frequency(kHz)
7V
12V
18V
30V
Si826x
22 Rev. 1.4
6. Pin Descriptions (SOIC-8, DIP8)
Figure 17. Pin Configuration
Table 11. Pin Descriptions (SOIC-8, DIP8)
Pin Name Description
1 NC* No connect.
2 ANODE Anode of LED emulator. VO follows the signal applied to this input with respect to the
CATHODE input.
3 CATHODE Cathode of LED emulator. VO follows the signal applied to ANODE with respect to this input.
4 NC* No connect.
5 GND Externa l MOSFET source connection and ground reference for VDD. This terminal is typically
connected to ground but may be tied to a negative or positive voltage.
6V
OOutput signal. Both VO pins are required to be shorted together for 4.0 A compliance.
7V
OOutput signal. Both VO pins are required to be shorted together for 4.0 A compliance.
8V
DD Output-side power supply input referenced to GND (30 V max).
*Note: No Connect. These pins are not internally connected. To maximize CMTI performance, these pins should be
connected to the ground plane.
1
2
3
4
8
7
6
5
NC
ANODE
CATHODE
NC
VDD
VO
VO
SOIC-8, DIP8
Industry Standard Pinout
GND
UVLO
e
Si826x
Rev. 1.4 23
7. Pin Descriptions (SDIP6)
Figure 18. Pin Configuration
Table 12. Pin Descriptions (SDIP6)
Pin Name Description
1 ANODE Anode of LED emulator. VO follows the signal applied to this input with respect to the
CATHODE input.
2 NC* No connect.
3 CATHODE Cathode of LED emulator. VO follows the signal applied to ANODE with respect to this input.
4 GND Externa l MOSFET source connection and ground reference for VDD. This terminal is typically
connected to ground but may be tied to a negative or positive voltage.
5V
OOutput signal.
6V
DD Output-side power supply input referenced to GND (30 V max).
*Note: No Connect. These pins are not internally connected. To maximize CMTI performance, these pins should be
connected to the ground plane.
1
3
6
5
4
ANODE
CATHODE
VDD
VO
GND
SDIP6
Industry Standard Pinout
2
NC
UVLO
e
Si826x
24 Rev. 1.4
8. Ordering Guide
Table 13. Si826x Ordering Guide1,2,3
New Ordering
Part Number
(OPN)
Ordering Options
Output
Configuration Cross
Reference UVLO
Voltage Insulation
Rating Temp Range Pkg Type
Si8261AAC-C-IS 0.6 A driver HCPL-0314 5 V 3.75 kVrms –40 to +125 °C SOIC-8
Si8261BAC-C-IS 4.0 A driver — 5 V 3.75 kVrms –40 to +125 °C SOIC-8
Si8261AAC-C-IP 0.6 A driver HCPL-3140 5 V 3.75 kVrms –40 to +125 °C DIP8/GW
Si8261BAC-C-IP 4.0 A driver TLP 350
HCPL-3120 5 V 3.75 kVrms –40 to +125 °C DIP8/GW
Si8261AAD-C-IS 0.6 A driver ACPL-W314 5 V 5.0 kVrms –40 to +125 °C SDIP6
Si8261BAD-C-IS 4.0 A driver TLP 700F 5 V 5.0 kVrms –40 to +125 °C SDIP6
Notes:
1. All packages are RoHS-compliant with peak solder reflow temperatures of 260 °C according to the JEDEC industry
standard classifications.
2. “Si” and “SI” are used interchangeab ly.
3. AEC-Q100 qualified.
Si826x
Rev. 1.4 25
Si8261ABC-C-IS 0.6 A driver HCPL-0314 8 V 3.75 kVrms –40 to +125 °C SOIC-8
Si8261BBC-C-IS 4.0 A driver — 8 V 3.75 kVrms –40 to +125 °C SOIC-8
Si8261ABC-C-IP 0.6 A driver HCPL-3140 8 V 3.75 kVrms –40 to +125 °C DIP8/GW
Si8261BBC-C-IP 4.0 A driver TLP 350
HCPL-3120 8 V 3.75 kVrms –40 to +125 °C DIP8/GW
Si8261ABD-C-IS 0.6 A driver ACPL-W314 8 V 5.0 kVrms –40 to +125 °C SDIP6
Si8261BBD-C-IS 4.0 A driver TLP 700F 8 V 5.0 kVrms –40 to +125 °C SDIP6
Table 13. Si826x Ordering Guide1,2,3
New Ordering
Part Number
(OPN)
Ordering Options
Output
Configuration Cross
Reference UVLO
Voltage Insulation
Rating Temp Range Pkg Type
Notes:
1. All packages are RoHS-compliant with peak solder reflow temperatures of 260 °C according to the JEDEC industry
standard classifications.
2. “Si” and “SI” are used interchangeab ly.
3. AEC-Q100 qualified.
Si826x
26 Rev. 1.4
Si8261ACC-C-IS 0.6 A driver HCPL-0314 12 V 3.75 kVrms –40 to +125 °C SOIC-8
Si8261BCC-C-IS 4.0 A driver — 12 V 3.75 kVrms –40 to +125 °C SOIC-8
Si8261ACC-C-IP 0.6 A driver HCPL-3140 12 V 3.75 kVrms –40 to +125 °C DIP8/GW
Si8261BCC-C-IP 4.0 A driver TLP 350
HCPL-3120 12 V 3.75 kVrms –4 0 to +125 °C DIP8/GW
Si8261ACD-C-IS 0.6 A driver ACPL-W314 12 V 5.0 kVrms –40 to +125 °C SDIP6
Si8261BCD-C-IS 4.0 A driver TLP 700F 12 V 5.0 kVrms –40 to +125 °C SDIP6
Table 13. Si826x Ordering Guide1,2,3
New Ordering
Part Number
(OPN)
Ordering Options
Output
Configuration Cross
Reference UVLO
Voltage Insulation
Rating Temp Range Pkg Type
Notes:
1. All packages are RoHS-compliant with peak solder reflow temperatures of 260 °C according to the JEDEC industry
standard classifications.
2. “Si” and “SI” are used interchangeab ly.
3. AEC-Q100 qualified.
Si826x
Rev. 1.4 27
9. Package Outline: 8-Pin Narrow Body SOIC
Figure 19 illustrates the package details for the Si826x in an 8-pin narrow-body SOIC package. Table 14 lists the
values for the dimensions shown in the illustration.
Figure 19. 8-Pin Narrow Body SOIC Package
Table 14. 8-Pin Narrow Body SOIC Package Diagram Dimensions
Symbol Millimeters
Min Max
A1.351.75
A1 0.10 0.25
A2 1.40 REF 1.55 REF
B0.330.51
C0.190.25
D4.805.00
E3.804.00
e 1.27 BSC
H5.806.20
h0.250.50
L0.401.27
08
Si826x
28 Rev. 1.4
10. Land Pattern: 8-Pin Narrow Body SOIC
Figure 20 illustrates the recommended land pattern details for the Si826x in an 8-pin narrow-body SOIC. Table 15
lists the values for the dimensions shown in the illustration.
Figure 20. 8-Pin Narrow Body SOIC Land Pattern
Table 15. 8-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension Feature (mm)
C1 Pad Column Spacing 5.40
E Pad Row Pitch 1.27
X1 Pad Width 0.60
Y1 Pad Length 1.55
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X173-8 N for
Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Si826x
Rev. 1.4 29
11. Package Outline: DIP8
Figure 21 illustrates the package details for the Si826x in a DIP8 package. Table 16 lists the values for the
dimensions shown in the illustration.
Figure 21. DIP8 Package
Table 16. DIP8 Package Diagram Dimensions
Dimension Min Max
A — 4.19
A1 0.55 0.75
A2 3.17 3.43
b 0.35 0.55
b2 1.14 1.78
b3 0.76 1.14
c 0.20 0.33
D 9.40 9.90
E 7.37 7.87
E1 6.10 6.60
E2 9.40 9.90
e 2.54 BSC.
L 0.38 0.89
aaa — 0.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Si826x
30 Rev. 1.4
12. Land Pattern: DIP8
Figure 22 illustrates the recommended land pattern details for the Si826x in a DIP8 package. Table 17 lists the
values for the dimensions shown in the illustration.
Figure 22. DIP8 Land Pattern
Table 17. DIP8 Land Pattern Dimensions*
Dimension Min Max
C8.858.90
E2.54 BSC
X0.600.65
Y1.651.70
*Note: This Land Pattern Design is based on the IPC-7351 specification.
Si826x
Rev. 1.4 31
13. Package Outline: SDIP6
Figure 23 illustrates the package details for the Si826x in an SDIP6 package. Table 18 lists the values for the
dimensions shown in the illustration.
Figure 23. SDIP6 Package
Table 18. SDIP6 Package Diagram Dimensions
Dimension Min Max
A—2.65
A1 0.10 0.30
A2 2.05 —
b0.310.51
c0.200.33
D 4.58 BSC
E 11.50 BSC
E1 7.50 BSC
e 1.27 BSC
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Si826x
32 Rev. 1.4
L0.401.27
h0.250.75
θ0° 8°
aaa — 0.10
bbb — 0.33
ccc — 0.10
ddd — 0.25
eee — 0.10
fff — 0.20
Table 18. SDIP6 Package Diagram Dimensions (Continued)
Dimension Min Max
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Si826x
Rev. 1.4 33
14. Land Pattern: SDIP6
Figure 24 illustrates the recommended land pattern details for the Si826x in an SDIP6 package. Table 19 lists the
values for the dimensions shown in the illustration.
Figure 24. SDIP6 Land Pattern
Table 19. SDIP6 Land Pattern Dimensions*
Dimension Min Max
C 10.45 10.50
E1.27 BSC
X0.550.60
Y2.002.05
*Note: This Land Pattern Design is based on the IPC-7351 specification.
Si826x
34 Rev. 1.4
15. Top Markings
15.1. Si826x Top Marking (Narrow Body SOIC)
15.2. Top Marking Explanation
Line 1 Marking:
Customer Part Number 826 = ISOdriver product series
C = Input configuration
1 = Opto input type
I = Peak output current
A=0.6A; B=4.0A
U = UVLO level
A = 5 V; B = 8 V; C = 12 V
V = Is ola tio n ra ting
C = 3.75 kV; D = 5.0 kV
Line 2 Marking: RTTTTT = Mfg Code Manufacturing Code from the Assembly Purchase
Order form.
“R” indicates revision.
Line 3 Marking:
Circle = 43 mils Diameter
Left-Justified “e4” Pb-Free Symbol
YY = Year
WW = Work Week Assigned by the Assembly House . Corr esponds to
the year and work week of the mold date.
Si826x
Rev. 1.4 35
15.3. Si826x Top Marking (DIP8)
15.4. Top Marking Explanation
Line 1 Marking:
Customer Part Number Si826 = ISOdriver product serie s
C = Input configuration
1 = Opto input type
I = Peak output current
A=0.6A; B=4.0A
U = UVLO level
A = 5 V; B = 8 V; C = 12 V
V = Is ola tio n ra ting
C = 3.75 kV; D = 5.0 kV
Line 2 Marking:
YY = Year
WW = Work Week Assigned by the Assembly House . Corr esponds to
the year and work week of the mold date.
RTTTTT = Mfg Code Manufacturing Code from the Assembly Purchase
Order form.
“R” indicates revision.
Line 3 Marking:
Circle = 51 mils Diameter
Center-Justified “e4” Pb-Free Symbol
CO = Country of Origin Country of Origin
ISO Code Abbreviation
Si826x
36 Rev. 1.4
15.5. Si826x Top Marking (SDIP6)
15.6. Top Marking Explanation
Line 1 Marking: Device Si826 = ISOdriver product series
C = Input configuration
1 = Opto input type
Line 2 Marking:
Device Rating I = Peak output current
A=0.6A; B=4.0A
U = UVLO level
A = 5 V; B = 8 V; C = 12 V
V = Is ola tio n ra ting
C = 3.75 kV; D = 5.0 kV
Line 3 Marking: RTTTTT = Mfg Code Manufacturing Code from the Assembly Purchase
Order form.
“R” indicates revision.
Line 4 Marking: YY = Year
WW = Work Week Assigned by the Asse m bly House. Correspond s to the
year and work week of the mold date.
Si826x
Rev. 1.4 37
DOCUMENT CHANGE LIST
Revision 0.9 to Revision 1.0
Updated Table 2 on page 4.
Added Figure 1 on page 7.
Updated "3.1. T heor y of Op e ra tio n" on page 15.
Updated Figures 10, 11, and 12 on page 17.
Removed “5.5. Parametric Differences between
Si826x and HCPL-0302 and HCPL-3120 Opto
Drivers”.
Revision 1.0 to Revision 1.1
Updated Figu re 1 on page 7.
Updated Ordering Guide Table 13 on page 24.
Removed references to moisture sensitivity levels from
table note.
Revision 1.1 to Revision 1.2
Removed “Sampling” from Ordering Guide Table 13
on page 24.
Revision 1.2 to Revision 1.3
Updated Table 3 on page 9.
Added CQC certificate numbers.
Updated Table 5 on page 10.
Updated Rate d Mains Voltage for 1000 VRMS ratings.
Updated Table 6 on page 10.
Removed VIOSM specificatio n.
Updated Table 9 on page 14.
Replaced IO with Peak Output Current IOPK.
Updated Figu re 13 on page 18.
Updated Figu re 14 on page 18.
Updated Figu re 15 on page 19.
Changed VDD minimum throughout document to
reflect 6.5 V, not 5 V, as normal operation.
Revision 1.3 to Revision 1.4
Removed references to LGA8 throughout.
Deleted all IEC 60747-5 and IEC 61010 refere nces
throughout and added VDE 0884-10 references
throughout.
Updated all certification body’s certificate and file
reference numbers throughout.
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