DAC-08 8-Bit High Speed Multiplying D/A Converter Distinctive Characteristics @ Fast settling output current 85nsec @ Full scale current prematched to +1.0 LSB Direct interface to TTL, CMOS, ECL, HTL, NMOS @ Nonlinearity to +0.1% max over temperature range @ High output impedance and compliance 10V to +18V Differential current outputs Wide range multiplying capability 1.0MHz bandwidth Low FS current drift +10ppm/C Wide power supply range +4.5V to +18V Low power consumption 33mW @ +5V The DAC-08 series of 8-bit monolithic multiplying Digital- to-Analog Converters provide very high speed performance coupled with low cost and outstanding applications flexibility. Advanced circuit design achieves 85 nsec settling times with very low glitch and a low power consumption. Monotonic multiplying performance is attained over more than a 40 to 7 reference current range. Matching to within 1 LSB between reference and full scale currents eliminates the need for full scale trimming in most applications. Direct interface to all popular logic families with full noise immunity is provided by the high swing, adjustable threshold logic inputs. High voltage compliance dual complementary current outputs are provided, increasing versatility and enabling differential operation to effectively double the peak-to-peak output swing. In many applications, the outputs can be directly converted to voltage without the need for an external op amp. GENERAL DESCRIPTION All DAC-08 series models guarantee full 8-bit monotonicity, and nonlinearities as tight as 0.1% over the entire operating temperature range are available. Device performance is essen- tially unchanged over the +4.5V to +18V power supply range, with 33mW power consumption attainable at +5V supplies. The compact size and low power consumption make the DAC-08 attractive for portable and military /aerospace applica- tions. All devices are processed to MIL-STD-883. DAC-08 applications include 8-bit, 1.0usec A/D converters, servo-motor and pen drivers, waveform generators, audio encoders and attenuators, analog meter drivers, programmable power supplies, CRT display drivers, high speed modems and other applications where low cost, high speed and complete input/output versatility are requited. EQUIVALENT CIRCUIT NETWORK CURRENT SWITCHES Vageltl g nia 16 ~ 2 3 2 s 2 a 1] 3 3 3 : y 3 a 3 3 AmDAC-08 : " comb = LIC-190 Leadiess Chip-Pak CONNECTION DIAGRAMS - Top Views P-16-1 L-20-1 D-16-1 THRESHOLO [= sae [_] COMPENSATION Gur q 2 157] Vrer'~) v- Lys 1477) Vrer our [T]4 wf mse By C]s 1217] 8 Ls6 8, C16 ui fT] & 8; (]7 10[7] 86 o4 Co 8s LIC-191 Note: Pin 1 is marked for orientation. 3-1 03918B-ANADAC-08 MAXIMUM RATINGS (Ta = 25C Uniess Otherwise Noted) Operating Temperature V+ supply to V Supply 36V a O . DAC-08A0, G, AL, L 55'C to +125 C Logic Inputs V to V+ plus 36V DAC-O8EQ, CQ, HO, EN, CN, HN OCto+70C Vic Vto V+ Storage Temperature 65C to +150C Analog Current Outputs See Fig. 12 Power Dissipation 500mw Reference Inputs (V14, Vis) Vto V+ Derate above 100C 10mw/C Reference Input Differential Voltage (Viq4 to V15) +18V Lead Temperature (Soldering, 60 sec) 300C Reference Input Current (144) 5.0mA ELECTRICAL CHARACTERISTICS (Vg = #15V, Inep = 2.0mA} AmDAC-08A AmDAC-08 AmDAC-08H AmDAC-08E AmDAC-08C Parameter Description Test Conditions Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Units Resolution 8 8 3 8 8 8 8 8 8 Bits Monotonicity a 8 8 8 8 8 8 8 8 Bits Nontinearity Ta = MIN. to MAX. +0.1 +0,19 +0.39 %FS To 21/2 LSB, all bits Dacon 85 135 85 135 ts Settling Time switched ON or OFF DAC-08E os = 1 Ta = 28C DAcoaC 85 50 85 150 tpl. Each Bit 35 60 35 60 35 60 a re = Ta = 28C ns PHL elay ane 35 60 35 60 35 60 TCles Full Scale Tempco +10 =50 210 250 210 +80 ppm c Full scale current Voc Output Voltage Compliance | change < 1/2 LSB -10 +18 -10 +18 -10 +18 Volts Rout > 20Meg2 typ. Vreg = 10.000V lesa Full Scale Current R14. FAy5 = 5.000k2 1.984 1.992 2.000 1.94 1.89 2.04 1.94 199 2.04 mA Ta = 25C fess Full Scale Symmetry lesa ~ lesz 205 14.0 1.0 28.0 220 16 BA Izg Zero Scale Current 0.1 1.0 02 20 0.2 4a uA =-5, / 1 a 2 21 2.0 2.1 tesR Output Current Range v 5.0V 8 20 2 8 mA V7=-12.0V to ~18V 0 2.0 4.2 0 2.0 42 2.0 42 Vit ; Lagic "0" 08 08 08 Logic Input Vic = OV Volts Levels . Vin Logic 1" 20 20 20 : VIN = 10V to i Logic 0 IN -2.0 10 2.0 -10 -2.0 | -10 ie Lagic Input ote Vic =OV +0.8V uA UH Currant Logic 1 Vin = 20N ro 0.002 | 10 0.002 | 10 0.002 | 10 Vis Logic Input Swing Vo = -15V -10 HE ~10 +18 10 +18 Voits VTHA Logic Threshold Range Vg = 215V -10 413.5 -10 413.5 -10 +135 Volts Hs Reference Bias Current 1.0 3.0 -1.0 -3.0 -1.0 3.0 BA divdt Reference Input Slew Rate 4.0 8.0 40 8.0 40 8.0 mAs PSSIEgs Vt+=45V to 18V 20.0003 +0.01 +0.0003 | =0.01 +0,0003 | +0.01 Power Supply itivity %/% PSS! s_ nee way te ~18V +0.002 } =0.01 +0.002 | 10.01 0.002 | +0.01 + : 23 38 ! Vg > :S.0V, Iper = 1.0mA 23 38 23 38 I- 4.a | 58 43 | 68 43 | -58 + Vg = +5.0V,-15V, 24 38 24 38 24 38 mA = Power Supply Current IRE = 2.0mA 64 78 6.4 -78 6.4 78 + Vg = t15V, IRER = 2.0mA 25 3.8 25 38 25 38 I- -65 | -78 65 | -78 65 | -78 t6.0V, tRep = 1.0mA 33 48 33 48 33 48 Pb Power Dissipation +5.0V, -15V, IREG = 2.0MA 108 136 108 136 108 136 mw t15V, IREF =2.0mA 135 174 435 174 136 174 3-2DAC-08 BASIC CONNECTIONS Rig AREF ra] 1 Bz By Be By Og. 8, Bg\ | Vrerlel oA Vreeiel 'g REF o AmDAC-08 15 _ Vaer'-) To Ris v7 COMP vr Yee = a J 16 13 i oar Lp re - * Me LIC-192 \ +VREF 255 FOR FIXED REFERENCE, TTL FS = x RrRer 256 OPERATION, TYPICAL VALUES ARE: lo + Ig = lpg FOR ALL VREF = +10.000V LOGIC STATES RREF = 5.000k Rig ~ RREF Co = 0.01uF Vic = OV (GROUND) Figure 1. Basic Positive Reference Operation. Low T.c, VREF o ait +H10V | tReptel = 20mA AmDAC-08 50kn <_w1.0V POT. > ' 15 APPROX 5.0kn LiC-193 Figure 2. Recommended Full Scale Adjustment Circuit. Pree 1g oo to = R AmDAC-OB 5 _ Vaer'-! Av z To LIC-194 VREF 255 les * > = REF 256 Note 1. RRef Sets lpg: R15 is for Bias Current Cancellation. Figure 3. Basic Negative Reference Operation. MsB ise Eo By 8 By By Bg Bg By By Iner = 2.000mA, i) oS 14 AmDAL-08 LIC-195 81 82 B3 B4 BS BE B7 BS | IgmA | To mA Eo Eo FULL SCALE 111 1 4 f 1 1.992 ooo | 9.960 000 FULLSCALE-LSB] ! 1 1 1 1 1 1 | 1.984 | .008 | -9.920| ~.os0 HALF SCALE+LSB | 1 G 0 0 0 O O 1 | 1.008 | 984 | -5.040 | ~4.920 HALF SCALE 1 0 0 0 0 G G D | 1.000 | 992 | ~5.000 | ~4.960 HALFSCALE-LSB] 0 7 1 1 4 1 91 992 | 1.000 | 4.960 | -5.000 ZEROSCALE+188| 0 0000001 008 | 1984 | .040 | -9.920 ZERO SCALE 0 0 0 09 0 0 0 0 | 00 | 1992 o00 | -9 960 Figure 4. Basic Unipolar Negative Operation. +10.000V ie] LIC-196 81 82 B3 84 65 B6 87 BB | EG Eo POS FULL SCALE ra 1 4 4 2 4 4 | ~9.920 | +10.000 POSFULLSCALE -LS8 | 1 1 1 1 1 1 1 0 | ~9aa0 | +9920 ZERO SCALE +LSB 1009 @ 0 a 1 | -0.080 | +0160 ZERO SCALE 10000000 o.000 | +0.080 ZERO SCALE -LSB o7 9 4 4 117 4 | 40080 0 000 NEGFULLSCALE+LSB| 0 0 0 0 0 6 0 1] +9920] -9.840 NEG FULL SCALE 0 0 0 0 0 0 0 | +000] -9.920 Figure 5. Basic Bipolar Output Operation. Mss te S.OWS? Vaee 6.000k2 By Bz By By 8 Bg B7 By ow lg +10V AmDAC-08 ve vo fo be -15v 5.Ok& LIC-197 Bl B2 83 B84 85 B6 B7 BB] EO POS FULL SCALE tora 4 1 4 4 1 | +8 960 POS FULL SCALE -LSB | 1 1 1 1 1 1 1 O | +9880 i+] ZERO SCALE + 0 0 0 a 0 0 Oo | +0040 (-} ZERO SCALE GO t+ 4 4 1 119 4 | -9 040 NEG FULL SCALE +LSB | 0 0 0 0 0 0 1 | -9.880 NEG FULL SCALE oa 008 9 0 0 0 | -9.960 Figure 6. Symmetrical Offset Binary Operation. 3-3BASIC CONNECTIONS (Cont.) DAC-08 R & Eo OTO tpg e Ry LIC-198 lee = 2B y FS = 35_ 'REF FOR COMPLEMENTARY OUTPUT (OPERATION AS NEGATIVE LOGIC DAC), CONNECT INVERTING INPUT OF OP-AMP TO 19 (PIN 2), CONNECT Ig (PIN 4) TO GROUND Figure 7. Positive Low Impedance Output Operation. Vout ig 1 4V a1sy b_0 Fo OTO -tes RL AmDAC-08 LIC-199 ice = 2 FS = Seg REF FOR COMPLEMENTARY (OPERATION AS A NEGATIVE LOGIC DAC}, CONNECT NON-INVERTING INPUT OF OP-AMP TO io {PIN 2); CONNECT Ig (PIN 4) TO GROUND. Figure 8. Negative Low Impedance Output Operation. TTL, OTL Von = #14 +15 CMOS, HTL HNIL Vow = *7.6V B1KR AmDAC-08 Vic VREF I) I ko tak Vee 62 ote OPTIONAL Rrep & RESISTOR = = > FOR OFFSET = = Rn Vornputs CMOS, HTL. NMOS r LiC-201 b 2 3 nan vad To TO PIN I 2 PINT S 20K2 v sane wit) TYPICAL VALUES: j oa j | Rin = 5k 5 -52u = Lic-200 +Viy = 10V SET VOLTAGE AT NODE A EQUAL TO DESIRED LOGIC THRESHOLD. Figure 9. Interfacing With Various Logic Families. Figure 10. Pulsed Reference Operation. Vrer lt ve LC toe MINIMUM IREF I Ke 2 CAPACITANCE O1uF hin | vr o= ae _ 14 Vin oo Rin 1% AmDAC-08 soav [ TxPROBE >] ov - ? rs -O0.4V a) Irer 2 Peak Negative Swing of tin. ~ L Vrerttl 14 AmDAC-08 19 o I tOu.T.) % 2 anita RR Ri6 100.7. Vaert) on" ! = 3 3 ef = RyglOPTIONALE = 15 AmDAC-08 0.01 uF Yin oan , +} A- co HIGH INPUT O.1yF OluF IMPEDANCE Lt fe) L - +bv -TBY 7 LIC-203 Rrer * Rig Lic-202 FOR TURN-ON, V; = 2.7V b) +Vper Must Be Above Peak Positive Swing of Vin. FOR TURN-OFF, Vy, =0.7V Figure 11. Accomodating Bipotar References. Figure 12. Settling Time Measurement. 3-4APPLICATIONS INFORMATION REFERENCE AMPLIFIER SET-UP The DAC-08 is a multiplying D/A converter in which the out- put current is the product of a digital number and the input reference current. The reference current may be fixed or may vary from nearly zero to +4.0mA. The full scale output current is a linear function of the reference current and is given by: I = 288 | here | =I FS 256 REF where |REF = !14. In positive reference applications (Fig. 1), an external positive teference voltage forces current through R44 into the VagFi+) terminal (pin 14) of the reference amplifier. Alternatively, a negative reference may be applied to Vaeri_) at pin 15 (Fig. 3); reference current flows from ground through Ryq into Vreert+) as in the positive reference case. This negative refer- ence connection has the advantage of a very high impedance presented at pin 15. The voltage at pin 14 is equal to and tracks the voltage at pin 15 due to the high gain of the internal reference amplifier. Ry5 (nominally equal to R44) is used to cancel bias current errors; Rys5 may be eliminated with only a minor increase in error. Bipolar references may be accommodated by offsetting Vaer or pin 15 as shown in Fig. 11, The negative common mode range of the reference amplifier is given by: Vcnj = V plus (lRee X 1.0k92) plus 2.5V. The positive common mode range is V+ less 1.5V. When a DC reference is used, a reference bypass capacitor is recommended. A 5.0V TTL logic supply is not recommended as a reference. If a regulated power supply is used as a refer- ence, Ryq should be split into two resistors with the junction bypassed to ground with a 0.1uF capacitor. For most applications, a +10.0V reference is recommended for optimum full scale temperature coefficient performance. This will minimize the contributions of reference amplifier Vos and TCVgs. For most applications the tight relationship between Iperf and leg will eliminate the need for trimming Ire. If required, full scale trimming may be accomplished by adjusting the value of R44, or by using a potentiometer for Riq4. An improved method of full scale trimming which elimi- nates potentiometer T.C. effects is shown in Fig. 2. Using lower values of reference current reduces negative power supply current and increases reference amplifier negative com- mon made range. The recommended range for operation with a DC reference current is +0.2mA to +4.0mA. The reference amplifier must be compensated by using a capacitor from pin 16 to V-. For fixed reference operation, a 0.01uF capacitor is recommended. For variable reference applications, see section entitled Reference Amplifier Com- pensation for Multiplying Applications. MULTIPLYING OPERATION The DAC-08 provides excellent multiplying performance with an extremely linear relationship between Irs and Imer over a range of 4.0mA to 4.0uA. Monotonic operation is maintained over a typical range of IReg from 100uA to 4.0mA; consult factory for devices selected for monotonic operation over wider {Reg ranges. REFERENCE AMPLIFIER COMPENSATION FOR MULTIPLYING APPLICATIONS AC reference applications will require the reference amplifier to be compensated using a capacitor from pin 16 to V. The value of this capacitor depends on the impedance presented to pin 14: for R74 values of 1.0, 2.5 and 5.06kQ, minimum vatues of Cg are 15, 37, and 75pF. Larger values of R14 require pro- portionately increased values of Cg for proper phase margin. 3-5 DAC-08 For fastest response to a pulse, low values of R74 enabling small Co values should be used. If pin 14 is driven by a high impedance such as a transistor current source, none of the above values will suffice and the amplifier must be heavily compensated which will decrease overall bandwidth and stew rate. For Ryq = 1.0kQ and Cg = 15pF, the reference amplifier slews at 4.0mA/ys enabling a transition from IRe = 0 to tger = 2.0mA in 500ns. Operation with pulse inputs to the reference amplifier may be accommodated by an alternate compensation scheme shown in Fig. 10. This technique provides lowest full scale transition times. An internal clamp allows quick recovery of the reference amplifier from a cutoff (IRE = 0) condition. Full scale transi- tion (0 to 2.0mA) occurs in 120ns when the equivalent im- pedance at pin 14 is 20022 and Ce. = 0. This yields a reference slew rate of 16mA/ys which is relatively independent of Rin and Vin values. LOGIC INPUTS The DAC-08 design incorporates a unique logic input circuit which enables direct interface to all popular logic families and provides maximum noise immunity. This feature is made possible by the large input swing capability, 2.02A logic input current and completely adjustable logic threshold voltage. For V = 15V, the logic inputs may swing between 10V and +18V. This enables direct interface with +15V CMOS logic, even when the DAC-08 is powered from a +5V supply. Mini- mum input logic swing and minimum logic threshold voltage are given by: V plus (Iqer X 1.0k22) plus 2.5V. The logic threshold may be adjusted over a wide range by placing an appropriate voltage at the logic threshold control pin (pin 1, Vic). For TTL and DTL interface, simply ground pin 1. When interfacing ECL, an IREF = 1.0mA is recommended. For interfacing other logic families, see Fig. 9. For general set-up of the logic control circuit, it should be noted that pin 1 will source 100zA typical; external circuitry should be designed to accommodate this current. Fastest settling times are obtained when pin 1 sees a low im- pedance. If pin 1 is connected to a 1.0kQ. divider, for example, it should be bypassed to ground by a 0.01yuF capacitor. ANALOG OUTPUT CURRENTS Both true and complemented output sink currents are pro- vided, when Ig + lo = leg. Current appears at the true output when a 1 is apptied to each logic input. As the binary count increases, the sink current at pin 4 increases propor- tionally, in the fashion of a positive logic D/A converter. When a 0 is applied to any input bit, that current is turned off at pin 4 and turned on at pin 2. A decreasing logic count increases Ig as in a negative or inverted logic D/A converter. Both outputs may be used simultaneously. If one of the out- puts is not required it must still be connected to ground or to a point capable of sourcing Is; do not leave an unused output pin open. Both outputs have an extremely wide voltage compliance enabling fast direct current-to-voltage conversion through a resistor tied to ground or other voltage source. Positive com- pliance is 36V above V-- and is independent of the positive supply. Negative compliance is given by V plus (lgeg * 1.0k2) plus 2.5V. The dual outputs enable double the usual peak-to-peak load swing when driving loads in quasi-differential fashion. This feature is especially useful in cable driving, CRT deflection and in other balanced applications such as driving center-tapped coils and transformers.DAC-08 POWER SUPPLIES The DAC-08 operates over a wide range of power supply voltages from a total supply of 9V to 36V. When operating at supplies of +5V or tess, IREF < IMA isrecommended. Low reference current operation decreases power consumption and increases negative compliance, reference amplifier negative common mode range, Negative logic input range, and negative logic threshold range. For example, operation at 4.5V with IRef = 2mA is not recom- mended because negative output compliance would be reduced to near zero. Operation from lower supplies is possible, however at least 8V total must be applied to insure turn-on of the internal bias network. : Symmetrical supplies are not required, as the DAC-08 is quite insensitive ta variations in supply voltage. Battery operation is feasible as no ground connection is required: however, an artificial ground may be useful to insure logic swings, etc. remain between acceptable limits. Power consumption may be calculated as follows: Pg = (I+) (V+) + (1+) (V) + (2 IReg) (V). A useful feature of the DAC-08 design is that supply current is constant and inde- Pendent of input logic states; this is useful in cryptographic applications and further serves to reduce the size of the power supply bypass capacitors. TEMPERATURE PERFORMANCE The nonlinearity and monotonicity specifications of the DAC-08 are guaranteed to apply over the entire rated operating tempera- ture range. Full scale output current drift is tight, typically +10ppm/C, with zero scale output current and drift essentially negligible compared to 1/2 LSB. Full scale output drift performance will be best with +10.0V references as Vog and TCVos of the reference amplifier will be very small compared to 10.0V. The temperature coefficient of the reference resistor Ry4 should match and track that of the out- put resistor for minimum overall full scale drift. Settling times of the DAC-08 decrease approximately 10% at 55C; at +125C an increase of about 15% is typical. SETTLING TIME The DAC-08 is capable of extremely fast settling times, typically 85nsec at Ipee = 2.0mA. Judicious circuit design and careful board layout must be employed to obtain full performance potential during testing and application. The logic switch design enables propagation delays of only 35nsec for each of the 8 bits. Settling time to within 1/2 LSB of the LSB is therefore 35nsec, with each progressively larger bit taking successively longer. The MSB settles in 85nsec, thus determining the overall settling time of 85nsec. Settling to 6-bit accuracy requires about 65 to 7Onsec. The output capacitance of the DAC-08 including the package is approximately 1SpF, therefore the output RC time constant dominates settling time if RL > 5002. Settling time and propagation delay are relatively insensitive to logic input amplitude and rise and fall times, due to the high gain of the logic switches. Settling time also remains essentially constant for IREF values down to 1.0mA, with gradual increases for lower pep values. The principal advantage of higher Imer values lies in the ability to attain a given output level with lower load resistors, thus reducing the output RC time constant. Measurement of settling time requires the ability to accurately resolve 4uA, therefore a 1k22 load is needed to provide adequate drive for most oscilloscopes. The settling time fixture of Fig. 12 uses a cascode design to permit driving a 1k foad with less than 5pF of parasitic capacitance at the measurement nade. At IneF values of less than 1mA, excessive RC damping of the output is difficult to prevent while maintaining adequate sensitivity. How- ever, the major carry from 01111111 to 10000000 provides an accurate indicator of settling time. This code change does not require the normal 6.2 time constants to settle to within +0.2% of the final value, and thus settling times may be observed at tower values of [Rer. DAC-08 switching transients of glitches are very low and may be further reduced by small capacitive loads at the output at a- minor sacrifice in settling time. Fastest operation can be obtained by using short leads, minimizing output capacitance and load resistor values, and by adequate bypassing at the supply, reference and Vic terminals. Supplies do not require large electrolytic bypass capacitors as the supply current drain is independent of input logic states; 0.1.F capacitors at the supply pins provide full transient protection. METALLIZATION AND PAD LAYOUT cOMP Vrer(-) Vaer(+) vt 8, Gs Bs OIE SIZE: 0.068 X 0.088 ORDERING INFORMATION* Order Package Temperature Number Type Range Nonlinearity DAC-08AQ Ceramic DIP -55 to + 125C +0.1% DAC-08Q Ceramic DIP - 55 to +125C +0.19% DAC-OBAL Leadiess 5 to + 126C +0.1% DAC-08L Leadiess 55 to + 125C +0.19% DAC-08HQ Ceramic DIP Oto +70C +0.1% DAC-08EQ Ceramic DIP Oto +70C +0.19% DAC-08CQ Ceramic DIP Oto +70C +0.39% DAC-O8HL Leadiess Oto +70C +0.1% DAC-O8EL Leadless Oto +70C 20.19% DAC-08CL Leadiess Oto +70C +0.39% DAC-08HN Plastic 0 to ~70C +0.1% DAC-O8EN Plastic Oto +70C +0.19% BAC-O8CN Plastic Oto +70C +0.39% DAC-08AX Dice 55 to +125C +0.1% DAC-08X Dice ~55 to + 125C +0.19% DAC-08HX Dice Oto +70C 0.1% DAC-08EX Dice Oto +70C 20.19% DAC-08CX Dice Oto +70C +0.39% *Also available with burn-in processing. To order add suffix B to part number. 3-6