1
Semiconductor
Features
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Exceeds 2kV ESD Protection MIL-STD-883, Method 3015
• Meets JEDEC Standard No. 20
• SCR - Latch-Up-Resistant CMOS Process and Circuit
Design
• Speed of Bipolar FAST/A/S with Significantly Reduced
Power Consumption
• Functionally and Pin-Compatible with Industry 54
Bipolar Types in the FAST, AS and S Series
• Balanced Propagation Delays
• Military Operating Temperature Range
- Ceramic (CERDIP) 54 Series: . . . . . . . . -55 to 125oC
•±24mA Output Drive Current, Drives 75Ω Lines with-
out Need for Terminations
• Fan Out (Over Temperature)
- ACL Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2400
- FAST Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
- AS Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
• Balanced Noise Immunity at 30% of Supply for AC
Type
• Supply Voltage Range
- AC Types. . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
- ACT Types. . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
Pinout
Description
The CD54AC02F3A and CD54ACT02F3A are quad 2-input
NOR gates that utilize the Harris Advanced CMOS Logic
technology.
Functional Diagram
1Y
1A
1B
2Y
2A
2B
GND
VCC
4Y
4B
4A
3Y
3B
3A
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Ordering Information
PART NUMBER TEMP.
RANGE (oC) PACKAGE PKG.
NO.
CD54AC02F3A -55 to 125 14 Ld CERDIP F14.3
CD54ACT02F3A -55 to 125 14 Ld CERDIP F14.3
NOTE:
1. Wafer and die for this part number is available which meets all elec-
trical specifications. Please contact your local sales office or Harris
customer service for ordering information.
TRUTH TABLE
INPUTS OUTPUTS
ABY
LLH
HLL
LHL
HHL
1A
1B
2A
2B
3A
3B
4A
4B
2
3
5
6
8
9
11
12
1
4
10
13
1Y
2Y
3Y
4Y
GND = 7
VCC = 14
July 1998
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1998
CD54AC02F3A,
CD54ACT02F3A
Quad 2-Input NOR Gate
File Number 3877.1
2
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC VCC or Ground Current, ICC or IGND (Note 2) . . . . . . . . .±100mA
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC (Note 3)
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Slew Rate, dt/dv
AC Types
1.5V to 3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
4.5V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
Thermal Resistance (Typical, Note 4) θJA (oC/W) θJC (oC/W)
CERDIP Package . . . . . . . . . . . . . . . . 85 26
Maximum Junction Temperature (Hermetic Pac kage or Die) . . . 175oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2. For up to 4 outputs per device, add ±25mA for each additional output.
3. Unless otherwise specified, all voltages are referenced to ground.
4. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN MAX MIN MAX
AC TYPES
High Level Input Voltage VIH - - 1.5 1.2 - 1.2 - V
3 2.1 - 2.1 - V
4.5 3.15
(Note 5) - 3.15
(Note 5) -V
5.5 3.85 - 3.85 - V
Low Level Input Voltage VIL - - 1.5 - 0.3 - 0.3 V
3 - 0.9 - 0.9 V
4.5 - 1.35
(Note 5) - 1.35
(Note 5) V
5.5 - 1.65 - 1.65 V
High Level Output Voltage VOH VIH or VIL -0.05 1.5 1.4 - 1.4 - V
-0.05 3 2.9 - 2.9 - V
-0.05 4.5 4.4 - 4.4 - V
-4 3 2.58 - 2.4 - V
-24 4.5 3.94
(Note 5) - 3.7
(Note 5) -V
-50
(Note 6, 7) 5.5 - - 3.85 - V
CD54AC02F3A, CD54ACT02F3A
3
Low Level Output Voltage VOL VIH or VIL 0.05 1.5 - 0.1 - 0.1 V
0.05 3 - 0.1 - 0.1 V
0.05 4.5 - 0.1 - 0.1 V
12 3 - 0.36 - 0.5 V
24 4.5 - 0.36
(Note 5) - 0.5
(Note 5) V
50
(Note 6, 7) 5.5 - - - 1.65 V
Input Leakage Current IIVCC or
GND - 5.5 - ±0.1
(Note 5) -±1
(Note 5) µA
Quiescent Device Current ICC 0 5.5 - 4
(Note 5) -80
(Note 5) µA
ACT TYPES
High Level Input Voltage VIH - - 4.5 to 5.5 2
(Note 5) -2
(Note 5) -V
Low Level Input Voltage VIL - - 4.5 to 5.5 - 0.8
(Note 5) - 0.8
(Note 5) V
High Level Output Voltage VOH VIH or VIL -0.05 4.5 4.4 - 4.4 - V
-24 4.5 3.94
(Note 5) - 3.7
(Note 5) -V
-50
(Note 6, 7) 5.5 - - 3.85 - V
Low Level Output Voltage VOL VIH or VIL 0.05 4.5 - 0.1 - 0.1 V
24 4.5 - 0.36
(Note 5) - 0.5
(Note 5) V
50
(Note 6, 7) 5.5 - - - 1.65 V
Input Leakage Current IIVCC or
GND - 5.5 - ±0.1
(Note 5) -±1
(Note 5) µA
Quiescent Device Current ICC VCC or
GND 0 5.5 - 4
(Note 5) -80
(Note 5) µA
AdditionalSupplyCurrent per
Input Pin TTL Inputs High
1 Unit Load
∆ICC VCC
-2.1 - 4.5 to 5.5 - 2.4 - 3 mA
NOTES:
5. Tested at 100%.
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
7. Test verifies a minimum transmission-line-drive capability of 75Ω for 54AC/ACT Series.
ACT Input Load Table
INPUT UNIT LOAD
All 0.32
NOTE: Unit load is ∆ICC limit specified in DC Electrical Specifications
Table, e .g., 2.4mA max at 25oC.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN MAX MIN MAX
CD54AC02F3A, CD54ACT02F3A
4
Switching Specifications Input tr, tf = 3ns, CL= 50pF (Worst Case)
PARAMETER SYMBOL VCC (V)
-55oC TO 125oC
UNITSMIN TYP MAX
AC TYPES
Propagation Delay, Input to Output tPLH, tPHL 1.5 - - 144 ns
3.3 (Note 9) 3 - 20.1 ns
5 (Note 10) 2 - 11.5 (Note 8) ns
Input Capacitance CI---10pF
Power Dissipation Capacitance CPD (Note 11) - - 55 - pF
ACT TYPES
Propagation Delay, Input to Output tPLH
tPHL 5 (Note 10) 2.1 - 12.2 (Note 8) ns
Input Capacitance CI---10pF
Power Dissipation Capacitance CPD (Note 11) - - 55 - pF
NOTES:
8. Limits tested at 100%.
9. 3.3V Min at 3.6V, Max at 3V.
10. 5V Min at 5.5V, Max at 4.5V
11. CPD is used to determine the dynamic power consumption per gate.
AC: PD = VCC2 fi(CPD + CL)
ACT: PD = VCC2 fi(CPD + CL) + VCC ∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
Burn-In Test Circuit Connections (Use DC II for F3A Burn-In and AC for Life Test)
DC
DC BURN-IN I DC BURN-IN II
OPEN GROUND VCC (6V) OPEN GROUND VCC (6V)
CD54AC/ACT02 1, 4, 10, 13 2, 3, 5-9, 11,12 14 1, 4, 10, 13 7 2,3, 5,6,8, 9,11,
12, 14
AC OPEN GROUND 1/2 VCC (3V) VCC (6V)
OSCILLATOR
50kHz 25kHz
CD54AC/ACT02 - 7 1, 4, 10, 13 14 2,3,5, 6,8,9, 11,
12 -
NOTE: Each pin except VCC and Gnd will have a resistor of 2kΩ-47kΩ.
FIGURE 1. PROPAGATION DELAY TIMES
tr = 3ns tf = 3ns
90%
VS
10% GND
INPUT
tPHL tPLH
VS
LEVEL
VI
VO
DUT
OUTPUT
RL (NOTE)
OUTPUT
LOAD
500Ω
CL
50pF
NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.
FIGURE 2. PROPAGATION DELAY TIMES
CD54AC CD54ACT
Input Level VCC 3V
Input Switching Voltage, VS0.5 VCC 1.5V
Output Switching Voltage, VS0.5 VCC 0.5 VCC
CD54AC02F3A, CD54ACT02F3A
