STK14C88-NF35U - Simtek Corporation

STK14C88-NF35U

This product conforms to specifications per the

terms of Simtek standard warranty. The product

has completed Simtek internal qualification testing

and has reached production status. Feb, 2008

Document Control #ML0066 Rev 2.0

FEATURES

• 35 ns Read Access & R/W Cycle Time

• Unlimited Read/Write Endurance

• Automatic Non-volatile STORE on Power Loss

• Non-Volatile STORE Under Hardware or

Software Control

• Automatic RECALL to SRAM on Power Up

• Unlimited RECALL Cycles

• 100k STORE Cycles

• 10-Year Non-volatile Data Retention

• Single 5V +10% Power Supply

• -55°C to 125°C Operating Range

• 32-Pin 300 mil SOIC (RoHS-Compliant)

DESCRIPTION

The Simtek STK14C88-NF35U is a 256Kb fast static

RAM with a non-vol atile Quantum Trap storage ele-

ment included with each memory cell.

The SRAM provides the fast access & cycle times,

ease of use and unlimited read & write endurance of

a normal SRAM.

Data transfers automatically to the non-volatile stor-

age cells when power loss is detected (the STORE

operation). On power up, data is automatically

restored to the SRAM (the RECALL operation). Both

STORE and RECALL operations are also available

under software control.

The Simtek nvSRAM is the first monolithic non-vola-

tile memory to offer unlimited writes and reads. It is

the highest performance, most reliable non-volatile

memory available.

BLOCK DIAGRAM

COLUMN I/O

COLUMN DEC

STATIC RAM

ARRAY

512 x 512

ROW DECODER

INPUT BUFFERS

Quantum Trap

512 x 512

STORE/

RECALL

CONTROL

STORE

RECALL

POWER

CONTROL

SOFTWARE

DETECT

HSB

CCX

CAP

- A

32Kx8 AutoStore nvSRAM with extended temperature

Feb, 2008

Document Control #ML0066 Rev 2.0

STK14C88-NF35U

PIN CONFIGURATIONS

PIN DESCRIPTIONS

Pin Name I/O Description

A14-A0Input Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array

DQ7-DQ0I/O Data: Bi-directional 8-bit data bus for accessing the nvSRAM

EInput Chi p Enable: The active low E input selects the device

WInput W r it e Enab l e: The acti ve lo w W enables data on the DQ pins to be written to the address

location latched by the falling edge of E

GInput Output Enable: The active low G input enables the data output buffers during read cycles.

De-asserting G high caused the DQ pins to tri-state.

VCC Power Supply Power: 5.0V , +10%

HSB I/O Hardware Store Busy: When low this output indicates a Store is in progress. When pulle d

low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor

keeps this pin high if not connected. (Connection Optional).

VCAP Power Supply AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from

SRAM to nonvolatile storage elements.

VSS Power Supply Ground

(TOP)

A14

A12

DQ0

DQ1

DQ2

VCAP

A13

A11

A10

DQ7

DQ6

VSS

VCC

HSB

DQ5

DQ3

DQ4

32-Pin 300 mil SOIC

STK14C88-NF35U

Feb, 2008

Document Control #ML0066 Rev 2.0

ABSOLUTE MAXIMUM RATINGSa

Voltage on Input Relative to Ground . . . . . . . . . . . . . –0.5V to 7.0V

Voltage on Input Relative to VSS . . . . . . . . . .–0.6V to (VCC + 0.5V)

Voltage on DQ0-7 or H SB . . . . . . . . . . . . . . . .–0.5V to (VCC + 0.5V)

Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .–55°C to 125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .–65°C to 150°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W

DC Output Current (1 outpu t at a time, 1s duration) . . . . . . . 15mA

Note a: Stresses greater than those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is a

stress rating only, and functional operation of the device at con-

ditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rat-

ing conditions for extended periods may affect reliability.

DC CHARACTERISTICS (VCC = 5.0V ± 10%)e

Note b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.

Note c: ICC2 and ICC4 are the average currents required for the duration of the respective STORE cycles (tSTORE) .

Note d: E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.

Note e: VCC reference levels throughout this datasheet refer to system VCC if that is where the power supply connection is made, or VCAP if the IC VCC

is connected to ground.

SYMBOL PARAMETER STK14C88-NF35U UNITS NOTES

MIN MAX

ICC1bAverage VCC Current 90 mA tAVAV = 35ns

ICC2cAverage VCC Current during STORE 3 mA All Inputs Don’t Care, VCC = max

ICC3bAverage VCC Current at tAVAV = 200ns

5V, 25°C, Typical 15 mA W ≥ (VCC – 0.2V)

All Others Cycling, CMOS Levels

ICC4cAverage VCAP Current during AutoStore Cycle 2 mA All Inputs Don’t Care

ISB1dAverage VCC Current

(Standby, Cycling TTL Input Levels) 30 mA tAVAV = 35ns, E ≥ VIH

ISB2dVCC Standby Current

(Standby, Stable CMOS Input Levels) 3mA

E ≥ (VCC

– 0.2V)

All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V)

IILK Input Leakage Current ±1μAVCC = max

VIN = VSS to VCC

IOLK Off-State Output Leakage Current ±5μAVCC = max

VIN = VSS to VCC, E or G ≥ VIH

VIH Input Logic “1” Voltage 2.2 VCC + .5 V All Inputs

VIL Input Logic “0” Voltage VSS – .5 0.8 V All Inputs

VOH Output Logic “1” Voltage 2.4 V IOUT = –4mA (except HSB)

VOL Output Logic “0” Voltage 0.4 V IOUT = 8mA (except HSB)

VBL Logic “0” Voltage on HSB Output 0.4 V IOUT = 3mA

TAOperating Temperature 55 125 °C

AC TEST CONDITIONS

CAPACITANCEf(TA = 25°C, f = 1.0MHz)

Note f: These parameters are guaranteed but not tested.

Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 3V

Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns

Input and Output Timing Reference Levels . . . . . . . . . . . . . . .1.5V

Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1

SYMBOL PARAMETER MAX UNITS CONDITIONS

CIN Input Capacitance 5 pF ΔV = 0 to 3V

COUT Output Ca pacitance 7 pF ΔV = 0 to 3V Figure 1: AC Output Loading

480 Ohms

30 pF

255 Ohms

5.0V

INCLUDING

SCOPE AND

OUTPUT

FIXTURE

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STK14C88-NF35U
SRAM READ CYCLES #1 & #2 (VCC = 5.0V ± 10%)e
Note g: W and HSB must be high during SRAM READ cycles.
Note h: I/O state assumes E and G < VIL and W > VIH; device is continuously selected.
Note i: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledg, h
SRAM READ CYCLE #2: E and G Controlledg
NO. SYMBOLS PARAMETER STK14C88-NF35U UNITS
#1, #2 Alt. MIN MAX
1t
ELQV tACS Chip Enable Access Time 35 ns
2t
AVAVg, tELEHgtRC Read Cycle Time 35 ns
3t
AVQVhtAA Address Access Time 35 ns
4t
GLQV tOE Output Enable to Data V alid 15 ns
5t
AXQXhtOH Output Hold after Address Change 5 ns
6t
ELQX tLZ Address Change or Chip Enable to Output Active 5 ns
7t
EHQZitHZ Address Change or Chip Disable to Output Inac tive 13 ns
8t
GLQX tOLZ Output Ena ble to Outp ut Active 0 ns
9t
GHQZitOHZ Outp ut Disa ble to Outp ut Ina ctive 13 ns
10 tELICCHftPA Chip Enable to Power Active 0 ns
11 tEHICCLftPS Chip Disable to Power Standby 35 ns
DATA VALID
5
tAXQX
3
tAVQV
DQ (DATA OUT)
ADDRESS
2
tAVAV
6
tELQX
STANDBY
DATA VALI D
4
tGLQV
DQ (DA TA OUT)
E
ADDRESS
G
ICC
ACTIVE
10
tELICCH
11
tEHICCL
7
tEHQZ
8
tGLQX
1
tELQV
9
tGH Q Z
2
tELEH 29
tEHAX
3
tAV QV
27

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   STK14C88-NF35U
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Document Control #ML0066 Rev 2.0
SRAM WRITE CYCLES #1 & #2 (VCC = 5.0V ± 10%)e
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E or W must be ≥ VIH during address transitions.
Note l: HSB must be high during SRAM WRITE cycles.
SRAM WRITE CYCLE #1: W Controlledk, l
SRAM WRITE CYCLE #2: E Controlledk, l
NO. SYMBOLS PARAMETER STK14C88-NF35U UNITS
#1 #2 Alt. MIN MAX
12 tAVAV tAVAV tWC Write Cycle Time 35 ns
13 tWLWH tWLEH tWP Write Pulse Width 25 ns
14 tELWH tELEH tCW Chip Enable to End of Write 25 ns
15 tDVWH tDVEH tDW Data Set-up to End of Write 12 ns
16 tWHDX tEHDX tDH Data Hold af ter  End of Write 0 ns
17 tAVWH tAVEH tAW Address Set-up to End of Write 25 ns
18 tAVWL tAVEL tAS Address Set-up to Start of Write 0 ns
19 tWHAX tEHAX tWR Address Hold after End of Write 0 ns
20 tWLQZi, j tWZ Write Enable to Output Disable 13 ns
21 tWHQX tOW Output Active after End of Write 5 ns
DATA OUT
E
ADDRESS
W
DATA IN
PREVIOUS DATA
12
tAVAV
16
tWHDX
19
tWHAX
13
tWLWH
18
tAVWL
17
tAVWH
DATA VALID
20
tWLQZ
15
tDVWH
HIGH IMPEDANCE
21
tWHQX
14
tELWH
12
tAVAV
16
tEHDX
13
tWLEH
19
tEHAX
18
tAVEL
17
tAVEH
DATA VALID
15
tDVEH
HIGH IMPEDANCE
14
tELEH
DATA OUT
E
ADDRESS
W
DATA IN

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STK14C88-NF35U
HARDWARE MODE SELECTION
Note m: HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile  cycle. After the STORE (if any) completes, 
the part will go into standby mode, inhibiting all operations until HSB rises.
HARDWARE STORE CYCLE  (VCC = 5.0V ± 10%)e
Note n: E and G low and W high for output behavior.
Note o: tRECOVER is only applicable after tSTORE is complete.
HARDWARE STORE CYCLE
E W HSB A13 - A0 (hex) MODE I/O POWER NOTES
H X H X Not Selected Output High Z Standby
L H H X Read SR AM Output Data Acti ve t
L L H X Write SRAM Input Data Active
X X L X Nonvolatile STORE Output High Z lCC2m
NO. SYMBOLS PARAMETER STK14C88-NF35U UNITS NOTES
Standard Alternate MIN MAX
22 tSTORE tHLHZ STORE Cycle Duration 10 ms
23 tDELAY tHLQZ Time Allowed to Complete SRAM Cycl e 1 μs
24 tRECOVER tHHQX Hardware STORE High to Inhibit Off 700 ns n, o
25 tHLHX Hardware STORE Pulse Width 15 ns
26 tHLBL Hardware STORE Low to STORE Busy 300 ns
DATA VALID
HSB (IN)
DATA VALID
25
tHLHX
23
tDELAY
22
tSTORE
24
tRECOVER
HIGH IMP EDANCE
26
tHLBL
HIGH IMPEDANCE
DQ (DATA OUT)
HSB (OUT)

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   STK14C88-NF35U
Feb, 2008
Document Control #ML0066 Rev 2.0
AutoStore™/POWER-UP RECALL (VCC = 5.0V ± 10%)e
Note p: tRESTORE starts from the time VCC rises above VSWITCH.
Note q: HSB is asserted low for 1μs when VCAP drops through VSWITCH. If an SRAM WRITE has not taken place since the last nonvolatile cycle, HSB
will be released and no STORE will take place.
AutoStore™/POWER-UP RECALL
NO. SYMBOLS PARAMETER STK14C88-NF35U UNITS NOTES
Standard Alternate MIN MAX
27 tRESTORE Power-up RECALL Duration 550 μsp
28 tSTORE tHLHZ STORE Cycle Duration 10 ms n, q
29 tVSBL Low Voltage Trigger (VSWITCH) to HSB  Low 300 ns l
30 tDELAY tBLQZ Time Allowed to Complete SRAM Cycle 1 μsn
31 VSWITCH Low Voltage Trigger Level 4.0 4.5 V
32 VRESET Low Voltage Reset Level 3.6 V
30
tDELAY
29
tVSBL
POWER-UP 
RECALL BROWN OUT
NO STORE
(NO SRAM WRITES)
NO RECALL
(VCC DID NOT GO 
BELOW VRESET)
BROWN OUT
AutoStore
NO RECALL
(VCC DID NOT GO 
BELOW VRESET)
BROWN OUT
AutoStore
RECALL WHEN
VCC RETURNS
ABOVE VSWITCH
AutoStore
HSB
W
28
tSTORE
27
tRESTORE
POWER-UP RECALL
31
VSWITCH
32
VRESET
VCC
DQ (DATA OUT)

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STK14C88-NF35U
SOFTWARE STORE/RECALL MODE SELECTION
SOFTWARE-CONTROLLED STORE/RECALL CYCLEv(VCC = 5.0V ± 10%)e
Note r: The six consecutive addresses must be in the order listed. W must be high during all six consecutive E or G controlled cycles to enable a non-
volatile cycle.
Note s: While there are 15 addresses on the STK14C88-NF35U, only the lower 14 are used to control software modes.
Note t: I/O state assumes G < VIL. Activation of nonvolatile cycles does not depend on state of G.
Note u: The software sequence is clocked on the falling edge of E controlled READs without involving G (double clocking will abort the sequence). See 
application note: MA0002 http://www.simtek.com/attachments/appNote02.pdf.
Note v: The six consecutive addresses must be  read in the order listed in the  Software STORE/RECALL Mode Selection Table: (0E38, 31C7, 03E0, 
3C1F, 303F, 0FC0) for a STORE cycle or (0E38, 31C7, 03E0,  3C1F, 303F, 0C63) for a RECALL cycle. W must be  high durin g all six  consecu-
tive cycles.
SOFTWARE STORE/RECALL CYCLE: E CONTROLLEDv
E W A13 - A0 (hex) MODE I/O POWER NOTES
LH
0E38
31C7
03E0
3C1F
303F
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Active n, r, s, t
0FC0 Nonvolatile STORE Output High Z lCC2
LH
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active n, r, s, t
NO. SYMBOLS PARAMETER STK14C88-NF35U UNITS NOTES
Standard Alternate MIN MAX
33 tAVAV tRC STORE/RECALL Initiation Cycle Time 35 ns n
34 tAVEL tAS Address Set-up Time 0 ns u,v
35 tELEH tCW Clock Pulse Width 25 ns u,v
36 tELAX Address Hold Time 20 ns u, v
37 tRECALL RECALL Duration 20 μs
DATA VALID HIGH IMPEDANCE
ADDRESS #6ADDRESS #1
DATA VALID
33
tAVAV
DATA VALID
DQ (DATA 
E
ADDRESS
28 37
tSTORE / tRECALL
33
tAVAV
34
tAVEL 35
tELEH
36
tELAX

STK14C88-NF35U

Feb, 2008

Document Control #ML0066 Rev 2.0

The STK14C88-NF35U has two separate modes of

operation: SRAM mode and nonvolatile mode. In

SRAM mode, the memory operates as a standard

fast static RAM. In nonvolatile mode, data is trans-

ferred from SRAM to nonvolatile elements (the

STORE operation) or from nonvolatile elements to

SRAM (the RECALL operation). In this mode SRAM

functions are disabled.

NOISE CONSIDERATIONS

The STK14C88-NF35U is a high-speed memory

and so must have a high-frequency bypass capaci-

tor of approximately 0.1μF connected between V CAP

and VSS, using leads and traces that are as short as

possible. As with all high-speed CMOS ICs, normal

careful routing of power , ground and signals will help

prevent noise problems.

SRAM READ

The STK14C88-NF35U performs a READ cycle

whenever E and G are low and W and HSB are

high. The address specified on pins A0-14 determines

which of the 32,768 data bytes will be accessed.

When the READ is initiated by an address transiti on,

the outputs will be valid after a delay of tAVQV (READ

cycle #1). If the READ is initia ted by E or G, the out -

puts will be valid at tELQV or at tGLQV, whichever is later

(READ cycle #2). The data outputs will repeatedly

respond to address changes within the tAVQV access

time without the need for transitions on any control

input pins, and will remain valid until another address

change or until E or G is brought high, or W or HSB is

brought low.

SRAM WRITE

A WRITE cycle is performed whenever E and W are

low and HSB is high. The address inputs must be

stable prior to entering the WRITE cycle and must

remain stable until either E or W goes high at the

end of the cycle. The data on the common I/O pins

DQ0-7 will be written into the memory if it is valid tDVWH

before the end of a W controlled WRITE or tDVEH

before the end of an E controlled WRITE.

It is recommended that G be kept high during the

entire WRITE cycle to avoid data bus contention on

common I/O lines. If G is left low, internal circuitry

will turn off the output buffers tWLQZ after W goes low.

POWER-UP RECALL

During power up, or after any low-power condition

(VCAP < VRESET), an internal RECALL request will be

latched. When VCAP once again exceeds the sense

voltage of VSWITCH, a RECALL cycle will automa tically

be initiated and will take tRESTORE to complete.

If the STK14C88-NF35U is in a WRITE state at the

end of power-up RECALL, the SRAM data will be cor-

rupted. To help avoid this situation, a 10K Ohm

resistor should be connected either between W and

system VCC or between E and system VCC.

SOFTWARE NONVOLATILE STORE

The STK14C88-NF35U software STORE cycle is ini-

tiated by executing sequential E controlled READ

cycles from six specific address locations. During

the STORE cycle an erase of the previous nonvola-

tile data is first performed, followed by a program of

the nonvolatile elements. The program operation

copies the SRAM data into nonvolatile memory.

Once a STORE cycle is initiated, further input and

output are disabled until the cycle is completed.

Because a sequence of READs from specific

addresses is used for STORE initiation, it is impor-

tant that no other READ or WRITE accesses inter-

vene in the sequence, or the sequence will be

aborted and no STORE or RECALL will take place.

To initiate the software STORE cycle, the following

READ sequence must be performed:

1. Read address 0E38 (hex) Valid READ

2. Read address 31C7 (hex) Valid READ

3. Read address 03E0 (hex) Valid READ

4. Read address 3C1F (hex) Valid READ

5. Read address 303F (hex) Valid READ

6. Read address 0FC0 (hex) Initiate STORE cycle

The software sequence must be clocked with E con-

trolled READs.

Once the sixth address in the sequence has been

entered, the STORE cycle will commence and the

chip will be disabled. It is important that READ cycles

and not WRITE cycles be used in the sequence,

although it is not necessary that G be low for the

sequence to be valid. After the tSTORE cycle time has

been fulfilled, the SRAM will again be activated for

READ and WRITE operation.

nvSRAM OPERATION

Feb, 2008

Document Control #ML0066 Rev 2.0

STK14C88-NF35U

SOFTWARE NONVOLATILE RECALL

A software RECALL cycle is initiated with a sequence

of READ operations in a manner similar to the soft-

ware STORE initiation. To initiate the RECALL cycle,

the following sequence of E controlled READ opera-

tions must be performe d:

1. Read address 0E38 (hex) Valid READ

2. Read address 31C7 (hex) Valid READ

3. Read address 03E0 (hex) Valid READ

4. Read address 3 C 1F (hex) Valid R EAD

5. Read address 303F (hex) Valid READ

6. Read address 0C63 (hex) Initiate RECALL cycle

Internally, RECALL is a two-step procedure. First, the

SRAM data is cleared, and second, the nonvolatile

information is transferred into the SRAM cells. After

the tRECALL cycle time the SRAM will once again be

ready for READ and WRITE operations. The RECALL

operation in no way alters the data in the nonvolatile

elements. The nonvolatile data can be recalled an

unlimited number of times.

AutoStore MODE

The STK14C88-NF35U can be powered in one of

three modes.

During normal AutoStore operation, the STK14C88-

NF35U will draw current from VCC to charge a capac-

itor connected to the VCAP pin. This stored charge

will be used by the chip to perform a single STORE

operation. After power up, when the voltage on the

VCAP pin drops below VSWITCH, the part will automati-

cally disconnect the VCAP pin from VCC and initiate a

STORE operation.

Figure 2 shows the proper connection of capacitors

for automatic store operation. A charge storage

capacitor having a capacity of between 68μF and

220μF (± 20%) rated at 6V should be provided.

In system power mode, both VCC and VCAP are con-

nected to the + 5V power supply without the 68μF

capacitor. In this mo de the AutoStore function of the

STK14C88-NF35U will operate on the stored sys-

tem charge as power goes down. The user must,

however, guarantee that VCC does not drop below

3.6V during the 10ms STORE cycle.

In order to prevent unneeded STORE operations,

automatic STOREs as well as those initiated by

externally driving HSB low will be ignored unless at

least one WRITE operation has taken place since the

most recent STORE or RECALL cycle. Software-

initiated STORE cycles are performed regardless of

whether a WRITE operation has taken place.

If the power supply drops faster than 20 μs/volt

before VCC reaches VSWITCH, then a 2.2 ohm resistor

should be inserted between the VCC pin on the IC

and the system supply to avoid momentary excess

of current between Vcc and Vcap.

AutoStore INHIBIT MODE

If an automatic STORE on power loss is not

required, then Vcc can be tied to ground and system

power applied to VCAP (Figure 3). This is the

AutoStore Inhibit mode, in which the AutoStore func-

tion is disabled. If the STK14C88-NF35U is oper-

ated in this configuration, references to Vcc should

be changed to VCAP throughout this data sheet. In

this mode, STORE operations may be triggered

through software control. It is not permissible to

change between these three options “on the fly.”

Figure 2: AutoStore Mode

6v, ±20%

0.1

Bypass

10k

Ω∗

Figure 3: AutoStore Inhibit Mode

0.1

Bypass

10kΩ∗

10kΩ

*If HSB is not used, it should be left unconnected.

STK14C88-NF35U

Feb, 2008

Document Control #ML0066 Rev 2.0

HSB OPERATION

The STK14C88-NF35U provides the HSB pin for

controlling and acknowledging the STORE opera-

tions. The HSB pin can be used to request a hard-

ware STORE cycle. When the HSB pin is driven low,

the STK14C88-NF35U will conditionally initiate a

STORE operation after tDELAY; an actual STORE cycle

will only begin if a WRITE to the SRAM took place

since the last STORE or RECALL cycle. The HSB pi n

has a very resistive pullup and is internally driven

low to indicate a busy condition while the STORE

(initiated by any means) is in progress. Pull up this

pin with an external 10K ohm resistor to VCAP if HSB

is used as a driver.

SRAM READ and WRITE operations that are in

progress when HSB is dri ven low by any means are

given time to complete before the STORE operation

is initiated. After HSB goes low, the STK14C88-

NF35U will continue SRAM o perations for tDELAY

. Dur-

ing tDELAY

, multiple SRAM READ operations may take

place. If a WRITE is in progress when HSB is pulled

low it will be allowed a time, tDELAY

, to complete. How-

ever, any SRAM WRITE cycles requested after HSB

goes low will be inhibited until HSB returns high.

The VCAP pins from the other STK14C88-NF35U

parts can be tied together and share a single capac-

itor. The capacitor size must be scaled by the num-

ber of devices connected to it. It is essential that all

parts have written to the SRAM for this STORE to

execute properly.

During any STORE operation, regardless of how it

was initiated, the STK14C88-NF35U will con tinue to

drive the HSB pin low, releasing it only when the

STORE is complete. Upon completion of the STORE

operation the STK14C88-NF35U will remain dis-

abled until the HSB pin returns high.

If HSB is not used, it sh ould be left unconnected.

BEST PRACTICES

nvSRAM products have been used effectively for

over 15 years. While ease-of-use is one of the prod-

uct’s main system values, experience gained work-

ing with hundreds of application s has resu lted in the

following suggestions as best practices:

• The non-volatile cells in an nvSRAM are pro-

grammed on the test floor during final test and

quality assurance. Incoming inspection routines

at customer or contract manufacturer’s sites will

sometimes reprogram these values. Final NV pat-

terns are typically repeating patterns of AA, 55,

00, FF, A5, or 5A. End product’s firmware should

not assume an NV array is in a set programmed

state. Routines that check memory content val-

ues to determine first time system configuration,

cold or warm boot status, etc. should always pro-

gram a unique NV pattern (e.g., complex 4-byte

pattern of 46 E6 49 53 hex or more random

bytes) as part of the final system manufacturing

test to ensure these system routines work consis-

tently.

• Power up boot firmware routines should rewrite

the nvSRAM into the desired state (autostore

enabled, etc.). While the nvSR AM is shipped in a

preset state, best practice is to again rewrite the

nvSRAM into the desired state as a safeguard

against events that might flip the bit inadvertent ly

(program bugs, incoming inspection routines,

etc.).

•The V

cap value specified in this datasheet

includes a minimum and a maximum value size.

Best practice is to meet this requireme nt and not

exceed the max Vcap value because the nvSRAM

internal algorithm calculates Vcap charge time

based on this max Vcap value. Customers that

want to use a larger Vcap value to make sure

there is extra store charge and store time should

discuss their Vcap size selection with Simtek to

understand any impact on the Vcap voltage level

at the end of a tRECALL period.

Feb, 2008

Document Control #ML0066 Rev 2.0

STK14C88-NF35U

PREVENTING STORES

The STORE function can be disabled on the fly by

holding HSB high with a driver capable of sourcing

30mA at a VOH of at least 2.2V, as it will have to over-

power the internal pull-do wn device that drives HSB

low for 20μs at the onset of a STORE. When the

STK14C88-NF35U is connected for AutoStore oper-

ation (system VCC connected to chip VCC and a 68μF

capacitor on VCAP) and VCC crosses VSWITCH on the

way down, the STK14C88-NF35U will attempt to

pull HSB low; if HSB doesn’t actually get below VIL,

the part will stop trying to pull HSB low and abort the

STORE attempt.

HARDWARE PROTECT

The STK14C88-NF35U offers hardware protection

against inadvertent STORE operation and SRAM

WRITEs during low-voltage conditions. When VCAP <

VSWITCH, all externa lly initiated STORE operations and

SRAM WRITEs will be inhibited.

AutoStore can be completely disabled by tying VCC

to ground and applying + 5V to VCAP. This is the

AutoStore Inhibit mode; in th is mode STOREs are only

initiated by explicit request usi ng either the software

sequence or the HSB pin.

LOW AVERAGE ACTIVE POWER

The STK14C88-NF35U draws significantly less cur-

rent when it is cycled at times longer than 50ns. Fig-

ure 4 shows the relationship between ICC and READ

cycle time. Worst-case current consumption is

shown for both CMOS and TTL input levels (commer-

cial temperature range, VCC = 5.5V, 100% duty cycle

on chip enable). Figure 5 shows the same relation-

ship for WRITE cycles. If the chip enable duty cycle

is less than 100%, only standby current is drawn

when the chip is disabled. The overall average cur-

rent drawn by the STK14C88-NF35U depends on

the following items: 1) CMOS vs. TTL input levels;

2) the duty cycle of chip enable; 3) the overall cycle

rate for accesses; 4) the ratio of READs to WRITEs;

5) the operating temperature; 6) the Vcc level; and

7) I/O loading.

Figure 4: Icc (max) Reads

Figure 5: Icc (max) Writes

100

50 100 150 200

Cycle Time (ns)

TTL

CMOS

Average Active Current (mA)

100

50 100 150 200

Cycle Time (ns)

TTL

CMOS

Averag e Active Curre nt (m A)

STK14C88-NF35U

Feb, 2008

Document Control #ML0066 Rev 2.0

Commercial and Industrial Ordering Information

Packaging Option

Blank = Tube

TR = Tape and Reel

Temperature Range

U = –55°C to 125°C (production testing)

Access Time

35 = 35ns

Lead Finish

F = 100% Sn (Matte Tin)

Package

N = Plastic 32-pin 300 mil SOIC

Part Number Description Access Times Temperature

STK14C88-NF35UTR 5V 32Kx8 AutoStore nvSRAM SOP32-300 35 ns access time -55ºC to 125 ºC

Ordering Information

STK14C88 - N F 35 U TR

Feb, 2008

Document Control #ML0066 Rev 2.0

STK14C88-NF35U

Package Diagrams

32 Lead 300 mil SOIC Gull Wing

DIM = INCHES

DIM = mm

MIN

MAX

MIN

MAX

( )

0.006 0.15

0.013 0.32

( )

0.021 0.53

0.041 1.04

( )

8 o

0 o

BSC

0.810 20.57

0.822 20.88

(

)

0.026 0.66

0.032 0.81

( )

0.004 0.10

0.010 0.25

( )

0.014 0.36

0.020 0.51

( )

0.086

0.090 2.18

2.29

( )

0.090 2.29

0.100 2.54

( )

0.12

0.22

.050 (1.27)

0.292 7.42

0.405 10.29

0.419 10.64

Pin 1

Index

( )

0.300 7.60

(

)

STK14C88-NF35U

Feb, 2008

Document Control #ML0066 Rev 2.0

Document Revision History

SIMTEK STK14C88-NF35U Datasheet, February 2008

This datasheet may only be printed for the expressed use of Simtek Customers. No part of the datasheet may be reproduced in any other

form or means without the express written permission from Simt ek Corporation. The infor mation cont ained in this publicat ion is believed to be

accurate, but changes may be made without notice. Simtek does not assume responsibility for, or grant or imply any warranty, including

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE regarding this information, the product or its use. Nothing herein consti-

tutes a license, grant or transfer of any rights to any Simtek patent, copyright, trademark, or other proprietary right.

Revision Date Summary

2.0 February 2008 New Document