DATA SH EET
Product specification
File under Integrated Circuits, IC24 1999 Oct 14
INTEGRATED CIRCUITS
74ALVCH162601
18-bituniversalbustransceiverwith
30 Ω termination resistor; 3-state
1999 Oct 14 2
Philips Semiconductors Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state 74ALVCH162601
FEATURES
•Complies with JEDEC standard
no. 8-1A
•CMOS low power consumption
•Direct interface with TTL levels
•MULTIBYTE flow-through
standard pin-out architecture
•Low inductance multiple VCC and
ground pins for minimum noise and
ground bounce
•All data inputs have bus hold
circuitry
•Integrated 30 Ω termination
resistors.
DESCRIPTION
The 74ALVCH162601 is an 18-bit universal transceiver featuring non-inverting
3-state bus compatible outputs in both send and receive directions. Data flow
in each direction is controlled by output enable (OEAB and OEBA), and clock
(CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is
latched if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus
data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB.
When OEAB is LOW, the outputs are active. When OEAB is HIGH, the outputs
are in the high-impedance state. The clocks can be controlled with the
clock-enable inputs (CEBA/CEAB).
Data flow for B-to-A is similar to that of A-to-B but uses OEBA,LE
BA and CPBA.
To ensure the high-impedance state during power-down, OEBA and OEAB
should be tied to VCC through a pull-up resistor, the minimum value of the
resistor is determined by the current-sinking/current-sourcing capability of the
driver.
The 74ALVCH162601 is designed with 30 Ω series resistors in both HIGH or
LOW output stage.
Active bus hold circuitry is provided to hold unused or floating data inputs at
a valid logic level.
QUICK REFERENCE DATA
Ground = 0; Tamb =25°C; tr=t
f= 2.5 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PDin µW).
PD=C
PD ×VCC2×fi+∑(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
∑(CL×VCC2×fo) = sum of outputs;
CL= output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI= GND to VCC.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
tPHL/tPLH propagation delay An,B
nto Bn,A
nC
L= 30 pF; VCC = 2.5 V 4.0 ns
CL= 50 pF; VCC = 3.3 V 3.1 ns
CI/O input/output capacitance 8.0 pF
CIinput capacitance 4.0 pF
CPD power dissipation capacitance per
latch notes 1 and 2
outputs enabled 21 pF
outputs disabled 3 pF
1999 Oct 14 3
Philips Semiconductors Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state 74ALVCH162601
FUNCTION TABLE
See note 1.
Note
1. XX = AB for A-to-B direction, BA for B-to-A direction;
H = HIGH voltage level;
L = LOW voltage level;
h = HIGH state must be present one set-up time before the LOW-to-HIGH transition of CPXX;
l = LOW state must be present one set-up time before the LOW-to-HIGH transition of CPXX;
X = don’t care;
↑= LOW-to-HIGH level transition;
NC = no change;
Z = high-impedance OFF-state.
ORDERING INFORMATION
INPUTS OUTPUTS STATUS
CEXX OEXX LEXX CPXX An,B
n
X H X X X Z disabled
X
XL
LH
HX
XH
LH
Ltransparent
H L L X X NC hold
L
LL
LL
L↑
↑h
lH
Lclock and display
L
LL
LL
LL
HX
XNC hold
TYPE NUMBER PACKAGE
TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE
74ALVCH162601DGG −40 to +85 °C 56 TSSOP plastic SOT364-1
1999 Oct 14 4
Philips Semiconductors Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state 74ALVCH162601
PINNING
PIN SYMBOL DESCRIPTION
1OEAB output enable A-to-B
2LE
AB latch enable A-to-B
3, 5, 6, 8, 9, 10, 12, 13, 14, 15,
16, 17, 19, 20, 21, 23, 24, 26 A0to A17 data inputs/outputs
4, 11, 18, 25, 32, 39, 46, 53 GND ground (0 V)
7, 22, 35, 50 VCC DC supply voltage
27 OEBA output enable B-to-A
28 LEBA latch enable B-to-A
29 CEBA clock enable B-to-A
30 CPBA clock input B-to-A
31, 33, 34, 36, 37, 38, 40, 41,
42, 43, 44, 45, 47, 48, 49, 51,
52, 54
B17 to B0data inputs/outputs
55 CPAB clock input A-to-B
56 CEAB clock enable A-to-B
1999 Oct 14 5
Philips Semiconductors Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state 74ALVCH162601
Fig.1 Pin configuration.
handbook, halfpage
162601
MNA287
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
52
51
50
55
56
54
53
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
27
28
GND
A1
VCC
A2
A3
A4
GND
A5
A6
A8
A9
A10
A11
GND
A12
A13
A14
VCC
A15
A16
GND
A17
OEBA
CEAB
CPAB
B0
GND
B1
B2
VCC
B3
B4
B5
GND
B6
B7
B8
B9
B10
B11
GND
B12
B13
B14
VCC
B15
B16
GND
B17
CPBA
CEBA
LEBA
OEAB
LEAB
A0
A7Fig.2 Bus hold circuit.
handbook, halfpage
to internal circuit
MNA291
VCC
data
input
1999 Oct 14 6
Philips Semiconductors Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state 74ALVCH162601
handbook, full pagewidth
CPAB
OEAB
MNA289
18 IDENTICAL CHANNELS
CEAB
LEAB
CPBA
LEBA
CEBA
OEBA
CP
CE
C1
1D
CP
An
Bn
CE
C1
1D
Fig.3 Logic diagram (one section).
1999 Oct 14 7
Philips Semiconductors Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state 74ALVCH162601
Fig.4 IEC logic symbol.
handbook, halfpage
EN4
C6
G5
G5
54
3
5
17
52
40
6
19
51
38
8
20
49
37
9
21
48
36
10
23
47
34
12
24
45
33
13
26
44
31
A0
B11
B12
B13
B14
B15
B16
B17
MNA290
B0
B1
B2
B3
B4
B5
B6
B7
13D
46D
28
14 43
15 42
16 41
B8
B9
B10
A11
A12
A13
A14
A15
A16
A17
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
27
29
OEBA
CEBA
CPBA
LEBA
30 5C6
EN1
C3
G2
G2
2
1
56
OEAB
CEAB
CPAB
LEAB
55 2C3
handbook, halfpage
MNA288
A0
A1
A2
A3
A4
A5
A6
A7
OEAB
LEAB
CPAB
CEAB
B0
B1
B2
B3
B4
B5
B6
B7
52
54
51
49
48
47
45
44
5
3
6
8
9
10
12
13
1
2
55
56
27
28
30
29
A8
A9
A10
A11
A12
A13
A14
A15
B8
B9
B10
B11
B12
B13
B14
B15
42
43
41
40
38
37
36
34
15
14
16
17
19
20
21
23 A16
A17
B16
B17 33
31
24
26
OEBA
LEBA
CPBA
CEBA
Fig.5 Logic symbol.
1999 Oct 14 8
Philips Semiconductors Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state 74ALVCH162601
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Above 55 °C the value of Ptot derates linearly with 8 mW/K.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VCC DC supply voltage
for max. speed performance CL= 30 pF 2.3 2.5 2.7 V
for max. speed performance CL= 50 pF 3.0 3.3 3.6 V
for low-voltage applications 1.2 2.4 3.6 V
VIDC input voltage 0 −VCC V
VODC output voltage 0 −VCC V
Tamb operating ambient temperature in free air −40 −+85 °C
tr, tfinput rise and fall times VCC = 2.3 to 3.0 V 0 −20 ns/V
VCC = 3.0 to 3.6 V 0 −10 ns/V
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC DC supply voltage −0.5 +4.6 V
IIK DC input diode current VI<0 −−50 mA
VIDC input voltage note 1 −0.5 +4.6 V
IOK DC output diode current VO>V
CC or VO<0 −±50 mA
VODC output voltage note 1 −0.5 VCC + 0.5 V
IODC output source or sink current VO=0toV
CC −±50 mA
ICC, IGND DC VCC or GND current −±100 mA
Tstg storage temperature −65 +150 °C
Ptot power dissipation for temperature range: −40 to +125 °C;
note 2 −600 mW
1999 Oct 14 9
Philips Semiconductors Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state 74ALVCH162601
DC CHARACTERISTICS
Over recommended operating conditions; voltages are referenced to GND (ground=0V).
Notes
1. All typical values are measured at Tamb =25°C.
2. Valid for data inputs of bus hold parts.
SYMBOL PARAMETER TEST CONDITIONS Tamb =−40 TO +85 °CUNIT
VI(V) OTHER VCC (V) MIN. TYP.(1) MAX.
VIH HIGH-level input voltage 2.3 to 2.7 1.7 1.2 −V
2.7 to 3.6 2.0 1.5 −
VIL LOW-level input voltage 2.3 to 2.7 −1.2 0.7 V
2.7 to 3.6 −1.5 0.8
VOH HIGH-level output voltage VIH or VIL IO=−100 µA 2.3 to 3.6 VCC −0.2 VCC −V
IO=−4 mA 2.3 VCC −0.4 VCC −0.11 −
IO=−6 mA 2.3 VCC −0.6 VCC −0.17 −
IO=−4 mA 2.7 VCC −0.5 VCC −0.09 −
IO=−8 mA 2.7 VCC −0.7 VCC −0.19 −
IO=−6 mA 3.0 VCC −0.6 VCC −0.13 −
IO=−12 mA 3.0 VCC −1.0 VCC −0.27 −
VOL LOW-level output voltage VIH or VIL IO= 100 µA 2.3 to 3.6 −GND 0.20 V
IO=4mA 2.3 −0.07 0.40
IO=6mA 2.3 −0.11 0.55
IO=4mA 2.7 −0.06 0.40
IO=8mA 2.7 −0.13 0.60
IO=6mA 3.0 −0.09 0.55
IO=12mA 3.0 −0.19 0.80
Ilinput leakage current VCC or
GND 2.3 to 3.6 −0.1 5 µA
IOZ 3-state output OFF-state
current VIH or VIL VO=V
CC or
GND 2.3 to 3.6 −0.1 10 µA
ICC quiescent supply voltage VCC or
GND IO= 0 2.3 to 3.6 −0.2 40 µA
∆ICC additionalquiescentsupply
current given per data I/O
pin with bus hold
VCC −0.6 IO= 0 2.3 to 3.6 −150 750 µA
IBHL bus hold LOW sustaining
current 0.7(2) 2.3(2) 45 −−µA
0.8(2) 3.0(2) 75 150 −
IBHH bus hold HIGH sustaining
current 1.7(2) 2.3(2) −45 −µA
2.0(2) 3.0(2) −75 −175 −
IBHLO bus hold LOW overdrive
current 3.6(2) 500 −−µA
I
BHHO bus hold LOW overdrive
current 3.6(2) −500 −−µA
1999 Oct 14 10
Philips Semiconductors Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state 74ALVCH162601
AC CHARACTERISTICS FOR VCC = 2.3 TO 2.7 V
Ground = 0 V; tr=t
f≤2.0 ns; CL=30pF.
Note
1. All typical values are measured at Tamb =25°C and VCC = 2.5 V.
SYMBOL PARAMETER TEST CONDITIONS Tamb =−40 TO +85 °CUNIT
WAVEFORMS VCC (V) MIN. TYP.(1) MAX.
tPHL/tPLH propagation delay
An,B
nto Bn,A
n
see Figs 6 and 10 2.3 to 2.7 1.3 4.0 5.3 ns
propagation delay
LEAB,LE
BA to Bn,A
n
see Figs 7 and 10 2.3 to 2.7 1.0 4.5 6.0 ns
propagation delay
CPAB,CP
BA to Bn,A
n
see Figs 7 and 10 2.3 to 2.7 1.5 4.7 6.4 ns
tPZH/tPZL 3-state output enable time
OEAB, OEBA to Bn,A
n
see Figs 8 and 10 2.3 to 2.7 1.6 3.9 6.1 ns
tPHZ/tPLZ 3-state output disable time
OEAB, OEBA to Bn,A
n
see Figs 8 and 10 2.3 to 2.7 1.8 2.6 5.7 ns
tWclockpulsewidth HIGH LEAB
or LEBA
see Figs 7 and 10 2.3 to 2.7 3.3 1.6 −ns
clock pulse width HIGH or
LOW CPAB or CPBA
see Figs 7 and 10 2.3 to 2.7 3.3 2.0 −ns
tsu set-up time
An,B
nto CPAB,CP
BA
see Figs 9 and 10 2.3 to 2.7 +2.3 −0.2 −ns
set-up time
An,B
nto LEAB,LE
BA
see Figs 9 and 10 2.3 to 2.7 1.3 0.1 −ns
set-up time
CEAB, CEBA to CPAB,CP
BA
2.3 to 2.7 +2.0 −0.4 −ns
thhold time
An,B
nto CPAB,CP
BA
see Figs 9 and 10 2.3 to 2.7 1.2 0.3 −ns
hold time
An,B
nto LEAB,LE
BA
see Figs 9 and 10 2.3 to 2.7 1.3 0.2 −ns
hold time
CEAB, CEBA to CPAB,CP
BA
2.3 to 2.7 1.1 0.4 −ns
fmax maximum clock pulse
frequency see Figs 7 and 10 2.3 to 2.7 150 190 −MHz
1999 Oct 14 11
Philips Semiconductors Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state 74ALVCH162601
AC CHARACTERISTICS FOR VCC = 2.7 V AND VCC = 3.0 TO 3.6 V
Ground = 0 V; tr=t
f≤2.5 ns; CL=50pF.
Notes
1. All typical values are measured at Tamb =25°C.
2. Typical values at VCC = 3.3 V.
SYMBOL PARAMETER TEST CONDITIONS Tamb =−40 TO +85 °CUNIT
WAVEFORMS VCC (V) MIN. TYP.(1) MAX.
tPHL/tPLH propagation delay
An,B
nto Bn,A
n
see Figs 6 and 10 2.7 −3.9 5.2 ns
3.0 to 3.6 1.6 3.1(2) 4.5
propagation delay
LEAB,LE
BA to Bn,A
n
see Figs 7 and 10 2.7 −4.3 5.9 ns
3.0 to 3.6 1.5 3.5(2) 5.1
propagation delay
CPAB,CP
BA to Bn,A
n
see Figs 7 and 10 2.7 −4.5 6.3 ns
3.0 to 3.6 1.6 3.7(2) 5.5
tPZH/tPZL 3-state output enable time
OEAB, OEBA to Bn,A
n
see Figs 8 and 10 2.7 −3.9 6.7 ns
3.0 to 3.6 1.6 3.1(2) 5.7
tPHZ/tPLZ 3-state output disable time
OEAB, OEBA to Bn,A
n
see Figs 8 and 10 2.7 −3.2 5.3 ns
3.0 to 3.6 1.8 2.9(2) 4.8
tWclock pulse width
LEAB,LE
BA to CPAB,CP
BA
see Figs 7 and 10 2.7 3.3 0.7 −ns
3.0 to 3.6 3.3 0.9(2) −
clock pulse width HIGH or
LOW CPAB,CP
BA
see Figs 7 and 10 2.7 3.3 1.2 −ns
3.0 to 3.6 3.3 0.9(2) −
tsu set-up time
An,B
nto CPAB,CP
BA
see Figs 9 and 10 2.7 2.4 0.0 −ns
3.0 to 3.6 +2.1 −0.2(2) −
set-up time
An,B
nto LEAB,LE
BA
see Figs 9 and 10 2.7 +1.2 −0.2 −ns
3.0 to 3.6 1.1 0.3(2) −
set-up time
CEAB, CEBA to CPAB,CP
BA
2.7 +2.0 −0.7 −ns
3.0 to 3.6 +1.7 −0.2(2) −
thhold time
An,B
nto CPAB,CP
BA
see Figs 9 and 10 2.7 1.1 0.3 −ns
3.0 to 3.6 +1.0 −0.1(2) −
hold time
An,B
nto LEAB,LE
BA
see Figs 9 and 10 2.7 1.6 0.1 −ns
3.0 to 3.6 1.4 0.1(2) −
hold time
CEAB, CEBA to CPAB,CP
BA
2.7 1.2 0.6 −ns
3.0 to 3.6 1.1 0.4(2) −
fmax maximum clock pulse
frequency see Figs 7 and 10 2.7 150 190 −MHz
3.0 to 3.6 150 240(2) −
1999 Oct 14 12
Philips Semiconductors Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state 74ALVCH162601
AC WAVEFORMS
Fig.6 The input An, Bn to output Bn, An propagation delay times.
handbook, halfpage
MNA292
An, Bn
input
Bn, An
output
tPHL tPLH
GND
VI
VM
VM
VOH
VOL
Notes: VCC = 2.3 to 2.7 V
VM= 0.5VCC;
VX=V
OL + 150 mV;
VY=V
OH −150 mV;
VI=V
CC;
VOL and VOH are typical output voltage drop that occur with the output load.
Notes: VCC = 3.0 to 3.6 V and VCC = 2.7 V
VM= 1.5 V;
VX=V
OL + 300 mV;
VY=V
OH −300 mV;
VI= 2.7 V;
VOL and VOH are typical output voltage drop that occur with the output load.
1999 Oct 14 13
Philips Semiconductors Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state 74ALVCH162601
handbook, full pagewidth
MNA293
LEXX, CPXX input
Bn, An output
tPHL tPLH
tW
1/fmax
VM
VOH
VI
GND
VOL
VMVM
Fig.7 Latch enable input LEAB, LEBA and clock input CPAB, CPBA to output Bn,A
n
propagation delay times;
pulse width and fmax of CPAB, CPBA.
handbook, full pagewidth
MNA294
tPLZ
tPHZ
outputs
disabled outputs
enabled
VY
VX
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
OEXX input
VI
VOL
VOH
VCC
VM
GND
GND
tPZL
tPZH
VM
VM
Fig.8 3-state enable and disable times.
1999 Oct 14 14
Philips Semiconductors Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state 74ALVCH162601
Fig.9 Data set-up and hold times for An and Bn inputs to LEAB, LEBA, CPAB or CPBA inputs.
The shaded areas indicate when the input is permitted to change for predictable output performance.
handbook, full pagewidth
MNA295
GND
VI
GND
VI
CPXX, LEXX input
An, Bn input
th
tsu
th
tsu
VM
VM
Fig.10 Load circuitry for switching times.
VCC VI
<2.7 V VCC
2.7 to 3.6 V 2.7 V
TEST S1
tPLH/tPHL open
tPLZ/tPZL 2×VCC
tPHZ/tPZH GND
handbook, full pagewidth
open
GND
50 pF
2 × VCC
VCC
VIVO
MNA296
D.U.T.
CL
RT
RL
500 Ω
RL
500 Ω
PULSE
GENERATOR
S1
Definitions for test circuit.
CL= load capacitance including jig and probe capacitance
(See Chapter “AC characteristics”).
RL= load resistance.
RT= termination resistance should be equal to the output impedance Zo
of the pulse generator.
1999 Oct 14 15
Philips Semiconductors Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state 74ALVCH162601
PACKAGE OUTLINE
UNIT A1A2A3bpcD
(1) E(2) eH
ELL
pQZywvθ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm 0.15
0.05 0.2
0.1 8
0
o
o
0.1
DIMENSIONS (mm are the original dimensions).
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
SOT364-1 93-02-03
95-02-10
wM
θ
A
A1
A2
D
Lp
Q
detail X
E
Z
e
c
L
X
(A )
3
0.25
128
56 29
y
pin 1 index
b
H
1.05
0.85 0.28
0.17 0.2
0.1 14.1
13.9 6.2
6.0 0.5 1.0
8.3
7.9 0.50
0.35 0.5
0.1
0.080.25
0.8
0.4
p
EvMA
A
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1
A
max.
1.2
0
2.5
5 mm
scale
MO-153EE
1999 Oct 14 16
Philips Semiconductors Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state 74ALVCH162601
SOLDERING
Introduction to soldering surface mount packages
Thistextgivesavery briefinsighttoacomplex technology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuitboard by screenprinting, stencillingor
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Wave soldering
Conventional single wave soldering is not recommended
forsurfacemount devices(SMDs)or printed-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
•Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
•For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
•Forpackageswith leadsonfour sides,thefootprint must
be placed at a 45°angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 Oct 14 17
Philips Semiconductors Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state 74ALVCH162601
Suitability of surface mount IC packages for wave and reflow soldering methods
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”
.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PACKAGE SOLDERING METHOD
WAVE REFLOW(1)
BGA, SQFP not suitable suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable(2) suitable
PLCC(3), SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended(3)(4) suitable
SSOP, TSSOP, VSO not recommended(5) suitable
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
1999 Oct 14 18
Philips Semiconductors Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state 74ALVCH162601
NOTES
1999 Oct 14 19
Philips Semiconductors Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state 74ALVCH162601
NOTES
© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Internet: http://www.semiconductors.philips.com
1999 68
Philips Semiconductors – a world wide company
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Printed in The Netherlands 245004/01/pp20 Date of release: 1999 Oct 14 Document order number: 9397 750 05257