DF6811 - Digital Core Design

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8-bit FAST Microcontrollers Family

ver 3.01

OVERVIEW

Document contains brief description of

DF6811 core functionality. The DF6811 is a

advanced 8-bit MCU IP Core with highly so-

phisticated, on chip peripheral capabilities.

DF6811 soft core is binary-compatible with the

industry standard 68HC11 8-bit microcontrol-

ler and can achieve a performance 45-100

million instructions per second. The DF6811

has FAST architecture that is 4 times faster

compared to original implementation. Core in

standard configuration has integrated on chip

major peripheral function. There are two serial

interfaces: an asynchronous serial communi-

cations interface (SCI) and a separate syn-

chronous serial peripheral interface (SPI). The

main 16-bit, free-running timer system has

implemented three input capture lines, five

output-compare lines, and a real-time interrupt

function. An 8-bit pulse accumulator subsys-

tem can count external events or measure

external periods.

Self-monitoring circuitry is included on-chip to

protect against system errors. A computer

operating properly (COP) watchdog system

protects against software failures. An illegal

opcode detection circuit provides a non-

maskable interrupt if illegal opcode is de-

tected. Two software-controlled power-saving

modes, WAIT and STOP, are available to

conserve additional power. These modes

make the DF6811 IP Core especially attrac-

tive for automotive and battery-driven applica-

tions. The DF6811 have built in the develop-

ment support features designed into DF6811.

The LIR signal is intended as a debugging aid.

This signal is driven to active low for the first

bus cycle of each new instruction, making it

easy to reverse assemble (disassemble) in-

structions from the display of a logic analyzer.

DF6811 is fully customizable, which means

it is delivered in the exact configuration to

meet users requirements. There is no need to

pay extra for not used features and wasted

silicon. It includes fully automated testbench

with complete set of tests allowing easy

package validation at each stage of SoC de-

sign flow.

CPU FEATURES

● FAST architecture, 4 times faster than the

original implementation

● Software compatible with industry stan-

dard 68HC11

● 10 times faster multiplication

● 16 times faster division

● 256 bytes of remapped System Function

Registers space (SFRs)

● Up to 16M bytes of Data Memory

● De-multiplexed Address/Data Bus to allow

easy connection to memory

● Two power saving modes: STOP, WAI

● Ready pin allows Core to operate with

slow program and data memories

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● Fully synthesizable, static synchronous

design with no internal tri-states

● No internal reset generator or gated clock

● Scan test ready

● Technology independent HDL source code

● Core can be fully customized

● 1 GHz virtual clock frequency compared to

original implementation

DESIGN FEATURES

♦ ONE GLOBAL SYSTEM CLOCK

♦ SYNCHRONOUS RESET

The DF6811 has 3 reset vectors

sources, which easy identify a cause of

system reset.

♦ ALL ASYNCHRONOUS INPUT SIGNALS ARE

SYNCHRONIZED BEFORE INTERNAL USE

9 DATA MEMORY:

The DF6811 can address up to 16M

bytes of Data Memory via the function in-

terconnect signals. The 256 bytes of Data

Memory in every 64k page is reserved for

the Function Registers. Extra DPP (Data

Page Pointer) register is used for segments

swapping. Data Memory can be imple-

mented as synchronous or asynchronous

RAM.

9 SYSTEM FUNCTION REGISTERS:

Up to 256 System Function Regis-

ters(SFRs) may be implemented to the

DF6811 design. SFRs are memory

mapped into Data Memory within any 4k

bytes address space.

9 PROGRAM MEMORY:

Up to 64kB of Program Memory may be

implemented to the DF6811 design. Pro-

gram Memory can be implemented as syn-

chronous or asynchronous ROM.

PERIPHERALS

The peripherals listed below are implemented

in standard configuration of DF6811.

● DoCDTM on Chip Debugger

○ Processor execution control

○ Read, write all processor contents

○ Hardware execution breakpoints

○ Three wire communication interface

● Four 8-bit I/O Ports

● Interrupt Controller

○ 20 interrupt sources

○ 17 priority levels

○ Dedicated Interrupt ve ctor for each interrupt

● Main16-bit timer/counter system

○ 16 bit free running co unter

○ Four stage prog rammable prescaller

○ Timer clocked by internal source

○ Real Time Interrupt

● 16-bit Compare/Capture Unit

○ Three independ ent input-capture functions

○ Five output-compare ch annels

○ Events capturing

○ Pulses and digital signals generation

○ Gated timers

○ Sophisticated comparator

○ Pulse width modulation

○ Pulse width measuring

● 8-bit Pulse accumulator

○ Two major modes of operation

○ Simple event counter

○ Gated time accumulation

○ Clocked by internal so urce or external pin

● SPI – Master and Slave Serial Peripheral

Interface

○ Supports speeds u p 1/8 of system clock

○ Software selectable polarity and phase of se-

rial clock SCK

○ System errors detection

○ Allows operation from a wide range of system

clock frequencies (build-in 5-bit timer)

○ Interrupt generation

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● Full-duplex UART - SCI

○ Standard Nonreturn to Zero form at (NRZ)

○ 8 or 9 bit data transfer

○ Integrated baud rate ge nerator

○ Noise, Overrun and Fram ing error detection

○ IDLE and BREAK characters generation

○ Wake-up block to recognize UART wake-up

from IDLE condition

○ Three SCI related interrupts

DELIVERABLES

♦ Source code:

◊ VHDL Source Code or/and

◊ VERILOG Source Code or/and

◊ Encrypted, or plain text EDIF

♦ VHDL & VERILOG test bench environ-

ment

◊ Active-HDL automatic simulation macros

◊ ModelSim automatic simulation macros

◊ Tests with reference responses

♦ Technical documentation

◊ Installation notes

◊ HDL core specification

◊ Datasheet

♦ Synthesis scripts

♦ Example application

♦ Technical support

◊ IP Core implementation support

◊ 3 months maintenance

● Delivery the IP Core updates, minor

and major versions changes

● Delivery the documentation updates

○ Phone & email support

LICENSING

Comprehensible and clearly defined licensing

methods without royalty fees make using of IP

Core easy and simply.

Single Design license allows use IP Core in

single FPGA bitstream and ASIC implementa-

tion.

Unlimited Designs, One Year licenses allow

use IP Core in unlimited number of FPGA bit-

streams and ASIC implementations.

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time restric-

tion except One Year license where time of

use is limited to 12 months.

● Single Design license for

○ VHDL, Verilog source code called HDL Source

○ Encrypted, or plain text EDIF called Netlist

● One Year license for

○ Encrypted Netlist only

● Unlimited Designs license for

○ HDL Source

○ Netlist

● Upgrade from

○ HDL Source to Netlist

○ Single Design to Unlimited Designs

CONFIGURATION

The following parameters of the DF6811 core

can be easy adjusted to requirements of

dedicated application and technology. Con-

figuration of the core can be prepared by ef-

fortless changing appropriate constants in

package file. There is no need to change any

parts of the code.

- used

•

DoCDTM Hardware Debugger - unused

-Harvard

•

Architecture type - Von Neumann

- Synchronous

•

Memories type - Asynchronou

- 64 kB

•

Data Memory size - 16 MB

- used

•

Memories wait-states - unused

- used

•

Power saving STOP mode - unused

- used

•

WATCHDOG Timer - unused

- used

•

Timer system & Com, Cap - unused

- used

•

Pulse Accumulator - unused

- used

•

PORTS A, B, C, D - unused

- used

•

SCI – UART Interface - unused

- used

•

SPI Interface - unused

- used

•

Support for MUL and DIV

Instructions - unused

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PINS DESCRIPTION

PIN ACTIVE TYPE DESCRIPTION

clk - input Global system clock

por Low input Power on reset vector fetch

cmf Low input Clock monitor fail vector fetch

prgdata[7:0] - input Program memory bus input

ready Low input Ready for Code and Data mem.

datai[7:0] - input Memory bus input

ufrdatai[7:0] - input UFRs data bus input

irq * input Interrupt input

xirq Low input Non-maskable interrupt input

portxi[7:0] - input Port A, B, C, D input

cap1,2,3 Low input Capture inputs

pai * input Pulse accumulator input

rxd Low input SCI receiver data input

si High input SPI slave input

mi High input SPI master input

scki * input SPI clock input

ss Low input SPI slave select

prgaddr[15:0] - output Program memory address bus

prgoe - output Program memory output enable

datao[7:0] - output Data memory & UFR bus output

addr[23:0] - output Data memory address bus

ramwe Low output Data memory write enable

ramoe Low output Data memory output enable

ufraddr[7:0] - output UFR address bus

ufrwe Low output UFRs write enable

ufroe Low output UFRs output enable

lir Low output Load instruction register

halt High output Halt clock system (STOP inst.)

portxo[7:0] - output Port A, B, C, D output

ddrx[7:0] - output Port A, B, C, D direction control

cmp1,2,3,4,5 * output Compare outputs

cmp1en,2,3,4,5 High output Output compare enable

txd Low output SCI transmitter data output

so High output SPI slave output

mo High output SPI master output

scko * output SPI clock output

scken High output SPI clock output enable

soen High output SPI Slave Output enable

clkdocd - input DoCDTM clock input

docddatai - input DoCDTM serial Data input

docddatao - output DoCDTM Serial Data Output

docdclk - output DoCDTM Serial Clock Output

* Kind of activity is configurable

SYMBOL

iramaddr(9:0)

iramwe

iramoe

portao(7:0)

portdo(7:0)

portco(7:0)

portbo(7:0)

portai(7:0)

portbi(7:0)

portci(7:0)

portdi(7:0)

iramdata(7:0)

ufrdatai(7:0)

irq

xirq

pai

cap1

cap2

cap3

clk

rxd

datao(7:0)

txd

soen

scki scko

scken

por

cmf

halt

ddra(7:0)

ddrd(7:0)

ddrc(7:0)

ddrb(7:0)

cmp1en

cmp2en

cmp3en

cmp4en

cmp5en

cmp1

cmp2

cmp3

cmp4

cmp5

lir

iromdata(7:0) iromaddr(12:0)

iromoe

iromwe

ready

ufraddr(7:0)

ufrwe

ufroe

clkdocd

docddatai

docddatao

docdclk

DoCD

Interface

xramaddr(23:0)

xramwe

xramoe

xramdata(7:0

moda

modb

dataen

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BLOCK DIAGRAM

Control Unit - Performs the core synchroni-

zation and data flow control. This module

manages execution of all instructions. The

Control Unit also manages execution of STOP

instruction and waking-up the processor from

the STOP mode.

Opcode Decoder - Performs an instruction

opcode decoding and the control functions for

all other blocks.

ALU - Arithmetic Logic Unit performs the

arithmetic and logic operations during execu-

tion of an instruction. Contains accumulator

(A, B), Condition Code Register (CCREG),

Index registers X, Y and related logic such as

arithmetic and logic unit, and multiplier/divider.

Bus Controller – Program Memory, Data

Memory & SFR’s (Special Function Register)

interface controls access into the program and

data memories and special registers. It con-

tains Program Counter (PC), Stack Pointer

(SP) register, INIT register (INIT), Data Page

Pointer (DPP), and related logic.

Interrupt Controller - DF6811 extended IC

has implemented 17-level interrupt priority

control. The interrupt requests may come from

external pins (IRQ and XIRQ) as well as from

particular peripherals. The DF6811 peripheral

systems generate maskable interrupts, which

are recognized only if the global interrupt

mask bit (I) in the CCR is cleared. Maskable

interrupts are prioritized according to default

arrangement (look at the table below) estab-

lished during reset. However any one source

may be elevated to the highest maskable pri-

ority position using HPRIO register. When

interrupt condition occurs, an interrupt status

flag is set to indicate the condition.

I/O Ports - All ports are 8-bit general-purpose

bi-directional I/O system. The PORTA,

PORTB, PORTC, PORTD data registers have

their corresponding data direction registers

DDRA, DDRB, DDRC, DDRD to control ports

data flow. It assures that all DF6811’s ports

have full I/O selectable registers. Writes to

any ports pins cause data to be stored in the

data registers. If any port pins are configured

as output then data registers are driven out of

those pins. Reads from port pins configured

as input causes that input pin is read. If port

pins is configured as output, during read data

configured as outputs do not cause data to be

driven out of those pins, but the data is stored

in the output registers. Thus, if the pins later

become outputs, the last data written to port

will be driven out the port pins.

portao

portdo

portco

portbo

iromdata

clk

por

datao

cap1

cap2

cap3

BUS

Controller

I/O

Ports

Opcode

Decoder

Control

Unit

Interrupt

Controller

Timer

with

Compare /

Capture

Unit

SCI Unit

SPI Unit

irq

cmp1

cmp2

cmp3

cmp4

cmp5

cmp1en

cmp2en

cmp3en

cmp4en

cmp5en

txd

rxd

scki

scko

scken

xirq

iromoe

iromwe

iromaddr

halt

portai

portdi

portci

portbi

lir

ddra

ddrd

ddrc

ddrb

Watchdog

Timer

Pulse

Accumulator

pai

ALU

ready

DoCD

Debugger

docdclk

docddatai

docddatao

clkdocd

iramdata

iramwe

iramaddr

iramoe

xramdata

xramwe

xramaddr

xramoe

ufrdata

ufrwe

ufraddr

ufroe

moda

soen

dataen

modb

Timer, Compare Capture & COP Watchdog

- This timer system is based on a free-running

16-bit counter with a 4-stage programmable

prescaler. A timer overflow function allows

software to extend the timing capability of the

system beyond the 16-bit range of the coun-

ter. Three independent input-capture functions

are used to automatically record the time

when a selected transition is detected at a

respective timer input pin. Five output-

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compare functions are included for generating

output signals or for timing software delays.

Since the input-capture and output-compare

functions may not be familiar to all users,

these concepts are explained in greater detail.

A programmable periodic interrupt circuit

called RTI is tapped off of the main 16-bit

timer counter. Software can select one of four

rates for the RTI, which is most commonly

used to pace the execution of software rou-

tines. The COP watchdog function is loosely

related to the main timer in that the clock input

to the COP system (clk*217) is tapped off the

free-running counter chain. The timer sub-

system involves more registers and control

bits than any other subsystem on the MCU.

Each of the three input-capture functions has

its own 16-bit time capture latch (input-capture

functions has its own 16-bit compare register.

All timer functions, including the timer overflow

and RTI, have their own interrupt controls and

separate interrupt vectors. Additional control

bits permit software to control the edge(s) that

trigger each input-capture function and the

automatic actions that result from output-

compare functions. Although hardwired logic

is included to automate many timer activities,

this timer architecture is essentially a soft-

ware-oriented system. This structure is easily

adaptable to a very wide range of applications

although it is not as efficient as dedicated

hardware for some specific timing applica-

tions.

SCI - The SCI is a full-duplex UART type

asynchronous system, using standard non

return to zero (NRZ) format : 1 start bit, 8 or 9

data bits and a 1 stop bit. The DF6811 resyn-

chronizes the receiver bit clock on all one to

zero transitions in the bit stream. Therefore

differences in baud rate between the sending

device and the SCI are not as likely to cause

reception errors. Three logic samples are

taken near the middle of data bit time, and

majority logic decides the sense for the bit.

For the start and stop bits seven logic sam-

ples are taken. Even if noise causes one of

these samples to be incorrect, the bit will still

be received correctly. The receiver also has

the ability to enter a temporary standby mode

(called receiver wakeup) to ignore messages

intended for a different receiver. Logic auto-

matically wakes up the receiver in time to see

the first character of the next message. This

wakeup feature greatly reduces CPU over-

head in multi-drop SCI networks. The SCI

transmitter can produce queued characters of

idle (whole characters of all logic 1) and break

(whole characters of all logic 0). In addition to

the usual transmit data register empty (TDRE)

status flag, this SCI also provides a transmit

complete (TC) indication that can be used in

applications with a modem.

SPI Unit – it’s a fully configurable mas-

ter/slave Serial Peripheral Interface, which

allows user to configure polarity and phase of

serial clock signal SCK. It allows the micro-

controller to communicate with serial periph-

eral devices. It is also capable of interproces-

sor communications in a multi-master system.

A serial clock line (SCK) synchronizes shifting

and sampling of the information on the two

independent serial data lines. SPI data are

simultaneously transmitted and received. SPI

system is flexible enough to interface directly

with numerous standard product peripherals

from several manufacturers. Data rates as

high as CLK/8. Clock control logic allows a

selection of clock polarity and a choice of two

fundamentally different clocking protocols to

accommodate most available synchronous

serial peripheral devices. When the SPI is

configured as a master, software selects one

of four different bit rates for the serial clock.

Error-detection logic is included to support

interprocessor communications. A write-

collision detector indicates when an attempt is

made to write data to the serial shift register

while a transfer is in progress. A multiple-

master mode-fault detector automatically dis-

ables SPI output drivers if more than one SPI

devices simultaneously attempts to become

bus master.

Pulse Accumulator – This system is based

on an 8-bit counter and can be configured to

operate as a simple event counter or for gated

time accumulation. Unlike the main timer, the

8-bit pulse accumulator counter can be read

or written at any time (the 16-bit counter in the

main timer cannot be written). Control bits

allow the user to configure and control the

pulse accumulator subsystem. Two maskable

interrupts are associated with the system,

each having its own controls and interrupt

vector. The PAI pin associated with the pulse

accumulator can be configured to act as a

clock (event counting mode) or as a gate sig-

nal to enable a free-running E divided by 64

clock to the 8-bit counter (gated time accu-

mulation mode). The alternate functions of the

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pulse accumulator input (PAI) pin present

some interesting application possibilities.

DoCDTM - Debug Unit – it’s a real-time hard-

ware debugger provides debugging capability

of a whole SoC system. In contrast to other

on-chip debuggers DoCD™ provides non-

intrusive debugging of running application. It

can halt, run, step into or skip an instruction,

read/write any contents of microcontroller in-

cluding all registers, internal, external, pro-

gram memories, all SFRs including user de-

fined peripherals. Hardware breakpoints can

be set and controlled on program memory,

internal and external data memories, as well

as on SFRs. Hardware breakpoint is executed

if any write/read occurred at particular address

with certain data pattern or without pattern.

The DoCDTM system includes three-wire in-

terface and complete set of tools to communi-

cate and work with core in real time debug-

ging. It is built as scalable unit and some fea-

tures can be turned off to save silicon and

reduce power consumption. A special care on

power consumption has been taken, and

when debugger is not used it is automatically

switched in power save mode. Finally whole

debugger is turned off when debug option is

no longer used.

OPTIONAL

PERIPHERALS

There are also available an optional pe-

ripherals, not included in presented DF6811

Microcontroller Core. The optional peripherals,

can be implemented in microcontroller core

upon customer request.

● I2C bus controller - Master

○ 7-bit and 10-bit addressing modes

○ NORMAL, FAST, HIGH speeds

○ Multi-master systems supported

○ Clock arbitration and synchronization

○ User defined timings on I2C lines

○ Wide range of system clock frequencies

○ Interrupt generation

● I2C bus controller - Slave

○ NORMAL speed 100 kbs

○ FAST speed 400 kbs

○ HIGH speed 3400 kbs

○ Wide range of system clock frequencies

○ User defined data setup time on I2C lines

○ Interrupt generation

● PWM – Pulse Width Modulation Timer

○ 4 independent 8-bit PWM channels, concate-

nated on two 16-bit PWM channel

○ Software-selectable duty from 0% to 100% and

pulse period

○ Software-selectable polarity of output wave-

form

● Fixed-Point arithmetic coprocessor

○ Multiplication - 16bit * 16bit

○ Division - 32bit / 16bit

○ Division - 16bit / 16bit

○ Left and right shifting - 1 to 31 bits

○ Normalization

● Floating-Point arithmetic coprocessor

IEEE-754 standard single precision

○ FADD, FSUB - addition, subtraction

○ FMUL, FDIV- multiplication, division

○ FSQRT- square root

○ FUCOM - compare

○ FCHS - change sign

○ FABS - absolute value

● Floating-Point math coprocessor - IEEE-

754 standard single precision real, word

and short integers

○ FADD, FSUB- addition, subtraction

○ FMUL, FDIV- multiplication, division

○ FSQRT- square root

○ FUCOM- compare

○ FCHS - change sign

○ FABS - absolute value

○ FSIN, FCOS- sine, cosine

○ FTAN, FATAN – tangent arcs tangent

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PERFORMANCE

The following table gives a survey about

the Core area and performance in the

ALTERA® devices after Place & Route:

Device Speed

grade Logic Cells Fmax

CYCLONE -6 2958 58 MHz

STRATIX -5 2957 62 MHz

APEX II -7 3092 50 MHz

APEX20KC -7 2972 43 MHz

APEX20KE -1 2972 39 MHz

ACEX1K -1 3023 33 MHz

FLEX10KE -1 3023 33 MHz

Core performance in ALTERA® devi ces

Area utilized by the each unit of DF6811 core

in vendor specific technologies is summarized

in table below.

Component Area

[LC] [FFs]

CPU* 1 986 284

Main Timer 180 50

COM/CAP 400 224

Watchdog 74 36

Pulse Acc. 44 19

SPI Interface 138 62

UART - SCI 272 129

I/O Ports 160 64

Total area 3 254 829

*CPU – consisted of ALU, Control Unit and Instruction Decoder, Bus

Controller with support for 16MB RAM, External IRQ and XIRQ pin

Interrupt Controller

Core components are a utilization

IMPROVEMENT

For user the most important is application

speed improvement. The most commonly

used arithmetic functions and theirs improve-

ment are shown in table below. Improvement

was computed as {M68HC11 clock periods}

divided by {DF6811 clock periods} required to

execute an identical function. More details are

available in core documentation

Function Improve-

ment

8-bit addition (immediate data)4

8-bit addition (direct addressing)4

8-bit addition (indirect addressing)4

8-bit subtraction (immedi ate data)4

8-bit subtraction (direct addressing)4

8-bit subtraction (indirect addressin g)4

16-bit addition (immediate data)4

16-bit addition (direct addressing)4

16-bit addition (indirect addr essing 4

16-bit subtraction (immediate data)4

16-bit subtraction (direct addressing)4

16-bit subtraction (indirect addressing 4

Multiplication 10

Fractional division 14,9

Integer division 16.4

DF68XX FAMILY OVERVIEW

The main features of each DF68XX family member have been summarized in table below. It gives

a briefly member characterization helping user to select the most suitable IP Core for its application.

User can specify its own peripheral set (including listed below and the others) and requests the core

modifications.

Design

Speed acceleration

Physical Linear mem-

ory space

Paged Data Memory

space

Motorola Memory Ex-

pansion Logic

Interrupt sources

Interrupt levels

Real Time Interrupt

Data Pointers

READY for Prg. and

Data memories

Compare\Capture

Main Timer System

SCI (UART)

I\O Ports

SPI M/S Interface

Watchdog Timer

Pulse accumulator

Interface for

additional SFRs

DoCD Debugger

Size – ASIC gates

DF6805 4.1 64k 64k - 7 7 - - * 2/2* 1* *4+ *-6 700

DF6808 3.2 64k 64k - 7 7 - - * 2/2* 1* *4*-8 900

DF6811 4.4 64k 16M - 20 17 1* * 5/3* 1* *4*** 12 000

DF6811CPU 4.4 64k 16M - 3 3 + 1* * + + + + + + + 6 500

DF68XX family of High Performance Microcontro ller Cores

+ optional

* configurable

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CONTACTS

For any modification or special request

please contact to Digital Core Design or local

distributors.

Headquarters:

Wroclawska 94

41-902 Bytom, POLAND

e-mail: i

tel. : +48 32 282 82 66

fax : +48 32 282 74 37

Distributors:

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