MC6802 MC6808 MC6802NS MICROPROCESSOR The MC6802 registers WITH CLOCK AND OPTIONAL RAM is a monolithic and accumulators 8-bit microprocessor of the present MC~OO that contains all the plus an internal clock oscillator and driver on the same chip. In addition, the MCW02 has 128 bytes of on-board RAM located at hex addresses $~ to $O07F. The first 32 bytes of RAM, at hex addresses $~ to $001 F, may be retained in a low power mode by utilizing VCC standby; thus, facilitating memory ietention during a power-down situation. The MC6802 is completely software compatible with the MC68W as well as the entire M~W family of parts. Hence, the MC6802 is expand- ..,,....,., t..>i able to WK words. The MC6802NS is identical to the MC6802 without standby RAM feature. The MC6808 is identical to the MC6802 without on-board RAM, On-Chip Clock 128x8 Circuit Bit On-Chip 32 Bytes of RAM Software-Compatible Expandable Standard 8-Bit . 16-8it with the MC68~ to 64K Words TTL-Compatible Word Inputs and Outputs Size Memory Interrupt RAM are Retainable Addressing ~>,,~ ;\J: .!$ ;~,~: ~\R,!. t *$\i, `$. ~.~., $\iM ~..;,, , ,W ..,~$!,`~ .,, ... ~.~:;, `>~. ,? .*..:Xl~,o,, .f+$.t,,. *$,, .1,>,, ~,.t..~.$ ~:t<y:i "..> ,.,.. ,, ,,.,)? ,$$.!., .,. ..\,.\.\, +$;, ,{, ~.$>&, . ,,:.4,.,~.> .:s$.. ,..b ~ >l,i,y. ,,\\, `J.i:..$ > ~y$ ,' ... ~./,, .,,.,{+? ,, " `,{$;:,?.:$: ~s.q, ~~,i$~ .,,. a:.,,3,, ,~,i , ..>.,', ~~ .:> ,\\.)t. ~' ,,.,,a,+:>., `~,.-' .~,~ ?;:<, \%:>t `...f$,+ ~J: ,.KK,*? ~,,, !::,, ;.!,, .,J~ ~.?., ,..,. ,,~t~r.tc ,>....,..,. ~,,).$ Capability ORD&Q~,~lJjFOR ,,,$% ~~.*> Freq&&nc$@fiz) :$:f~ls$ ,,{.:. Ceramic ~:,,"v \ *?.O L Suffix ~~ ,"".NA.Jx$:i \ `:.ik 1.0 ~:<$. ., `,`$?$ 1.0 .,~;... .*:`.;::,,$ +,?.. * >?:$>l,. \ 1.5 ,if .,:\ .\:.\ a " 1.5 .,.. .,.;(>~ti~ ...% *...l..~'!:::: 1.5 ~\J., .13,, i v, ,3* ,\ t.i.v,\ 2.0 >;~j.',.]. ~~\ ., ,~,~~,.,t:; . 2.0 ~e~ti~ P Suffix 1.0 1.0 1.0 1.0 1.5 1.5 1.5 2.0 2.0 Temperature PIN ASSIGNMENT Vss[ 1. 40 )fl EsET HALT[ 2 39 ]EXTAL VR[ 3 38 ] XTAL FQ [ 4 MATION ,,:, ,,. Package Type P SUFFIX LASTIC PACKAGE CASE 711 Order Number Ooc to 70"C - 40C to 85C Ooc to 70"C O"c to 70c O"c to 70"C -40C to 85C O"c to 70c Ooc to 700c O"c to 70c M C6802L MCM02CL MC6802NSL M C6808L M C68A02L M C68A02CL MC68A08L MC68B02L MC68B08L O"c to 700c -40C to 85C Ooc to 700c Ooc to 700c Ooc to 700c -40C to 85C O"c to 70c Ooc to 700c O"c to 700c MC6802P MC6802CP M C6802N SP M C6808P MC68A02P M C68A02CP M C68A08P MC68B02P MC68B08P 37 ]E VLIA[ 5 36 ] RE** NMI[ 6 35 ] VCC BA[ 7 34 J R/~ 8 33 ] DO Vcc[ AO [ 9 32 ]Dl Al [ 10 31 ]D2 A2 [ 11 30 ] D3 A3 ~ 12 29 ] D4 A4 [ 13 28 ] D5 A5 [ 14 27 ] D6 A6 [ 15 26 ] D7 A7 [ 16 25 ]A15 A8 [ 1? 24 ]A14 A9 [ 18 23 ]A13 A1O[ 19 Standby* 22 ]A12 * pin 35 mUSt be tied to 5 V on the MC6802NS * * pin 36 must be tied to ground for the Mc6808 @MOTOROLA lNc , 1984 DS9818-R3 TYPICAL Vcc 0 Counter/ Timer Vcc M C6W6 1/0 15 ROM, 1/0, Cso Control ~ 2 k BVtes ROM 10 !/0 Lines 3 Lines Timer , Vcc 0 - ~Q - MR VMA _ RESET + HALT VMA Clock ~ ~ ~ -- ~ ~ Parallel IJO 1 Timer RESET ~ ~ MICROCOMPUTER E R 1~ - RE + -- R ` w MC6802 BA - EXTAL ~ {n AO-A1O, CPI Csl AO-A15 AO-A15 XTAL - SVmbol Input Temperature Range M C680A02, M C6802C, M C680B02 TA M C680A02C M C6802N S MC6808, Storage MC68A08, Temperature THERMAL system chip. interfacing is ~hh It is not int.~n~ be limited it be expandable the and to this,C{~~~&* with Microcomputer Resistance `**. ,"~~~' ,,$:,Th[s\,{~put ,.:\. circuitrv to protect the propriate `c logic voltage level (e.g., either VSS or VCC). ,.. \:~ \ Sy:p@&*$ (Junction contains to +7.0 - 5$,&,~&T80 ,~., $?$,,, s, Tstg Characteristic Thermal Unit o to *TO "'~ M C68B08 Range CHARACTERISTICS Average svstem is svstem "!*!KQutS against damage due to high static :&+,,,e..!:.,., v it is ad. v ~a;$$~:~~~$t~ltagesor eleCttiC fields; however, -0.3 to +7.0 ~t vised that normal precautions be taken to ,:,,\>..*' .' ~~':< *,:?IW avoid application of anv voltage higher than oto +70 -?~::~' maximum rated voltages to this high.- . impedance circuit. Reliability of operation is - 40 to + 8p<g,, t enhanced if unused inputs are tied to an apo to +,gQ<.. `!$ ,, -0.3 Vin Voltage M C6802, Value Vcc Voltage Operating microcomputer combination this cost ef- MPU \,<J*, *Ri.!~$.>, ~> RATINGS Rating SupplV in a minimum a typical The ot@r `~@&ln \ *\*:, faml$~,tts$j:{$iW \*.SS::[.:,j.:. .+.. *T ...,.~i., ~l!,:l!, ,~ \\J, `> .,)...,t;+: ,.: ~~:: i.., ~: \:,q::,$q?>:J,f t,:$ .~.!.. ~.:... ,. ,$.~ i,<>, \,Ii\. .>,$.,`&? ` i. ., \,*i.,!,.,,. .,,,~~:,!, -...2:.p., ,',> *.>\) lit. `~.' ,., .f:~s,,)W ` $~: *ii," ~'~?l~. ,, `*K>+.}! -- MAXIMUM shown the M6800 o CP2 of the but that DO-D7 DO-D7 center that shows microcomputer. a ROM ml MPU DO-D7 This block diagram fective Value Unit to Ambient) Plastic Ceramic ,//, .*,., ~, ~,.<.}: ~~, ,.:~ :1, ,,,..,~$. `$~:::,,t,. , ~$' ,,!, .,.,.,. , ~,~ .... ,,.~.$) :* :., "~v~,. ,i,. The average chip-juncti~~%p~rature, TJ = TA+ (pD.Q$A) `?~~$ POWER TJ, CONSIDERATIONS in `C can be obtained from: (1) ,Jj:.:'~$+ *]~?{i>, ` .t!i~. Where: ~:~,~$"%~ient ~~~~~Package Temperature, Thermal `C Resistance, Junction-to-Ambient, OC/W ,\@F$~2$\m= plNT+ pPORT t "PINT= ICC x Vcc, Watts - Chip Internal Power ~?~:~,<$, ....-.\\,!;)$ ,T~~, ;h'""" PpORT= Port Power Dissipation, Watts - User Determined ~,$:.,, , !<~,(p ,..' .+,. < PPORT may become $~{,~ost applications pPORT@ PINT and can be neglected. dr$~ ~arlington bases or sink LED loads, ~::: ~ ~n approximate PD= Solving K: relationship between PD and TJ (if PpORT is neglected) significant if the device to is: (TJ +273C) equations is configured (2) 1 and 2 for K gives: K= PD*(TA+2730C) +OJA*PD2 (3) Where K is a constant pertaining to the particular part. K can be determined for a known TA. Using this value of K the values of PD and TJ can be obtained value of TA, from equation 3 by measuring PD (at equilibrium) by solving equations (1) and (2) iteratively for any Semiconductor 2 Products Inc. DC ELECTRICAL CHARACTERISTICS I (Vcr = 5.0 Vdc f 5%, VSR = 0, TA = O to 70"C, Characteristic I Logic, Input High Voltage Input Low Voltage Input Leakage Output unless Svmb RESET Logic, Current (Vin =0 to 5.25 V, VCC= EXTAL, Max I Unit I I v~~ I - ,, Vcc=min) (i Load= - 145wA, VCC= rein) (lLoad= - 100wA, VCC= rein) Output Low Voltage Internal Power AO-A15, (Measured VCC= at TA= E rein) OC) Power Down Power Up VCC Standby Standby VMA, Current Capacitance (Vln=O, VOH BA (lLoad = 1.6 mA, Dissipation R/~, Vss+O.8 -- -- 1.0 2.5 VSS+2.4 - -- VSS+2.4 - - Vss+2.4 - VOL - PINT -- VSBB 4.0 v PA ,+!. ..8 ISBB f=l.O DO- D7 MHz) Logic Inputs, AO-A15, CONTROL TIMING (VCC=5.O V +5%, VSS=O, TA=TL to TH, unless r R/~, Cin EXTAL VMA Cout otherwjw ri~$,j ) \?*..L MC6802 Mcmo2Ns MC6B08 Characteristics Min Frequency ~'`1:.,,,-\\ >:,.. of Operation t,) .<? `.' ,,;t..!.,:, "+$9 , ,. ,.,, s,,,. >,. .,\,,\ *!\*\*.,!.,\.!,. Frequency External Oscillator Oscillator Processor Controls Frequency Start Up Time (HALT, MR, RE, RESET, ~ ~lk,.,'wt~,. MOTOROLA " f. fXTAL 4xfo trc 0.1 5 3 v' mA pF pf MC6BA02 I MC68B02 I \ Max 1.0 1.0 4,0 1.0 I1 0.4 4.0 0.4 I 6.0 I 0.4 I 100 - lMI - 11001 200 - 140 - 110 -- Im -- T Semiconductor @ ~~$~, *,iti -- ,t:, >., .R*.@ 4.75 # TA=250C, - *$>~';25 -i. $):, -- -, ,:> "~: as B.O *Y~< *:, >,.,,.,,... .};,,:, ..*;.+,' $ ., ;~,>10 12.5 *' . ,$, .,:.,+it~:~' 6.5 10 .f, **, ,+ `.'?l~.-' -- -,.!., `:$")., 12 ` ~~~,:'.:>~j)i VSB I " LL ;s-0.3 .-- Iin DO-D7 -205pA, Crystal I t High Voltage (l Load= Crystal I TVD >> ~~u RESET Logic max) noted) Min I v~~+2.0 VIH EXTAL otherwise 01 I 6.0 I 1.0 lW I 1 8.0 1 1 Products Inc. I MHz 1 I MHz I -Ims - - I 8.0 ns Im I ns I BUS TIMING CHARACTERISTICS MC8B02 Ident. Svmbol Characteristic Number Min Max Min tcyc 0667 10 0.5 10 pWEL 450 500 280 5000 210 5000 PWEH 450 9500 280 9700 220 9700 , `A$*.'J 8+ 25 - 25 - - 20 - 20 E Low 3 Pulse Width, E H)gh 4 Clock 9 Address 12 Non- Muxed 17 Read Data Setup 18 Read Data Hold Tme 19 Write Data Delay Tme 21 Write Data Hold Time* tDH~V 29 Usable and data :~, {f Rise and Fall Time Hold T{me* hold times to E (See Nate 5) Time tested rather than FIGURE 24? ps n~>,, "?{. ~:~$i? ,t:,'''%$~:i$is 20 iAVl tAv2 160 - lm - 270 - - 50$:` $$~~t ~ ..&.$;$i$,.rlj>i ~,.. "s - tDSR 100 - 70 ~:t ,<;~@ " - ns IDHR 10 - 10 tDDW - 225 30 - 1000/o tested 2 - Max tAH tACC T:me (See No!e 41 are periodically Unit 10 Pulse Width, *Address MC8BB08 Max 2 Valid Tme MC6BB02 MC68A08 10 Cvcle Time Access MC6B08 MC6BA02 Min 1 Address MC6802NS .$, - "?.;>i~'1o -.+~ :1,70 a,+ :YQ:::~:': ~,* *k$2Q~' \ ~,, *, `+:$..%;%~: .,;$l:~ ..... ....,~~~,t .~+.,.,. ,$. $\.* *,4,. , ,,~:t. ,.,-.. .,,. }'<.,f::y>x~,.+:?. Yt> %...rh$:<>~. ,..:., 535 - - - 160 "s ns 20 _ ns 235 - ns BUS TIMl NGm4e `$)?iwe~? ,;*., .:.-,.i.,,<,.~ E -- R/~, Address (Non- Muxed) Read Data Non-Muxed , Write Data Non- Muxed NOTES: ,*i: ~ ~: ~{ `f' 1. ~@&~~<Wvels ,.,,,\,, shown z,~~$<ufement **~,$$..\ . ~ji~~~.~lectricals points shown shown for the MCN02 4.''& sable access are VLSO.4 V, VH z2,4 V, unless otherwise are 0.8 V and 2.0 V, unless otherwise time is computed apply to the MCM02NS bv: 12+ 3+4- specified. noted. and MC~08, unless otherwise noted. 17. 5. If programs are not executed from on-board RAM, TAV1 applies. If programs are to be stored and executed from on-board RAM, TAV2 applies. For normal data storage in the on-board RAM, this extended delav does not apply. Programs cannot be executed from on-board RAM when using A and B parts (M C68A02, MCMA08, MC~B02, MC68B08). On-board RAM can be used for data storage with all parts 6. All electrical and control characteristics are referenced from: TL=OOC minimum and TH = 70C maximum. .. MOTOROLA Semiconductor 4 Products Inc. FIGURE 3 - BUS TIMING TEST LOAD 4.75 v ? C= 130 pF for DO-D7, E =W pF for AO-A15, R/~, and VMA =30 pF for BA R= 11.7 k~ for DO-D7, E = 16.5 kQ for AO-A15, R/~, and VMA =24 kQ for BA FIGURE 4 - TYPICAL DATA BUS OUTPUT DELAY versus CAPACITIVE LOADING 600 I I I I - lo H=-205@max@2.4v lo L=l,6mAmax@0.4V 500 -VCC=50V - TA = 25C ~ 5 u z G > 400 300 a d 0 200 / 100 CL fncludesstrav o 200 100 0 CL, LOAD 400 300 CAPACITANCE capacitance 500 600 (PF) I ..::\ . FIGURE 6 - EXPANd%@:~*OCK A15 A14 A13 A12 25 24 23 22 All 2SX AlQ,.+ A~w' 19"'" 18 DIAGRAM A8 A7 A6 A5 A4 A3 A2 Al 17 16 15 14 13 12 11 10 AO 9 i L m36 `AMEnab'e : =A35 : I `Ccstandb, Instruction Register VCC= Pin 8 Vcc= Pin 35 for VSS=Pins VSS= I ~ m m MCW02NS 1, 21 P\n 36 for MC~08 26 27 28 29 30 31 32 33 D? D6 D5 D4 D3 D2 DI DO MOTOROLA Semiconductor 5 Products Inc. I MPU REGISTERS -- read/write memory that may A general block diagram of the MCW02 is shown in Figure 6. As shown, the number and configuration of the registers that is convenient. are the same as for the MCWOO. The 128x 8-bit RAM* has been added to the basic MPU. The first 32 bytes can be re- of information in the stack must be non-volatile. In those have any applications when location (address) that require power is lost, storage the stack tained during power-up and power-down conditions via the RE signal. The MC6802NS is identical to the MC6802 except for the standby feature on the first 32 bytes of RAM, The standby feature does not exist on the must be tied to 5 V. The MC6808 is identical MC6802NS to the and thus MC6802 except pin 35 for on- board RAM. Since the MC6808 does not have on-board RAM pin 36 must be tied to ground allowing the processor to utilize up to WK bytes of external memory. The MPU has three 16-bit registers and three 8-bit registers available for use by the programmer (Figure 7). PROGRAM The points STACK CONDITION program counter is a two program byte (16-bit) register that Overflow address. pointer down/pop-up stack. is a two available byte register location that contains in an external This stack is normally a random the diti~p are not executed plies. For normal when using from data storage A and B parts on-board in the on-board (M C68A02, RAM, TAVI RAM, MC68A08, this extended MC68B02, ,~d Register ,$&?~Ju~~Within access applies. ?&$e (b6 and .+@~ure 8 shows push- bit 3 the b7) are ones. order of saving the microprocessor the stack. :*\i :!:.,$!ti,.~$:>.~r.& i ~.. `If programs (V), ,Q#'~~y,frorn bit 7 (C), and Half Carry from (H). These,~i+~+~~~fle Condition Code Register are used as testable .$d$dit]pns for the conditional branch instructions. Bit 4 is.$'@~@Y@rupt mask bit (1), The unused bits of the Con- POINTER of the next REq{$FEF CODE The condition cq~#:~t~]M~er indicates the results of an Arithmetic Logic U*#~~&~eration: Negative (N), Zero (Z), COUNTER to the current The stack address (ALU). .- If b~-s are to be stored dela~does not apply. M&68 B08). On-board and executed Programs RAM cannot from on-board be executed from can be used for data storage RAM, TAV2 on-board with apRAM -- all parts. UNIT I lx ] 15 Register Index 0 Pc Program 15 Counter 0 SP Stack 7 Pointer 0 Condition Codes Register Carry (From eit 7) Overflow Zero ~ Half Carry (From Semiconductor @ 6 . Bit 3) Products Inc. FIGURE8- SAVING THE STATUS OF THE MICROPROCESSOR IN THE STACK m-9 H SP = Stack I I 1' I b Pointer CC = Condition Codes ACCB = Accumulator B ACCA = Accumulator A (AI= called the Proce$sor IX H = I ndex Register, Higher Order B Bits I XL Register, Lower Order B Bits = Index PCH = Program Counter, Higher Order 8 Bits PCL = Program Counter, Lower Order B Bits Status Byte! m-2 m -1 m m+l m+2 ---- H- MPU SIGNAL ., .:;.,. .. .iJ.\ .,..:,.>, Proper operation and timing signals of the MPU requires that certain control be provided to accomplish specific func- tions and that other signal lines be monitored to determine the state of the processor. These control and timing signals are similar to those of the MCM~ except that TSC, D&~, ~1, 42 input, and two unused and the following signal RAM Enable (RE) VCC Standby +2 Output The following have been elimin~td~:w the HALT line must go high for one clock cycle. HALT should be tied high if mt used. This and timing Crystal Connections EXTAL Memory Ready (MR) Enable pins , ~~on~ bus available will be at a high state, valid memory .,~+,ws will beat a low state. The address bus will display `%~~'*LEddress of the next instruction. ,.. operation, transition of ,f~, ~ -- To ensure single instruction HALT line must occur tpcs before the falling edge of E (E) is a summary lines have been ~*~Q: .~,4,.: ` +$\. \ .>::~,,,.1:, ~' ~::\>$.(.,f:l> and XTAL > qk$~i., "*F .:+>.~ ,,>>!.,L,k \ ,f,$:, *;>, ,>L~,,, \ +&,`? `$+::+,>,. .,,. ,t:,'f.'>!.:l.+.;'>~" .,., of the?~,P~ signals: `,~~ * \?.:t,.,,. ` :\J .ici'. /?.~.~, engineering design sure proper operation READ/WRITE This memory practice in general adthe the and is good and necessary to en- of the part. (R/~) TTL-compatible devices whether output signals the peripherals the MPU is in a read (high) and or write Sixteen pins are used for t%~a~dress bus. The outputs are capable of driving one >a~~dar&TTL load and 90 pF, These (low) state. The normal standby state of this signal is read (high). When the processor is halted, it will be in the read state. This output is capable of dtiving one standard TTL load and 90 pF. lines do not have thr~~k~t~?capability. ~. :,.$ .:.!},.. !:\. ,,,, VALID ADDRESS DATA BUS (AO-A15) .,, ,~,,:$t <r..,,,.,, ~ BUS (DO@p MEMORY ADDRESS (VMA) This output indicates to peripheral devices that there is a valid address on the address bus, In normal operation, this signal should be utilized for enabling peripheral interfaces Eight pins,~~ti~d for the data bus. It is bidirectional, transferrin~~da~$?{o and from the memory and peripheral devicest~~$ `{w has three-state output buffers capable of such as the PIA and AC IA. This signal is not three-state. One standard TTL load and 90 pF may be directly driven by this active high signal. drivin~!~~~tandard TTL load and 130 pF. D~~J$~s will be in the output mode when the internal RA~$~s accessed and RE will be high. This prohibits external data entering the MPU. It should be noted that the internal RAM is fully decoded from $~ to $W7F. External RAM at is ac- BUS AVAILABLE (BA) - The bus available signal will normally be in the low state; when activated, it will go to the high state indicating that the microprocessor has stopped and that the address bus is available (but not in a three-state condition). This will occur if the ~ line is in the low state HALT or the processor When this input is in the low state, all activity in the machine will be halted. This input is level sensitive, In the HALT mode, the machine will stop at the end of an instruc- tion of a WAIT instruction. At such time, all three-state output drivers will go to their off-state and other outputs to their normally inactive level. The processor is removed from the $~0 to $W7F cessed. must be disabled when internal RAM MOTOROLA Semiconductor @ 7 is in the WAIT state as a result of the execu- Products Inc. I WAIT state by the occurrence or nonmaskable one standard INTERRUPT interrupt. TTL of a maskable This output (mask bit I = O) is capable tion of a routine to initialize the processor from its reset condition. All the higher order address lines will be forced high. For the restart, the last two ($ FFFE, $FFFF) locations in of driving load and 30 pF. REQUEST memory will be used to load the program by the program counter. During the restart (~Q) before mask it recognizes the request. bit in the condition code down sequences are shown in Figures 9 and 10, res~~~~:ly. RESET, when brought low, must be held low~$~~~~~ttiree clock cycles. This allows adequate time to res~:~:~;t$ternally to the reset. This is independent of the tk~~pb~~?-up reset At that time, if the register is not set, the machine will begin an interrupt sequence. The index register, program counter, accumulators, and condition code register are stored away on the stack. Next the MPU will respond to the interrupt request by setting the interrupt mask bit high so that no further interrupts end of the cycle, a 16-bit vectoring in memory locations $FFF8 and may occur. high threshold without bouncing{JF@~/~f~$?ng, or otherwise causing an erroneous reset (less ?k~:~~three clock cycles). This may cause improper MPmu~era~lon until the next valid At the address which is located $FFF9 is loaded which reset. causes the MPU to branch to an interrupt routine in memory. The HALT line must be in the high state for interrupts to be serviced. is low, A nominal Interrupts will be latched 3 k~ pullup resistor wire-OR and optimum control directly to VCC if not used. internally while to VCC should of interrupts. NON-MASKABLE (NMI) ,}.,.,*.;S!,5 `*8S input requests that a nonbe generated within the pro- cessor. As .w~~%:i{*@tnterrupt request signal, the processor will compl~e ?%J#current instruction that is being executed before i~~?q~~~~~zes the NM I signal, The interrupt mask bit in may be tied the con~~~on code register has no effect on NMI. ~Xfi+e,in~~x register, program counter, accumulators, RESET This lNT<KN&T A low-going ed~b$:+~~}this maskable interr,~~~ se@ence HALT be used for ~Q that is addressed routine, the inter- rupt mask bit is set and must be reset before the MPU can be interrupted by ~Q. Power-up and reset timing and ~ower- A low level on this input requests that an interrupt sequence be generated within the machine. The processor will wait until it completes the current instruction that is being excuted interrupt input is used to reset and start the MPU from a power-down condition, resulting from a power failure or an initial start-up of the processor. When this line is low, the MPU is inactive and the information in the registers will be lost. If a high level is detected on the input, this will sig;al the MPU to begin the restart sequence. -- and ,,,,modwn code registers are stored away on the stack. At the address which is located ~,en'~of the cycle, a 16-bit vectoring .\;\).~<s:, ,., ~.?wmemory locations $FFFC and $FFFD is loaded causing the ,:.~i,~, 1,,.\%:,, *{~j;:'+MPU to branch to an interrupt service routine in memory. ,. +, A nominal 3 k~ pullup resistor to VCC should be used for .\.,~ wire-OR This will start eKwu$~*:$)t:.,> "*'!. ..... and optimum control of interrupts. ml may be tied Vcc E RESET I (See Note Below) Option 2 (See Figure 10 for Power-down Condition) RE .- * NOTE: If option 1 is chosen, RESET and RE pins can be tied together MOTOROLA Semiconductor 8 Products Inc. FIGURE 10 - POWER-DOWN to VCC if not used. Inputs ~Q and NM I are hardware interrupt lines that are sampled when E is high and will start the interrupt routine on directly a low E following the completion of an instruction. Figure 11 is a flowchart describing the major paths and interrupt vectors of the microprocessor. gives the memory map for interrupt decision Table 1 `CC7 vectors TABLE 1 - MEMORY MAP FOR INTERRUPT VECTORS Vector MS LS Description Restart $FFFE $FFFF $FFFC $FFFD Non-Maskable $FFFA $FFFB Software Interrupt $FFF8 $FFF9 Interrupt Request Interrupt 1 FIGURE 1 Execute Interrupt Routine I ,V, Execute Instruction Bb NM I $FFFC $FFFD + MOTOROLA @ Semiconductor 9 TQ $FFF8 $FFF9 Products Inc. SEQUENCE I a m FIGURE 12 - CRYSTAL SPECIFICATIONS 38 39 n , 1 coutT AA " -. T , I Cin Crystal Loading ---- ---- -- --. ---- -- -- , ~! `These Crystals are representative of other types +$~cut parallel resonance crystal parameters only. ~~ cR% may also be used. and 39 Pin -. m MOTOROLA Semiconductor 10 Products FIGURE14- MEMORY READY SYNCHRONIZATION r 4xfo Oscillator I u The tpcs setup E will be stretched The E clock will resume is referenced asserted. normal to transitions There is no direct operation at the end of the fi cycle during of E were it not stretched. means of determining If tpcs when MOTOROLA @ setup the tpcs which MR assertion time is not met, references occur, unless Semiconductor 11 meets the tpcs E will fail at the second setup time, The tpcs possible the svnchron!zing transition circuit is in in- setup time time after MR is of Figure Products Inc. time 14 is used. I RAM ENABLE (RE - A TTL-compatible MC8B02+ MC6802NS RAM enable input RAM of the MC~02. When placed chip memory is enabled to respond the low state, RAM is disabled. to disable reading and writing power-down situation. RAM MPU INSTRUCTION ONLY) controls SET ... the on-chip The instruction in the high state, the onto the MPU controls. In set has 72 different are binary and decimal store, conditional or This pin may also be utilized the on-chip RAM during a Enable must be low three instructions. Included arithmetic, logical, shift, rotate, unconditional branch, interrupt stack manipulation instructions (Tables 2 through struction set is the same as that for the MC68~. load, and 6). The in- cycles before VCC goes below 4.75 V during power-down. RAM enable must be tied low on the MC6808. RE should be tied to the correct high or low state if not used. EXTAL AND These XTAL inputs are used for the internal be crystal controlled. resonant fundamental divide-by-four circuit oscillator that may There are seven address These connections are for a parallel crystal (see Figure 12). (AT-cut. ) A has been added so a 4 MHz crystal may grammer, four times the required be grounded. An RC network source E clock frequency. on pins 38and directly usable 39. An RC network frequency than tpW@L. dynamic clock The is used, MC6802, parts except external clock MEMORY of 1 MHz, @%l#iWes as a frequency for the internal to retain READY it may not be halted MC6808 and RAM, are and require the information. (MR) MR is a TTL-compatible input signal `:~..\ DIRECT allows in- These used. This is necessary to ens~e ~[d~er operation of the ,:) part, A maximum stretch is,,J@~#}<:,* ~..5+, ;$ \.::.i,,a!j~ ~i,t.. ~~t}+ ENABLE (E) .,*,, ~,, This pin supplies t~d:'~f$@for the MPU and the rest of the addressing, VCC ~$#ti$BY ~m}~h RA~*as retention be connected Direct the lowest is containaddressing 256 bytes in the 255. Enhanced execu- instructions. ADDRESSING addressing, the address contained in the se- is used as the higher eight bits of the address of the operand. The third byte of the instruction is used as the lower eight bits of the address for the operand. This is an absolute address in memory. These are three-byte of instructions. ONLY) ADDRESSING In indexed addressing, the address contained in the second byte of the instruction is added to the index register's lowest eight bits in the MPU. The carry is then added to the higher order eight bits of the index register. This result is then used to address memory. The modified address is held in a temporary address register so there is no change to the index register. These are two-byte instructions. to VCC. MOTOROLA address zero through cond byte of the instruction supplies the dc voltage to the first 32 bytes of well as the RAM Enable (RE) control logic. Thus, of data in this portion of the RAM on a power-up, pin must of the operand of the instruction. locations are two-byte In extended power-down, or standby condition is guaranteed. Maximum current drain at VSB maximum is ISBB, For the MC~02NS this i.e., INDEXED (MC6802 the address byte the user to directly EXTENDED system. This is a,,~~,$:-:~flase, TTL-compatible clock. This clock may be c~~'~~,ofled by a memory read signal. This is is capable A or instructions. tion times are achieved by storing data in these locations. In most configurations, it should be a random-access memory. tegral numbers of half periods, thus ,+J:o%n~ interface to slow memories. Memory Ready timi~'%'%~n in Figure 15. MR should be tied high (connect.~d~~ctly to VCC) if not `the MC6800. This output TTL load and 130 pF. accumulator ADDRESSING In direct machine, equivalent to~.~~~~ driving o:~'*~t~@ard .:Ji:)./!;}).\,,$( either These are one-byte `*'$'}*Yuction. The MPU addresses this location when it fetches ..:J<,K .,.'-. ~!ip,;.....*+?.\ .!,, the immediate instruction for execution. These are two- or `NJ three-byte instructions. d: .,? $<.,. , ,.:), ,i?~:l `.'i'~,+,~ controllin~f%~@t- E wj{:~~%~~~tched be microseconds. ,~$~~j,rnm~diate addressing, the operand is contained in the $j-,o~ti byte of the instruction except LDS and LDX which $!.ha~ the operand in the second and third bytes of the in- normal M R is low, instruction With a bus IMME4:TEADDRESSING ed in the second When the ?:+ ching of E. Use of M R requires synchronization $~~t~@4xfo signal, as shown in Figure 14. When MR is hi~$~~?,@]l be in operation. addressing, accumulat@#r~~A3@ pacified. for more MC6802NS by a proof both ADDRESSING In accumuld~/~&/y type TTL or CMOS would .,,.,,, $,>.. `.~,,.., ,,,,,..$:,~: Pin 38 is to oscillator will work well as long as the TTL or CMOS output drives the on-chip oscillator. LC networks are not recommended to be used in place of the crystal. If an external thak<~~$ w~sed mo~&:~*~#tion can be found in Table 7 alo~$~w the associated execution time that is ~J~$~''f#$machine cycles. ACCUMULATO~k(A~X) is not modes the addressing type of instruction and the codin~~i,t,~in the instruction. A summary of the addressing rn~h@~sfoP'a particular instruction be used in lieu of a 1 MHz crystal for a more cost-effective system. An example of the crystal circuit layout is shown in Figure 13. Pin 39 may be driven externally by a TTL input signal with Semiconductor @ 12 Products Inc. ~ IMPLIED byte of the instruction is added to the program counter's lowest eight bits plus two. The carry or borrow is then added ADDRESSING addressing mode, address (i. e., stack pointer, one-byte instructions. In the implied index the instruction register, etc.). gives the These to the high eight bits. This allows the user to address data within a range of - 125 to + 129 bytes of the present instruc- are tion. RELATIVE These are two-byte instructions. ADDRESSING In relative addressing, the address contained ABA ADC ADD AND ASL ASR Add Accumulators Add with Carry Add Lqical And Arithmetic Shift Left ArithmetK Shfi Right BCC BCS BEQ BGE BGT BHI BIT BLE BLS BLT BMI BNE BPL BRA BSR BVC BVS Branch if Carry Clear Branch if Carry Set Branch if Equal to Zero Branch if Greater or Equal Zero Brawh if Greater than Zero Bra~h if Higher Bit Test Bra~h t Less or Equal Branch if Lower or Same Branch if Less than Zero Brawh f Minus Brawh f Not Equal to Zero Bramh if Pfus Bra~h Always Brawh to Subroutine Brawh f Ovetilow Clear Branch if Overflow Set ,*!* in the second CLR CLV CMP COM CPX Clear Ovetilow Compare Complement Compare Index Register DAA DEC DES DEX Decimal Adjust Decrement Decrement Stack Pointer Decrement Itiex Register EOR Exclusive OR INC INS INX $~$~~,} ,$:~EW' "%&A ,$ Increment ~....;\..:.. STS Increment Stack Pointer~' `~"::~}STX Increment Index Re@T&:tt SUB JMP JSR LDA LDS LDX LSR .t$...)'j,,,, .$. Rotate $#:\$~~ Rotate~~!@t,"+ Retu~?Wfnterrupt R~w:,&@rn Subroutine ~+ ~~lx, SBA ..*:gubtr'&t Accumulators SBC,, ~dtitract with CarV SE@~*'!I, *&et Car~ ROL ROR RTI RTS Load St@k P&hter NEG NOP CBA CLC CLI MOTOROLA Swl Set Interrupt Mask Set Overflow Store Accumulator Store Stack Register Store Index Register Subtract Software Interrupt TAB TAP TBA TPA TST TSX Txs Transfer Transfer Transfer Transfer Test Transfer Transfer WAI Wait for Interrupt Semiconductor @ 13 Accumulators Accumulators to Condition Code Reg. Accumulators Condition Code Reg. to Accumulator Stack Pointer to Index Register Idex Register to Stack Pointer Products Inc. 1 TABLE3- ACCUMULATOR AND MEMORY INSTRUCTIONS -.. ADDRESSING IMMED MNEMONIC OPERATIONS kdd Add Carry INOEX 1P-= (All OP. A.M. ADD8 8+M. A8A A.E ADCA A- M+C. AOC8 B+ 5 labels 10 Co"tenlsl B r : : M+CB j A A A * B . . BITB a.bl . .: ! CLR 00 M 0, d~. ! CLRA 00 A F e, *: *: * lee, r"dl Adl"sl, Jecre("er, COMA . . COMB 9 . NEG . NEGA . . NEGB * DAA . . DEC * OECA . . DEC8 * EORA . . EORB .* INC . INCA . . INCB * LOAA .* LDAB . . ORAA . . ORAB . . PSHA . . A t s,.e OR ,Icre,,,erll Acmltr III CI.SIVP Data Dala PSH B . . . . PULB . ROL . ROLA ROLB . . ROR . . RORA . . RORB ASL . . ASLA * . . Rtght Ar, th("el, c AsLa jh, ft R,ght, Sht7R, Ar, th,net, ght, c ASR 27163 2' LogIc 7463 A 0-[13'11!1 bl B 1 2~B753 A STAB 2F753 B SU8A 2~B043 A SUEB 2iFOC3 8M. SBA I ABA S8CA 2B243 A 2F243 8 L S6 CB TAB TEA 27063 TST TSTA TSTB + MSP Note -n bO M P,l A !,1 Code Number of MPU N"(nber of Proqra,n Arlthmet(c PI"S Ar, fhmel(c M,,,.,, 8oolea(I AND cO.te,~lS .t - Acc",n"la!or + Boolean Inclus,ve ~ Bo.learl Exclus, m Cotnple,"e"t IHexadetl(nall, Cycles, memo.f Bytes, IoCat,o<l addressing mode oo,. !ed to be Slack ,Ils!r"ct,ons aft . . ., .,1 . . . . . . . * . . * B . . B A . . . . A-DO . B-00 . . MCB !A 00 HIP i COOE SVMBOLS OR H ve OR, 01 M, Hall ,a,,y {("m b,r 3, mask l"l~,<"pl N Negal, "e (s,gn bdtl BI1 = Zero, z Zero 00 Byte v overflow, c Carry R Reset Albvays s Set Always = zero, Po(r>ter, addressing lbyte) 2's complement from TeSI and stl . MOTOROLA C A Tra,, sfe< Into, IMP LIEO . . o ,ncl,, ded t,, the COIL,,I)II for 9 e E CONOITION 0Ptr210n C P,l Semiconductor 14 No! b,t 7 f lrue, cleared olherw, se Affected Products .- e A LEG ENO. OP . PU LA LefI jh, ft Left, 2's Negate) ~ CBA 1's Cornplen>erll, ?ota:e $$, x CMPB COM ActIBltrs Co,.plernen(, ?ola!e ; CMPA Cot,,oare J"II . 8.M CLR8 `"sh 0 A!ti. Co mpafe lr, I : A AM Clear Load 4 H BITA 311 Test Excl. :ONO. AND8 ANDA 4nd OPERAT!ON register refer = ADDA A,mlrrs 4ddw,lh BOOLEAN/ARITHMETIC IES MC Inc. - I I TABLE 4 - INDEX REGISTER AND STACK MANIPULATION INSTRUCTIONS CONO, II POINTER MNEMONIC OPERATIONS Compare Index lleg Decrement Index Reg DEX Stack Pntr OES Increment Irldex Reg INx Irlcrement Stack Pntr INS Load Index Reg Load Stack 3 8E 3 LoS Reg ST X Store Stack Pntr STS Irldx Reg Stack . lrldx Prltr Pntr TXS Rea TSX I T CE Pntr Stack F LOX Irldex Store = OP CPX Decrement o IE( ME -- 3 -- OP 9C -- 4 -- . Y lNOEX EXTNO -- I OP-= OP -- 3 DE 4 2 EE 62 FE 5 3 3 9E 4 2 BE 5 3 5 2 AE T EF 62 DF 1 `2 FF 6 3 9F 5 2 AF 7 BF 6 3 -- -- 2 Ifi BOOLEAN/Arithmetic -- -- 09 4 34 4 08 4 31 4 35 4 30 -- 4 -- OPERATION H CO ND. RELATIVE -- INOEX EXTNO I N COOE T T --T T I H N -- z -- -- -- IMPLIEO -- -- COOE m `LIED < y AC62 -- Z REG V C REG. 10 If <Zero 20 N@V=l 9 Branchlf M!nus 2B N=l Branchlf Not Equal Zero 26 2=0 If Overflow Clear 2B Set * T * * # OPERATIONS MNEMONIC OP -- Branch Always 20 None Branch If Carry Clear 24 C=o 0 Branch Ii Carry Set 25 C=l Branch If = Zero 27 2=1 Branch If >Zero 2C N@V=O Branch II > Zero 2E z+[N@V)=O 22 C+z=o 2F Z+(N@V)=l C+z=l Branchlf Branch Higher If <Zero Branchlf Branch Lowr Or&me 23 J? Branch If Ovetilow 29 V=o V=l Branch If Plus 2A N=o Branch To Subroutine 80 Branch Jump Jump To Subroutine 9 No Operalion From Interrupt Return From Subroutine Operations (Figure 16) 3 01 Return MftWre See Special 3 Advances Prog, Cntr. Only -- 3B Wait fOr Interrupt -- m MOTOROLA -- See Special 3E Semiconductor 15 Operations (Figure 16) Products Inc. -- * * , O * * * * * * * @ ,0 !-- L 1** 39 3F Interrupt 6 Vc 1* 9* * -- I FIGURE 16 - SPECIAL OPERATIONS SPECIAL OPERATIONS JSR, JUMP TO SUBROUTINE: Main ,-- Pc Program Stack 1P + --- SP-2 [n+2] SP-1 [.+21 L H Ha"d["+2]LFormn+2 SP `K = 8-Bit Unsigned [.+2] Value ~ Main Program ~ n EXTND [ BSR, + "+1 SP- 1 SP TO MaIn 80 "+1 * "+2 RTI, L + Main SP-- 1 SP Instr 7- Bit Signed FROM Stack SP-2 K = Offset' FROM RETURN & Program = BSR Next H `K= RETURN [.+3] SUBROUTINE: n RTS, [n+3]H H "+3 ~ JUMP: Stack SP-2 "+2 BRANCH JMP, H ,1+2 Value; H Formed [n+2] H [n+21 L From [n+2] Hand [n+2]L SUBROUTINE: --. INTERRUPT: ,.j& Stack `:* 1 I Condltlon Code 1 H Acmllr Acmltr I B A Index Reql$Ier(XH) Index Register pCH pCL .+.?> . .?..'?':*',)* TABLE 6 - CONDITION `$?.,, `,,*,t-* ,,:,,.. **1 ,,,. CODE REGISTER MANIPULATION INSTRUCTIONS CO ND. ,t..i. IMPLIED OPERATIONS MNEMONIC OP - = BOOLEAN OPERATION CO OEREG 5 4 3 2 1 0 H I N z v c CLC Oc 2 1 0 -c * R CLI OE 2 1 0-1 R Clear Overflow CLV DA 2 1 o-v Set Carry SEC 00 2 I 1-. SEI OF 2 1 1 1 Set Ouerflow SEV OB 2 1 1 Acmltr TAP 06 2 1 A-CCR TPA 07 2 1 CCR Clear Carry Clear Interrupl &t Interrupt Mask Mask A+CCR CCR -+ Acmltr A CO NO ITION CODE REGISTER NOTES: [Bltsel C 9 R s s . s I9 -*V ftest[st --@-- o -,A rueandc 1 (Bit Vl Test Result =lOOOOOOOq 7 (Bit (B!t Cl Test Result #OOOOOOOO~ 8 (Bit V) Test: 2'scomplement 3 (Bit C) Test Decimal 9 (B!t N) Test: (Not cleared 10 (All) 4 (Bit V) Test: Operand =10000 11 (Bit 5 (Bit V) Test: Operand =Olllllll 6 (B,t V) Test: Setequalto 12 (All) ualueof most s[gnlficant If prevlouslv BCD Character greater than rl!ne~ set ) OOOprior toexecut(on? pr!ortoexecut[on? result of N@ Caftershdt hasoccurred MOTOROLA Test: Sign bat of most significant 16 (MS) from bvte = 1? subtracttonof MS bvtes~ Code Register from Stack. (See Special Dperatlonsl Set when interrupt occurs. If previously set, a Non Maskable IS required to ex!t the wait state Interrupt Set accordjng Semiconductor @ ouerflow Result less than zero7(Blt15=l) Load Condlt!on 1) .1. learedotherw(se) 2 N) I* to the contents of Accumulator Producfs Inc. A. .- TABLE 7 - INSTRUCTION ADDRESSING ,-. MODES AND ASSOCIATED EXECUTION . . .,. - ., MachineCycle) TIMES ( I Imes In ABA ADC ADD AND ASL ASR BCC BCS BEA BGE BGT BHI BIT BLE BLS BLT BM I BNE BPL BRA BSR BVC BVS CBA CLC CLI CLR CLV CMP COM CPX DAA DEC DES DEX EOR xc X* x 20 2 : : 2345. 2345, .67.. ..67.. **** **9* 9009 ;. 2 :*O . . . ***e* ****e 9 X* ; ;45, e***@ ***o *e *a*** ***** **** ee e. 9*9** *e* . . 2oe . ***** ***** ., 4 4 4 4 4 4 . 4 4 4 4 4 4 4 8 4 4 2* 2. 2, **** *9** 670 ,.* Swl TAB TAP TBA TPA TST TSX TSX WAI *9** **** .* *** **** oe** 12 2 2 2 2 2..67 **** ***O *9** : 4 9 NOTE MOTOROLA @ Semiconductor 17 Products Inc. I SUMMARY OF CYCLE-BY-CYCLE OPERATION -. Table 8 provides present a detailed on the address description of the information bus, data bus, v@id memory as the control program is executed. The information categorized in groups according to addressing modes address line (VMA), and the read/write line (R/W) during each cycle for each instruction. This information is useful in compating actual with expetted results during debug of both software and hardware ADC ADD AND BIT CMP EOR LDA ORA SBC SUB 2 CPX LDS LDX 3 number of cycles per instruction. with the same addressing mode ecute in the same manner; (In general, instructions and number of cycles ex- exceptions are indicateq, in the "o;~k,., *;.f,~./t.,}\:R.~< ,,,,> <r, /,:.,: ,,..... J., .J'k. :<+,,\i.?:.<~ table. ) 1 1 Op Code Address 1 2 1 Op Code Address + 1 1 Op Code Address is and :3,, ` `:: Op cd%> ~. , , t/+\.\t\e,\ ~~~q~~~ta ,... ..,} ..~}:,,. ,~\ . .<,., ~~ .:.hi `*::?i:>, ~ $"` . $: s*@,., 1 $%, P Code 1 1 2 1 Op Code Address + 1 3 1 Op Code Address + 2 1 1 1 1 1 1 1 Op Code 1 1 1 1 1 1 Op Code ,$"% `Operand `:~..!$<t \ +). .~,/t',& 1, Operand ,.i.,..:~~ .\,,>\,. Data (High Order BVte) Data (Low Order Bvte) DIRECT ADC ADD AND BIT CMP EOR LDA ORA SBC SUB 2 3 3 CPX LDS LDX 4 1 1 STA I Address of Operand Operand Data Address of Operand Operand Data (High Order BVte} Operand Data (Low Order Byte) .- Op Code Destination 4 Irrelevant Address Data (Note 1) Data from Accumulator STS STX Op Code 1, `+%$YP Op Code + I 5 ,.<,: .x :.?. Address+ 1 ?O Address of Operand 1 Address of Operand 1 Address of Operand Address of Operand 0 0 Register Data (High Order BVte) Irrelevant Data (Note 1) Register Data (Low Order Byte) :,:.; INDEXED JMP 5 1 1 Op Code Address 2 1 Op Code Address + 1 3 0 Index Register 4 0 Index Register Plus Offset 1 1 Op Code Address 2 1 Op Code Address + 1 3 0 0 Index Register Index Register Plus Offset Index Register Plus Offset 4 3 1 1 1 0 Index Register 4 0 Index Register Plus Offset 5 1 1 Index Register Plus Offset 5 CPX LDS LDX 1 2 6 6 (w/o Carry) (w/o Carry) Op Code Address Op Code Address + 1 (w/o CarrV) Index Register Plus Offset + 1 MOTOROLA Semiconductor 18 --------- + 1 1 1 1 1 Offset 1 Irrelevant Data (Note 1) 1 1 1 1 Irrelevant Data (Note 1) Op Code Op Code Offset Irrelevant Data (Note 1) 1 Irrelevant Data (Note 1) 1 1 1 1 Operand Irrelevant Data (Note 1) 1 Irrelevant Data (Note 1) 1 1 Operand Data (High Order BVte) Ooerand Data (Low Order Data Op Code Offset Products Inc. Bvte) -. PACKAGE DIMENSIONS L SUFFIX CERAMIC PACKAGE CASE 71W5 NOTES 1. POSITIONAL TOLERANCE OF LEAOS (0), SHALL BE WITHIN 0.25 mm (0.010) AT MAXIMUM MATERIAL CO NO ITION, IN RELATION TO SEATING PLANE ANO EACH OTHER. 2. DIMENSION LTOCENTEROFLEAOS WHEN FORMEO PARALLEL. 3. OIMENSION B DOES NOT INCLUOE MOLD FLASH. ,- Motorola out of the reserves the right application to make changes or use of anv product to any products or circuit herein described to improve herein; neither reliability, does Semiconductor 3501 ED BLUESTEIN BLVD., function it convevanv or design, license Motorola under does its patent not assume rights any Iiabilitvarising nor the rights of others. Products Inc. AUSTIN, TEXAS 78721 A SUBSIDIARY OF MOTOROLA INC. "S-981,-*, -- TABLE Address Mode and Instructions INDEXED .. Cycle # Cycles OPERATIONS VMA Line SUMMARY (CONTINUED) R/~ Line Address Bus Data Bus (Continued) 1 1 Op Code Address 1 OP Code 2 Op Code Address + 1 1 Offset 3 0 Index Register 1 Irrelevant Data (Note 1) 4 0 0 Index Register Plus Offset 1 Irrelevant Data (Note 1) Index Register Plus Offset 1 Irrelevant Data (Note 1) 1 STA 6 5 Index Register Plus Offset 0 Op Code Address 1 2 Op Code Address + 1 3 0 Index Register 4 0 Index Register Plus Offset 1 1 1 5 1 Index 6 0 Index Register Plus Offset 1 Index 0 1 LSR NEG ROL ROR TST 7 (w/o Carry} 1 1 1 6 ASL ASR CLR COM DEC INC 8 - 7 110 (w/o Carry) Register Plus Offset 1 Register Plus Offset Note 3) STS STX 7 JS R 1 1 Op Code Address 2 1 Op Code Address + 1 3 0 Index 4 0 Index Register Plus Offset 5 Index Register Plus Offset 6 0 1 7 1 1 1 1 2 3 4 8 5 --. 6 7 8 Register (w/o Carry) . ..! ,,$ ,<$>:$,,+ Index Register Plus Offset ...< ..\,!"~: ` .?,. ~~':. .{,? Index Register Pl@ Offset + 1 .<~$., .!,: ~a? Op Code Address ~&$>t~rx,, Irrelevant Data (Note 1) Irrelevant Data (Note 1) Operand Data (High Order BVte) Operand Data (Low Order Byte) Op Code Offset 0 1 1 Irrelevant 0 0 0 Irrelevant Data (Note 1) Irrelevant Data (Note 1) Irrelevant Data (Note 1) Data (Note 11 Return Address (Low Order Byte) Return Address (High Order Byte] 1 EXTENDED 1 JMP ADC ADD AND BIT CMP EOR LDA ORA SOC SUB 1 5 ASL ASR CLR COM DEC INC LSR NEG ROL ROR TST 6 m I Op Code 1 JumD Address (Low Order Bvte) Jump Address (High Order Byte) Op Code Address 1 Op Code Op Code Address + 1 1 1 1 1 Address of Operand (High Order Address of Operand (Low Order Byte} Op Code Address + 2 Byte) 1 Address of Operand 1 1 1 1 1 Op Code Address Op Code Address + 1 1 Address of Operand (High Order BVte) Op Code Address + 2 1 1 1 1 1 1 1 0 Address of Operand ( Low Order Byte) Address of Operand Address of ODerand + 1 Operand Data Op Code Operand Data (High Order Ouerand Data (Low Order Bvte) Byte) 1 1 Op Code Address 2 1 Op Code Address + 1 3 1 Op Code Address + 2 4 0 1 Operand Destination Address 5 Operand Destination Address 1 1 Op Code Address 2 Op Code Address + 1 1 Address of Operand (High Order BVte) 3 1 1 Op Code Address + 2 Address of Operand ( Low Order BVte) 4 1 Address of Operand Current 5 0 110 Address of Operand 1 1 1 Address of Operand 0 New Operand 6 f 1 1 T Op Code Destination Address (High Order Byte) Destination Address (Low Order Byte) Irrelevant Data (Note Op Code Irrelevant Operand Semiconductor 19 Data Data (Note 1) Data (Note 3) (Not 3) MOrOROLA 1) Data from Accumulator Products Inc. TABLE 8 - OPERATIONS Address Mode and I rsstructions EXTENDED Cycles Cycle # SUMMARY (CONTINUED) Rm VMA Line Address Bus Line I I Data Bus (Continued) 1 1 1 Op Code Address Op Code Op Code Address + 1 Address of Operand (High Order 8yte) Op Code Address + 2 Address of Operand 4 0 Address of Operand Irrelevant (Low Order ~$~:) .,'i.\'\t. :,!,:.? ..,,4,.:, ...,,.~ 1) .:;::<, .~) i:,, 5 1 1 Address of Operand 1 STS STX 2 3 6 6 JS R Operand Data (High Order $,Y#& + 1 Operand Data ( LOW ~q,$~;<~~ OP Code Address+ 1 Op Code Address+ 2 Subroutine Address Op Cod:~{ 7 1 1 1 1 1 0 8 0 Op Code Address + 2 ;#wevant 9 --1 Op Code Address + 2 `~ddress of Subroutine 1 T 2 3 4 5 6 T Op Code Op Code Address Starting N>~?nstruction Stack Pointer - 1 Return''#&ess ...$ . !?!?,y\,,''?*a RS~~n"'~Wdress Stack Pointer - 2 $~~~yd%t Data Stack Pointer ( Low Order BVte) (High Order (Note 1) Data (Note 1) Byte) (Low Order Byte) INHERENT ABA ASL ASR CBA CLC CL I CLR CLV COM DAA DEC iNC LSR NEG NOP ROL ROR SBA SEC SE I SEV TAB T-AP TBA TPA TST 2 2 I Op Code 1 OP Code of Next 1 1 0 0 Op Code Op Code of Next 4 2 Data (Note 1) Irrelevant Data (Note 1) OP Code of Next ., ,`s 3 ~~~a-ck Pointer 4 Stack Pointer - 1 Data Accumulator Data Op Code Address Op Code Address + 1 Op Code of Next Stack Pointer Irrelevant Stack Pointer Operand + 1 Instruction Accumulator Op Code Instruction Data (Note 1) Data from Stack Op Code Op Code Address + 1 1 1 1 1 1 1 Index 1 Irrelevant Data New Stack Pointer 1 Irrelevant Data Op Code Address Op Code Address of Next Instruction Order BVte) (High Address of Next Order Byte) (Low Op Code Address Op Code Address + 1 Stack Pointer New Index Register Op Code Address Register 3 Stack Pointer 4 Stack Pointer + 1 1 1 1 1 5 Stack Pointer + 2 1 Op Code Address + 1 5 Instruction Irrelevant Op Code 1 PSH MOTOROLA Semiconductor @ 20 ---- Instruction I T + .".,.,.$!...>,,.. ~,i \,i+ ~:a ,+,y . Address of Subr@$~'e$~figh Order BVte) .J.. isl~: ,,,.,. Address of ~$r&@jl*e (Low Order BVte) 1 9 Address of Operand Data (Note Op Code of Next Instruction Irrelevant Data (Note 1) Irrelevant Data (Note 1) Op Code Op Code of Next Instruction Irrelevant Data (Note 2) Irrelevant Data (Note 1) Instruction Products Inc. I TABLE I Address Mode and Instructions INHERENT Cycles Cycle # 8 - OPERATIONS VMA Line SUMMARY (CONCLUDED) R/~ Line Address Bus Data Bus I .---- . ....--.--., (Continued) WA I 9 RTI 10 Swl 1 Op Code 1 Op Code of Next o Return - 1 0 Return - 2 0 Index Register (Low Order BVte) Stack Pointer - 3 0 Index Register (High Order BVte) 1 Stack Pointer - 4 0 Contents of Accumulator 8 1 Stack Pointer - 5 0 Contents of Accumulator 9 1 Stack Pointer - 6 1 1 1 Op Code Address 2 1 OP Code Address+ 3 1 Stack Pointer 4 1 Stack Pointer 5 1 Stack Pointer 6 1 7 Address (High Order Byte) B $, ~<'!+;` <\.., \,v*.t~ of Cond. Codqz@e~~Ste~ *,.?,.,?; ~ ~: `: ~~!, Op Code ,.:. ~~s\ 1 1 OP Code Address 1 Op Code Address + 1 1 Irrelevant 1 1rrelevant 3 0 Stack Pointer 1 Stack Pointer t 1 1 5 1 Stack Pointer + 2 1 6 1 Stack Pointer + 3 1 7 1 Stack Pointer + 4 8 1 Stack Pointer + 5 9 1 10 1 -`$ 1- $$,,, es:<.\.*:<2~, ,<,.t,.-+<:, ~ A Contents 1 4 Instruction Address (Low Order Byte) 2 Data ( N~~~;#,)$,~"+v Da~~~fl&~&$'~ :s'..>~** Contents of. Con~$~ode Register Stack .~+;i~< `\,; Q-}~. Cont@fi&t~ Accumulator B from \ ,,,~:$, G~$~@'ts,of Accumulator A from a:<~ ;~~~-%egister from Stack (High `$t~f~~ from Stack Stack Order 1 1 2 1 3 1 4 1 f$k~,,, Index Register from Stack (Low Order `~~'"" `BVte) ,,,:..,.,$. ~,.- `t. ~k?\ 3. 1 Next Instruction Address from Stack Stack Pointer + 6 ~,,.:,. `*:\L >,,,.* ,/.>? (High Order Byte) .~' JJ `" ~.i,.. ,,* 1 Next Instruction Address from Stack Stack Pointer + 7 ,..:. ,,;.J. .,.$,., ,N:>t,> " (Low Order Evte) .i.~,:lx ..:.Y.:<: ,,.\ ..~ Op Code 1 Op Code Address $\, ~"aiy. 1 Irrelevant Data (Note 1 ) Op Code Address + 1% ;,% ,Jj ,,$,,%L,*,,.+ .?$T\,,:*G$:, o Return Address (Low Order BVte) Stack Pointer V,,t o Return Address (High Order BVte) Stack Pointer - 1 "~$ 1 Stack Poi,~~r 5 Stack PQfri~$,- *.,,, 1 Sta~*~$er -- `:J. 1 $$a:@ @nter - , .$ :%t~h:$ointer _ .$.~,.. .\, t:,!+,, ~ ,:%;w~:;,.@tack Pointer - 6 12 1 7 8 9 lQ o 0 0 3 1 4 0 0 5 6 7 Index Register (Low Order Byte) Index Register (High Order Contents BVte) of Accumulator A Contents of Accumulator B Contents of Cond. Code Ragister 1 Irrelevant 1 1'*:+* *$$ `Vector .>.<+Y,..: ~{.~$?,, Address FFFA (Hex) 1 Address of Subroutine BVte) (High Order Vector Address FFFB (Hex) 1 Address of Subroutine BVte) (Low Order ~ ,2,*G,: \ >~y ~$,,1> ,,`.-.,. h,+ RELATIVE ,~,. s?, ..$,+,., .,, ,,.:,,> ~~,.Fy BCC BHI BN E ,..,!~~ \$,:. BCS BLE BPL ~,+.~: ~ !> -., ,t,~ 4 BEQ BLS BRA ,?\ $.$* ....$ BGE BLT BVC `.$?,`$:, >.,.:.~ BGT BM I BV~$~J~~k, .'.',.. `, \'\.,, .? +i?. BSR ,.`":?,*{. ":i,$* . \iy?:)~:~$i, ,~!' ,<,..?. w+., ,$; .:3~.d,\,.\ I ..,,!, ~$x'+. .,*\ ,* ~<.. ~<::<:.,4i..\:t.r:, 8 $.+ye\\ .>,3. , .'.1<$., \,j ;:;>+>~ `.>$ ,$ r; ` 1 Data (Note 1) 1 1 Op Code Address 1 Op Code 2 1 OP Code Address + 1 1 Branch Offset 3 0 Op Code Address + 2 1 Irrelevant Data (Note 1) 4 0 Branch Address 1 Irrelevant Data (Note 1) 1 1 Op Code Address 1 Op Code 2 1 Op Code Address + 1 1 Branch Offset 3 0 Return 1 Irrelevant 4 1 Stack Pointer Return Address (Low Order BVte) Return Address (High Order BVte) Address of Main Program Data (Nota 1) 5 1 Stack Pointer - 1 o 0 6 Stack Pointer - 2 1 Irrelevant Data (Note 7 0 0 1 Irrelevant Data (Note 1) 8 0 Subroutine 1 Irrelevant Data (Note 1) Return Address of Main Program Address (Note 4) 1) NOTES: 1. If device Depending which IS addressed during on bus capacitance, 2. Data is Ignored by the MPU. 3. For TST, VMA= O and Operand 4. MS BVte of Address this cycle uses VMA, then the Data data from the previous cvcle may be retained Bus will go to the high-impedance three-state condition on the Data Bus. data does not change. Bus= MS Byte of Address of BSR instruction MOTOROLA and LS Byte of Address Semiconductor @ 21 Bus= LS Byte of Sub-Routine Products Inc. Address.