IDT54/74FCT3646/A 3.3V CMOS OCTAL IDT54/74FCT3648/A TRANSCEIVER/ IDT54/74FCT3651/A REGISTERS (3-STATE) IDT54/74FCT3652/A Integrated Device Technology, Inc. PRODUCT PREVIEW FEATURES: * 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 25 mil Center SSOP Packages Extended commercial range of 40C to +85C + Voc = 3.3V +0.3V, Normal Range or Vcc = 2.7V to 3.6V, Extended Range * CMOS power levels (10,.W typ. static) + Rail-to-Rail output swing for increased noise margin Military product compliant to MIL-STD-883, Class B DESCRIPTION: The IDT54/74FCTS646/A, IDT54/74FCT3648/A, IDT54/ 74FCT3651/A and 1DT54/74FCT3652/A consist of a bus transceiver with 3-state D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. The FCT3651/3652 utilize GAB and GBA signals to control the transceiver functions. The FCT3646/3648 utilize the en- able control (G) and direction (DIR) pins to control the trans- ceiver functions. SAB and SBA control pins are provided to select either real- time or stored data transfer. The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between stored and real- time data. A LOW input level selects real-time data and a HIGH selects stored data. Data on the A or B data bus, or both, can be stored in the internal D flip-flops by LOW-to-HIGH transitions at the appro- priate clock pins (CPAB or CPBA), regardless of the select or enable control pins. The IDT54/74FCT3xxx/A have series current limiting resis- tors. These offerlow ground bounce, minimal undershoot, and controlled output fall times-reducing the need for external series terminating resistors. FUNCTIONAL BLOCK DIAGRAM ONLY 1 OF 8 CHANNELS Al FCT3646/3652 ONLY The IDT logo is a registered trademark of integrated Device Technology, Inc. ror eee 3094 drw 01 TO 7 OTHER CHANNELS MILITARY AND COMMERCIAL TEMPERATURE RANGES 1994 Integrated Device Technology. Inc. 8.14 APRIL 1994 DSC-4649/. 1IDT54/7AFCT3646/A, IDT54/74FCT3648/A, IDT54/74FCT3651/A, IDT54/74FCT3652/A 3.3V CMOS OCTAL TRANSCEIVER/REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS FCT3646/3648 FCT3651/3652 CPAB [[]1 CPAB ([]1 SAB (2 SAB (2 GND [7] 12 GND [[] 12 3094 drw 02 3094 drw 03 DIP/SOIC/SSOP DIP/SOIC/SSOP TOP VIEW TOP VIEW LOGIC SYMBOLS PIN DESCRIPTION | j | jf jf J 4 Pin Names Description 7 hae At Az As A4 As As A7 As At - As Data Register A Inputs oIR Data Register B Outputs 3646/3648 ONLY ~ 4 Saen Bi - Ba Data Register B Inputs 7 G Bi Bz Bs B4 Bs Be B7 Bs Data Register A Outputs en a ee CPAB, CPBA Clock Pulse Inputs Lipptitrls SAB, SBA Output Data Source Select Inputs a CPAB A1 A2 As A4 As As Az As DIR, G Output Enable Inputs (3646/3648) a GAB, GBA GAB 3651/3652 ONLY Output Enable Inputs (3651/3652) | CPBA 3094 tbl 01 Bi Bz B3 B4 Bs Be B7 Ba TT tT Tr tT TT rt 3094 drw 04 8.14 2IDT54/74FCT3646/A, IDT54/74FCT3646/A, IDT54/74FCT3651/A, IDT54/74FCTI652/A 3.3V CMOS OCTAL TRANSCEIVER/REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES FUNCTION TABLE (3646/3648) Inputs Data VO) Operation or Function G DIR | CPAB | CPBA | SAB | SBA A1- As Bi - Bs FCT3646 FCT3648 H x Horl | HorLk x Xx Input Input Isolation Isolation H x tT t x x Store A and B Data Store A and B Data L L x x x L Output Input Real-Time B Data to A Bus | Real-Time B Data to A Bus L L x HorL| X H Stored B Data to A Bus Stored B Data to A Bus L H x x L x Input Output _| Real-Time A Data to B Bus | Real-Time A Data to B Bus L H_ | HorL X H xX Stored A Data to B Bus Stored A Data to B Bus 3094 tbl 02 FUNCTION TABLE (3651/3652) Inputs Data /O Operation or Function GAB | GBA | CPAB | CPBA| SAB | SBA A1- Ag B1- Ba FCT3651 FCT3652 L H HorL | Horlk X x Input Input Isolation Isolation L H t t X X Store A and B Data Store A and B Data Xx H T HorLl X X Input Unspecified(*) | Store A, Hold B Store A, Hold B H H t t x(2) X Input Output Store A in Both Registers] Store A in Both Registers L xX Horlk T x X |Unspecified() Input Hold A, Store B Hold A, Store B L L tT t x x(2) Output Input Store B in Both Registers] Store B in Both Registers L L xX Xx X L Output Input Real-Time B Data to A Bus] Real-Time B Data to A Bus L L Xx HorL | X H Stored B Data to A Bus Stored B Data to A Bus H H Xx Xx L xX Input Output Real-Time A Data to B Bus | Real-Time A Data to B Bus H H_ |HorL| xX H x Stored A Data to B Bus Stored A Data to B Bus H L HorL | HorL H H Output Output Stored A Data to B Bus Stored A Data to B Bus and Stored B Data to A and Stored B Data to A Bus Bus NOTES; 1 3094 tbl 03 . The data output functions may be enabled or disabled by various signals at the GAB or GBA inputs. Data input functions are always enabled, i.e. data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. 2. Select control = L: clocks can occur simultaneously. Select control = H: clocks must be staggered in order to load both registers. H = HIGH, L = LOW, X = Don't Care, # = LOW-to-HIGH transition. w . Ain B Register. 4. Bin A Register. 8.14IDT54/74FCT3646/A, IDTS4/74FCT3648/A, IDT54/74FCT3651/A, IDT54/74FCT3652/A 3.3V CMOS OCTAL TRANSCEIVER/REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES | Pury | II | us| Ltt | Us| A ] ] B HY tl WII 3651/3652 GAB GBA CPAB- CPBA L L x x 3646/3648 DIR G CPAB- CPBA L L 4 X REAL-TIME TRANSFER BUS BTOA min | sus} |{ [7 | US AT HEEL | 3651/3652 GAB GBA CPAB- CPBA x H tT x L x x t L H tT tT 3646/3648 DIR G CPAB- CPBA H L t x L L x T x H T T STORAGE FROM A AND/OR B -l NN = Cc <3) TL WW SAB SBA 3651/3652 GAB GBA CPAB CPBA_ SAB SBA X L H H x x L x SAB SBA 3646/3648 DIR CPAB CPBA SAB SBA x ot HoOL x x LX REAL-TIME TRANSFER BUS ATOB 3094 drw 05 3094 drw 06 | Qe SAB SBA 3651/3652 GAB GBA CPAB CPBA SAB SBA x x H L Hor H or H H xX X (1) X x 3646/3648 DIR G CPAB CPBA SAB SBA L L xX Hor x H H x SAB SBA L Hor xX H x X TRANSFER STORES x x DATA TO A AND/OR B x x 3094 drw 08 NOTE: 1. FCT3646/3648 cannot transfer data to A bus and B bus simultaneously. 3094 drw 07 8.14 4IDT54/74FCT3646/A, IDT54/74FCT3648/A, IDT54/74FCT3651/A, IDT54/74FCT3652/A 3.3V CMOS OCTAL TRANSCEIVER/REGISTERS (3-STATE) ABSOLUTE MAXIMUM RATINGS) MILITARY AND COMMERCIAL TEMPERATURE RANGES CAPACITANCE (Ta = +25C, { = 1.0MHz) Symbol Rating Commercial] Military _| Unit Symbol | Parameter?) Conditions | Typ. | Max. | Unit VTERM(2) Terminal Voltage |-0.5to+4.6] -O5to+46] V CIN Input VIN = OV 3.5 6.0 | pF we to Capacitance - Cout Output VOUT = OV 4.0 8.0 | pF VTeRM(3){ Terminal Voltage |0.510+7.0] O5to+70] V Capacitance with Respect to Pe GND NOTE: 3094 Ink 05 - 1. This parameter is id at ch terization but nat . VTERM(4)| Terminal Voltage 0 5to 0.5 to Vv sp measured at characterization ut not tested with Respect to Voc + 0.5 Vcc + 0.5 GND TA Operating 40 10 +85 | -551to +125] C Temperature TBIAS Temperature -55 to +125 | -65 to +135 | C Under Bias TsTG Storage 55 to +125] 6510 +150 | C Temperature PT Power Dissipation 1.0 1.0 Ww lout DC Output -60 to +60 | -60to+60 | mA Current NOTES: 3094 Ink 04 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT- INGS may cause permanent damage to the device. This is a stress rating onty and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect reliability. 2. Vcc terminals. 3. Input terminals. 4. Output and I/O terminals. 8.14IDT54/74FCT3646/A, IDT54/74FCT3648/A, IDT54/74FCT3651/A, IDT54/74FCT3652/A 3.3V CMOS OCTAL TRANSCEIVER/REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: Ta = 40C to +85C, Vcc = 2.7V to 3.6V; Military: Ta = -55C to +125C, Vcc = 2.7V to 3.6V Symbol Parameter Test Conditions(1) Min. | Typ.2) | Max. | Unit ViH Input HIGH Level (Input pins) Guaranteed Logic HIGH Level 2.0 5.5 Vv Input HIGH Level (I/O pins) 2.0 |Vcc+0.5 VIL Input LOW Level Guaranteed Logic LOW Level 0.5 _ 0.8 Vv (Input and I/O pins) NH Input HIGH Current (Input pins){) Vcc = Max. Vi=5.5V _ H pA Input HIGH Current (1/0 pins)() Vi = Vcc +1 UL Input LOW Current (Input pins){6) Vi = GND _- _ +1 Input LOW Current (I/O pins)( Vi = GND _ + lozH High Impedance Output Current Voc = Max. Voz= Vcc _ +1 HA hoz (3-State Output pins)() Vo = GND +1 VIK Clamp Diode Voltage Vcc = Min., lIN =-18mA _ 0.7 ~1.2 Vv lobH Output HIGH Current Vcc = 3.3V, VIN= Vidor Vil, Vo= 1.5Vi3) -36 -60 -110 | mA lopt Output LOW Current Vcc = 3.3V, VIN= ViHor VIL, Vo= 1.5V(3) 50 80 200 | mA Vou Output HIGH Voltage Vcc = Min. JOH = -O.1mA Voc-0.248 _ Vv VIN = Vinior Vit loH = -3mMA 2.4 3.0 _ Vcc =3.0V loH = -6mA MIL. 2.4(5) 3.0 _ VIN = ViH or VIL loH = -8mA COML. Vor Output LOW Voltage Vcc = Min. lo. = 0.1mA _ _ 0.2 Vv VIN = ViHor Vit lo. = 16mA _ 0.2 0.4 lo. = 24mA _ 0.3 0.5 los Short Circuit Current(4) Vcc = Max., Vo = GND@) -60 ~135 -240 | mA VH Input Hysteresis _ _ 150 _ mV Ioch Quiescent Power Supply Current Vcc = Max., COML. _ 0.1 10 HA IccH Vin = GND or Vcc lecz MIL. 0.1 100 NOTES: 3094 Ink 06 AnrRwWNy+ Duration of the test should not exceed ane second. . For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. . Typical values are at Voc = 3.3V, +25C ambient. . Not more than one output should be tested at one time . This parameter is guaranteed but not tested. VoH = Vcc -0.6V at rated current. . The test limits for this parameter is + 5yA at Ta = -55C 8.14(DT54/74FCT3646/A, IDT54/74FCT3648/A, IDT54/74FCT3651/A, IDT54/74FCT3652/A 3.3V CMOS OCTAL TRANSCEIVER/REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions( Min. | Typ? | Max. | Unit Alec Quiescent Power Supply Current | Vcc = Max. VIN = Vec -0.6V) pA lecp Dynamic Power Supply Current(4) | Vcc = Max. Vin = Voc pA/ Outputs Open Vin = GND MHz GAB = GBA = GND or G= DIR = GND One Input Toggling 50% Duty Cycle Ic Total Power Supply Current() Vcc = Max. VIN = Voc mA Outputs Open Vin = GND fop = 10MHz 50% Duty Cycle GAB = GBA = GND or G=DIR=GND VIN = Voc -0.6V One Bit Toggling VIN = GND at fi = SMHz 50% Duty Cycle Vcc = Max. VIN = Vcc Outputs Open VIN = GND fcoP = 10MHz 50% Duty Cycle GAB = GBA = GND or G= DIR = GND Vin = Vcc -0.6V Eight Bits Toggling VIN = GND at fi = 5MHz 50% Duty Cycle NOTES: 3094 tbl 07 1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Voc = 3.3V, +25C ambient. 3. Per TTL driven input; all other inputs at Vcc or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested. 6. Ic = QUIESCENT + IINPUTS + IDYNAMIC Ic = Icc + Alec DHNT + Icco (fepNcp/2 + fiNi) Icc = Quiescent Current (Icct, IccH and Iccz) Alcc = Power Supply Current for a TTL High Input Dx = Duty Cycle for TTL Inputs High Nr = Number of TTL Inputs at Dx Iccp = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fcop = Clock Frequency for Register Devices (Zero for Non-Register Devices) Nop = Number of Clock Inputs at fcr fi = Input Frequency Ni = Number of Inputs at fi 8.14 7IDT54/74FCT3646/A, IDT54/74FCT3648/A, IDT54/74FCT3651/A, IDT54/74FCT3652/A 3.3V CMOS OCTAL TRANSCEIVER/REGISTERS (3-STATE) SWITCHING CHARACTERISTICS OVER OPERATING RANGE) MILITARY AND COMMERCIAL TEMPERATURE RANGES FCT3646/3648/ FCT3646A/3648A/ 3651/3652 3651 A/3652A Com'l. Mil. Com'l. Mil. Symbol Parameter Condition Min?) | Max. | min | max. | min | max. | min(2) | max. | Unit tPLH Propagation Delay Ci = 50pF 2.0 9.0 2.0 11.0 2.0 6.3 2.0 7.7 ns tPHL Bus to Bus Ru = 5000, tPZH Output Enable Time, G, 2.0 14.0 2.0 15.0 2.0 9.8 2.0 105 | ns tPZL DIR to Bus (646, 648 only) tPZH Output Enable Time, GAB, 2.0 14.0 2.0 15.0 2.0 9.8 2.0 10.5 | ns tPZL GBA to Bus (651, 652 only) tPHZ Output Disable Time, G, 2.0 9.0 2.0 11.0 2.0 6.3 2.0 7.7 ns tPLZ DIR to Bus {646, 648 only) tPHZ Output Disable Time, GAB, 2.0 9.0 2.0 11.0 2.0 6.3 2.0 7.7 ns tPLZ GBA to Bus (651, 652 only) tPLH Propagation Delay 2.0 9.0 2.0 10.0 2.0 6.3 2.0 7.0 ns tPHL Clock to Bus tPLH Propagation Delay SBA or 2.0 11.0 2.0 12.0 2.0 7.7 2.0 8.4 ns tPHL SAB to Bus tsu Set-up Time HIGH or LOW 4.0 _ 45 _ 2.0 - 2.0 _ ns Bus to Clock tH Hold Time HIGH or LOW 2.0 _ 2.0 _ 1.6 _ 1.5 _ ns Bus to Clock tw Clock Pulse Width, 6.0 _ 6.0 _ 5.0 _ 5.0 ns HIGH or LOW NOTES: 3094 tbl 08 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Propagation Delays and Enable/Disable times are with Vcc = 3.3V +0.3V, Normal Range. For Vcc = 2.7V to 3.6V, Extended Range, all Propagation Delays and Enable/Disable times should be degraded by 20%. 8.14IDT54/74FCT3646/A, IDT54/74FCT3648/A, IDTS4/74FCT3651/A, IDT54/74FCT3652/A 3.3V CMOS OCTAL TRANSCEIVER/REGISTERS (3-STATE) TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS g Vcc e Open 1 GND 5000 1 VIN V ouT Pulse Generator DUT. SOpF 500Q 3094 drw 09 SET-UP, HOLD AND RELEASE TIMES DATA 3V 1.5V INPUT tw TIMING 3V INPUT 4 ov ASYNCHRONOUS CONTROL PRESET 3V CLEAR 1.5V ETC. - ov SYNCHRONOUS CONTROL PRESET = aa CLEAR = Ov CLOCK ENABLE ETC. 3094 drw 10 PROPAGATION DELAY av SAME PHASE 15V INPUT TRANSITION ov VoH OUTPUT 15V VoL 3V OPPOSITE PHASE 15V INPUT TRANSITION ov 3094 drw 12 MILITARY AND COMMERCIAL TEMPERATURE RANGES SWITCH POSITION Test Switch Open Drain Disable Low 6V Enable Low Disable High Enable High GND All Other tests Open DEFINITIONS: 3094 Ink 09 C.i= Load capacitance: includes jig and probe capacitance. Rt= Termination resistance: should be equal to Zout of the Pulse Generator. PULSE WIDTH LOW-HIGH-LOW PULSE 1.5V tw HIGH-LOW-HIGH 1.5V PULSE 3094 drw 11 ENABLE AND DISABLE TIMES ENABLE DISABLE 3Vv CONTROL fi isy INPUT 54 / ? ov OUTPUT 3V NORMALLY LOW VoL OUTPUT "gy (VOH NORMALLY HIGH Ny ov 3094 drw 13 NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable- HIGH. . Pulse Generator for All Pulses: Rate < 1.0MHz: tr < 2.5ns; tk < 2.5ns. 2 3. If Vcc is below 3V, input voltage swings should be adjusted not to exceed Vec 8.14 9IDT54/74FCT3646/A, IDT54/74FCT3648/A, IDT54/74FCT3651/A, IDT54/74FCT3652/A 3.3V CMOS OCTAL TRANSCEIVER/REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT XX FCT Xx XX X x Temp. Range Family Device Type Package Process Blank Commercial B MIL-STD-883, Class B P Plastic DIP (P20-1) D CERDIP (D20-1) so Small Outline IC (SO20-2) PY Shrink Small Outline Package (SO20-7) 646 Non-Inverting Octal Transceiver/Register 648 Inverting Octal Transceiver/Register 651 Inverting Octal Transceiver/Register 652 Non-Inverting Octal Transceiver/Register 646A 648A 651A 652A | 3 3.3 Volt { | 54 55C to +125C | 74 -40C to +85C 2094 drw 14 8.14 10