HD6432197RF - Renesas Technology / Hitachi Semiconductor

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Renesas Technology Corp.

Customer Support Dept.

April 1, 2003

To all our customers

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Hitachi Single-Chip Microcomputer

H8S/2199R Series

H8S/2199R

HD6432199R

H8S/2198R

HD6432198R

H8S/2197R

HD6432197R

H8S/2197S

HD6432197S

H8S/2196R

HD6432196R

H8S/2196S

HD6432196S

H8S/2199R F-ZTAT™

HD64F2199R

Hardware Manual

ADE-602-232

Rev 1.0

02/23/01

Hitachi, Ltd.

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s

patent, copyright, trademark, or other intellectual property rights for information contained in

this docu ment. Hitachi bears no responsibility for problems that may arise with th ir d pa r ty’s

rights, including intellectual property rights, in connection with use of the information

contained in this document.

2. Products and product specifications may be subject to change without no tice. Confirm that you

have received the latest prod uct standards or specifications before final design, purchase or

use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.

However, contact Hitachi’s sales office before using the product in an application that

demand s especially high quality and r e liab ility or where its failure or m a lfun c tion may directly

threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear

power, combustion control, transportation, traffic, safety equipment or medical equipment for

life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi

particularly fo r maximum rating, operating supply voltage range, heat radiation ch aracteristics,

installation conditions and other char acteristics. Hitachi bears no responsibility for failure or

damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,

consider normally foreseeable failure rates or failure modes in semiconductor devices and

employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi

product does not cause bodily injury, fire or other consequential damage due to operation of

the Hitachi pro duct.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document

without written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi

semiconductor pro duct s .

Rev. 1.0, 01/01, page I of IV

Comparison between H8S/2199 Series and

H8S/2199R Series

Item H8S/2199 Series H8S/2199R Series Remarks

OSD

Initialization

mode of bits 12

and 11 in the

OSD format

(DFORM)

Initialized by a reset, or in

module stop mode, sle ep

mode, standby mode,

watch mode, subactive

mode, or subsleep mode.

Initialized by a reset.

When rewriting bits 12

and 11, make sure the

module stop bit in the

sync separ ator is not

cleared to 0.

Bit 12: FSCIN (4/2fsc

input select bit)

Bit 11: FSCEXT (4/2fsc

external input select bit)

Character

display size at

vertical 2 times

x horizontal 2

times

Number of charac ters in

a row is 16 Number of charac ters in

a row is 32

4/2fsc clock in

superimposed

mode

Necessary Unnecessary

Horizontal

display output

mask area in

superimposed

mode

H reference face

CVin

AFCH

(internal sync H)

H display output

mask area

Approx. 3.0µs Approx. 8.0µs

H reference face

CVin

AFCH

(internal sync H)

H display output

mask area

Approx. 4.0µs Approx. 7.0µs

Vertical display

output mask

area in

superimposed

mode

NTSC, 4.43 NTSC, and

MPAL: 16 lines after

external Vs ync is

detected

PAL, SECAM, and

NPAL: 21 lines after

external Vs ync is

detected

NTSC, 4.43 NTSC, and

MPAL: 6 lines after

external Vs ync is

detected

PAL, SECAM, and NPAL:

6 lines after external

Vsync is detected

Horizontal

starting displa y

position when

HCKSEL = 1

Compared to when

HCKSEL = 0, shifted left

by approx. 1.7 µs if AFC

= 9 MHz, and by approx.

1.1 µs if AFC = 7 MHz

Same position as when

HCKSEL = 0

Rev. 1.0, 01/01, page II of IV

Item H8S/2199 Series H8S/2199R Series Remarks

OSD

Dot clock source

in text display

mode

AFC reference clock AFC reference clock or

4/2fsc clock The data slicer can

operate when 4/2fsc

clocks is selected in text

display mode.

Bit 1 in SEPA CR:

DOTCKSL

Data slicer

Operating

frequency AFC reference clock = 9

MHz AFC reference clock = 7

or 9 MHz

Data bit size 16 bits 16 or 32 bits Bit 0 in SEPA CR:

DSL32B

Sync separator

initialization

mode

Initialized by a reset. Initialized by a reset, or in

module stop mode, sle ep

mode, standby mode,

watch mode, subactive

mode, or subsleep mode.

Note that bit 5 (CCMPSL)

in SEPIMR is only

initialized by a reset.

Bit 5: CCMPSL

(selection of Csync

separation comparator

input and control of

input/output of

Csync/Hsync terminal)

HHKON2 No corresponding bit Bit is available Bit 1 in SEPCR:

HHKON2

New bits Bit 1 in SEPCR:

Reserved Bit 1 in SEPCR:

HHKON2

Controls HHK operation

during V-blanking.

Bit1 Description

HHKON2

Does not operate

(initial value)

Operates

Bit 1 in SEPA CR:

Reserved Bit 1 in SEPA CR:

DOTCKSL

Selects the dot clock

source. When this bi t is

set to 1, clear bit 3

(HCKSEL) in SEPCR to

The data slicer can

operate when 4/2fsc

clocks is selected in text

display mode.

Rev. 1.0, 01/01, page III of IV

Item H8S/2199 Series H8S/2199R Series Remarks

Bit1 Description

DOTCKSL

AFC reference clock

(initial value)

4/2fsc clock

Sync separator

New bits Bit 0 in SEPA CR:

Reserved Bit 0 in SEPA CR:

DSL32B

Selects the slice mode

for the data slicer.

Bit0 Description

DSL32B

16-bit mode

(initial value)

32-bit mode

The data slicer can

operate when AFC is set

to either 7 or 9 MHz.

However, the slice lin e

must be set to one line.

Rev. 1.0, 01/01, page IV of IV

Rev. 1.0, 02/01, page i of xxii

Preface

This LSI is a single-chip microcomputer made up of the H8S/2000 CPU with an internal 32-bit

architecture as its core, and the peripheral functions required to configure a system.

This LSI is equipped with ROM, RAM, digital servo circuits, a sync separator, an OSD, a data

slicer, seven types of timers, three types of PWMs, two types of serial communication interfaces

(SCIs), an I2C bus interface (IIC), a D/A converter, an A/D converter, and I/O ports as on-chip

supporting modules. This LSI is suitable for use as an embedded processor for high-level control

systems. Its on- c hip ROM is flash mem ory (F-Z TATTM*) that provides flexibility as it can be

reprogrammed in no time to cope with all situations from the early stages of mass production to

full-scale mass production. This is particularly applicable to application devices with

specifications that will m ost probab ly change.

Note: * F-ZTATTM is a trademark of Hitachi, Ltd.

Target Users: This manual was written for users who will be using the H8S/2199R Series and

H8S/2199R F-ZTATTM in the design of application systems. Members of this

audience are expected to understand the fundamentals of electrical circuits, logical

circuits, and microcomputers.

Objective: This manual was wr itten to explain the hardware fun ctions and electrical

characteristics of the H8S/2199R Series and H8S/2199R F-ZTATTM to the above

audience. Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for

a detailed description of the instruction set.

Notes on reading this manu a l:

• In order to understand the overall functions of the chip

Read the manual according to the contents. This manual can be roughly categorized into parts

on the CPU, system control functions, peripheral functions and electrical characteristics.

• In order to understand the details of the CPU's functions

Read the H8S/2600 Series, H8S/2000 Series Programming Manual.

• In order to understand the details of a register when its name is known

The addresses, b its, and initial values of th e register s ar e summ a r ized in Appendix B, Internal

I/O Registe rs.

Example: Bit order: The MSB is on the left and the LSB is on the right.

Related Manuals: The latest versions of all r elated manuals are available from our web site.

Please ensure you have the latest versions of all documents you require.

http://www.hitachi.co.jp/Sicd/English/Products/micome.htm

Rev. 1.0, 02/01, page ii of xxii

H8S/2199R Series and H8S/2199R F-ZTATTM manuals:

Manual Title ADE No.

H8S/2199R Series, H8S/2199R F-ZTATTM Hardware Manual This manual

H8S/2600 Series, H8S/2000 Series Programming Manual ADE-602-083

Users manuals for development tools:

Manual Title ADE No.

C/C++ Compiler Users Manual ADE-702-059

Simulator Debugger (for Windows) Users Manual ADE-702-037

Hitachi Embedded Work sho p U sers Manual ADE-702-201

Application Notes:

Manual Title ADE No.

C/C++ Compiler Edition ADE-502-044

H8S Series Technical Q & A ADE-502-059

F-ZTAT Technical Q & A ADE-502-046

Rev. 1.0, 02/01, page iii of xxii

Contents

Section 1 Overview............................................................................................1

1.1 Overview...........................................................................................................................1

1.2 Internal Block Diagram.....................................................................................................7

1.3 Pin Arrangement and Functions........................................................................................9

1.3.1 Pin Arrangement..................................................................................................9

1.3.2 Pin Functions .......................................................................................................11

Section 2 CPU....................................................................................................19

2.1 Overview...........................................................................................................................19

2.1.1 Features................................................................................................................19

2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU..................................20

2.1.3 Differences from H8/300 CPU ............................................................................20

2.1.4 Differences from H8/300H CPU..........................................................................21

2.2 CPU Operating Modes......................................................................................................22

2.2.1 Normal Mode (Not available for this LSI)...........................................................22

2.2.2 Advanced Mode...................................................................................................24

2.3 Address Space...................................................................................................................27

2.4 Register Configuration......................................................................................................28

2.4.1 Overview..............................................................................................................28

2.4.2 General Registers.................................................................................................29

2.4.3 Control Registers .................................................................................................30

2.4.4 Initial Register Values..........................................................................................31

2.5 Data Formats.....................................................................................................................32

2.5.1 General Register Data Formats............................................................................32

2.5.2 Memory Data Formats.........................................................................................34

2.6 Instruction Set...................................................................................................................35

2.6.1 Overview..............................................................................................................35

2.6.2 Instructions and Addressing Modes.....................................................................36

2.6.3 Table of Instructions Classified by Function .......................................................37

2.6.4 Basic Instruction Formats ....................................................................................47

2.6.5 Notes on Use of Bit-Manipulation Instructions ...................................................48

2.7 Addressing Modes and Effective Address Calculation.....................................................49

2.7.1 Addressing Mode.................................................................................................49

2.7.2 Effective Address Calculation .............................................................................52

2.8 Processing States...............................................................................................................56

2.8.1 Overview..............................................................................................................56

2.8.2 Reset State............................................................................................................57

2.8.3 Exception-Handling State....................................................................................58

2.8.4 Program Execution State......................................................................................59

Rev. 1.0, 02/01, page iv of xxii

2.8.5 Power-Down State...............................................................................................60

2.9 Basic Timing.....................................................................................................................61

2.9.1 Overview..............................................................................................................61

2.9.2 On-Chip Memory (ROM, RAM).........................................................................61

2.9.3 On-Chip Supporting Module Access Timing.......................................................62

2.10 Usage Note........................................................................................................................63

2.10.1 TAS Instruction....................................................................................................63

2.10.2 STM/LDM Instruction.........................................................................................63

Section 3 MCU Operating Modes .....................................................................65

3.1 Overview...........................................................................................................................65

3.1.1 Operating Mode Selection ...................................................................................65

3.1.2 Register Configuration.........................................................................................65

3.2 Register Descriptions........................................................................................................66

3.2.1 Mode Control Register (MDCR) .........................................................................66

3.2.2 System Control Register (SYSCR)......................................................................66

3.3 Operating Mode (Mode 1) ................................................................................................67

3.4 Address Map in Each Operating Mode.............................................................................68

Section 4 Power-Down State.............................................................................71

4.1 Overview...........................................................................................................................71

4.1.1 Register Configuration.........................................................................................75

4.2 Register Descriptions........................................................................................................76

4.2.1 Standby Control Register (SBYCR) ....................................................................76

4.2.2 Low-Power Control Register (LPWRCR)...........................................................78

4.2.3 Timer Register A (TMA).....................................................................................80

4.2.4 Module Stop Control Register (MSTPCR)..........................................................81

4.3 Medium-Speed Mode........................................................................................................82

4.4 Sleep Mode .......................................................................................................................83

4.4.1 Sleep Mode..........................................................................................................83

4.4.2 Clearing Sleep Mode............................................................................................83

4.5 Module Stop Mode............................................................................................................84

4.5.1 Module Stop Mode ..............................................................................................84

4.6 Standby Mode...................................................................................................................85

4.6.1 Standby Mode......................................................................................................85

4.6.2 Clearing Standby Mode .......................................................................................85

4.6.3 Setting Oscillation Settling Time after Clearing Standby Mode ..........................85

4.7 Watch Mode......................................................................................................................87

4.7.1 Watch Mode.........................................................................................................87

4.7.2 Clearing Watch Mode..........................................................................................87

4.8 Subsleep Mode..................................................................................................................88

4.8.1 Subsleep Mode.....................................................................................................88

4.8.2 Clearing Subsleep Mode......................................................................................88

Rev. 1.0, 02/01, page v of xxii

4.9 Subactive Mode ................................................................................................................89

4.9.1 Subactive Mode ...................................................................................................89

4.9.2 Clearing Subactive Mode.....................................................................................89

4.10 Direct Transition...............................................................................................................90

4.10.1 Overview of Direct Transition.............................................................................90

Section 5 Exception Handling ...........................................................................91

5.1 Overview...........................................................................................................................91

5.1.1 Exception Handling Types and Priority...............................................................91

5.1.2 Exception Handling Operation.............................................................................92

5.1.3 Exception Sources and Vector Table...................................................................92

5.2 Reset..................................................................................................................................94

5.2.1 Overview..............................................................................................................94

5.2.2 Reset Sequence ....................................................................................................94

5.2.3 Interrupts after Reset............................................................................................95

5.3 Interrupts...........................................................................................................................96

5.4 Trap Instruction.................................................................................................................97

5.5 Stack Status after Exception Handling..............................................................................98

5.6 Notes on Use of the Stack.................................................................................................9 9

Section 6 Interrupt Controller............................................................................101

6.1 Overview...........................................................................................................................101

6.1.1 Features................................................................................................................101

6.1.2 Block Diagram.....................................................................................................102

6.1.3 Pin Configuration.................................................................................................103

6.1.4 Register Configuration.........................................................................................103

6.2 Register Descriptions........................................................................................................104

6.2.1 System Control Register (SYSCR)......................................................................104

6.2.2 Interrupt Control Registers A to D (ICRA to ICRD)...........................................105

6.2.3 IRQ Enable Register (IENR) ...............................................................................106

6.2.4 IRQ Edge Select Registers (IEGR)......................................................................107

6.2.5 IRQ Status Register (IRQR) ................................................................................108

6.2.6 Port Mode Register 1 (PMR1).............................................................................109

6.3 Interrupt Sources...............................................................................................................110

6.3.1 External Interrupts ...............................................................................................110

6.3.2 Internal Interrupts.................................................................................................111

6.3.3 Interrupt Exception Vector Table ........................................................................112

6.4 Interrupt Operation............................................................................................................115

6.4.1 Interrupt Control Modes and Interrupt Operation................................................115

6.4.2 Interrupt Control Mode 0.....................................................................................117

6.4.3 Interrupt Control Mode 1.....................................................................................119

6.4.4 Interrupt Exception Handling Sequence..............................................................122

6.4.5 Interrupt Response Times....................................................................................123

Rev. 1.0, 02/01, page vi of xxii

6.5 Usage Notes......................................................................................................................124

6.5.1 Contention between Interrupt Generation and Disabling.....................................124

6.5.2 Instructions that Disable Interrupts......................................................................125

6.5.3 Interrupts during Execution of EEPMOV Instruction..........................................125

Section 7 ROM..................................................................................................127

7.1 Overview...........................................................................................................................127

7.1.1 Block Diagram.....................................................................................................127

7.2 Overview of Flash Memory..............................................................................................128

7.2.1 Features................................................................................................................128

7.2.2 Block Diagram.....................................................................................................129

7.2.3 Flash Memory Operating Modes .........................................................................130

7.2.4 Pin Configuration.................................................................................................134

7.2.5 Register Configuration.........................................................................................134

7.3 Flash Memory Register Descriptions................................................................................135

7.3.1 Flash Memory Control Register 1 (FLMCR1) .....................................................135

7.3.2 Flash Memory Control Register 2 (FLMCR2) .....................................................138

7.3.3 Erase Block Register 1 (EBR1) ...........................................................................141

7.3.4 Erase Block Register 2 (EBR2) ...........................................................................141

7.3.5 Serial/Timer Control Register (STCR) ................................................................142

7.4 On-Board Programming Modes........................................................................................144

7.4.1 Boot Mode...........................................................................................................145

7.4.2 User Program Mode.............................................................................................150

7.5 Programming/Erasing Flash Memory...............................................................................151

7.5.1 Program Mode (n=1 when the target address ra nge is H'00000 to H'3FFFF

and n=2 when the target address range is H'40000 to H'47FFF)..........................151

7.5.2 Program-Verify Mode (n = 1 when the target address range is H'00000 to

H'3FFFF and n = 2 when the target address range is H'40000 to H'47FFF)........152

7.5.3 Erase Mode (n = 1 when the target address range is H'00 000 to H'3FFFF

and n = 2 when the target address range is H'40000 to H'47FFF)........................154

7.5.4 Erase-Verify Mode (n = 1 when the target address range is H'00000 to

H'3FFFF and n = 2 when the target address range is H'40000 to H'47FFF)........156

7.6 Flash Memory Protection..................................................................................................157

7.6.1 Hardware Protection ............................................................................................157

7.6.2 Software Protection..............................................................................................158

7.6.3 Error Protection....................................................................................................159

7.7 Interrupt Handling when Programming/Erasing Flash Memory.......................................160

7.8 Flash Memory Programmer Mode....................................................................................161

7.8.1 Programmer Mode Setting...................................................................................161

7.8.2 Socket Adapters and Memory Map......................................................................161

7.8.3 Programmer Mode Operation ..............................................................................162

7.8.4 Memory Read Mode............................................................................................163

7.8.5 Auto-Program Mode............................................................................................166

Rev. 1.0, 02/01, page vii of xxii

7.8.6 Auto-Erase Mode.................................................................................................168

7.8.7 Status Read Mode................................................................................................169

7.8.8 Status Polling.......................................................................................................171

7.8.9 Programmer Mode Transition Time.....................................................................172

7.8.10 Notes on Memory Programming..........................................................................172

7.9 Note on Switching from F-ZTAT Version to Mask-ROM Version..................................173

Section 8 RAM ..................................................................................................175

8.1 Overview...........................................................................................................................175

8.1.1 Block Diagram.....................................................................................................175

Section 9 Clock Pulse Generator .......................................................................177

9.1 Overview...........................................................................................................................177

9.1.1 Block Diagram.....................................................................................................177

9.1.2 Register Configuration.........................................................................................177

9.2 Register Descriptions........................................................................................................178

9.2.1 Standby Control Register (SBYCR) ....................................................................178

9.2.2 Low-Power Control Register (LPWRCR)...........................................................179

9.3 Oscillator...........................................................................................................................180

9.3.1 Connecting a Crystal Resonator...........................................................................180

9.3.2 External Clock Input............................................................................................182

9.4 Duty Adjustment Circuit...................................................................................................185

9.5 Medium-Speed Clock Divider..........................................................................................185

9.6 Bus Master Clock Selection Circuit..................................................................................185

9.7 Subclock Oscillator Circuit...............................................................................................186

9.7.1 Connecting 32.768 kHz Crystal Resonator..........................................................186

9.7.2 When Subclock is not Needed.............................................................................187

9.8 Subclock Waveform Shaping Circuit................................................................................187

9.9 Notes on the Resonator.....................................................................................................187

Section 10 I/O Port.............................................................................................189

10.1 Overview...........................................................................................................................189

10.1.1 Port Functions......................................................................................................189

10.1.2 Port Input .............................................................................................................189

10.1.3 MOS Pull-Up Transistors ....................................................................................192

10.2 Port 0.................................................................................................................................193

10.2.1 Overview..............................................................................................................193

10.2.2 Register Configuration.........................................................................................194

10.2.3 Pin Functions .......................................................................................................195

10.2.4 Pin States..............................................................................................................195

10.3 Port 1.................................................................................................................................196

10.3.1 Overview..............................................................................................................196

10.3.2 Register Configuration.........................................................................................196

Rev. 1.0, 02/01, page viii of xxii

10.3.3 Pin Functions .......................................................................................................200

10.3.4 Pin States..............................................................................................................201

10.4 Port 2.................................................................................................................................202

10.4.1 Overview..............................................................................................................202

10.4.2 Register Configuration.........................................................................................202

10.4.3 Pin Functions .......................................................................................................205

10.4.4 Pin States..............................................................................................................207

10.5 Port 3.................................................................................................................................208

10.5.1 Overview..............................................................................................................208

10.5.2 Register Configuration.........................................................................................208

10.5.3 Pin Functions .......................................................................................................212

10.5.4 Pin States..............................................................................................................215

10.6 Port 4.................................................................................................................................216

10.6.1 Overview..............................................................................................................216

10.6.2 Register Configuration.........................................................................................216

10.6.3 Pin Functions .......................................................................................................219

10.6.4 Pin States..............................................................................................................221

10.7 Port 6.................................................................................................................................222

10.7.1 Overview..............................................................................................................222

10.7.2 Register Configuration.........................................................................................223

10.7.3 Pin Functions .......................................................................................................228

10.7.4 Operation .............................................................................................................230

10.7.5 Pin States..............................................................................................................231

10.8 Port 7.................................................................................................................................232

10.8.1 Overview..............................................................................................................232

10.8.2 Register Configuration.........................................................................................233

10.8.3 Pin Functions .......................................................................................................238

10.8.4 Operation .............................................................................................................239

10.8.5 Pin States..............................................................................................................240

10.9 Port 8.................................................................................................................................241

10.9.1 Overview..............................................................................................................241

10.9.2 Register Configuration.........................................................................................242

10.9.3 Pin Functions .......................................................................................................248

10.9.4 Pin States..............................................................................................................250

Section 11 Timer A............................................................................................251

11.1 Overview...........................................................................................................................251

11.1.1 Features................................................................................................................251

11.1.2 Block Diagram.....................................................................................................252

11.1.3 Register Configuration.........................................................................................252

11.2 Register Descriptions........................................................................................................253

11.2.1 Timer Mode Register A (TMA)...........................................................................253

11.2.2 Timer Counter A (TCA) ......................................................................................255

Rev. 1.0, 02/01, page ix of xxii

11.2.3 Module Stop Control Register (MSTPCR)..........................................................255

11.3 Operation...........................................................................................................................256

11.3.1 Operation as the Interval Timer...........................................................................256

11.3.2 Operation as Clock Timer....................................................................................256

11.3.3 Initializing the Counts..........................................................................................256

Section 12 Timer B............................................................................................257

12.1 Overview...........................................................................................................................257

12.1.1 Features................................................................................................................257

12.1.2 Block Diagram.....................................................................................................257

12.1.3 Pin Configuration.................................................................................................258

12.1.4 Register Configuration.........................................................................................258

12.2 Register Descriptions........................................................................................................259

12.2.1 Timer Mode Register B (TMB)...........................................................................259

12.2.2 Timer Counter B (TCB).......................................................................................261

12.2.3 Timer Load Register B (TLB) .............................................................................261

12.2.4 Port Mode Register A (PMRA) ...........................................................................262

12.2.5 Module Stop Control Register (MSTPCR)..........................................................263

12.3 Operation...........................................................................................................................264

12.3.1 Operation as the Interval Timer...........................................................................264

12.3.2 Operation as the Auto Reload Timer ...................................................................264

12.3.3 Event Counter......................................................................................................264

Section 13 Timer J.............................................................................................265

13.1 Overview...........................................................................................................................265

13.1.1 Features................................................................................................................265

13.1.2 Block Diagram.....................................................................................................265

13.1.3 Pin Configuration.................................................................................................267

13.1.4 Register Configuration.........................................................................................267

13.2 Register Descriptions........................................................................................................268

13.2.1 Timer Mode Register J (TMJ) .............................................................................268

13.2.2 Timer J Control Register (TMJC)........................................................................271

13.2.3 Timer J Status Register (TMJS)...........................................................................274

13.2.4 Timer Counter J (TCJ).........................................................................................275

13.2.5 Timer Counter K (TCK) ......................................................................................275

13.2.6 Timer Load Register J (TLJ)................................................................................276

13.2.7 Timer Load Register K (TLK).............................................................................276

13.2.8 Module Stop Control Register (MSTPCR)..........................................................277

13.3 Operation...........................................................................................................................278

13.3.1 8-bit Reload Timer (TMJ-1) ................................................................................278

13.3.2 8-bit Reload Timer (TMJ-2) ................................................................................278

13.3.3 Remote Controlled Data Transmission................................................................279

13.3.4 TMJ-2 Expansion Function..................................................................................282

Rev. 1.0, 02/01, page x of xxii

Section 14 Timer L............................................................................................283

14.1 Overview...........................................................................................................................283

14.1.1 Features................................................................................................................283

14.1.2 Block Diagram.....................................................................................................284

14.1.3 Register Configuration.........................................................................................285

14.2 Register Descriptions........................................................................................................286

14.2.1 Timer L Mode Register (LMR) ...........................................................................286

14.2.2 Linear Time Counter (LTC).................................................................................288

14.2.3 Reload/Compare Match Register (RCR) .............................................................288

14.2.4 Module Stop Control Register (MSTPCR)..........................................................289

14.3 Operation...........................................................................................................................290

14.3.1 Compare Match Clear Operation.........................................................................290

14.3.2 Auto-Reload Operation........................................................................................291

14.3.3 Interval Timer Operation .....................................................................................292

14.3.4 Interrupt Request..................................................................................................292

14.4 Typical Usage ...................................................................................................................293

14.5 Reload Timer Interrupt Request Signal.............................................................................293

Section 15 Timer R............................................................................................295

15.1 Overview...........................................................................................................................295

15.1.1 Features................................................................................................................295

15.1.2 Block Diagram.....................................................................................................295

15.1.3 Pin Configuration.................................................................................................297

15.1.4 Register Configuration.........................................................................................297

15.2 Register Descriptions........................................................................................................298

15.2.1 Timer R Mode Register 1 (TMRM1)...................................................................298

15.2.2 Timer R Mode Register 2 (TMRM2)...................................................................300

15.2.3 Timer R Control/Status Register (TMRCS).........................................................303

15.2.4 Timer R Capture Register 1 (TMRCP1)..............................................................305

15.2.5 Timer R Capture Register 2 (TMRCP2)..............................................................306

15.2.6 Timer R Load Register 1 (TMRL1).....................................................................306

15.2.7 Timer R Load Register 2 (TMRL2).....................................................................307

15.2.8 Timer R Load Register 3 (TMRL3).....................................................................307

15.2.9 Module Stop Control Register (MSTPCR)..........................................................308

15.3 Operation...........................................................................................................................309

15.3.1 Reload Timer Counter Equipped with Capturing Function TMRU-1..................309

15.3.2 Reload Timer Counter Equipped with Capturing Function TMRU-2..................310

15.3.3 Reload Counter Timer TMRU-3..........................................................................310

15.3.4 Mode Identification..............................................................................................311

15.3.5 Reeling Controls..................................................................................................311

15.3.6 Acceleration and Braking Processes of the Capstan Motor.................................311

15.3.7 Slow Tracking Mono-Multi Function..................................................................312

15.4 Interrupt Cause..................................................................................................................314

Rev. 1.0, 02/01, page xi of xxii

15.5 Settings for Respective Functions.....................................................................................315

15.5.1 Mode Identification..............................................................................................315

15.5.2 Reeling Controls..................................................................................................316

15.5.3 Slow Tracking Mono-Multi Function..................................................................316

15.5.4 Acceleration and Braking Processes of the Capstan Motor.................................317

Section 16 Timer X1..........................................................................................319

16.1 Overview...........................................................................................................................319

16.1.1 Features................................................................................................................319

16.1.2 Block Diagram.....................................................................................................320

16.1.3 Pin Configuration.................................................................................................321

16.1.4 Register Configuration.........................................................................................322

16.2 Register Descriptions........................................................................................................323

16.2.1 Free Running Counter (FRC)...............................................................................323

16.2.2 Output Comparing Registers A and B (OCRA and OCRB) ................................324

16.2.3 Input Capture Registers A through D (ICRA through ICRD)..............................325

16.2.4 Timer Interrupt Enabling Register (TIER)...........................................................327

16.2.5 Timer Control/Status Register X (TCSRX).........................................................330

16.2.6 Timer Control Register X (TCRX)......................................................................334

16.2.7 Timer Output Comparing Control Register (TOCR)...........................................336

16.2.8 Module Stop Control Register (MSTPCR)..........................................................338

16.3 Operation...........................................................................................................................339

16.3.1 Operation of Timer X1.........................................................................................339

16.3.2 Counting Timing of the FRC...............................................................................340

16.3.3 Output Comparing Signal Outputting Timing .....................................................341

16.3.4 FRC Clearing Timing ..........................................................................................341

16.3.5 Input Capture Signal Inputting Timing................................................................342

16.3.6 Input Capture Flag (ICFA through ICFD) Setting Up Timing.............................343

16.3.7 Output Comparing Flag (OCFA and OCFB) Setting Up Timing ........................344

16.3.8 Overflow Flag (CVF) Setting Up Timing............................................................344

16.4 Operation Mode of Timer X1 ...........................................................................................345

16.5 Interrupt Causes................................................................................................................346

16.6 Exemplary Uses of Timer X1 ...........................................................................................347

16.7 Precautions when Using Timer X1...................................................................................348

16.7.1 Competition between Writing and Clearing with the FRC..................................348

16.7.2 Competition between Writing and Counting Up with the FRC...........................349

16.7.3 Competition between Writing and Comparing Match with the OCR..................350

16.7.4 Changing Over the Internal Clocks and Counter Operations...............................351

Section 17 Watchdog Timer (WDT)..................................................................353

17.1 Overview...........................................................................................................................353

17.1.1 Features................................................................................................................353

17.1.2 Block Diagram.....................................................................................................354

Rev. 1.0, 02/01, page xii of xxii

17.1.3 Register Configuration.........................................................................................355

17.2 Register Descriptions........................................................................................................356

17.2.1 Watchdog Timer Counter (WTCNT)...................................................................356

17.2.2 Watchdog Timer Control/Status Register (WTCSR)...........................................356

17.2.3 System Control Register (SYSCR)......................................................................359

17.2.4 Notes on Register Access.....................................................................................360

17.3 Operation...........................................................................................................................361

17.3.1 Watchdog Timer Operation .................................................................................361

17.3.2 Interval Timer Operation .....................................................................................362

17.3.3 Timing of Setting of Overflow Flag (OVF).........................................................363

17.4 Interrupts...........................................................................................................................364

17.5 Usage Notes......................................................................................................................364

17.5.1 Contention between Watchdog Timer Counter (WTCNT) Write and Increment 364

17.5.2 Changing Value of CKS2 to CKS0 ......................................................................365

17.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................365

Section 18 8-Bit PWM ......................................................................................367

18.1 Overview...........................................................................................................................367

18.1.1 Features................................................................................................................367

18.1.2 Block Diagram.....................................................................................................367

18.1.3 Pin Configuration.................................................................................................368

18.1.4 Register Configuration.........................................................................................368

18.2 Register Descriptions........................................................................................................369

18.2.1 8-bit PWM Data Registers 0, 1, 2 and 3 (PWR0, PWR1, PWR2, PWR3)...........369

18.2.2 8-bit PWM Control Register (PW8CR)...............................................................370

18.2.3 Port Mode Register 3 (PMR3).............................................................................371

18.2.4 Module Stop Control Register (MSTPCR)..........................................................372

18.3 8-Bit PWM Operation.......................................................................................................373

Section 19 12-Bit PWM ....................................................................................375

19.1 Overview...........................................................................................................................375

19.1.1 Features................................................................................................................375

19.1.2 Block Diagram.....................................................................................................376

19.1.3 Pin Configuration.................................................................................................377

19.1.4 Register Configuration.........................................................................................377

19.2 Register Descriptions........................................................................................................378

19.2.1 12-Bit PWM Control Registers (CPWCR, DPWCR)..........................................378

19.2.2 12-Bit PWM Data Registers (DPWDR, CPWDR) ..............................................381

19.2.3 Module Stop Control Register (MSTPCR)..........................................................382

19.3 Operation...........................................................................................................................383

19.3.1 Output Waveform ................................................................................................383

Rev. 1.0, 02/01, page xiii of xxii

Section 20 14-Bit PWM.....................................................................................385

20.1 Overview...........................................................................................................................385

20.1.1 Features................................................................................................................385

20.1.2 Block Diagram.....................................................................................................386

20.1.3 Pin Configuration.................................................................................................386

20.1.4 Register Configuration.........................................................................................387

20.2 Register Descriptions........................................................................................................388

20.2.1 PWM Control Register (PWCR)..........................................................................388

20.2.2 PWM Data Registers U and L (PWDRU, PWDRL)............................................389

20.2.3 Module Stop Control Register (MSTPCR)..........................................................390

20.3 14-Bit PWM Operation.....................................................................................................391

Section 21 Prescalar Unit...................................................................................393

21.1 Overview...........................................................................................................................393

21.1.1 Features................................................................................................................393

21.1.2 Block Diagram.....................................................................................................394

21.1.3 Pin Configuration.................................................................................................395

21.1.4 Register Configuration.........................................................................................395

21.2 Registers............................................................................................................................396

21.2.1 Input Capture Register 1 (ICR1)..........................................................................396

21.2.2 Prescalar Unit Control/Status Register (PCSR)...................................................396

21.2.3 Port Mode Register 1 (PMR1).............................................................................399

21.3 Noise Cancel Circuit.........................................................................................................400

21.4 Operation...........................................................................................................................400

21.4.1 Prescalar S (PSS) .................................................................................................400

21.4.2 Prescalar W (PSW)..............................................................................................401

21.4.3 Stable Oscillation Wait Time Count....................................................................401

21.4.4 8-bit PWM ...........................................................................................................402

21.4.5 8-bit Input Capture Using IC Pin.........................................................................402

21.4.6 Frequency Division Clock Output .......................................................................402

Section 22 Serial Communication Interface 1 (SCI1) .......................................403

22.1 Overview...........................................................................................................................403

22.1.1 Features................................................................................................................403

22.1.2 Block Diagram.....................................................................................................405

22.1.3 Pin Configuration.................................................................................................406

22.1.4 Register Configuration.........................................................................................406

22.2 Register Descriptions........................................................................................................407

22.2.1 Receive Shift Register 1 (RSR1) .........................................................................407

22.2.2 Receive Data Register 1 (RDR1).........................................................................407

22.2.3 Transmit Shift Register 1 (TSR1)........................................................................408

22.2.4 Transmit Data Register 1 (TDR1)........................................................................408

Rev. 1.0, 02/01, page xiv of xxii

22.2.5 Serial Mode Register 1 (SMR1)...........................................................................409

22.2.6 Serial Control Register 1 (SCR1).........................................................................412

22.2.7 Serial Status Register 1 (SSR1) ...........................................................................416

22.2.8 Bit Rate Register 1 (BRR1) .................................................................................419

22.2.9 Serial Interface Mode Register 1 (SCMR1).........................................................426

22.2.10 Module Stop Control Register (MSTPCR)..........................................................427

22.3 Operation...........................................................................................................................428

22.3.1 Overview..............................................................................................................428

22.3.2 Operation in Asynchronous Mode.......................................................................430

22.3.3 Multiprocessor Communication Function............................................................440

22.3.4 Operation in Synchronous Mode .........................................................................448

22.4 SCI Interrupts....................................................................................................................456

22.5 Usage Notes......................................................................................................................457

Section 23 I2C Bus Interface (IIC)....................................................................465

23.1 Overview...........................................................................................................................465

23.1.1 Features................................................................................................................465

23.1.2 Block Diagram.....................................................................................................466

23.1.3 Pin Configuration.................................................................................................467

23.1.4 Register Configuration.........................................................................................468

23.2 Register Descriptions........................................................................................................469

23.2.1 I2C Bus Data Register (ICDR).............................................................................469

23.2.2 Slave Address Register (SAR).............................................................................472

23.2.3 Second Slave Address Register (SARX) .............................................................474

23.2.4 I2C Bus Mode Register (ICMR)...........................................................................475

23.2.5 I2C Bus Control Register (ICCR).........................................................................479

23.2.6 I2C Bus Status Register (ICSR)............................................................................486

23.2.7 Serial/Timer Control Register (STCR) ................................................................490

23.2.8 DDC Switch Register (DDCSWR)......................................................................491

23.2.9 Module Stop Control Register (MSTPCR)..........................................................494

23.3 Operation...........................................................................................................................495

23.3.1 I2C Bus Data Format............................................................................................495

23.3.2 Master Transmit Operation..................................................................................496

23.3.3 Master Receive Operation....................................................................................499

23.3.4 Slave Receive Operation......................................................................................502

23.3.5 Slave Transmit Operation....................................................................................505

23.3.6 IRIC Setting Timing and SCL Control................................................................506

23.3.7 Automatic Switching from Formatless Tran sfer to I2C Bus Format Transfer......508

23.3.8 Noise Canceler.....................................................................................................509

23.3.9 Sample Flowcharts...............................................................................................509

23.3.10 Initializing Internal Status....................................................................................513

23.4 Usage Notes......................................................................................................................515

Rev. 1.0, 02/01, page xv of xxii

Section 24 A/D Converter..................................................................................521

24.1 Overview...........................................................................................................................521

24.1.1 Features................................................................................................................521

24.1.2 Block Diagram.....................................................................................................522

24.1.3 Pin Configuration.................................................................................................523

24.1.4 Register Configuration.........................................................................................524

24.2 Register Descriptions........................................................................................................525

24.2.1 Software-Triggered A/D Result Register (ADR).................................................525

24.2.2 Hardware-Triggered A/D Result Register (AHR) ...............................................525

24.2.3 A/D Control Register (ADCR) ............................................................................526

24.2.4 A/D Control/Status Register (ADCSR) ...............................................................529

24.2.5 Trigger Select Register (ADTSR)........................................................................532

24.2.6 Port Mode Register 0 (PMR0).............................................................................532

24.2.7 Module Stop Control Register (MSTPCR)..........................................................533

24.3 Interface to Bus Master.....................................................................................................534

24.4 Operation...........................................................................................................................535

24.4.1 Software-Triggered A/D Conversion...................................................................535

24.4.2 Hardware- or External-Triggered A/D Conversion .............................................536

24.5 Interrupt Sources...............................................................................................................537

Section 25 Address Trap Controller (ATC).......................................................539

25.1 Overview...........................................................................................................................539

25.1.1 Features................................................................................................................539

25.1.2 Block Diagram.....................................................................................................539

25.1.3 Register Configuration.........................................................................................540

25.2 Register Descriptions........................................................................................................540

25.2.1 Address Trap Control Register (ATCR)..............................................................540

25.2.2 Trap Address Register 2 to 0 (TAR2 to TAR0)...................................................542

25.3 Precautions in Usage.........................................................................................................543

25.3.1 Basic Operations..................................................................................................543

25.3.2 Enabling...............................................................................................................545

25.3.3 Bcc Instruction.....................................................................................................545

25.3.4 BSR Instruction....................................................................................................549

25.3.5 JSR Instruction.....................................................................................................550

25.3.6 JMP Instruction....................................................................................................552

25.3.7 RTS Instruction....................................................................................................553

25.3.8 SLEEP Instruction ...............................................................................................554

25.3.9 Competing Interrupt.............................................................................................558

Section 26 Servo Circuits...................................................................................563

26.1 Overview...........................................................................................................................563

26.1.1 Functions..............................................................................................................563

26.1.2 Block Diagram.....................................................................................................564

Rev. 1.0, 02/01, page xvi of xxii

26.2 Servo Port..........................................................................................................................565

26.2.1 Overview..............................................................................................................565

26.2.2 Block Diagram.....................................................................................................565

26.2.3 Pin Configuration.................................................................................................568

26.2.4 Register Configuration.........................................................................................569

26.2.5 Register Description.............................................................................................569

26.2.6 DFG/DPG Input Signals......................................................................................573

26.3 Reference Signal Generators.............................................................................................574

26.3.1 Overview..............................................................................................................574

26.3.2 Block Diagram.....................................................................................................574

26.3.3 Register Configuration.........................................................................................576

26.3.4 Register Description.............................................................................................577

26.3.5 Operation .............................................................................................................582

26.4 HSW (Head-switch) Timing Generator............................................................................597

26.4.1 Overview..............................................................................................................597

26.4.2 Block Diagram.....................................................................................................597

26.4.3 HSW Timing Generator Configuration................................................................599

26.4.4 Register Configuration.........................................................................................600

26.4.5 Register Description.............................................................................................600

26.4.6 Operation .............................................................................................................614

26.4.7 Interrupts..............................................................................................................620

26.4.8 Cautions...............................................................................................................621

26.5 High-Speed Switching Circuit for Four-Head Special Playback ......................................622

26.5.1 Overview..............................................................................................................622

26.5.2 Block Diagram.....................................................................................................622

26.5.3 Pin Configuration.................................................................................................623

26.5.4 Register Description.............................................................................................623

26.6 Drum Speed Error Detector ..............................................................................................626

26.6.1 Overview..............................................................................................................626

26.6.2 Block Diagram.....................................................................................................626

26.6.3 Register Configuration.........................................................................................628

26.6.4 Register Description.............................................................................................629

26.6.5 Operation .............................................................................................................634

26.6.6 fH Correction in Trick Play Mode.......................................................................636

26.7 Drum Phase Error Detector...............................................................................................637

26.7.1 Overview..............................................................................................................637

26.7.2 Block Diagram.....................................................................................................638

26.7.3 Register Configuration.........................................................................................639

26.7.4 Register Description.............................................................................................640

26.7.5 Operation .............................................................................................................643

26.7.6 Phase Comparison................................................................................................645

26.8 Capstan Speed Error Detector...........................................................................................646

26.8.1 Overview..............................................................................................................646

Rev. 1.0, 02/01, page xvii of xxii

26.8.2 Block Diagram.....................................................................................................647

26.8.3 Register Configuration.........................................................................................648

26.8.4 Register Description.............................................................................................649

26.8.5 Operation .............................................................................................................654

26.9 Capstan Phase Error Detector...........................................................................................656

26.9.1 Overview..............................................................................................................656

26.9.2 Block Diagram.....................................................................................................656

26.9.3 Register Configuration.........................................................................................658

26.9.4 Register Description.............................................................................................659

26.9.5 Operation .............................................................................................................662

26.10 X-Value and Tracking Adjustment Circuit.......................................................................664

26.10.1 Overview..............................................................................................................664

26.10.2 Block Diagram.....................................................................................................664

26.10.3 Register Description.............................................................................................666

26.11 Digital Filters ....................................................................................................................669

26.11.1 Overview..............................................................................................................669

26.11.2 Block Diagram.....................................................................................................670

26.11.3 Arithmetic Buffer .................................................................................................672

26.11.4 Register Configuration .........................................................................................673

26.11.5 Register Description.............................................................................................674

26.11.6 Filter Characteristics............................................................................................682

26.11.7 Operations in Case of Transient Response...........................................................684

26.11.8 Initialization of Z-1..............................................................................................684

26.12 Additional V Signal Generator..........................................................................................686

26.12.1 Overview..............................................................................................................686

26.12.2 Pin Configuration .................................................................................................687

26.12.3 Register Configuration .........................................................................................687

26.12.4 Register Description.............................................................................................687

26.12.5 Additional V Pulse Signal....................................................................................689

26.13 CTL Circuit.......................................................................................................................692

26.13.1 Overview..............................................................................................................692

26.13.2 Block Diagram.....................................................................................................693

26.13.3 Pin Configuration .................................................................................................694

26.13.4 Register Configuration .........................................................................................694

26.13.5 Register Description.............................................................................................695

26.13.6 Operation .............................................................................................................709

26.13.7 CTL Input Section................................................................................................712

26.13.8 Duty Discriminator ..............................................................................................715

26.13.9 CTL Output Section.............................................................................................721

26.13.10 Trapezoid Waveform Circuit ............................................................................724

26.13.11 Note on CTL Interrupt ......................................................................................725

26.14 Frequency Dividers...........................................................................................................726

26.14.1 Overview..............................................................................................................726

Rev. 1.0, 02/01, page xviii of xxii

26.14.2 CTL Frequency Divider.......................................................................................726

26.14.3 CFG Frequency Divider.......................................................................................730

26.14.4 DFG Noise Removal Circuit................................................................................739

26.15 Sync Signal Detector.........................................................................................................741

26.15.1 Overview..............................................................................................................741

26.15.2 Block Diagram.....................................................................................................742

26.15.3 Pin Configuration .................................................................................................743

26.15.4 Register Configuration .........................................................................................743

26.15.5 Register Description.............................................................................................744

26.15.6 Noise Detection....................................................................................................752

26.15.7 Activation of the Sync Signal Detector ................................................................755

26.16 Servo Interrupt..................................................................................................................756

26.16.1 Overview..............................................................................................................756

26.16.2 Register Configuration .........................................................................................756

26.16.3 Register Description.............................................................................................756

Section 27 Sync Separator for OSD and Data Slicer.........................................765

27.1 Overview...........................................................................................................................765

27.1.1 Features................................................................................................................766

27.1.2 Block Diagram.....................................................................................................766

27.1.3 Pin Configuration.................................................................................................768

27.1.4 Register Configuration.........................................................................................768

27.2 Register Description..........................................................................................................769

27.2.1 Sync Separation Input Mode Register (SEPIMR)................................................769

27.2.2 Sync Separation Control Register (SEPCR)........................................................774

27.2.3 Sync Separation AFC Control Register (SEPACR).............................................777

27.2.4 Horizontal Sync Signal Threshold Register (HVTHR)........................................779

27.2.5 Vertical Sync Signal Threshold Register (VVTHR)............................................783

27.2.6 Field Detection Window Register (FWIDR) .......................................................786

27.2.7 H Complement and Mask Timing Register (HCMMR).......................................788

27.2.8 Noise Detection Counter (NDETC).....................................................................790

27.2.9 Noise Detection Level Register (NDETR) ..........................................................791

27.2.10 Data Slicer Detection Window Register (DDETWR)..........................................792

27.2.11 Internal Sync Frequency Register (INFRQR)......................................................794

27.3 Operation...........................................................................................................................795

27.3.1 Selecting Source Signals for Sync Separation .....................................................795

27.3.2 Vsync Separation.................................................................................................801

27.3.3 Hsync Separation.................................................................................................802

27.3.4 Field Detection.....................................................................................................803

27.3.5 Noise Detection....................................................................................................803

27.3.6 Automatic Frequency Controller (AFC)..............................................................804

27.3.7 Module Stop Control Register (MSTPCR)..........................................................809

Rev. 1.0, 02/01, page xix of xxii

Section 28 Data Slicer........................................................................................811

28.1 Overview...........................................................................................................................811

28.1.1 Features................................................................................................................811

28.1.2 Block Diagram.....................................................................................................812

28.1.3 Pin Configuration.................................................................................................813

28.1.4 Register Configuration.........................................................................................814

28.1.5 Data Slicer Use Conditions..................................................................................814

28.2 Register Description..........................................................................................................815

28.2.1 Slice Even- (Odd-) Field Mode Register (SEVFD, SODFD)..............................815

28.2.2 Slice Line Setting Registers 1 to 4 (SLINE1 to SLINE4)....................................819

28.2.3 Slice Detection Registers 1 to 4 (SDTCT1 to SDTCT4) .....................................821

28.2.4 Slice Data Registers 1 to 4 (SDATA1 to SDATA4)............................................824

28.2.5 Module Stop Control Register (MSTPCR)..........................................................825

28.2.6 Monitor Output Setting Register (DOUT)...........................................................826

28.3 Operation...........................................................................................................................827

28.3.1 Slice Line Specification.......................................................................................827

28.3.2 Slice Sequence.....................................................................................................830

28.4 32-Bit Slice Operation ......................................................................................................831

Section 29 On-Screen Display (OSD) ...............................................................835

29.1 Overview...........................................................................................................................835

29.1.1 Features................................................................................................................835

29.1.2 Block Diagram.....................................................................................................837

29.1.3 Pin Configuration.................................................................................................838

29.1.4 Register Configuration.........................................................................................839

29.1.5 TV Formats and Display Modes..........................................................................840

29.2 Description of Display Functions......................................................................................840

29.2.1 Superimposed Mode and Text Display Mode......................................................840

29.2.2 Character Configuration.......................................................................................841

29.2.3 On-Screen Display Configuration........................................................................842

29.3 Settings in Character Units................................................................................................843

29.3.1 Character Configuration.......................................................................................843

29.3.2 Character Colors ..................................................................................................843

29.3.3 Halftones/Cursors ................................................................................................844

29.3.4 Blinking ...............................................................................................................845

29.3.5 Button Display.....................................................................................................846

29.3.6 Character Data ROM (OSDROM).......................................................................847

29.3.7 Display Data RAM (OSDRAM)..........................................................................849

29.4 Settings in Row Units .......................................................................................................854

29.4.1 Button Patterns.....................................................................................................854

29.4.2 Display Enlargement............................................................................................854

29.4.3 Character Brightness............................................................................................854

Rev. 1.0, 02/01, page xx of xxii

29.4.4 Cursor Color, Brightness, Halftone Levels..........................................................854

29.4.5 Row Registers (CLINEn, n = rows 1 to 12).........................................................856

29.5 Settings in Screen Units....................................................................................................861

29.5.1 Display Positions .................................................................................................861

29.5.2 Turning the OSD Display On and Off.................................................................862

29.5.3 Display Method....................................................................................................862

29.5.4 Blinking Period....................................................................................................862

29.5.5 Borders.................................................................................................................863

29.5.6 Background Color and Brightness.......................................................................863

29.5.7 Character, Cursor, and Background Chroma Saturation......................................863

29.5.8 Display Position Registers (HPOS and VPOS)....................................................864

29.5.9 Screen Control Register (DCNTL) ......................................................................866

29.6 Other Settings....................................................................................................................871

29.6.1 TV Format............................................................................................................871

29.6.2 Display Data RAM Control .................................................................................871

29.6.3 Timing of OSD Display Updates Using Register Rewriting ...............................871

29.6.4 4fsc/2fsc...............................................................................................................871

29.6.5 OSDV Interrupts..................................................................................................871

29.6.6 OSD Format Register (DFORM).........................................................................872

29.7 Digital Output ...................................................................................................................876

29.7.1 R, G, and B Outputs.............................................................................................876

29.7.2 YCO and YBO Outputs .......................................................................................879

29.7.3 Digital Output Specification Register (DOUT) ...................................................880

29.7.4 Module Stop Control Register (MTSTPCR)........................................................882

29.8 Notes on OSD Font Creation ............................................................................................884

29.8.1 Note 1 on Font Creation (Fon t Width).................................................................884

29.8.2 Note 2 on Font Creation (Borders) ......................................................................884

29.8.3 Note 3 on Font Creation (Blinking).....................................................................886

29.8.4 Note 4 on Font Creation (Buttons).......................................................................887

29.9 OSD Oscillator, AFC, and Dot Clock...............................................................................888

29.9.1 Sync Signals.........................................................................................................888

29.9.2 AFC Circuit..........................................................................................................888

29.9.3 Dot Clock.............................................................................................................888

29.9.4 4/2fsc....................................................................................................................889

29.10 OSD Operation in CPU Operation Modes........................................................................891

29.11 Character Data ROM (OSDROM) Access by CPU..........................................................892

29.11.1 Serial Timer Control Register (STCR) ................................................................892

Section 30 Power Supply Circuit.......................................................................893

30.1 Overview...........................................................................................................................893

30.2 Power Supply Connection (Internal Power Supply Step-Down Circuit On-Chip) ...........893

Rev. 1.0, 02/01, page xxi of xxii

Section 31 Electrical Characteristics .................................................................895

31.1 Absolute Maximum Ratings .............................................................................................895

31.2 Electrical Characteristics of HD6432199R, HD6432198R, HD6432197R, and

HD6432196R....................................................................................................................896

31.2.1 DC Characteristics of HD6432199R, HD6432198R, HD6432197R, and

HD6432196R.......................................................................................................896

31.2.2 Allowable Output Currents of HD6432199R, HD6432198R, HD6432197R, and

HD6432196R.......................................................................................................903

31.2.3 AC Characteristics of HD6432199R, HD6432198R, HD6432197R, and

HD6432196R.......................................................................................................904

31.2.4 Serial Interface Timing of HD6432199R, HD6432198R, HD6432197R, and

HD6432196R.......................................................................................................907

31.2.5 A/D Converter Characteristics of HD6432199R, HD6432198R, HD6432197R, and

HD6432196R.......................................................................................................911

31.2.6 Servo Section Electrical Characteristics of HD6432199R, HD6432198R,

HD6432197R, and HD6432196R........................................................................912

31.2.7 OSD Electrical Characteristics of HD6432199R, HD6432198R, HD6432197R, and

HD6432196R.......................................................................................................914

31.3 Electrical Characteristics of HD6432197S and HD6432196S..........................................918

31.3.1 DC Characteristics of HD6432197S and HD6432196S - Preliminary -..............918

31.3.2 Allowable Output Currents of HD6432197S and HD6432196S .........................925

31.3.3 AC Characteristics of HD6432197S and HD6432196S.......................................926

31.3.4 Serial Interface Timing of HD6432197S and HD6432196S................................929

31.3.5 A/D Converter Characteristics of HD6432197S and HD6432196S ....................933

31.3.6 Servo Section Electrical Characteristics of HD6432197S and HD6432196S......934

31.3.7 OSD Electrical Characteristics of HD6432197S and HD6432196S....................936

31.4 Electrical Characteristics of HD64F2199R.......................................................................940

31.4.1 DC Characteristics of HD64F2199R ...................................................................940

31.4.2 Allowable Output Currents of HD64F2199R......................................................947

31.4.3 AC Characteristics of HD64F2199R ...................................................................948

31.4.4 Serial Interface Timing of HD64F2199R ............................................................951

31.4.5 A/D Converter Characteristics of HD64F2199R.................................................955

31.4.6 Servo Section Electrical Characteristics of HD64F2199R...................................956

31.4.7 OSD Electrical Characteristics of HD64F2199R.................................................958

31.4.8 Flash Memory Characteristics .............................................................................962

Appendix A Instruction Set ...............................................................................965

A.1 Instructions........................................................................................................................965

A.2 Instruction Codes..............................................................................................................976

A.3 Operation Code Map.........................................................................................................986

A.4 Number of Execution States..............................................................................................990

A.5 Bus Status during Instruction Execution.........................................................................1000

Rev. 1.0, 02/01, page xxii of xxii

A.6 Change of Condition Codes............................................................................................ 1014

Appendix B Internal I/O Registers.................................................................1019

B.1 Addresses........................................................................................................................1019

B.2 Function List...................................................................................................................1028

Appendix C Pin Circuit Diagrams..................................................................1159

C.1 Pin Circuit Diagrams.......................................................................................................1159

Appendix D Port States in Each Processing State..........................................1173

D.1 Pin Circuit Diagrams....................................................................................................... 1173

Appendix E Usage Notes................................................................................1174

E.1 Power Supply Rise and Fall Order..................................................................................1174

E.2 Sample External Circuits ................................................................................................ 117 6

E.3 Handling of Pins When OSD Is Not Used......................................................................1181

Appendix F Product Lineup ...........................................................................1182

Appendix G Package Dimensions..................................................................1183

Rev. 1.0, 02/01, page 1 of 1184

Section 1 Overview

1.1 Overview

The H8S/2199R Series comprises microcomputers (MCUs) built around the H8S/2000 CPU,

adopting Hitachi's proprietary architecture, and equipped with on-chip supporting modules.

The H8S/2000 has an internal 32-bit architecture, is provided with sixteen 16-bit general registers

and a concise, optimized instruction set designed for high-speed operation, and can address a 16-

Mbyte linear address space.

The H8S/2199R Series is equipped with a digital servo circuit, sync separator, OSD, data slicer,

ROM, RAM, seven types of timers, three types of PWM, two types of serial communication

interface, an I2C bus interface, A/D converter, and I/O port as on-chip supporting modules.

The on-chip ROM is either flash memory (F-ZTAT*) or mask ROM, with a capacity of 256,

128, 112, 96, or 80 kbytes. ROM is connected to the CPU via a 16-bit data bus, enabling both

byte and word data to be accessed in one state. Instruction fetching has been speeded up, and

processing speed increased.

Using the H8S/2199R Series can implement a system suitable for VTR control. This manual

describes the H8S/2199R Series hardware. For details on instructions, see the H8S/2600 and

H8S/2000 Series Programming Manual.

Note: * F-ZTAT is a trademark of Hitachi, Ltd.

Rev. 1.0, 02/01, page 2 of 1184

Table 1.1 Features of the H8S/2199R Series

Item Specifications

CPU • General-register architecture

 Sixteen 16-bit general registers (also usable as sixteen 8-bit registers

or eight 32-bit registers)

• High-speed operation suitable for real-time control

 Maximum operating frequency: 10 MHz/4 to 5.5 V

 High-speed arithmetic operations

8/16/32-bit register-register add/subtract: 100 ns (10-MHz operation)

16 × 16-bit register-register multiply: 2000 ns (10-MHz operation)

32 ÷ 16-bit register-register divide: 2000 ns (10-MHz operation)

• Instruction set suitable for high-speed operation

 Sixty-five basic instructions

 8/16/32-bit transfer/arithmetic and logic instructions

 Unsigned/signed multiply and divide instructions

 Powerful bit-manipulation instructions

• CPU operating modes

 Advanced mode: 16-Mbyte address space

Timer • Seven types of timer are incorporated

 Timer A

• 8-bit interval timer

• Clock source can be selected among 8 types of internal clock of

which frequencies are divided from the system clock (φ) and

subclock (φSUB)

• Functions as clock time base by subclock input

 Timer B

• Functions as 8-bit interval timer or reload timer

• Clock source can be selected among 7 types of internal clock or

external event input

 Timer J

• Functions as two 8-bit down counters or one 16-bit down counter

(reload timer/event counter timer/timer output, etc., 5 types of

operation modes)

• Remote controlled transmit function

• Take up/Supply Reel Pulse Frequency division

Rev. 1.0, 02/01, page 3 of 1184

Item Specifications

Timer  Timer L

• 8-bit up/down counter

• Clock source can be selected among 2 types of internal clock, CFG

frequency division signal, and PB and REC-CTL (control pulse)

• Compare-match clearing function/auto reload function

 Timer R

• Three reload timers

• Mode discrimination

• Reel control

• Capstan motor acceleration/deceleration detection function

• Slow tracking mono-multi

 Timer X1 (except for the H8S/2197S and H8S/2196S)

• 16-bit free-running counter

• Clock source can be selected among 3 types of internal clock and

DVCFG

• Two output compare outputs

• Four input capture inputs

 Watchdog timer

• Functions as watchdog timer or 8-bit interval timer

• Generates reset signal or NMI at overflow

Prescaler unit  Divides system clock frequency and generates frequency division

clock for supporting module functions

 Divides subclock frequency and generates input clock for Timer A

(clock time base)

 Generates 8-bit PWM frequency and duty period

 8-bit input capture at external signal edge

 Frequency division clock output enabled

PWM • Three types of PWM are incorporated

 14-bit PWM: Pulse resolution type x 1 channel (except for the

H8S/2197S and H8S/2196S)

 8-bit PWM: Duty control type x 4 channels (H8S/2197S and

H8S/2196S : 2 channel)

 12-bit PWM: Pulse pitch control type x 2 channels

Rev. 1.0, 02/01, page 4 of 1184

Item Specifications

Serial

communication

interface (SCI)

 Asynchronous mode or synchronous mode selectable

 Desired bit rate selectable with built-in baud rate generator

 Multiprocessor communication function

I2C bus interface

(2 channels)

(H8S/2197S and

H8S/2196S :

1 channel)

 Conforms to Phillips I2C bus interface standard

 Start and stop conditions generated automatically

 Selection of acknowledge output levels when receiving, and automatic

loading of acknowledge bit when transmitting

 Selection of acknowledgement mode or serial mode (without

acknowledge bit)

A/D converter  Resolution: 10 bits

 Input: 12 channels

 High-speed conversion: 13.4 µs minimum conversion time (10 MHz

operation)

 Sample-and-hold function

 A/D conversion can be activated by software or external trigger

Address trap

controller  Interrupt occurs when the preset address is found during bus cycle

 To-be-trapped addresses can be individually set at three different

locations

I/O port  56 input/output pins

 8 input-only pins

 Can be switched for each supporting module

Servo circuit • Digital servo circuits on-chip

 Input and output circuits

 Error detection circuit

 Phase and gain compensation

Sync signal

(servo) • On-chip sync signal detection circuit

 Can separately detect horizontal and vertical sync signals

 Noise detection function

Sync separator

for OSD and data

slicer

• Sync separator including AFC

 Horizontal and vertical sync signals separated from the composite

video signal

 Noise detection

 Selection of sync separation methods

Rev. 1.0, 02/01, page 5 of 1184

Item Specifications

OSD (On Screen

Display)  Screen of 32 characters × 12 lines

 384 types of characters (H8S/2199R F-ZTAT : 512 types of characters

H8S/2197S and H8S/2196S : 256 types of characters)

 Character configuration: 12 dots × 18 lines

 Character colors: Eight hues

 Background colors: Eight hues

 Cursor colors: Eight hues

 Halftone display

 Button display

Data slicer  Slice lines: Four lines (H8S/2197S and H8S/2196S : two lines)

 Slice levels: Seven levels

 Sampling clock generated by AFC

 Slice interrupt

 Error detection

 Flash memory or mask ROM (Refer to the product line-up)

 High-speed static RAM

Product Name ROM RAM

H8S/2199R 128 k (256 k*)

bytes 4 k (8 k*) bytes

H8S/2198R 112 k bytes 4 k bytes

H8S/2197R 96 k bytes

H8S/2196R 80 k bytes

4 k bytes

H8S/2197S 96 k bytes

H8S/2196S 80 k bytes

3 k bytes

Memory

Power-down

state  Medium-speed mode

 Sleep mode

 Module stop mode

 Standby mode

 Subclock operation

Subactive mode, watch mode, subsleep mode

Interrupt

controller  Six external interrupt pins (IRQ5 to IRQ0)

 44 internal interrupt sources (H8S/2197S and H8S/2196S : 35 internal

interrupt sources)

 Three priority levels settable

Rev. 1.0, 02/01, page 6 of 1184

Item Specifications

Clock pulse

generator • Two types of clock pulse generator on-chip

 System clock pulse generator: 8 to 10 MHz

 Subclock pulse generator: 32.768 kHz

Packages  112-pin plastic QFP (FP-112)

Product Code

Series Mask ROM

Versions F-ZTAT

Versions ROM/RAM

(bytes)

Packages

H8S/2199R HD6432199R HD64F2199R 128 k/4 k

(256 k*/

8 k*)

FP-112

HD6432198R  112 k/4 k FP-112

HD6432197R  96 k/4 k FP-112

HD6432196R  80 k/4 k FP-112

HD6432197S  96 k/3 k FP-112

HD6432196S  80 k/3 k FP-112

Product lineup

Note: * F-ZTAT version

Rev. 1.0, 02/01, page 7 of 1184

1.2 Internal Block Diagram

Figure 1.1 shows an internal block diagram of the H8S/2199R Series.

P23/SDA1

P25/SDA0

P22/SCK1

P26/SCL0

P21/SO1

P27/SYNCI

P20/SI1

P24/SCL1

VCL

MD0

RES

OSC2

OSC1

Hsync(Csync) Sync signal

detection

CAPPWM

CTL(+)

CTLSMT(i)

CTLBias

CVin2

Csync/Hsync

VLPF/Vsync

CTL(–)

AUDIO FF

VIDEO FF

Vpulse

CTL FB

CTL REF

CTLAmp(o)

DFG

CFG

DRMPWM

DPG

P13/IRQ3

P15/IRQ5

P12/IRQ2 Interrupt

controller

R A M

R O M

Internal data bus

External data bus

External address bus

External data bus

External address bus

Internal address bus

Servo pins (CTL input/output

amplifier, three-level output, etc.)

CVin1

CVout

OSD

(Analog input/output) Sync

separation

Sub-carrier

oscillator

AFC

H8S/2000 CPU

Bus

controller

Address trap

controller

P16/IC

P11/IRQ1

P17/TMOW

P10/IRQ0

P14/IRQ4

P03/AN3

P05/AN5

P02/AN2

P06/AN6

P01/AN1

P07/AN7

P00/AN0

P04/AN4

ANA

AN9

AN8

ANB

P83/C.Rotary/R

P85/COMP/B

P82/EXCTL

P86/EXTTRG

P81/EXCAP/YBO

P87/DPG

P80/YCO

P84/H.Amp SW/G

P33/PWM1

P35/PWM3

P32/PWM0

P36/BUZZ

P31/SV2

P37/TMO

P30/SV1

P34/PWM2

P43/FTIC

P45/FTOA

P42/FTIB

P46/FTOB

P41/FTIA

P47/RPTRG

P40/PWM14

P44/FTID

P73/PPG3

P75/PPG5/RP9

P72/PPG2

P76/PPG6/RPA

P71/PPG1

P77/PPG7/RPB

P70/PPG0

P74/PPG4/RP8

4fscout/2fscout

AFC pc

AFC osc

AFC LPF

4fscin/2fscin

P63/RP3

P65/RP5

P62/RP2

P66/RP6/ADTRG

P61/RP1

P67/RP7/TMBI

P60/RP0

P64/RP4

14-bit PWM

12-bit PWM

8-bit PWM Prescaler unit

Watchdog

timer

Timer L

Timer A

SCI1 Timer B

Timer J

C bus

interface

Timer R

A/D converter Timer X1

Port 7 Port 6 Port 4 Port 3

Port 2Port 1Port 0Port 8 Analog

port

Subclock pulse

generator

Subclock pulse

pulse generator

Servo circuit Data slicer

OSD

Figure 1.1 Internal Block Diagram of H8S/2199R Series (except for the H8S/2197S and

H8S/2196S)

Rev. 1.0, 02/01, page 8 of 1184

Figure 1.2 shows an internal block diagram of the H8S/2197S and H8S/2196S.

P23/SDA1

P25

P22/SCK1

P26

P21/SO1

P27

P20/SI1

P24/SCL1

VSS

VCL

VSS

VCC

VSS

VCC

MD0

RES

OSC2

OSC1

Hsync(Csync) Sync signal

detection

SVSS

SVCC

CAPPWM

CTL(+)

CTLSMT(i)

CTLBias

CVin2

Csync/Hsync

VLPF/Vsync

CTL(–)

AUDIO FF

VIDEO FF

Vpulse

CTL FB

CTL REF

CTLAmp(o)

DFG

CFG

DRMPWM

DPG

P13/IRQ3

P15/IRQ5

P12/IRQ2 Interrupt

controller

R A M

R O M

Internal data bus

External data bus

External address bus

External data bus

External address bus

Internal address bus

Servo pins (CTL input/output

amplifier, three-level output, etc.)

CVin1

CVout

OSD

(Analog input/output) Sync

separation

Sub-carrier

oscillator

AFC

H8S/2000 CPU

Bus

controller

Address trap

controller

P16/IC

P11/IRQ1

P17/TMOW

P10/IRQ0

P14/IRQ4

P03/AN3

P05/AN5

P02/AN2

P06/AN6

P01/AN1

P07/AN7

P00/AN0

P04/AN4

ANA

AN9

AN8

ANB

AVCC

AVSS

P83/C.Rotary/R

P85/COMP/B

P82/EXCTL

P86/EXTTRG

P81/EXCAP/YBO

P87/DPG

P80/YCO

P84/H.Amp SW/G

P33/PWM1

P35

P32/PWM0

P36/BUZZ

P31/SV2

P37/TMO

P30/SV1

P34

P43

P45

P42

P46

P41

P47/RPTRG

P40

P44

P73/PPG3

P75/PPG5/RP9

P72/PPG2

P76/PPG6/RPA

P71/PPG1

P77/PPG7/RPB

P70/PPG0

P74/PPG4/RP8

4fscout/2fscout

AFC pc

AFC osc

AFC LPF

4fscin/2fscin

P63/RP3

P65/RP5

P62/RP2

P66/RP6/ADTRG

P61/RP1

P67/RP7/TMBI

P60/RP0

P64/RP4

12-bit PWM

8-bit PWM Prescaler unit

Watchdog

timer

Timer L

Timer A

SCI1 Timer B

Timer J

I2C bus

interface

Timer R

A/D converter

Port 7 Port 6 Port 4 Port 3

Port 2Port 1Port 0Port 8 Analog

port

Subclock pulse

generator

Subclock pulse

pulse generator

Servo circuit

Data slicer

OSD

Figure 1.2 Internal Block Diagram of the H8S/2197S and H8S/2196S

Rev. 1.0, 02/01, page 9 of 1184

1.3 Pin Arrangement and Functions

1.3.1 Pin Arrangement

Figure 1.3 shows the pin arrangement of the H8S/2199R Series.

P33/PWM1

P34/PWM2

MD0

VCL

OSC2

OSC1

RES

FWE

P40/PWM14

P41/FTIA

P42/FTIB

P43/FTIC

P44/FTID

P45/FTOA

P46/FTOB

P47/RPTRG

P21/SO1

P20/SI1

P22/SCK1

P23/SDA1

P24/SCL1

P25/SDA0

P26/SCL0

P27/SYNCI

P32/PWM0

P31/SV2

P30/SV1

P70/PPG0

P71/PPG1

P72/PPG2

P73/PPG3

P74/PPG4/RP8

P75/PPG5/RP9

P76/PPG6/RPA

P77/PPG7/RPB

P80/YCO

P81/EXCAP/YBO

P82/EXCTL

P83/C.Rotary/R

P84/H.Amp SW/G

P85/COMP/B

P86/EXTTRG

P87/DPG

DFG

VIDEO FF

AUDIO FF

DRM PWM

CAP PWM

Vpulse

Csync

P35/PWM3

P36/BUZZ

P37/TMO

P60/RP0

P61/RP1

P62/RP2

P63/RP3

P64/RP4

P65/RP5

P66/RP6/ADTR

P67/RP7/TMBI

P17/TMOW

P16/IC

P15/IRQ5

P14/IRQ4

P13/IRQ3

P12/IRQ2

P11/IRQ1

P10/IRQ0

P00/AN0

P01/AN1

P02/AN2

P03/AN3

P04/AN4

P05/AN5

P06/AN6

1SV

FP-112

(Top view)

2CTLREF 83

3CTL(+) 82

4CTL(–) 81

5CTLBias 80

6CTLFB 79

7CTLAmp(o) 78

8CTLSMT(i) 77

9CFG 76

10SV

11AFCpc 74

12AFCosc 73

13AFCLPF 72

14Csync/Hsync 71

15VLPF/Vsync 70

16CVin2 69

17CVin1 68

18OV

19CVout 66

20OV

214fscout/2fscout 64

224fscin/2fscin 63

ANB 61

25ANA 60

26AN9 59

27AN8 58

28P07/AN7 57

100

101

102

103

104

105

106

107

108

109

110

111

112

Figure 1.3 Pin Arrangement of H8S/2199R Series (except for the H8S/2197S and

H8S/2196S)

Rev. 1.0, 02/01, page 10 of 1184

Figure 1.4 shows the pin arrangement of the H8S/2197S and H8S/2196S.

P33/PWM1

P34

MD0

VCL

OSC2

OSC1

RES

P40

P41

P42

P43

P44

P45

P46

P47/RPTRG

P21/SO1

P20/SI1

P22/SCK1

P23/SDA1

P24/SCL1

P25

P26

P27

P32/PWM0

P31/SV2

P30/SV1

P70/PPG0

P71/PPG1

P72/PPG2

P73/PPG3

P74/PPG4/RP8

P75/PPG5/RP9

P76/PPG6/RPA

P77/PPG7/RPB

P80/YCO

P81/EXCAP/YBO

P82/EXCTL

P83/C.Rotary/R

P84/H.Amp SW/G

P85/COMP/B

P86/EXTTRG

P87/DPG

DFG

VIDEO FF

AUDIO FF

DRM PWM

CAP PWM

Vpulse

Csync

P35

P36/BUZZ

P37/TMO

P60/RP0

P61/RP1

P62/RP2

P63/RP3

P64/RP4

P65/RP5

P66/RP6/ADTR

P67/RP7/TMBI

P17/TMOW

P16/IC

P15/IRQ5

P14/IRQ4

P13/IRQ3

P12/IRQ2

P11/IRQ1

P10/IRQ0

P00/AN0

P01/AN1

P02/AN2

P03/AN3

P04/AN4

P05/AN5

P06/AN6

1SV

FP-112

(Top view)

2CTLREF 83

3CTL(+) 82

4CTL(–) 81

5CTLBias 80

6CTLFB 79

7CTLAmp(o) 78

8CTLSMT(i) 77

9CFG 76

10SV

11AFCpc 74

12AFCosc 73

13AFCLPF 72

14Csync/Hsync 71

15VLPF/Vsync 70

16CVin2 69

17CVin1 68

18OV

19CVout 66

20OV

214fscout/2fscout 64

224fscin/2fscin 63

ANB 61

25ANA 60

26AN9 59

27AN8 58

28P07/AN7 57

100

101

102

103

104

105

106

107

108

109

110

111

112

Figure 1.4 Pin Arrangement of H8S/2197S and H8S/2196S

Rev. 1.0, 02/01, page 11 of 1184

1.3.2 Pin Functions

Table 1.2 summarizes the functions of the H8S/2199R Series pins.

Table 1.2 Pin Functions

Type Symbol Pin No. I/O Name and Function

VCC 56, 112 Input Power supply:

All Vcc pins should be connected to the system

power supply (+5V)

VSS 57, 79,

110 Input Ground:

All Vss pins should be connected to the system

power supply (0V)

SVCC 10 Input Servo power supply:

SVcc pin should be connected to the servo

analog power supply (+5V)

SVSS 1 Input Servo ground:

SVss pin should be connected to the servo

analog power supply (0V)

AVCC 36 Input Analog power supply:

Power supply pin for A/D converter. It should be

connected to the system power supply (+5V)

when the A/D converter is not used

AVSS 23 Input Analog ground:

Ground pin for A/D converter. It should be

connected to the system power supply (0V)

OVCC 18 Input OSD power supply:

OVCC should be connected to the OSD analog

power supply (+5 V)

OVSS 20 Input OSD ground:

OVSS should be connected to the OSD analog

power supply (0 V)

Power

supply

VCL 81 Input Smoothing capacitor connection:

Connect 0.1-µF power-smoothing capacitance

between VCL and VSS

OSC1 78 Input

OSC2 80 Output

Connected to a crystal oscillator. It can also

input an external clock. See section 9, Clock

Pulse Generator, for typical connection diagrams

for a crystal oscillator and external clock input

X1 76 Input

Clock

X2 75 Output

Connected to a 32.768 kHz crystal oscillator.

See section 9, Clock Pulse Generator, for typical

connection diagrams

Rev. 1.0, 02/01, page 12 of 1184

Type Symbol Pin No. I/O Name and Function

Operating

mode

control

MD0 82 Input Mode pin:

This pin sets the operating mode. This pin

should not be changed while the MCU is in

operation

RES 77 Input Reset input:

When this pin is driven low, the chip is reset

System

control

FWE 74 Input Flash memory enable:

Enables/disables flash memory programming.

This pin is available only with MCU with flash

memory on -chip.

IRQ0 37 Input External interrupt request 0:

External interrupt input pin for which rising edge

sense, falling edge sense or both edges sense

are selectable

Interrupts

IRQ1

IRQ2

IRQ3

IRQ4

IRQ5

Input External interrupt requests 1 to 5:

External interrupt input pins for which rising or

falling edge sense are selectable

IC 43 Input Input capture input:

Input capture input pin for prescaler unit

Prescaler

unit

TMOW 44 Output Frequency division clock output:

Output pin for clock of which frequency is divided

by prescaler

TMBI 45 Input Timer B event input:

Input pin for events to be input to Timer B counter

IRQ1

IRQ2 38

39 Input Timer J event input:

Input pin for events to be input to Timer J RDT-

1or RDT-2 counter

TMO 53 Output Timer J timer output:

Output pin for toggle at underflow of RDT-1 of

Timer J, or remote controlled transmit data

Timers

BUZZ 54 Output Timer J buzzer output:

Output pin for toggle which is selectable among

fixed frequency, 1Hz frequency divided from

subclock (32 kHz), and frequency division CTL

signal

Rev. 1.0, 02/01, page 13 of 1184

Type Symbol Pin No. I/O Name and Function

IRQ3 40 Input Timer R input capture:

Input pin for input capture of Timer R TMRU-1 or

TMRU-2

FTOA*

FTOB* 68

67 Output Timer X1 output compare A and B output:

Output pin for output compare A and B of Timer

Timers

FTIA*

FTIB*

FTIC*

FTID*

Input Timer X1 input capture A, B, C and D input:

Input pin for input capture A, B, C and D of Timer

PWM0

PWM1

PWM2*

PWM3*

Output 8-bit PWM square waveform output:

Output pin for waveform generated by 8-bit PWM

0, 1, 2 and 3

PWM

PWM14* 73 Output 14-bit PWM square waveform output:

Output pin for waveform generated by 14-bit

PWM

SCK1 63 Input

/output SCI clock input/output:

Clock input pins for SCI 1

SI1 65 Input SCI receive data input:

Receive data input pins for SCI 1

Serial

commu-

nication

interface

(SCI) SO1 64 Output SCI transmit data output:

Transmit data output pins for SCI 1

SCL0*

SCL1 59

61 Input

/output I2C bus interface clock input/output:

Clock input/output pin for I2C bus interface

SDA0*

SDA1 60

62 Input

/output I2C bus interface data input/output:

Data input/output pin for I2C bus interface

I2C bus

interface

SYNCI* 58 Input I2C bus interface clock input:

I2C formatless serial clock input

Rev. 1.0, 02/01, page 14 of 1184

Type Symbol Pin No. I/O Name and Function

AN7 to

AN0 28 to 35 Input Analog input channels 7 to 0:

Analog data input pins. A/D conversion is

started by a software triggering

AN8

AN9

ANA

ANB

Input Analog input channels 8, 9, A and B:

Analog data input pins. A/D conversion is

started by an external trigger, a hardware trigger,

or software

A/D

converter

ADTRG 46 Input A/D conversion external trigger input:

A/D conversion for analog data input pins 8, 9, A,

and B is started by an external trigger

AUDIO FF 106 Output Audio FF:

Output pin for audio head switching signal

VIDEO FF 105 Output Video FF:

Output pin for video head switching signal

CAPPWM 108 Output Capstan mix:

12-bit PWM output pin giving result of capstan

speed error and phase error after filtering

DRMPWM 107 Output Drum mix:

12-bit PWM output pin giving result of drum

speed error and phase error after filtering

Vpulse 109 Output Additional V pulse:

Three-level output pin for additional V signal

synchronized to the VIDEO FF signal

C.Rotary 99 Output Color rotary signal:

Output pin for color signal processing control

signal in four-head special-effects playback

H.AmpSW 100 Output Head-amp switch:

Output pin for preamplifier output select signal in

four-head special-effects playback.

COMP 101 Input Compare input:

Input pin for signal giving the result of

preamplifier output comparison in four-head

special-effects playback.

CTL (+)

CTL (-) 3

4 Input

/output CTL head (+) and (-) pins:

I/O pins for CTL signals

Servo

circuits

CTL Bias 5 Input CTL primary amp bias supply:

Bias supply pin for CTL primary amp

Rev. 1.0, 02/01, page 15 of 1184

Type Symbol Pin No. I/O Name and Function

CTL Amp

(o) 7 Output CTL amp output:

Output pin for CTL amp

CTL SMT

(l) 8 Input CTL Schmitt amp input:

Input pin for CTL Schmitt amp

CTLFB 6 Input CLT feedback input:

Input pin for CTL amp high-range characteristics

control

CTLREF 2 Output CTL amp reference voltage output:

Output pin for 1/2Vcc (SV)

CFG 9 Input Capstan FG input:

Schmitt comparator input pin for CFG signal

DFG 104 Input Drum FG input:

Schmitt input pin for DFG signal

DPG 103 Input Drum PG input:

Schmitt input pin for DPG signal

EXCTL 98 Input External CTL input:

Input pin for external CTL signal

Csync 111 Input Mixed sync signal input:

Input pin for mixed sync signal

EXCAP 97 Input Capstan external sync signal input:

Signal input pin for external synchronization of

capstan phase control

EXTTRG 102 Input External trigger signal input:

Signal input pin for synchronization with

reference signal generator

SV1 87 Output Servo monitor output pin 1:

Output pin for servo module internal signal

SV2 86 Output Servo monitor output pin 2:

Output pin for servo module internal signal

Servo

circuits

PPG7 to

PPG0 95 to 88 Output PPG:

Output pin for HSW timing generator. To be

used when head switching is required as well as

AUDIO FF and VIDEO FF

Rev. 1.0, 02/01, page 16 of 1184

Type Symbol Pin No. I/O Name and Function

Csync/

Hsync 14 Input/

output Sync signal input/output:

Composite sync signal input/output or horizontal

sync signal input

VLPF/

Vsync 15 Input Sync signal input:

Pin for connecting external LPF for vertical sync

signal or input pin for vertical sync signal

AFC pc 11 Input/

output AFC oscillation:

Pin for connecting external circuit for AFC

oscillation

AFC osc 12 Input/

output AFC oscillation:

Pin for connecting external circuit for AFC

oscillation

AFC LPF 13 Input/

output Pin for connecting external LPF for AFC

4 fsc in/

2 fsc in 22 Input fsc oscillation:

Input pin for subcarrier oscillator. 4fsc or 2fsc

can be selected

fsc: Subcarrier frequency

4 fsc out/

2 fsc out 21 Output fsc oscillation:

Output pin for subcarrier oscillator. 4fsc or 2fsc

can be selected

fsc: Subcarrier frequency

Sync

separator

CVin2 16 Input Composite video input:

Composite video signal input. Input 2-Vp-p

composite video signal, and the sync tip of the

signal is clamped to about 2.0 V

CVin1 17 Input Composite video input:

Composite video signal input for OSD. Input 2-

Vp-p composite video signal, and the sync tip of

the signal is clamped to about 1.4 V

CVout 19 Output Composite video output:

Composite video signal output for OSD. 2-Vp-p

composite video signal is output

R 99 Output OSD digital output:

Color signal R output

G 100 Output OSD digital output:

Color signal G output

OSD

B 101 Output OSD digital output:

Color signal B output

Rev. 1.0, 02/01, page 17 of 1184

Type Symbol Pin No. I/O Name and Function

OSD YCO 96 Output OSD digital output:

Character data output

YBO 97 Output OSD digital output:

Character display position output

Data

slicer CVin2 16 Input Composite video input:

Composite video signal input. Input 2-Vp-p

composite video signal, and the sync tip of the

signal is clamped to about 2.0 V.

P07 to P00 28 to 35 Input Port 0:

8-bit input pins

P17 to P10 44 to 37 Input

/output Port 1:

8-bit I/O pins

P27 to P20 58 to 65 Input

/output Port 2:

8-bit I/O pins

P37 to P30 53 to 55

83 to 87 Input

/output Port 3:

8-bit I/O pins

P47 to P40 66 to 73 Input

/output Port 4:

8-bit I/O pins

P67 to P60 45 to 52 Input

/output Port 6:

8-bit I/O pins

P77 to P70 95 to 88 Input

/output Port 7:

8-bit I/O pins

P87 to P80 103 to

96 Input

/output Port 8:

8-bit I/O pins

RP7 to RP0 45 to 52 Output Realtime output port:

8-bit realtime output pins

RPB to

RP8 95 to 92 Output Realtime output port:

4-bit realtime output pins

I/O port

RPTRG 66 Input Realtime output port trigger input:

Input pin for realtime output port trigger

Note: * Not available in the H8S/2197S or H8S/2196S.

Rev. 1.0, 02/01, page 18 of 1184

Rev. 1.0, 02/01, page 19 of 1184

Section 2 CPU

2.1 Overview

The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that

is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-

bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is

ideal for realtim e co ntrol.

2.1.1 Features

The H8S/2000 CPU has the following features.

• Upward-compatible with H8/300 and H8/300H CPUs

Can execute H8/300 and H8/300H object programs

• General-register architecture

Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)

• Sixty-five basic instructions

8/16/32-bit arithmetic and logic instructions

Multiply and divide instr uctions

Powerful bit-manipulation instructions

• Eight addressing modes

Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]

Immediate [#xx:8, #xx:16, or #xx:32]

Program-counter relative [@(d:8,PC) or @(d:16,PC)]

Memory indirect [@@aa:8]

• 16-Mbyte address space

Program: 16 Mbytes

Data: 16 Mbytes (4 Gbytes architecturally)

• High-speed operation

All frequently-used in structions execu te in one or two states

Maximum clock rate: 10 MHz

8/16/32-bit register-register add/subtract: 100 ns

8 × 8-bit register-register multiply: 1200 ns

Rev. 1.0, 02/01, page 20 of 1184

16 ÷ 8-bit register-register divide: 1200 ns

16 × 16-bit register-register multiply: 2000 ns

32 ÷ 16-bit register-register divide: 2000 ns

• Two CPU operating modes

Normal mode*/Advanced mode

• Power-down state

Transition to power-down state by SLEEP instruction

CPU clock speed selection

Note: * Normal mode is no t available for this LSI.

2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU

The differences between the H8S/2600 CPU and the H8S/2000 CPU are shown below.

• Register configuration

The MAC register is supported only by the H8S/2600 CPU.

• Basic instructions

The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the

H8S/2600 CPU.

• Number of execution states

The number of execution states of the MULXU and MULXS instructions differ as follows.

Number of Execution States

Instruction

Mnemonic H8S/2600 H8S/2000

MULXU.B Rs, Rd 3 12 MULXU

MULXU.W Rs, Erd 4 20

MULXS.B Rs, Rd 4 13 MULXS

MULXS.W Rs, Erd 5 21

There are also differences in the address space, EXR register functions, power-down state, etc.,

depending on the product.

2.1.3 Differences from H8/300 CPU

In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements.

• More general registers and control registers

Eight 16-bit extended registers, and one 8-bit control register, have been added.

Rev. 1.0, 02/01, page 21 of 1184

• Expanded address space

Normal mode supports the same 64-kbyte address space as the H8/300 CPU.

Advanced mode supports a maximum 16-Mbyte address space.

• Enhanced addressing mode

The addressing modes have been enhanced to make effective use of the 16-Mbyte address

space.

• Enhanced instructions

Addressing modes of bit-manipulation instructions have been enhanced.

Signed mu ltiply and div id e instructions hav e been added.

Two-bit shift instructions have been added.

Instructio ns for saving and restorin g multiple registers have been added.

A test and set instruction has been added.

• Higher speed

Basic instructions execute twice as fast.

2.1.4 Differences from H8/300H CPU

In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements.

• Additional control register

One 8-bit control register has been added.

• Enhanced instructions

Addressing modes of bit-manipulation instructions have been enhanced.

Two-bit shift instructions have been added.

Instructio ns for saving and restorin g multiple registers have been added.

A test and set instruction has been added.

• Higher speed

Basic instructions execute twice as fast.

Rev. 1.0, 02/01, page 22 of 1184

2.2 CPU Operating Modes

The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a

maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address

space (architecturally the maximum total address space is 4 Gbytes, with a maximum of 16

Mbytes for the program area and a maximum of 4 Gbytes for the data area).

The mode is selected by the mode pins of the microcontroller.

CPU operating mode

Normal mode*

Advanced mode

Maximum 64 kbytes for program

and data areas combined

Maximum 16 Mbytes for program

and data areas combined

Note: * Normal mode is not available for this LSI.

Figure 2.1 CPU Operating Modes

2.2.1 Normal Mode (Not available for this LSI)

The exception vector table and stack have the same structure as in the H8/300 CPU.

(1) Address Space

A maximum address space of 64 kbytes can be accessed.

(2) Extended Registers (En)

The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit

segments of 32-bit registers. When En is used as a 16-bit register it can contain any value,

even when the corresponding general register (Rn) is used as an address register. If the

general register is referenced in the register indirect addressing mode with pre-decrement (@-

Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the

corresponding extended register (En) will be affected.

(3) Instruction Set

All instructions and addressing modes can be used. Only the lower 16 bits of effective

addresses (EA) are valid.

Rev. 1.0, 02/01, page 23 of 1184

(4) Exception Vector Table and Memory Indirect Branch Addresses

In normal mode the top area starting at H'0000 is allocated to the exception vector table. One

branch address is stored per 16 bits. The configuration of the exception vector table in normal

mode is shown in figure 2.2. For details of the exception vector table, see section 5, Exception

Handling.

H'0000

H'0001

H'0002

H'0003

H'0004

H'0005

H'0006

H'0007

H'0008

H'0009

H'000A

H'000B

Reset exception vector

Exception vector 1

Exception vector 2

Exception vector table

(Reserved for system use)

Figure 2.2 Exception Vector Table (Normal Mode)

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions

uses an 8-bit abso lute address included in the instruction code to specify a memory operand

that contains a branch address. In normal mode the operand is a 16-bit word operand,

providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000

to H'00FF. Note that this area is also used for the exception vector table.

Rev. 1.0, 02/01, page 24 of 1184

(5) Stack Structure

When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and

cond ition-co de register (CCR) ar e pushed onto th e stack in exception hand ling, the y are stored

as shown in figure 2.3. The extended control register (EXR) is not pushed onto the stack. For

details, see section 5, Exception Handling.

(a) Subroutine Branch (b) Exception Handling

(16 bits) CCR

CCR*

(16 bits)

SP SP

Note: * Ignored when returning.

Figure 2.3 Stack Structure in Normal Mode

2.2.2 Advanced Mode

(1) Address Space

Linear access is provided to a 16-Mbyte maximum address space (architecturally a maximum

16-Mbyte program area and a maximum 4-Gbyte data area, with a maximum of 4 Gbytes for

program and data areas combined).

(2) Extended Registers (En)

The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit

segments of 32-bit registers or address registers.

(3) Instruction Set

All instructions and addressing modes can be used.

Rev. 1.0, 02/01, page 25 of 1184

(4) Exception Vector Table and Memory Indirect Branch Addresses

In advanced mode the top area starting at H'00000000 is allocated to the exception vector table

in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored

in the lower 24 bits (figure 2.4). For details of the exception vector table, see section 5,

Exception Handling.

H'00000000

H'00000003

H'00000004

H'0000000B

H'0000000C

Exception vector table

Reserved

Reset exception vector

(Reserved for system use)

Reserved

Exception vector 1

Reserved

H'00000010

H'00000008

H'00000007

Figure 2.4 Exception Vector Table (Advanced Mode)

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions

uses an 8-bit abso lute address included in the instruction code to specify a memory operand

that contains a branch address. In advanced mode the operand is a 32-bit longword operand,

providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is

regarded as H'00. Branch addresses can be stored in the area from H'00000000 to

H'000000FF. Note that the first part of this range is also the exception vector table.

Rev. 1.0, 02/01, page 26 of 1184

(5) Stack Structure

In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine

call, and the PC and condition-code register (CCR) are pushed onto the stack in exception

handling, they are stored as shown in figure 2.5. The extended control register (EXR) is not

pushed onto the stack. For details, see section 5, Exception Handling.

(a) Subroutine Branch (b) Exception Handling

(24 bits)

CCR

(24 bits)

SP SP

Reserved

Figure 2.5 Stack Structure in Advanced Mode

Rev. 1.0, 02/01, page 27 of 1184

2.3 Address Space

Figure 2.6 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear

access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte

(architecturally 4-Gbyte) address space in advanced mode.

(b) Advanced mode

H'0000

H'FFFF

H'00000000

H'FFFFFFFF

H'00FFFFFF

(a) Normal mode*

Data area

Program area

Cannot be used

with this LSI

Note: * Normal mode is not available for this LSI.

Figure 2.6 Memory Map

Rev. 1.0, 02/01, page 28 of 1184

2.4 Register Configuration

2.4.1 Overview

The CPU has the internal registers shown in figure 2.7. There are two types of registers:

general registers and control registers.

T– – ––I2 I1 I0

EXR

76543210

23 0

15 0 7 0 7 0

R0H

R1H

R2H

R3H

R4H

R5H

R6H

R7H

R0L

R1L

R2L

R3L

R4L

R5L

R6L

R7L

General Registers (Rn) and Extended Registers (En)

Control Registers (CR)

Legend:

EXR

I2 to I0

CCR

ER0

ER1

ER2

ER3

ER4

ER5

ER6

ER7 (SP)

IUIHUNZVC

CCR

76543210

: Half-carry flag

: User bit

: Negative flag

: Zero flag

: Overflow flag

: Carry flag

: Stack pointer

: Program counter

: Extended control register

: Trace bit

: Interrupt mask bits

: Condition-code register

: Interrupt mask bit

: User bit or interrupt mask bit

Note: * Does not affect operation in this LSI.

Figure 2.7 CPU Registers

Rev. 1.0, 02/01, page 29 of 1184

2.4.2 General Registers

The CPU has eight 32-bit general registers. These general registers are all functionally alike and

can be used as both address registers and data registers. When a general register is used as a data

used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).

The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R

(R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit

registers. The E registers (E0 to E7) are also referred to as extended registers.

The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and

RL (R0L to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8-

bit reg iste rs.

Figure 2.8 illustrates the usage of the g e n e ral reg isters. Th e usage of each register can b e selected

independently.

● Address registers

● 32-bit registers ● 16-bit registers ● 8-bit registers

ER registers

(ER0 to ER7)

E registers (extended registers)

(E0 to E7)

R registers

(R0 to R7)

RH registers

(R0H to R7H)

RL registers

(R0L to R7L)

Figure 2.8 Usage of General Registers

General register ER7 has the function of stack pointer (SP) in addition to its general-register

function, and is used im plicitly in exception handling and subroutine calls. Fig ure 2.9 shows the

stack.

Rev. 1.0, 02/01, page 30 of 1184

SP (ER7)

Free area

Stack area

Figure 2.9 Stack

2.4.3 Control Registers

The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR),

and 8-bit condition-code register (CCR).

(1) Program Counter (PC)

This 24-bit counter indicates the address of the next instruction the CPU will execute. The

length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored.

(When an in str uction is fetche d, the least significant PC bit is regarded as 0.)

(2) Extended Control Register ( EXR)

An 8-bit register. In this LSI, this register does not affect operation.

Bit 7: Trace Bit (T)

This bit is reserv ed. In this LSI, th is bit does not af fect operation.

Bits 6 to 3: Reserved

These bits are reserved. They are always read as 1.

Bits 2 to 0: Interrupt Mask Bits (I2 to I0)

These bits are reserved. In this LSI, these bits do not affect operation.

(3) Condition: Code Reg ister (CCR)

This 8-bit register contains internal CPU status information, including an interrupt mask bit (I)

and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.

Bit 7: Interrupt Mask Bit (I)

Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit

setting.) The I bit is set to 1 by hardware at the start of an exception-handling sequence.

For details, see section 6, Interrupt Controller.

Rev. 1.0, 02/01, page 31 of 1184

Bit 6: User Bit or Interrupt Mask Bit (UI)

Can be written and read by software u sing the LDC, STC, ANDC, ORC, and XORC

instruction s. This bit can also be used as an interrup t m ask bit. For details, see sectio n 6,

Interrupt Controller.

Bit 5: Half-Carry Flag (H)

When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed,

this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When

the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if

there is a carry or bor row at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L,

CMP.L, or NEG.L instructio n is executed, the H f lag is set to 1 if there is a carry or borr ow

at bit 27, and cleared to 0 otherwise.

Bit 4: User Bit (U)

Can be written and read by software u sing the LDC, STC, ANDC, ORC, and XORC

instructions.

Bit 3: Negative Flag (N)

Stores the value of the most significant bit (sign bit) of data.

Bit 2: Zero Flag (Z)

Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.

Bit 1: Overflow Flag (V)

Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise.

Bit 0: Carry Flag (C)

Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:

(a) Add instructions, to indicate a carry

(b) Subtract instructions, to indicate a borrow

The carry flag is also used as a bit accumulator by bit-manipulation instructions.

Some instructions leave some or all of the flag bits unchanged. For the action of each

instruction on the flag bits, see section 29, Appendix A.1, List of Instructions.

Operations can be perfo r med on the CCR bits by the LDC, STC, ANDC, ORC, and XORC

instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch

(Bcc) instructions.

2.4.4 Initial Register Values

Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the

trace bit in EXR to 0, and sets the interrupt m ask bits in CCR and EXR to 1. The other CCR bits

and the general registers are n ot initialized. In p ar ticular, the stack pointer (ER7) is not initialized.

The stack pointer should therefore be initialized by an MOV.L instruction executed immediately

after a reset.

Rev. 1.0, 02/01, page 32 of 1184

2.5 Data Formats

The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data.

Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte

operand d ata. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit

BCD data.

2.5.1 General Register Data Formats

Figure 2.10 shows the data formats in general registers.

7 0

MSB LSB

7043

Upper digit Lower digit

Don't care

7 043

Upper digit Lower digit

Don't care

6543271

7 0

Don't care 65432710

Don't care

Data FormatData type

1-bit data

4-bit BCD data

Byte data

General Register

RnH

RnL

RnH

RnL

RnH

RnL

Figure 2.10 General Register Data Formats (1)

Rev. 1.0, 02/01, page 33 of 1184

15 0

MSB LSB

15 0

MSB LSB

31 16

MSB

15 0

LSB

En Rn

Data Type

Word data

Longword data

General Register

ERn

Data format

ERn

RnH

RnL

MSB

LSB

: General register ER

: General register E

: General register R

: General register RH

: General register RL

: Most significant bit

: Least significant bit

Legend:

Figure 2.11 General Register Data Formats (2)

Rev. 1.0, 02/01, page 34 of 1184

2.5.2 Memory Data Formats

Figure 2.12 shows the data formats in memory.

The CPU can access word data and longword data in memory, but word or longword data must

begin at an even address. If an attempt is made to access word or longword data at an odd

address, no address error occurs but the least significant bit of the address is regarded as 0, so the

access starts at the preceding address. This also applies to instruction fetches.

76 543210

MSB LSB

MSB

LSB

Address

Address L

Address 2M

Address 2N

Address 2N+1

Address 2N+2

Address 2N+3

1-bit data

Byte data

Word data

Longword data

Data Type Data Format

Address 2M+1

Figure 2.12 Memory Data Formats

When ER7 (SP) is used as an address register to access the stack, the operand size should be word

size or longword size.

Rev. 1.0, 02/01, page 35 of 1184

2.6 Instruction Set

2.6.1 Overview

The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in

table 2.1.

Table 2.1 Instruction Classification

Function Instructions Size Types

MOV BWL

POP*1, PUSH*1 WL

LDM*5, STM*5 L

Data transfer

MOVFPE*3, MOVTPE*3 B

ADD, SUB, CMP, NEG BWL

ADDX, SUBX, DAA, DAS B

INC, DEC BWL

ADDS, SUBS L

MULXU, DIVXU, MULXS, DIVXS BW

EXTU, EXTS WL

Arithmetic

TAS*4 B

Logic operations AND, OR, XOR, NOT BWL 4

Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR,

ROTXL, ROTXR BWL 8

Bit manipulation RSET, BCLR, BNOT, BTST, BLD, BILD, BST,

BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR B 14

Branch Bcc*2, JMP, BSR, JSR, RTS  5

System cont rol TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC,

XORC, NOP  9

Block data transfer EEPMOV  1

Total: 65 types

Notes: B: byte size; W: word size; L: longword size.

1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-

SP.

POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-

SP.

2. Bcc is the general name for conditional branch instructions.

3. Cannot be used in the H8S/2199 Series.

4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

5. Only registers ER0 to ER6 should be used when using the STM/LDM instruction.

Rev. 1.0, 02/01, page 36 of 1184

2.6.2 Instructions a nd Addressing Modes

Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2000 CPU

can use.

Table 2.2 Combinatio ns of Instructions and Addressing Modes

Addressing Modes

Function

Arithmetic operationsSystem control

Branch

Logic

operation

Instruction

MOV

POP, PUSH

LDM*

, STM*

ADD, CMP

SUB

ADDX, SUBX

ADDS, SUBS

INC, DEC

DAA, DAS

NEG

EXTU, EXTS

TAS*

MOVFPE,

MOVTPE*

MULXU,

DIVXU

MULXS,

DIVXS

AND, OR,

XOR

ANDC,

ORC, XORC

NOT

Bcc, BSR

JMP, JSR

RTS

TRAPA

RTE

SLEEP

LDC

STC

NOP

Shift

Bit manipulation

Block data transfer

Data transfer

BWL

#xx

—

BWL

—

BWL

—

BWL

—

BWL

—

BWL

—

BWL

—

BWL

—

BWL

@ERn

—

BWL

@(d:16, ERn)

—

BWL

@(d:32, ERn)

—

BWL

@-ERn/@ERn+

—

@aa:8

—

BWL

@aa:16

—

@aa:24

—

BWL

@aa:32

—

@(d:8, PC)

—

@(d:16, PC)

—

@@aa:8

—

Legend:

B: Byte

W: Word

L: Longword

Notes: 1. Cannot be used in this LSI.

2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

3. Only registers ER0 to ER6 should be used when using the STM/LDM instruction.

Rev. 1.0, 02/01, page 37 of 1184

2.6.3 Table of Instructions Classified by Function

Tables 2.3 to 2.10 summarize the functions of the instructions. The notation used in table 2.3 is

defined below.

Operation Notation

Rd General register (destination)*

Rs General register (source)*

Rn General register*

ERn General register (32-bit register)

(EAd) Destination operand

(EAs) Source operand

EXR Extended control register

CCR Condition-code register

N N (negative) flag in CCR

Z Z (zero) flag in CCR

V V (overflow) fl ag in CCR

C C (carry) fla g in CCR

PC Program counter

SP Stack pointer

#IMM Immediate data

Disp Displacement

+ Addition

− Subtraction

× Multiplication

÷ Division

∧ Logical AND

∨ Logical OR

⊕ Logical exclusive OR

→ Move

∼ NOT (logical complement)

:8/:16/:24/:32 8-, 16-, 24-, or 32-bit length

Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to

R7, E0 to E7), and 32-bit registers (ER0 to ER7).

Rev. 1.0, 02/01, page 38 of 1184

Table 2.3 Data Transfer Instructions

Instruction Size*1 Function

MOV B/W/L (EAs) → Rd, Rs → (EAd)

Moves data between two general registers or between a general

MOVFPE B Cannot be used in this LSI

MOVTPE B Cannot be used in this LSI

POP W/L @SP+ → Rn

Pops a general register from the stack

POP.W Rn is identical to MOV.W @SP+, Rn

POP.L ERn is identical to MOV.L @SP+, ERn

PUSH W/L Rn → @-SP

Pushes a general register onto the stack

PUSH.W Rn is identical to MOV.W Rn, @-SP

PUSH.L ERn is identical to MOV.L ERn, @-SP

LDM*2 L @SP+ → Rn (register list)

Pops two or more general registers from the stack

STM*2 L Rn (register list) → @-SP

Pushes two or more general registers onto the stack

Note: 1. Size refers to the operand size.

B: Byte

W: Word

L: Longword

2. Only registers ER0 to ER6 should be used when using the STM/LDM instruction.

Rev. 1.0, 02/01, page 39 of 1184

Table 2.4 Arithmetic Instructions

Instruction Size*1 Function

ADD

SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd

Performs addition or subtraction on data in two general registers,

or on immediate data and data in a general register. (Immediate

byte data cannot be subtracted from byte data in a general

ADDX

SUBX B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd

Performs addition or subtraction with carry on byte data in two

general registers, or on immediate data and data in a general

INC

DEC B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd

Increments or decrements a general register by 1 or 2. (Byte

operands can be incremented or decremented by 1 only)

ADDS

SUBS B Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd

Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit

DAA

DAS B/W Rd decimal adjust → Rd

Decimal-adjusts an addition or subtraction result in a general

MULXU B/W Rd × Rs → Rd

Performs unsigned multiplication on data in two general registers:

either 8 bits × 8 bits → 16 bits or 16 bits ×16 bits → 32 bits

MULXS B/W Rd × Rs → Rd

Performs signed multiplication on data in two general registers:

either 8 bits × 8 bits → 16 bits or 16 bits ×16 bits → 32 bits

DIVXU B/W Rd ÷ Rs → Rd

Performs unsigned division on data in two general registers:

either 16 bits ÷ 8 bits × 8-bit quotient and 8-bit remainder or 32

bits ÷ 16 bits × 16-bit quotient and 16-bit remainder

Rev. 1.0, 02/01, page 40 of 1184

Instruction Size*1 Function

DIVXS B/W Rd ÷ Rs → Rd

Performs signed division on data in two general registers: either

16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷

16 bits → 16-bit quotient and 16-bit remainder

CMP B/W/L Rd - Rs, Rd - #IMM

Compares data in a general register with data in another general

the result

NEG B/W/L 0 - Rd → Rd

Takes the two's complement (arithmetic complement) of data in

a general register

EXTU W/L Rd (zero extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size, or the

lower 16 bits of a 32-bit register to longword size, by padding

with zeros on the left

EXTS W/L Rd (sign extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size, or the

lower 16 bits of a 32-bit register to longword size, by extending

the sign bit

TAS B @ERd - 0, 1 → (<bit 7> of @ERd)*2

Tests memory contents, and sets the most significant bit (bit 7)

to 1

Notes: 1. Size refers to the operand size.

B: Byte

W: Word

L: Longword

2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

Rev. 1.0, 02/01, page 41 of 1184

Table 2.5 Logic Instructions

Instruction Size* Function

AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd

Performs a logical AND operation on a general register and

another general register or immediate data

OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd

Performs a logical OR operation on a general register and

another general register or immediate data

XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd

Performs a logical exclusive OR operation on a general register

and another general register or immediate data

NOT B/W/L ~ Rd → Rd

Takes the one's complement (logical complement) of general

Note: * Size refers to the operand size.

B: Byte

W: Word

L: Longword

Table 2.6 Shift Instructions

Instruction Size* Function

SHAL

SHAR B/W/L Rd (shift) → Rd

Performs an arithmetic shift on general register contents

A 1-bit or 2-bit shift is possible

SHLL

SHLR B/W/L Rd (shift) → Rd

Performs a logical shift on general register contents

A 1-bit or 2-bit shift is possible

ROTL

ROTR B/W/L Rd (rotate) → Rd

Rotates general register contents

1-bit or 2-bit rotation is possible

ROTXL

ROTXR B/W/L Rd (rotate) → Rd

Rotates general register contents through the carry flag

1-bit or 2-bit rotation is possible

Note: * Size refers to the operand size.

B: Byte

W: Word

L: Longword

Rev. 1.0, 02/01, page 42 of 1184

Table 2.7 Bit Manipulation Instructio ns

Instruction Size* Function

BSET B 1 → (<bit-No.> of <EAd>)

Sets a specified bit in a general register or memory operand to

1. The bit number is specified by 3-bit immediate data or the

lower three bits of a general register

BCLR B 0 → (<bit-No.> of <EAd>)

Clears a specified bit in a general register or memory operand to

0. The bit number is specified by 3-bit immediate data or the

lower three bits of a general register

BNOT B ~ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)

Inverts a specified bit in a general register or memory operand.

The bit number is specified by 3-bit immediate data or the lower

three bits of a general register

BTST B ~ (<bit-No.> of <EAd>) → Z

Tests a specified bit in a general register or memory operand

and sets or clears the Z flag accordingly. The bit number is

specified by 3-bit immediate data or the lower three bits of a

general register

BAND B C ∧ (<bit-No.> of <EAd>) → C

ANDs the carry flag with a specified bit in a general register or

memory operand and stores the result in the carry flag

BIAND B C ∧ [~(<bit-No.> of <EAd>)] → C

ANDs the carry flag with the inverse of a specified bit in a

general register or memory operand and stores the result in the

carry flag

The bit number is specified by 3-bit immediate data

BOR B C ∨ (<bit-No.> of <EAd>) → C

ORs the carry flag with a specified bit in a general register or

memory operand and stores the result in the carry flag

BIOR B C∨ [~(<bit-No.> of <EAd>)] → C

ORs the carry flag with the inverse of a specified bit in a general

flag

The bit number is specified by 3-bit immediate data

Rev. 1.0, 02/01, page 43 of 1184

Instruction Size* Function

BOXR B C ⊕ (<bit-No.> of <EAd>) → C

Exclusive-ORs the carry flag with a specified bit in a general

flag

BIXOR B C ⊕ [~ (<bit-No.> of <EAd>)] → C

Exclusive-ORs the carry flag with the inverse of a specified bit in

a general register or memory operand and stores the result in

the carry flag

The bit number is specified by 3-bit immediate data

BLD B (<bit-No.> of <EAd>) → C

Transfers a specified bit in a general register or memory

operand to the carry flag

BILD B ~ (<bit-No.> of <EAd>) → C

Transfers the inverse of a specified bit in a general register or

memory operand to the carry flag

The bit number is specified by 3-bit immediate data

BST B C → (<bit-No.> of <EAd>)

Transfers the carry flag value to a specified bit in a general

BIST B ~ C → (<bit-No.> of <EAd>)

Transfers the inverse of the carry flag value to a specified bit in a

general register or memory operand

The bit number is specified by 3-bit immediate data

Note: * Size refers to the operand size.

B: Byte

Rev. 1.0, 02/01, page 44 of 1184

Table 2.8 Branch Instructions

Instruction Size* Function

Bcc  Branches to a specified address if a specified condition is true

The branching conditions are listed below

JMP  Branches unconditionally to a specified address

BSR  Branches to a subroutine at a specified address

JSR  Branches to a subroutine at a specified address

RTS  Returns from a subroutine

Mnemonic Description Condition

BRA (BT) Always (True) Always

BRN (BF) Never (False) Never

BHI HIgh CVZ = 0

BLS Low of Same CVZ = 1

BCC (BHS) Carry Clear (High or Same) C = 0

BCS (BLO) Carry Set (LOw) C = 1

BNE Not Equal Z = 0

BEQ EQual Z = 1

BVC oVerflow Clear V = 0

BVS oVerflow Set V = 1

BPL PLus N = 0

BMI MInus N = 1

BGE Greater or Equal NV = 0

BLT Less Than N ⊕ V = 1

BGT Greater Than Z∨ (N ⊕ V) = 0

BLE Less or Equal Z∨ (N ⊕ V) = 1

Rev. 1.0, 02/01, page 45 of 1184

Table 2.9 System Control Instructions

Instruction Size* Function

TRAPA  Starts trap-instruction exception handling

RTE  Returns from an exception-handling routine

SLEEP  Causes a transition to a power-down state

LDC B/W (EAs) → CCR, (EAs) → EXR

Moves contents of a general register or memory or immediate

data to CCR or EXR. Although CCR and EXR are 8-bit

registers, word-size transfers are performed between them and

memory. The upper 8 bits are valid

STC B/W CCR → (EAd), EXR → (EAd)

Transfers CCR or EXR contents to a general register or memory.

Although CCR and EXR are 8-bit registers, word-size transfers

are performed between them and memory. The upper 8 bits are

valid

ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR

Logically ANDs the CCR or EXR contents with immediate data

ORC B CCR∨ #IMM → CCR, EXR∨ # IMM → EXR

Logically ORs the CCR or EXR contents with immediate data

XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR

Logically exclusiv e-ORs the CCR or EXR contents with

immediate data

NOP  PC + 2 → PC

Only increments the program counter

Note: * Size refers to the operand size.

B: Byte

W: Word

Rev. 1.0, 02/01, page 46 of 1184

Table 2.10 Block Data Transfer Instructions

Instruction Size* Function

EEPMOV.B  if R4L ≠ 0 then

Repeat @ER5+→@er6+

R4L−1→R4L

Until R4L = 0

else next;

EEPMOV.W  if R4 ≠ 0 then

Repeat @ER5+→@er6+

R4−1→R4

Until R4 = 0

else next;

Transfers a data block according to parameters set in general

registers R4L or R4, ER5, and ER6

R4L or R4: size of block (bytes)

ER5: starting source address

ER6: starting destination address

Execution of the next instruction begins as soon as the transfer

is completed

Rev. 1.0, 02/01, page 47 of 1184

2.6.4 Basic Instruction Formats

The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation

field (op field), a register field (r field), an effective address extension (EA field), and a condition

field (cc).

Figure 2.13 shows examples of instruction formats.

op rn rm

NOP, RTS, etc.

ADD.B Rn, Rm, etc.

MOV.B@(d:16, Rn), Rm, etc.

(1) Operation field only

(2) Operation field and register fields

(3) Operation field, register fields, and effective address extension

rn rm

EA (disp)

(4) Operation field, effective address extension, and condition field

op cc EA (disp) BRA d:16, etc.

Figure 2.13 Instruction Formats (Examples)

(1) Operation Field

Indicates the function of the instruction, the addressing mode, and the operation to be carried

out on the operand. The operation field always includes the first four bits of the instruction.

Some instructions have two operation fields.

(2) Register Field

Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or

4 bits. Some instructions have two register fields. Some have no register field.

(3) Effective Address Extension

Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.

(4) Condition Field

Specifies the branching condition of Bcc instructions.

Rev. 1.0, 02/01, page 48 of 1184

2.6.5 Notes on Use of Bit-Manipulation Instructions

The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, carry out bit

manipulation, then write back the byte of data. Caution is therefore required when using these

instructions on a register containing write-only bits, or a port.

The BCLR instruction can be used to clear internal I/O register flags to 0. In this case, the

relevant flag need not be read beforehand if it is clear that it has been set to 1 in an interrupt

handling routine, etc.

Rev. 1.0, 02/01, page 49 of 1184

2.7 Addressing Modes and Effective Address Calculation

2.7.1 Addressing Mode

The CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset

of these addressing modes. Arithmetic and logic instructions can use the register direct and

immediate modes. Data transfer instructions can use all addressing modes except program-

counter relative and memory indirect. Bit-manipulation instructions use register direct, register

indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR,

BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in

the operand.

Table 2.1 1 Addressing Modes

No. Addressing Mode Symbol

1 Register direct Rn

2 Register indirect @ERn

3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn)

4 Register indirect with post-increment

@-ERn

5 Absolute address @aa:8/#@aa:16/@aa:24/@aa:32

6 Immediate #xx:8/#xx:16/#xx:32

7 Program-counter relative @(d:8,PC)/@(d:16,PC)

8 Memory indirect @@aa:8

(1) Register Direct–Rn

The register field of the instruction code specifies an 8-, 16-, or 32-bit general register

containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0

to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as

32-bit registers.

(2) Register Indirect–@Ern

The register field of the instruction code specifies an address register (ERn) which contains the

address of the operand in memory. If the address is a program instruction address, the lower

24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00).

(3) Register Indirect with Displacement–@(d:16, ERn) or @(d:32, ERn)

A 16-bit or 32-bit displacement contained in the instruction is added to an address register

(ERn) specified by the register field of the instruction, and the sum gives the address of a

memory operand. A 16-bit displacement is sign-extended when added.

Rev. 1.0, 02/01, page 50 of 1184

(4) Register Indirect with Post-Increment or Pre-Decrement–@ERn+ or @-ERn

(a) Register indirect with post-increment–@ERn+

The register field of the instruction code specifies an address register (ERn) which contains

the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the

address register contents and the sum is stored in the address register. The value added is 1

for byte access, 2 for word access, or 4 for longword access. For word or longword access,

the register value should be even.

(b) Register indirect with pre-decrement–@-ERn

The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register

field in the instruction code, and the result becomes the address of a memory operand. The

result is also stored in the address register. The value subtracted is 1 for byte access, 2 for

word access, or 4 for longword access. For word or longword access, the register value

should be even.

(5) Absolute Address–@aa:8, @aa:16, @aa:24, or @aa:32

The instruction code contains the absolute address of a memory operand. The absolute

address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits

long (@aa:32).

To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits

(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1

(H'FFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit

absolute address can access the entire address space.

A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper

8 bits are all assumed to be 0 (H'00).

Table 2.12 indicates the accessible absolute address ranges.

Table 2.12 Absolute Address Access Ranges

Absolute Address Normal Mode Advanced Mode

8 bits

(@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF

16 bits

(@aa:16) H'000000 to H007FFF, H'FF8000 to

H'FFFFFF

Data address

32 bits

(@aa:32)

Program instruction

address 24 bits

(@aa:24)

H'0000 to H'FFFF

H'000000 to H'FFFFFF

Rev. 1.0, 02/01, page 51 of 1184

(6) Immediate–#xx:8, #xx:16, or #xx:32

The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an

operand.

The ADDS, SUBS, INC, and DEC instru ctions contain imme diate data implicitly. Some bit

manipulation instructions contain 3-bit immediate data in the instruction code, sp ecifying a bit

number. The TRAPA instruction contains 2-bit immediate data in its instruction code,

specifying a vector address.

(7) Program-Counter Relative–@(d:8, PC) or @(d:16, PC)

This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained

in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch

address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all

assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the

first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to

+64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction.

The resulting value should be an even number.

(8) Memory Indirect–@@aa:8

This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-

bit absolute address specifying a memory operand. This memory operand contains a branch

address. The upper bits of the absolute address are all assumed to be 0, so the address range is

0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In

normal mode the memory operand is a word operand and the branch address is 16 bits long.

In advanced mode the memory operand is a longword operand, the first byte of which is

assumed to be all 0 (H'00).

Note that the first part of the address range is also the exception vector area. For further

details, see section 5, Exception Handling.

(a) Normal Mode*

Note: * Not available for this LSI

(b) Advanced Mode

Branch address Specified by

@aa:8

Specified by

@aa:8 Reserved

Branch address

Figure 2.14 Branch Address Specification in Memory Indirect Mode

Rev. 1.0, 02/01, page 52 of 1184

If an odd address is specified in word or longword memory access, or as a branch address, the

least significant bit is regarded as 0, causing data to be accessed or an instruction code to be

fetched at the address preceding the specified address. (For further information, see section

2.5.2, Memory Data Formats.)

2.7.2 Effective Address Calculation

Table 2.13 indicates how effective addresses are calculated in each addressing mode.

In normal mode* the upper 8 bits of the effective address are ignored in order to generate a 16-bit

address.

Note: * Not available fo r this LSI.

Rev. 1.0, 02/01, page 53 of 1184

Table 2.13 Effective Address Calculation

No. Addressing Mode and

Instruction Format Effective Address

Calculation

Effective Address (EA)

1 Register direct (Rn)

op rm rn

Operand is general register

contents

2 Register indirect (@ERn)

General register contents

31 0 31 0

rop

24 23

Don’t

care

3 Register indirect with displacement

@(d:16, ERn) or @(d:32, ERn)

General register contents

Sign extension disp

31 0

op r disp Don’t

care

24 23

4 Register indirect with post-increment or pre-decrement

• Register indirect with post-increment @ERn+

General register contents

1, 2, or

31 0 31 0

Don’t

care

24 23

• Register indirect with pre-decrement @–ERn

General register contents

1, 2, or

Byte

Word

Longword

Operand

Size Value

Added

31 0

op rDon’t

care

24 23

Rev. 1.0, 02/01, page 54 of 1184

No. Addressing Mode and

Instruction Format Effective Address

Calculation

Effective Address (EA)

5 Absolute address

@aa:8

@aa:16

@aa:32

31 08 7

@aa:24

31 016 15

31 0

op abs

abs

H'FFFF

24 23

Don’t

care

Don’t

care

Don’t

care

Don’t

care

24 23

Sign

exten-

sion

6 Immediate #xx:8/#xx:16/#xx:32

op IMM

Operand is immediate data

7 Program-counter relative

@(d:8, PC)/@(d:16, PC)

disp 31 0

24 23

op disp

PC contents

Don’t

care

Sign

exten-

sion

Rev. 1.0, 02/01, page 55 of 1184

No. Addressing Mode and

Instruction Format Effective Address

Calculation

Effective Address (EA)

8 Memory indirect @@aa:8

• Normal mode*

31 8 7

H'000000 31 0

16 15

op abs

abs

Memory

contents

H'00

24 23

Don’t

care

• Advanced mode

31 8 7

abs

H'000000

31 0

24 23

op abs

Memory contents Don’t

care

Note: * Not available for this LSI.

Rev. 1.0, 02/01, page 56 of 1184

2.8 Processing States

2.8.1 Overview

The CPU has four main processing states: the reset state, exception-handling state, program

execution state, and power-down state. Figure 2.15 shows a diagram of the processing states.

Figure 2.16 indicates the state transitions.

Reset state

The CPU and all on-chip supporting modules have been initialized and are stopped.

Exception-handling

state

A transient state in which the CPU changes the normal processing flow in response

to a reset, interrupt or trap instruction.

Program execution

state

The CPU executes program instructions in sequence.

Power-down state

CPU operation is stopped

to conserve power.*

Sleep mode

Standby mode

Processing

states

Note: *

The power-down state also includes a medium-speed mode, modue stop mode, sub-active mode,

sub-sleep mode and watch mode.

Figure 2.15 Processing States

Rev. 1.0, 02/01, page 57 of 1184

Reset state

Exception-handling state

Sleep mode

Standby mode

Power-down state

Program execution state

Interrupt request

External interrupt request

RES = High

Request for exception handling

SLEEP instruction

with LSON=0,

SSBY=1,

TMA3=0

SLEEP instruction

with LSON=0,

SSBY=0

Notes:

End of exception handling

From any state, a transition to the reset state occurs whenever RES goes low. A transition can

also be made to the reset state when the watchdog timer overflows.

The power-down state also includes a watch mode, subactive mode, subsleep mode, etc. For

details, see section 4, Power-Down State.

Figure 2.16 State Transitions

2.8.2 Reset State

When the RES input goes low all current processing stops and the CPU enters the reset state. All

interrupts are disabled in the reset state. Reset exception handling starts when the RES signal

changes from low to high.

The reset state can also be entered by a watchdog timer overflow. For details, see section 17,

Watchdog Timer.

Rev. 1.0, 02/01, page 58 of 1184

2.8.3 Exception-Handling State

The exception-handling state is a transient state that occurs when the CPU alters the normal

processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address

(vector) from the exception vector table and branches to that address.

(1) Types of Exception Handling and Their Priority

Exception handling is performed for resets, interrupts, and trap instructions. Table 2.14

indicates the types of exception handling and their priority. Trap instruction exception

handling is always accepted in the program execution state.

Exception handling and the stack structure depend on the interrupt control mode set in

SYSCR.

Table 2.14 Exception Handling Types and Priority

Priority Type of Exception Detection Timing Start of Exception Handling

Reset Synchronized with

clock Exception handling starts immediately

after a low-to-high transition at the

RES pin, or when the watchdog timer

overflows

Interrupt End of instruction

execution or end of

exception-handling

sequence*1

When an interrupt is requested,

exception handling starts at the end

of the current instruction or current

exception-handling sequence

High

Low Trap instruction When TRAPA

instruction is executed Exception handling starts when a trap

(TRAPA) instruction is executed*2

Notes: 1. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions,

or immediately after reset exception handling.

2. Trap instruction exception handling is always accepted in the program execution state.

(2) Reset Exception Handling

After the RES pin has gone low and the reset state has been entered, when RES goes high

again, reset exception handling starts. When reset exception handling starts the CPU fetches a

start address (vector) from the exception vector table and starts program execution from that

address. All interrupts, including NMI, are disabled during reset exception handling and after

it ends.

(3) Interrupt Exception Handling and Trap Instruction Exception Handling

When interrupt or trap-instruction exception handling begins, the CPU references the stack

pointer (ER7) and pushes the program counter and other control registers onto the stack. Next,

the CPU alters the settings of the interrupt mask bits in the control registers. Then the CPU

fetches a start address (vector) from the exception vector table and program execution starts

from that start address.

Rev. 1.0, 02/01, page 59 of 1184

Figure 2.17 shows the stack after exception handling ends.

(16 bits)

SP CCR

CCR

(24 bits)

SP CCR

Normal Mode

Advanced Mode

Notes: 1. Ignored when returning.

2. Normal mode is not available for this LSI.

Figure 2.17 Stack Structure after Exception Handling (Examples)

2.8.4 Program Execution State

In this state the CPU executes program instructions in sequence.

Rev. 1.0, 02/01, page 60 of 1184

2.8.5 Power-Down State

The power-down state includes both modes in which the CPU stops operating and modes in which

the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode,

standby mode, subsleep mode, and watch mode. There are also three other power-down modes:

medium-speed mode, module stop mode, and subactive mode. In medium-speed mode, the CPU

operates on a medium-speed clock. Module stop mode permits halting of the operation of

individual modules, other than the CPU. Subactive mode, subsleep mode, and watch mode are

power-down modes that use subclock input. For details, see section 4, Power-Down State.

(1) Sleep Mode

A transition to sleep mode is made if the SLEEP instruction is executed while the software

standby bit (SSBY) in the standby control register (SBYCR) and the LSON bit in the low-

power control register (LPWRCR) are both cleared to 0. In sleep mode, CPU operations stop

immediately after execution of the SLEEP instruction. The contents of CPU registers are

retained.

(2) Standby Mode

A transition to standby mode is made if the SLEEP instruction is executed while the SSBY bit

in SBYCR is set to 1 and th e LSON bit in LPWRCR and th e TMA3 bit in the TMA (timer A)

are both cleared to 0. In standby mode, the CPU and clock halt and all MCU operations stop.

As long as a specified voltage is supplied, the contents of CPU registers and on-chip RAM are

retained.

Rev. 1.0, 02/01, page 61 of 1184

2.9 Basic Timing

2.9.1 Overview

The CPU is driven by a system clock, denoted by the symbol φ. The period from one rising edge

of φ to the next is refer r ed to as a “state.” The memory cycle or bus cycle consists of one or two

states. Different methods are used to access on-chip memory and on-chip supporting modules.

2.9.2 On-Chip Memory (ROM, RAM)

On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and

word transfer instruction. Figure 2.18 shows the on-chip memory access cycle.

Internal address bus

Internal read signal

Internal data bus

Internal write signal

Internal data bus

Bus cycle

Address

Read data

Write data

Read access

Write access

Figure 2.18 On-Chip Memory Access Cycle

Rev. 1.0, 02/01, page 62 of 1184

2.9.3 On-Chip Supporting Mo dule Access Timing

The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits

wide, depending on the particular internal I/O register being accessed. Figure 2.19 shows the

access timing for the on-chip supporting modules.

Internal address bus

Internal read signal

Internal data bus

Internal write signal

Internal data bus

Bus cycle

Address

Read access

Write access

Read data

Write data

Figure 2.19 O n-Chip Supporting Module Access Cycle

Rev. 1.0, 02/01, page 63 of 1184

2.10 Usage Note

2.10.1 TAS Instruction

Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS

instruction is not generated by the Hitachi H8S and H8/300 series C/C++ compilers. If the TAS

instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or

ER5 is used.

2.10.2 STM/LDM Instruction

ER7 is not used as the register that can be saved (STM)/restored (LDM) when using STM/LDM

instruction, because ER7 is the stack pointer. Two, three, or four registers can be saved/restored

by one STM/LDM instruction. The following ranges can be specified in the register list.

Two registers : ER0ER1, ER2ER3, or ER4ER5

Three registers : ER0ER2 or ER4 ER6

Four registers : ER0ER3

The STM/LDM instruction including ER7 is not generated by the Hitachi H8S and H8/300 series

C/C++compilers.

Rev. 1.0, 02/01, page 64 of 1184

Rev. 1.0, 02/01, page 65 of 1184

Section 3 MCU Operating Modes

3.1 Overview

3.1.1 Operating Mode Selectio n

This LSI has one operating mode (mode 1). This mode is selected depending on settings of the

mode pin (MD0).

Table 3.1 lists the MCU operating modes.

Table 3.1 MCU Operating Mo de Selection

MCU Operating Mode MD0 CPU Operating Mode Description

0 0  

1 1 Advanced Single-chip mode

The CPU's architecture allows for 4 Gbytes of address space, but this LSI actually accesses a

maximum of 16 Mbytes.

Mode 1 operation starts in single-chip mode after reset release.

This LSI can only be used in mode 1. This means that the mode pins must be set at mode 1. Do

not changes the inputs at the mode pins during operation.

3.1.2 Register Configuration

This LSI has a mode control register (MDCR) that indicates the inputs at the mode pin (MD0) and

a system control register (SYSCR) and that controls the operation of this LSI. Table 3.2

summarizes these registers.

Table 3.2 MCU Registers

Name Abbreviation R/W Initial Value Address*

Mode control register MDCR R Undetermined H'FFE9

System control register SYSCR R/W H'09 H'FFE8

Note: * Lower 16 bits of the address.

Rev. 1.0, 02/01, page 66 of 1184

3.2 Register Descriptions

3.2.1 Mode Control Register (MDCR)

—*

5—————

—

——————

—R

MDS0

Bit :

Initial value :

R/W

Note: *

Determined by MD0 pin

MDCR is an 8-bit read-only register monitors the current operating mode of this LSI.

Bits 7 to 1: Reserved.

These bits cannot be modified and are always read as 0.

Bit 0: Mode Select 0 (MDS0)

This bit indicates the value which reflects the input levels at mode pin (MD0) (the current

operating mode). Bit MDS0 corresponds to MD0 pin. They are read-only bits-they cannot be

written to. The mode pin (MD0) input levels are latched into these bits when MDCR is read.

3.2.2 System Control Register (SYSCR)

—

R/W

—

——— RR

INTM1 INTM0 XRST ——

Bit :

Initial value :

R/W :

Bits 7 and 6



Reserved: These bits cannot be modified and are always read as 0.

Rev. 1.0, 02/01, page 67 of 1184

Bits 5 and 4



Interrupt control modes 1 and 0 (INTM1, INTM0)

These bits are for selecting the interrupt control mode of th e interrupt con tr oller. For details o f the

interrupt control modes, see section 6.4.1, Interrupt Control Modes and Interrupt Operation.

Bit 5 Bit 4

INTM1 INTM0 Interrupt

Control Mode Description

0 0 Interrupt is controlled by bit I (Initial value) 0

1 1 Interrupt is controlled by bits I and UI, and ICR

0  Cannot be used in this LSI 1

1  Cannot be used in this LSI

Bit 3



External Reset (XRST): Indicates the reset source. When the watchdog timer is used, a

reset can be generated by watchdog timer overflow as well as by external reset input. XRST is a

read-only bit. It is set to 1 by an external reset and cleared to 0 by watchdog timer overflow.

Bit 3

XRST Description

0 A reset is generated by watchdog timer overflow

1 A reset is generated by an external reset (Initial value)

Bits 2 and 1



Reserved: These bits cannot be modified and are always read as 0.

Bit 0



Reserved: This bit is always read as 1.

3.3 Operating Mode (Mode 1)

The CPU can access a 16 Mbyte address space in advanced mode.

Rev. 1.0, 02/01, page 68 of 1184

3.4 Address Map in Each Operating Mode

H8S/2196R H8S/2197R

Memory indirect

branch address

Absolute address, 16 bits

4 kbytes

Vector area

On-chip ROM

(80 kbytes)

Internal I/O register

On-chip RAM

Vector area

On-chip ROM

(96 kbytes)

Internal I/O register

OSD ROM

(24 kbytes)

On-chip RAM

(4 kbytes)

H'000000 H'000000

H'017FFF

H'FFD000

H'040000

H'045FFF

H'FFD2FF

H'FFD800

H'FFDAFF

H'FFEFB0

H'FFFFAF

H'FFFFB0

H'FFFFFF

H'0000FF

H'007FFF

H'013FFF

H'FF8000

H'FFD000

H'FFD2FF

H'FFEFB0

H'FFFF00

H'FFFFAF

H'FFFFB0

H'FFFFFF

OSD RAM (768 bytes)

OSD ROM

(24 kbytes)

H'040000

H'045FFF

H'FFD800

H'FFDAFF

OSD RAM (768 bytes)

Absolute address,

8 bits

Absolute address, 16 bits

Figure 3.1 Address Map (1)

Rev. 1.0, 02/01, page 69 of 1184

H8S/2198R H8S/2199R

Vector area

On-chip ROM

(112 kbytes)

Internal I/O register

On-chip RAM

(4 kbytes)

Vector area

On-chip ROM

(128 kbytes)

Internal I/O register

On-chip RAM

(4 kbytes)

H'000000 H'000000

H'01FFFF

H'FFD000

H'FFD2FF

H'FFEFB0

H'FFFFAF

H'FFFFB0

H'FFFFFF

H'01BFFF

H'FFD000

H'FFD2FF

H'FFEFB0

H'FFFFAF

H'FFFFB0

H'FFFFFF

OSD ROM

(24 kbytes)

H'040000

H'045FFF

H'FFD800

H'FFDAFF

OSD RAM (768 bytes)

OSD ROM

(24 kbytes)

H'040000

H'045FFF

H'FFD800

H'FFDAFF

OSD RAM (768 bytes)

H8S/2199R (F-ZTAT version)

Vector area

Flash memory

(256 kbytes)

Internal I/O register

On-chip RAM

(8 kbytes)

H'000000

H'FFD000

H'FFD2FF

H'FFDFB0

H'FFFFAF

H'FFFFB0

H'FFFFFF

Flash memory (OSD)

(32 kbytes)

H'03FFFF

H'047FFF

H'FFD800

H'FFDAFF

OSD RAM (768 bytes)

Figure 3.2 Address Map (2)

Rev. 1.0, 02/01, page 70 of 1184

H8/2196S H8/2197S

Vector area Vector area

On-chip ROM

(80k bytes) On-chip ROM

(96k bytes)

Internal I/O register

Internal I/O register Internal I/O register

Internal I/O register

On-chip RAM

(3k bytes) On-chip RAM

(3k bytes)

H'000000 H'000000

H'017FFF

H'FFD800

H'FFF3B0

H'FFFFAF

H'FFFFB0

H'FFFFFF

H'013FFF

H'FFD800

H'FFF3B0

H'FFFFAF

H'FFFFB0

H'FFFFFF

OSD ROM

(16k bytes)

H'040000

H'043FFF

H'040000

H'043FFF

OSD ROM

(16k bytes)

OSD RAM

(768 bytes) OSD RAM

(768 bytes)

H'FFDAFF H'FFDAFF

H'FFD000

H'FFD2FF

H'FFD000

H'FFD2FF

Figure 3.3 Address Map (3)

Rev. 1.0, 02/01, page 71 of 1184

Section 4 Power-Down State

4.1 Overview

In addition to the normal program execution state, this LSI has a power-down state in which

operation of the CPU and oscillator is halted and power dissipa tion is reduced . Low-power

operation can be achieved by individually controlling the CPU, on-chip supporting modules, and

so on.

This LSI operating modes are as follows:

1. High-speed mode

2. Medium-speed mode

3. Sub-active mode

4. Sleep mode

5. Sub-sleep mode

6. Watch mode

7. Module stop mode

8. Standby mode

Of these, 2 to 8 are power-down modes. Certain combinations of these modes can be set.

After a reset, the MCU is in high-speed m ode.

Table 4.1 shows the internal chip states in each mode, and table 4.2 shows the conditions for

transition to the various modes. Figure 4.1 shows a mode transition diagram.

Rev. 1.0, 02/01, page 72 of 1184

Table 4.1 H8S/2199R Series Internal States in Each Mode

Function High-Speed

Medium-

Speed Sleep Module

Stop Watch Sub-active Sub-sleep Standby

System clock Functioning Functioning Functioning Functioning Halted Halted Halted Halted

Subclock pulse generator Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning

Instructions Halted Halted Halted Halted CPU

operation Registers Functioning Medium-

speed Retained Functioning Retained Subclock

operation Retained Retained

IRQ0

IRQ1 Functioning Functioning Functioning Functioning

IRQ2

IRQ3

IRQ4

External

interrupts

IRQ5

Functioning Functioning Functioning Functioning

Halted Halted Functioning Halted

I/O Functioning Functioning Retained Functioning Halted Functioning Retained Halted

Timer A Functioning Functioning Functioning Functioning

/halted

(retained)

Subclock

operation Subclock

operation Halted

(retained)

Timer B

Timer J

Timer L

Functioning

/halted

(retained)

Halted

(retained) Halted

(retained)

Timer R

On-chip

supporting

module

operation

Timer X1*2

Functioning Functioning Functioning

Functioning

/halted

(reset)

Halted

(reset) Halted

(reset)

Watchdog

timer Functioning Functioning Functioning Functioning Halted

(retained) Halted

(retained)

8-bit PWM

14-bit PWM*2 Functioning Functioning Functioning Functioning

/halted

(retained)

Halted

(retained) Halted

(retained)

12-bit PWM Functioning Functioning Halted

(reset) Functioning

/halted

(reset)

Halted

(reset) Halted

(reset)

PSU Functioning Functioning Functioning Functioning

/halted Subclock

operation Subclock

operation Halted

SCI1 Functioning

/halted*1 Halted*1 Halted*1 Halted*1 Halted*1

IIC Functioning

/halted

(retained)

Halted

(retained) Halted

(retained)

A/D

Functioning Functioning Functioning

Functioning

/halted

(reset)

Halted

(reset) Halted

(reset)

Servo circuit Functioning Functioning Halted

(reset) Functioning

/halted

(reset)

Halted

(reset) Halted

(reset)

Sync

separator Functioning Functioning Halted

(retained) Functioning

/halted

(retained)

Halted

(retained) Halted

(retained)

Data slicer Halted

(reset)

OSD

Functioning Functioning Halted

(reset) Functioning

/halted

(reset)

Halted

(reset) Halted

(reset)

Notes: 1. "Halted (retained)" means that internal register values are retained. The internal state

is "operation suspended."

2. "Halted (reset)" means that internal register values and internal states are initialized.

3. In module stop mode, only modules for which a stop setting has been made are halted

(reset or retained).

Rev. 1.0, 02/01, page 73 of 1184

4. In the power-down mode, the analog section of the servo circuits are not turned off,

therefore Vcc (Servo) current does not go low. When power-down is needed,

externally shut down the analog system power.

*1 The SCI1 status differs from the internal register. For details, refer to section 22, Serial

Communication Interface 1.

*2 Not available in the H8S/2197S or H8S/2196S.

Program-halted state

Conditions for mode transition (1) Conditions for mode transition (2)

Interruption factor

Sleep

(high-speed)

mode

Sleep

(medium-speed)

mode

Subsleep

mode

Program execution state

Reset state

Flag

SLEEP

instruction

Interrupt

LSON SSBY TMA3 DTON

a010*

b*110

c0111

d1111

e00**

f101*

gSCK1 to 0 = 0

SCK1 to 0 ≠ 0 (either 1 bit = 0)

Power-down mode

Active

(high-speed)

mode

Active

(medium-speed)

mode

Subactive

mode

Program-halted state

Watch

mode

Standby

mode

IRQ0

1, Timer A interruption

All interruption (excluding servo system)

IRQ0

5, Timer A interruption

Interrupt

SLEEP

instruction

SLEEP

instruction

Note: When a transition is made between

modes by means of an interrupt,

transition cannot be made on interrupt

source generation alone. Ensure that

interrupt handling is performed after

accepting the interrupt request

SLEEP

instruction a

Interrupt

SLEEP

instruction

SLEEP

instruction

SLEEP

instruction

SLEEP

instruction

ghd

SLEEP

instruction

Interrupt 2

Interrupt 3

Interrupt 2Interrupt 4

SLEEP

instruction

SLEEP

instruction SLEEP

instruction 1

Note: * Don't care

Figure 4.1 Mode Transitions

Rev. 1.0, 02/01, page 74 of 1184

Table 4.2 Power-Down Mo de Transition Conditions

Control Bit States at Time of

Transition

State before

Transition SSBY TMA3 LSON DTON State after Transition

by SLEEP Instruction State after Return

by Interrupt

0 * 0 * Sleep High-speed/

medium-speed*1

0 * 1 *  

1 0 0 * Standby High-speed/

medium-speed*1

1 0 1 *  

1 1 0 0 Watch High-speed/

medium-speed*1

1 1 1 0 Watch Subactive

1 1 0 1  

High-speed/

medium-

speed

1 1 1 1 Subactive 

0 0 * *  

0 1 0 *  

0 1 1 * Subsleep Subactive

1 0 * *  

1 1 0 0 Watch High-speed/

medium-speed*2

1 1 1 0 Watch Subactive

1 1 0 1 High-speed/

medium-speed*2 

Subactive

1 1 1 1  

Notes: * Don't care

: Do not set.

1. Returns to the state before transition.

2. Mode varies depending on the state of SCK1 to SCK0.

Rev. 1.0, 02/01, page 75 of 1184

4.1.1 Register Configuration

The power-down state is controlled by the SBYCR, LPWRCR, TMA (Timer A), and MSTPCR

registers. Table 4.3 summarizes these registers.

Table 4.3 Power-Down State Registers

Name Abbreviation R/W Initial Value Address*

Standby control register SBYCR R/W H'00 H'FFEA

Low-power co ntrol register LPWRCR R/W H'00 H'FFEB

MSTPCRH R/W H'FF H'FFEC Module stop control register

MSTPCRL R/W H'FF H'FFED

Timer mode register A TMA R/W H'30 H'FFBA

Note: * Lower 16 bits of the address.

Rev. 1.0, 02/01, page 76 of 1184

4.2 Register Descriptions

4.2.1 Standby Control Register (SBYCR)

R/W

——

R/W

R/WR/W

STS1

R/W

STS2

R/W

SSBY STS0 SCK1 SCK0

Bit :

Initial value :

R/W :

SBYCR is an 8-bit readable/writable register that performs power-down mode control.

SBYCR is initialized to H'0 0 by a reset.

Bit 7



Software Standby (SSBY): Determines the op er a ting mode, in combination with other

control bits, when a power-down mode transition is made by executing a SLEEP instruction. The

SSBY setting is not changed by a mode transition due to an interrupt, etc.

Bit 7

SSBY Description

0 Transition to sleep mode after execution of SLEEP instruction in high-speed mode

or medium-speed mode

Transition to subsleep mode after execution of SLEEP instruction in subactive

mode (Initial value)

1 Transition to standby mode, subactive mode, or watch mode after execution of

SLEEP instruction in high-speed mode or medium-speed mode

Transition to watch mode or high-speed mode after execution of SLEEP instruction

in subactive mode

Rev. 1.0, 02/01, page 77 of 1184

Bits 6 to 4



Standby Timer Select 2 to 0 (STS2 t o STS0): These bits select the time th e MCU

waits for the clock to stabilize when standby mode, watch mode, or subactive mode is cleared and

a transition is made to high-speed mode or medium-speed mode by means of a specific interrupt

or instruction. With crystal oscillation, see tab le 4 . 5 and make a selection according to the

operating frequency so that the standby time is at least 10 ms (the oscillation settling time).

Bit 6 Bit 5 Bit 4

STS2 STS1 STS0 Description

0 0 0 Standby time = 8192 states

0 0 1 Standby time = 16384 states

0 1 0 Standby time = 32768 states

0 1 1 Standby time = 65536 states

1 0 0 Standby time = 131072 states

1 0 1 Standby time = 262144 states

1 1 * Reserved

Note: * Don't care

Bits 3 and 2



Reserved: These bits cannot be modified and are always read as 0.

Bits 1 and 0



System Clock Select 1 and 0 (SCK1 , SCK0): These bits select the CPU clock for

the bus master in high-speed mode and medium-speed mode.

Bit 1 Bit 0

SCK1 SCK0 Description

0 0 Bus master is in high-speed mode (Initial value)

0 1 Medium-speed clock is φ/16

1 0 Medium-speed clock is φ/32

1 1 Medium-speed clock is φ/64

Rev. 1.0, 02/01, page 78 of 1184

4.2.2 Low-Power Contro l Register (LPWRCR)

R/W R/W

———

R/W

NESEL

R/W

LSON

R/W

DTON SA1 SA0

Bit :

Initial value :

R/W :

LPWRCR is an 8-bit readable/writable register that performs power-down mode control.

LPWRCR is initialized to H'0 0 by a reset.

Bit 7



Direct-Transfer on Flag (DTON): Specifies whether a direct transition is made between

high-speed mode, medium-speed mode, and subactive mode when making a power-down

transition by executing a SLEEP instruction. The operating mode to which the transition is made

after SLEEP instruction execution is determined by a combination of other control bits.

Bit 7

DTON Description

0 • When a SLEEP instruction is executed in high-speed mode or medium-speed

mode, a transition is made to sleep mode, standby mode, or watch mode

• When a SLEEP instruction is executed in subactive mode, a transition is made

to subsleep mode or watch mode (Initial value)

1 • When a SLEEP instruction is executed in high-speed mode or medium-speed

mode, transition is made directly to subactive mode, or a transition is made to

sleep mode or standby mode

• When a SLEEP instruction is executed in subactive mode, a transition is made

directly to high-speed mode, or a transition is made to subsleep mode

Rev. 1.0, 02/01, page 79 of 1184

Bit 6



Low-Speed on Flag (LSON): Determines the o perating mode in combination with o ther

control bits when making a power-down transition by executing a SLEEP instruction. Also

controls whether a transition is made to high-speed mode or to subactive mode when watch mode

is cleared.

Bit 6

LSON Description

0 • When a SLEEP instruction is executed in high-speed mode or medium-speed

mode, transition is made to sleep mode, standby mode, or watch mode

• When a SLEEP instruction is executed in subactive mode, a transition is made

to watch mode, or directly to high-speed mode

• After watch mode is cleared, a transition is made to high-speed mode

(Initial value)

1 • When a SLEEP instruction is executed in high-speed mode a transition is made

to watch mode, subactive mode, sleep mode or standby mode

• When a SLEEP instruction is executed in subactive mode, a transition is made

to subsleep mode or watch mode

• After watch mode is cleared, a transition is made to subactive mode

Bit 5



Noise Elimination Sampling Frequency Select ( NESEL): Selects the frequency at which

the subclock (φw) generated by the subclock pulse generator is sampled with the clock (φ)

generated by the system clock oscillator. When φ = 5 MHz or higher, clear this bit to 0.

Bit 5

NESEL Description

0 Sampling at φ divided by 16

1 Sampling at φ divided by 4

Bits 4 to 2



Reserved: These bits cannot be modified and are always read as 0.

Bits 1 and 0



Subactive Mode Clock Select 1 and 0 (SA1, SA0): These bits select the CPU

operating clock in the subactive mode. These bits cannot be modified in the subactive mode.

Bit 1 Bit 0

SA1 SA0 Description

0 0 Operating clock of CPU is φw/8 (Initial value)

0 1 Operating clock of CPU is φw/4

1 * Operating clock of CPU is φw/2

Note: * Don’t care

Rev. 1.0, 02/01, page 80 of 1184

4.2.3 Timer Register A (TMA)

R/W

——

R/WR/WR/WR/W

TMA3

R/W

TMA2

R/W

TMAIE

R/(W)*

TMAOV TMA1 TMA0

Bit :

Initial value :

R/W :

Note: * Only 0 can be written, to clear the flag.

The timer register A (TMA) controls timer A interrupts and selects input clock.

Only bit 3 is explained here. For details of other bits, see section 11.2.1, Timer Mode Register A.

TMA is a readable/writable r egister which is initialized to H'30 by a reset.

Bit 3



Clock Source, Prescaler Select (TMA3): Selects timer A clock source b e tween PSS and

PSW. It also controls transition operation to the power-down mode. The operation mode to which

the MCU is transited after SLEEP instruction execution is determined by the combination with

other control bits.

For details, see the description of clock select 2 to 0 in section 11.2.1, Timer Mode Register A.

Bit 3

TMA3 Description

0 • Timer A counts φ-based prescaler (PSS) divided clock pulses

• When a SLEEP instruction is executed in high-speed mode or medium-speed

mode, a transition is made to sleep mode or software standby mode

(Initial value)

1 • Timer A counts φw-based prescaler (PSW) divided clock pulses

• When a SLEEP instruction is executed in high-speed mode or medium-speed

mode, a transition is made to sleep mode, watch mode, or subactive mode

• When a SLEEP instruction is executed in subactive mode, a transition is made

to subsleep mode, watch mode, or high-speed mode

Rev. 1.0, 02/01, page 81 of 1184

4.2.4 Module Stop Control Register (MSTPCR)

MSTP15

R/W

MSTPCRH

MSTP14

R/W

MSTP13

R/W

MSTP12

R/W

MSTP11

R/W

MSTP10

R/W

MSTP9

R/W

MSTP8

R/W

MSTP7

R/W

MSTP6

R/W

MSTP5

R/W

MSTP4

R/W

MSTP3

R/W

MSTP2

R/W

MSTP1

R/W

MSTP0

R/W

MSTPCRL

Bit :

Initial value :

R/W :

MSTPCR comprises two 8-bit readable/writable registers that perform module stop mode control.

MSTPCR is initialized to H'FFFF by a reset.

MSTRCRH and MSTPCRL Bits 7 to 0



Module Stop ( MSTP 15 to MSTP 0): These bits

specify module stop mode. See table 4.4 for the method of selecting on-chip supporting modules.

MSTPCRH, MSTPCRL

Bits 7 to 0

MSTP 15 to MSTP 0 Description

0 Module stop mode is cleared

1 Module stop mode is set (Initial value)

Rev. 1.0, 02/01, page 82 of 1184

4.3 Medium-Speed Mode

When the SCK1 and SCK0 bits in SBYCR are set to 1 in high-speed mode, the operating mode

changes to medium-speed mode at the end of the bus cycle. In medium-speed mode, the CPU

operates on the operating clock (φ16, φ32 or φ64) specified by the SCK1 and SCK0 bits. The on-

chip supporting modules other than the CPU always operate on the high-speed clock (φ).

In medium-speed mode, a bus access is executed in the specified number of states with respect to

the bus master operating clock. For example, if φ16 is selected as the operating clock, on-chip

memory is accessed in 16 states, and internal I/O registers in 32 states.

Medium-speed mode is cleared by clearing the both bits SCK1 and SCK0 to 0. A transition is

made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle.

If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit in LPWRCR

are cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt,

medium-speed mode is restored.

If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, and the LSON bit in

LPWRCR and the TMA3 bit in TMA (Timer A) are both cleared to 0, a transition is made to

software standby mode. When standby mode is cleared by an external interrupt, medium-speed

mode is restored.

When the RES pin is driven low, a transition is made to the reset state, and medium-speed mode is

cleared. The same applies in the case of a reset caused by overflow of the watchdog timer.

Figure 4.2 shows the timing for transition to and clearance of medium-speed mode.

Medium-speed mode

Internal φ,

supporting module clock

CPU clock

Internal address bus

Internal write signal

SBYCR SBYCR

Figure 4.2 Medium- Speed Mode Transition and Clea rance Timing

Rev. 1.0, 02/01, page 83 of 1184

4.4 Sleep Mode

4.4.1 Sleep Mode

If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit in LPWRCR

are both cleared to 0, the CPU will enter sleep m ode. In sleep m o de, CPU operation stops but the

contents of the CPU's internal registers are retained. Other supporting modules (excluding some

functions) do not stop.

4.4.2 Clearing Sleep Mode

Sleep mode is cleared by any interrupt, or with the RES pin.

Clearing with an Interrupt: When an interrupt request signal is input, sleep mode is cleared and

interrupt ex ception hand ling is started. Sleep m ode will not be cleared if interrup ts ar e d isabled,

or if interrupts other than NMI have been masked by the CPU.

Clearing with the RES

RESRES

RES Pin: When the RES pin is driven low, th e reset state is entered. When the

RES pin is driven high after the prescribed reset input period, the CPU begins reset exception

handling.

Rev. 1.0, 02/01, page 84 of 1184

4.5 Module Stop Mode

4.5.1 Module Stop Mode

Module stop mode can be set for individual on-chip supporting modules.

When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of

the bus cycle and a transition is made to module stop mode. The CPU continues operating

independently.

Table 4.4 shows MSTP bits and the on-chip supporting modules.

When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module

starts operating again at the end of the bus cycle. In module stop mode, the internal states of

modules excluding some modules are retained.

After reset release, all modules are in module stop mode.

When an on-chip supporting module is in module stop mode, read/write access to its registers is

disabled.

Table 4.4 MSTP Bits and Corresponding On-Chip Supporting Modules

MSTP15 Timer A

MSTP14 Timer B

MSTP13 Timer J

MSTP12 Timer L

MSTP11 Timer R

MSTP10 Timer X1*

MSTP9 Sync separator

MSTPCRH

MSTP8 Serial communication interface 1 (SCI1)

MSTP7 I2C bus interface (IIC0)*

MSTP6 I2C bus interface (IIC1)

MSTP5 14-bit PWM*

MSTP4 8-bit PWM

MSTP3 Data slicer

MSTP2 A/D converter

MSTP1 Servo circuit, 12-bit PWM

MSTPCRL

MSTP0 OSD

Note: * This bit has no function in the H8S/2197S or H8S/2196S.

Rev. 1.0, 02/01, page 85 of 1184

4.6 Standby Mode

4.6.1 Standby Mode

If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, the LSON bit in

LPWRCR is cleare d to 0, a nd the T MA3 bit in T MA (Timer A) is cleared to 0 , standby mode will

be entered. In this mode, the CPU, on-chip supporting modules, and oscillator (except for

subclock oscillator) all stop. However, the contents of the CPU's in ternal registers and data in the

on-chip RAM, as well as on-chip pe r ip heral circuits (with some exception s), are maintained in the

current state. (Tim er X1 and SCI1 are partially reset.) The I /O p o rt, at this time, is caused to the

high impedance state.

In this mo d e the oscillator stops, and therefore p ower dissipation is significantly reduced.

4.6.2 Clearing Standby Mode

Standby mode is cleared by an external interrupt (pin IRQ0 to IRQ1), or by means of the RES pin.

Clearing with an Interrupt: When an IRQ0 to IRQ1 interrupt request signal is input, clock

oscillation starts, and after the elapse o f the time set in bits STS2 to STS0 in SYSCR, stable clock s

are supplied to the entire chip, standby mode is cleared, and interrupt exception handling is

started.

Standby mode cannot be cleared with an IRQ0 to IRQ1 interrupt if the corresponding enable bit

has been cleared to 0 or has been masked by the CPU.

Clearing with the RES

RESRES

RES Pin: When the RES pin is driven low, clo ck oscillation is started. At the

same time as clock oscillation starts, clocks are supplied to the entire chip. Note that the RES pin

must be he ld low until clock oscillation stabilizes. Wh en the RES pin goes high, the CPU begins

reset exception handling.

4.6.3 Setting Oscillation Settling Time after Clea ring Standby Mode

Bits STS2 to STS0 in SBYCR should be set as described below.

Using a Crysta l Oscillator: Set bits STS2 to STS0 so that the standby time is at least 10 ms (the

oscillation settling time).

Table 4.5 shows the standby times for different operating frequencies and settings of bits STS2 to

STS0.

Rev. 1.0, 02/01, page 86 of 1184

Table 4.5 Oscillation Set t ling Time Settings

STS2 STS1 STS0 Standby Time 10 MHz 8 MHz Unit

0 8192 states 0.8 1.0 0

1 16384 states 1.6 2.0

0 32768 states 3.3 4.1

1 65536 states 6.6 8.2

0 131072 states 13.1*1 16.4*1 0

1 262144 states 26.2 32.8

1 * Reserved  

Notes: * Don't care

1. Recommended time setting

Using an External Clock: Any value can be set.

Rev. 1.0, 02/01, page 87 of 1184

4.7 Watch Mode

4.7.1 Watch Mode

If a SLEEP instruction is executed in high-speed mode, medium-speed mode or subactive mode

when the SSBY in SBYCR is set to 1, the DTON bit in LPWRCR is clear ed to 0, and the TMA3

bit in TMA (Timer A) is set to 1, the CPU will mak e a transition to watch mode.

In this mode, the CPU and all on-chip supporting modules except timer A stop. As long as the

prescribed voltage is supplied, the contents of CPU registers, some on-chip supporting module

registers, and on-chip RAM, are retained, and I/O ports are placed in the high-impedance state.

4.7.2 Clearing Watch Mode

Watch mode is cleared by an interrupt (Timer A interrupt, or pin IRQ0 to IRQ1), or by means of

the RES pin.

Clearing with an Interrupt: When an interrupt request signal is input, watch mode is cleared and

a transition is made to high-speed mode or medium-speed mode if the LSON bit in LPWRCR is

cleared to 0, or to subactiv e m ode if the LSON bit is set to 1. When mak in g a transition to

medium- speed mode, after the elapse of the time set in bits STS2 to STS0 in SBYCR, stable

clocks are supplied to the entire chip, and interrupt exception handling is started.

Watch mode cannot be cleared with an IRQ0 to IRQ1 interrupt if the corresponding enable bit has

been cleared to 0, or with an on-chip supporting module interrupt if acceptance of the relevant

interrupt has been disabled by the interrupt enable register or masked by the CPU.

See section 4.6.3, Setting Oscillation Settling Time after Clearing Standby Mode, for the

oscillation settling tim e setting when making a transitio n from watch mode to high-speed m ode or

medium-speed mode.

Clearing with the RES

RESRES

RES Pin: See Clearing with the RES Pin in section 4.6.2, Clearing Standby

Mode.

Rev. 1.0, 02/01, page 88 of 1184

4.8 Subsleep Mode

4.8.1 Subsleep Mode

If a SLEEP instruction is executed in subactive mode when the SSBY in SBYCR is cleared to 0,

the LSON bit in LPWRCR is set to 1, and the TMA3 bit in TMA (Timer A) is set to 1, the CPU

will make a transition to subsleep m ode.

In this mode, the CPU and all on-chip supporting modules other than Timer A stop. As long as

the prescribed voltage is supplied, the contents of CPU registers, some on-chip supporting module

registers, and on-chip RAM, are retained, and I/O ports are placed in the high-impedance state.

4.8.2 Clearing Subsleep Mode

Subsleep mode is cleared by an interrupt (Timer A interrupt, or pin IRQ0 to IRQ5), or by means

of the RES pin.

Clearing with an Interrupt: When an interrupt request signal is input, subsleep mode is cleared

and interrupt exception handling is started. Subsleep mode cannot be cleared with an IRQ0 to

IRQ5 interrupt if the corresponding enable bit has been cleared to 0, or with an on-chip supporting

module interrupt if acceptance of the relevant interrupt has been disabled by the interrupt enable

Clearing with the RES

RESRES

RES Pin: See (2) Clearing with the RES Pin in section 4.6.2, Clearing Standby

Mode.

Rev. 1.0, 02/01, page 89 of 1184

4.9 Subactive Mode

4.9.1 Subactive Mode

If a SLEEP instruction is executed in high-speed mode when the SSBY bit in SBYCR, the DTON

bit in LPWRCR, and th e TMA3 bit in TMA (timer A) are all set to 1, the CPU will m a ke a

transition to subactive mod e. When an interr u pt is generated in watch mode, if the LSON bit in

LPWRCR is set to 1, a tr ansition is made to subactive mode. When an inter rupt is generated in

subsleep mode, a transition is made to subactive mode.

In subactive mode, the CPU performs sequential program execution at low speed on the subclock.

In this mode, all on-chip supporting modules other than timer A stop.

4.9.2 Clearing Subactive Mode

Subsleep mode is cleared by a SLEEP instruction, or by means of the RES pin.

Clearing with a SLEEP Instruction: When a SLEEP instruction is executed while the SSBY bit

in SBYCR is set to 1, th e DTON bit in LPWRCR is cleared to 0 , and the TMA3 bit in TMA (timer

A) is set to 1, subactive mode is cleared and a transition is made to watch mode. When a SLEEP

instruction is executed while the SSBY bit in SBYCR is cleared to 0, the LSON bit in LPWRCR is

set to 1, and the TMA3 bit in TMA (timer A) is set to 1, a transitio n is made to sub sleep m ode.

When a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the DTON bit is

set to 1 and th e LSON bit is cleared to 0 in LPWRCR, and the TMA3 bit in TMA (timer A) is set

to 1, a transition is made directly to high-speed or medium-speed mode.

For details of direct transition, see section 4.10, Direct Transition.

Clearing with the RES

RESRES

RES Pin: See Clearing with the RES Pin in section 4.6.2, Clearing Standby

Mode.

Rev. 1.0, 02/01, page 90 of 1184

4.10 Direct Transition

4.10.1 Overview of Direct Transition

There are three operating modes in which the CPU executes programs: high-speed mode,

medium-speed mode, and subactive mode. A transition between high-speed mode and subactive

mode without halting the program* is called a direct transition. A direct transition can be carried

out by setting the DTON bit in LPWRCR to 1 and executing a SLEEP instruction. After the

transition, direct transition interrupt exception handling is started.

Direct Transition from High-Speed Mode to Subactive Mode: If a SLEEP instruction is

executed in high-speed m ode while the SSBY b it in SBYCR, the LSON bit and DTON b it in

LPWRCR, and the TMA3 b it in TMA (Timer A) are all set to 1, a transition is made to subactive

mode.

Direct Transition from Subactive Mode to High-Speed Mode/Medium-Speed Mode: If a

SLEEP instruction is executed in subactive mode while the SSBY bit in SBYCR is set to 1, the

LSON bit is cle a red to 0 a nd the DTON bit is set to 1 in LPWRCR, and the TMA3 bit in TMA

(timer A) is set to 1, after the elapse of the time set in b its STS2 to STS0 in SBYCR, a tran sition is

made to directly to high-speed mode or medium-speed mode.

Note: * At the time of transition from subactive mode to high- or medium-speed mode, an

oscillation stabilizatio n wait time is gener ated.

Rev. 1.0, 02/01, page 91 of 1184

Section 5 Exception Handling

5.1 Overview

5.1.1 Exception Handling Types and Priority

As table 5.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt.

Exception handling is prioritized as shown in table 5.1. If two or more exceptions occur

simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions

are accepted at all times in the program execution state.

Exception handling sources, the stack structure, and the operation of the CPU vary depending on

the interrupt control mode set by the INTM0 and INTM1 bits in SYSCR.

Table 5.1 Exception Types and Priority

Priority Exception

Type Start of Exception Handling

Reset Starts immediately after a low-to-high transition at the RES pin, or

when the watchdog timer overflows

Trace*1 Starts when execution of the current instruction or exception

handling ends, if the trace (T) bit is set to 1

Interrupt Starts when execution of the current instruction or exception

handling ends, if an interrupt request has been issued*2

Direct transition Started by a direct transition resulting from execution of a SLEEP

instruction

High

Low Trap instruction

(TRAPA)*3 Started by execution of a trap instruction (TRAPA)

Notes: 1. Traces are enabled only in interrupt control modes 2 and 3. (They cannot be used in

this LSI.) Trace exception handling is not executed after execution of an RTE

instruction.

2. Inte rrupt detection is not performed on c ompletion o f ANDC, ORC, XORC, or LDC

instruction execution, or on completion of reset exception handling.

3. Trap instruction exception handling requests are accepted at all times in the program

execution state.

Rev. 1.0, 02/01, page 92 of 1184

5.1.2 Exception Handling Operation

Exceptions originate from various sources. Trap instructions and interrupts are handled as

follows:

1. The program counter (PC) and condition-code register (CCR) are pushed onto the stack.

2. The interrupt mask bits are updated. The T bit is cleared to 0.

3. A vector address corresponding to the exception source is generated, and program execution

starts from that address.

For a reset exception, steps 2 and 3 above are carried out.

5.1.3 Exception Sources and Vector Table

The exception sources are classified as shown in figure 5.1. Different vector addresses are

assigned to different exception sources.

Table 5.2 lists the exception sources and their vector addresses.

Exception sources

• Reset

• Interrupts

• Trap instruction

Note: * In this LSI, the watchdog timer generates NMIs.

• Trace (cannot be used in this LSI)

• Direct transition

External interrupts NMI*, IRQ5 to IRQ0

Internal interrupts Interrupt sources in on-chip supporting modules

…

Figure 5.1 Exception Sources

Rev. 1.0, 02/01, page 93 of 1184

Table 5.2 Exception Vector Table

Exception Source Vector Number Vector Address*1

Reset 0 H'0000 to H'0003

1 H'0004 to H'0007

2 H'0008 to H'000B

3 H'000C to H'000F

4 H'0010 to H'0013

Reserved for system use

5 H'0014 to H'0017

Direct transition 6 H'0018 to H001B

External interrupt NMI*2 7 H'001C to H'001F

8 H'0020 to H'0023

9 H'0024 to H'0027

10 H'0028 to H'002B

Trap instruction (4 sources)

11 H'002C to H'002F

12 H'0030 to H'0033

13 H'0034 to H'0037

14 H'0038 to H'003B

Reserved for system use

15 H'003C to H'003F

#0 16 H'0040 to H'0043

#1 17 H'0044 to H'0047

Address trap

#2 18 H'0048 to H'004B

Internal interrupt (IC) 19 H'004C to H'004F

Internal interrupt (HSW1) 20 H'0050 to H'0053

IRQ0 21 H'0054 to H'0057

IRQ1 22 H'0058 to H'005B

IRQ2 23 H'005C to H'005F

IRQ3 24 H'0060 to H'0063

IRQ4 25 H'0064 to H'0067

External interrupt

IRQ5 26 H'0068 to H'006B

Internal interrupt*2 27

H'006C to H'006F

H'007C to H'007F

Reserved 32

H'0080 to H'0083

H'0084 to H'0087

Internal interrupt*3 34

H'0088 to H'008B

H'010C to H'010F

Notes: 1. Lower 16 bits of the address.

2. In this LSI, the watch dog timer generates NMIs.

3. For details on internal interrupt vectors, see section 6.3.3, Interrupt Exception Vector

Table.

Rev. 1.0, 02/01, page 94 of 1184

5.2 Reset

5.2.1 Overview

A reset has the h ig hest exception priority. Wh en the RES pin goes low, all processing halts and

the LSI enters the r eset state. A reset initializes the intern al state of the CPU and the registers of

on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set.

Reset exception handling begins when the RES pin changes from low to high.

The LSIs can also be reset by overflow of the watchdog timer. For details, see section 17,

Watchdog Timer.

5.2.2 Reset Sequence

The LSI enters the reset state when the RES pin goes low.

To ensure th at the chip is reset, hold the RES pin low during the oscillation stabilizing time of the

clock oscillator wh en powering on. To reset the ch ip during operation, h old the RES pin low for

at least 20 states. For pin states in a reset, see Appendix D, Port States in the Different Processing

States.

When the RES pin goes high after being held low for the necessary time, the chip starts reset

exception handling as follows:

1. The internal state of the CPU and the registers of the on-chip supporting modules are

initialized, and the I bit is set to 1 in CCR.

2. The reset exception vector address is read and transferred to the PC, and program execution

starts from the address indicated by the PC.

Figure 5.2 shows examples of the reset sequence.

Rev. 1.0, 02/01, page 95 of 1184

RES

Internal address bus

Internal read signal

Internal write signal

Internal data bus

Vector

fetch

(1)

(2)

(3)

(4)

: Reset exception vector address ((1) = H'0000 or H'000000)

: Start address (contents of reset exception vector address)

: Start address ((3) = (2))

: First program instruction

(1) (3)

High level

Internal

processing Fetch of first program

instruction

(2) (4)

Figure 5.2 Reset Sequence (Mode 1)

5.2.3 Interrupts after Reset

If an interrupt is accepted after a reset b ut before the stack po in ter (SP) is in itialized , the PC and

CCR will not be saved correctly, leading to a program crash. To prevent this, all in ter r upt

requests, including NMI, are disabled immediately after a reset. Since the first instruction of a

program is always executed immediately after the reset state ends, make sure that this instruction

initializes the stack pointer (example: MOV.L #xx:32, SP).

Rev. 1.0, 02/01, page 96 of 1184

5.3 Interrupts

Interrupt exception handling can be requested by six external sources (IRQ5 to IRQ0) and internal

sources in the on-chip supporting modules. Figure 5.3 shows the interrupt sources and the number

of interrupts of each type.

The on-chip supporting modules that can request interrupts include the watchdog timer (WDT),

prescaler unit (PSU), Timers A, B, J, L, R and X1 (TMR), serial communication interface (SCI),

A/D converter (ADC), I2C bus interface (IIC), servo circuits, sync detection, data slicer, OSD,

address trap, etc. Each interrupt source has a separate vector address.

NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The

interrupt controller has two interrupt control modes and can assign interrupts other than NMI to

either three priority/mask lev e ls to enable multip lexed interru pt control.

For details on interrupts, see section 6, Interrupt Controller.

WDT*

(1)

PSU (1)

TMR (15)*

SCI (4)

ADC (1)

IIC (3)*

Servo circuits (9)

Synchronized detection (1)

Address trap (3)

Interrupts

Internal

interrupts

External

interrupts

Notes: Numbers in parentheses are the numbers of interrupt sources.

In this LSI, the watchdog timer generates NMIs.

When the watchdog timer is used as an interval timer, it generates an interrupt

request at each counter overflow.

The number of interrupt sources is eight in the H8S/2197S or H8S/2196S.

The number of interrupt sources is one in the H8S/2197S or H8S/2196S.

NMI*

(1)

IRQ5 to IRQ0 (6)

Figure 5.3 Interrupt Sources and Number of Interrupts

Rev. 1.0, 02/01, page 97 of 1184

5.4 Trap Instruction

Trap instruction exception handling starts when a TRAPA instruction is executed. Trap

instruction exception handling can be executed at all times in the program execution state.

The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector

number from 0 to 3, as specified in the instruction code.

Table 5.3 shows the status of CCR and EXR after execution of trap instruction exception

handling.

Table 5.3 Status of CCR and EXR after Trap Instructio n Exception Handling

CCR EXR*

Interrupt

Control Mode I UI I2 to I0 T

0 1   

1 1 1  

Legend:

1: Set to 1

0: Cleared to 0

: Retains value prior to execution.

*: Does not affect operation in this LSI.

Rev. 1.0, 02/01, page 98 of 1184

5.5 Stack Status after Exception Handling

Figures 5.4 and 5.5 show the stack after completion of trap instruction exception handling and

interrupt exception handling.

CCR

CCR*

(16 bits)

SP→

Note: * Ignored on return.

Interrupt control modes 0 and 1

Figure 5.4 Stack Status after Exception Handling (Normal Mode)*

Note: * Normal mode is no t available for this LSI.

CCR

(24 bits)

SP→

Interrupt control modes 0 and 1

Figure 5.5 Stack Status after Exception Handling (Advanced Mode)

Rev. 1.0, 02/01, page 99 of 1184

5.6 Notes on Use of the Stack

When accessing word data or longword data, this chip assumes that the lowest address bit is 0.

The stack should always be accessed by word transfer instruction or longword transfer instruction,

and the value of the stack pointer (SP: ER7) should always be kept even.

Use the following instructions to save registers:

PUSH.W Rn (or MOV.W Rn, @-SP)

PUSH.L ERn (or MOV.L ERn, @-SP)

Use the following instructions to restor e r e gisters:

POP.W Rn (or MOV.W @SP+, Rn )

POP.L ERn (or MOV.L @SP+, ERn)

Setting SP to an odd value may lead to a malfunction. Figure 5.6 shows an example of what

happens when the SP value is odd.

[Legend] : Condition-code register

: Program counter

: General register R1L

: Stack pointer

H'FFFEFA

H'FFFEFB

H'FFFEFC

H'FFFEFD

H'FFFEFF

R1L

SP CCR

CCR

R1L

Note: This diagram illustrates an example in which the interrupt control mode is 0, is advanced mode.

TRAPA instruction executed MOV.B R1L, @-ER7

SP set to H'FFFEFF Data saved above SP Contents of CCR lost

Figure 5.6 Operation when SP Value is Odd

Rev. 1.0, 02/01, page 100 of 1184

Rev. 1.0, 02/01, page 101 of 1184

Section 6 Interrupt Controller

6.1 Overview

6.1.1 Features

This LSI controls interrupts by means of an interrupt controller. The interrupt controller has the

following features:

• Two Interrupt Control Modes

 Either of two interrupt control modes can be set by means of the INTM1 and INTM0 bits

in the system control register (SYSCR).

• Priorities Settable with ICR

 An interrupt control re gister (ICR) is provided fo r setting interru pt priorities. Thr ee

priority levels can be set for each module for all interrupts except NMI.

• Independent Vector Addresses

 All interrupt sources are assigned independent vector addresses, making it unnecessary for

the source to be identified in the interrupt handling routine.

• Six External Interrupt Pins

 NMI is the highest-priority interrupt, and is accepted at all times.

 Falling edge, rising edge, or both edge detection can be selected for interrupt IRQ0.

 Falling edge or rising edge can be individually selected for interrupts IRQ5 to IRQ1.

Note: * In this LSI, the watch dog timer generates NMIs.

Rev. 1.0, 02/01, page 102 of 1184

6.1.2 Block Diagram

Figure 6.1 shows a block diagram of the interrupt controller.

IRQ input

Internal

interrupt

requests

Legend:

IEGR

IENR

IRQR

ICR

SYSCR

: IRQ edge select register

: IRQ enable register

: IRQ status register

: Interrupt control register

: System control register

Interrupt

request

Vector

number

I, UI

IRQ input

unit IRQR

IEGR IENR

ICR

CPU

Interrupt controller

SYSCR INTM1, INTM0

CCR

Priority

determina-

tion

Figure 6.1 Block Diagram of Interrupt Controller

Rev. 1.0, 02/01, page 103 of 1184

6.1.3 Pin Configuration

Table 6.1 summarizes the pins of the interrupt controller.

Table 6.1 Interrupt Controller Pins

Name Symbol I/O Function

External interrupt

request 0 IRQ0 Input Maskable external interrupts; rising, falling, or both

edges can be selected

External interrupt

requests 1 to 5 IRQ1 to

IRQ5 Input Maskable external interrupts: rising, or falling

edges can be selected

6.1.4 Register Configuration

Table 6.2 summarizes the registers of the interrupt controller.

Table 6.2 Interrupt Controller Registers

Name Abbreviation R/W Initial Value Address*1

System control register SYSCR R/W H'00 H'FFE8

IRQ edge select register IEGR R/W H'00 H'FFF0

IRQ enable register IENR R/W H'00 H'FFF1

IRQ status register IRQR R/ (W)*2 H'00 H'FFF2

Interrupt control register A ICRA R/W H'00 H'FFF3

Interrupt control register B ICRB R/W H'00 H'FFF4

Interrupt control register C ICRC R/W H'00 H'FFF5

Interrupt control register D ICRD R/W H'00 H'FFF6

Port mode register 1 PMR1 R/W H'00 H'FFCE

Notes: 1. Lower 16 bits of the address.

2. Only 0 can be written, for flag clearing.

Rev. 1.0, 02/01, page 104 of 1184

6.2 Register Descriptions

6.2.1 System Control Register (SYSCR)

—

R/W

7——XRSTINTM0INTM1

——

—

Bit :

Initial value :

R/W :

SYSCR is an 8-bit r eadable register th at selects the interrup t co ntrol mod e .

Only bits 5, 4, 2 and 1 are described here; for details on the other bits, see section 3.2.2, System

Control Register (SYSCR).

SYSCR is initialized to H'08 by a reset.

Bits 5 and 4



Interrupt Control Mode (INTM1, INTM0) : These bits select one of two

interrupt control modes for the interrupt controller. The INTM1 bit must not be set to 1.

Bit 5 Bit 4

INTM1 INTM0 Interrupt Control

Mode Description

0 0 Interrupts are controlled by I bit (Initial value) 0

1 1 Interrupts are controlled by I and UI bits and ICR

0  Cannot be used in this LSI 1

1  Cannot be used in this LSI

Rev. 1.0, 02/01, page 105 of 1184

6.2.2 Interrupt Control Registers A to D (ICRA to ICRD)

R/W

7ICR4 ICR3 ICR2 ICR1 ICR0

R/W

ICR7

R/WR/WR/W

ICR6 ICR5

Bit :

Initial value :

R/W :

The ICR registers are four 8 - bit readable/writab le r e gisters that set the interr upt contro l level for

interrupts other than NMI.

The correspondence between ICR settings and interrupt sources is shown in table 6.3.

The ICR registers are initialized to H'00 by a reset.

Bits 7 to 0



Interrupt Control Level (ICR7 to ICR0 ): Set the control level f or the

corresponding interrupt source.

Bit n

ICRn Description

0 Corresponding interrupt source is control level 0 (non-priority) (Initial value)

1 Corresponding interrupt source is control level 1 (priority)

(n = 7 to 0)

Table 6.3 Correspondence between Interrupt Sources and ICR Settings

ICRA7 ICRA6 ICRA5 ICRA4 ICRA3 ICRA2 ICRA1 ICRA0 ICRA

Reserved Input

capture HSW1 IRQ0 IRQ1 IRQ2

IRQ3 IRQ4

IRQ5 Sync

separator,

OSD

ICRB7 ICRB6 ICRB5 ICRB4 ICRB3 ICRB2 ICRB1 ICRB0 ICRB

Data sli cer Sync

separator Servo

(drum,

capstan

latch)

Timer A Timer B Timer J Timer R Timer L

ICRC7 ICRC6 ICRC5 ICRC4 ICRC3 ICRC2 ICRC1 ICRC0 ICRC

Timer X1* Synchro-

nized

detection

Watchdog

timer Servo IIC1 SCI1

(UART) IIC0* A/D

ICRD7 ICRD6 ICRD5 ICRD4 ICRD3 ICRD2 ICRD1 ICRD0 ICRD

HSW2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved

Note: * This bit has no function in the H8S/2197S or H8S/2196S.

Rev. 1.0, 02/01, page 106 of 1184

6.2.3 IRQ Enable Register (IENR)

R/W

R/WR/WR/W

IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E

——

Bit :

Initial value :

R/W :

IENR is an 8-bit readable/writable register that controls enabling and disabling of interrupt

requests IRQ5 to IRQ0.

IENR is initialized to H'00 by a reset.

Bits 7 and 6



Reserved: These bits are always read as 0. Do not write 1 to them.

Bits 5 to 0



IRQ5 to IRQ0 Enable (IRQ5E to IRQ0E): These bits select whether IRQ5 to

IRQ0 are enabled or disabled.

Bit n

IRQnE Description

0 IRQn interrupt disabled (Initial value)

1 IRQn interrupt enabled

(n = 5 to 0)

Rev. 1.0, 02/01, page 107 of 1184

6.2.4 IRQ Edge Select Registers (IEGR)

R/W

—

—R/WR/WR/W

IRQ4EG

R/W

IRQ5EG IRQ3EG IRQ2EG IRQ1EG IRQ0EG1 IRQ0EG0

Bit :

Initial value :

R/W :

IEGR is an 8-bit readable/writable register that selects detected edge of the input at pins IRQ5 to

IRQ0.

IEGR register is in itialized to H'00 by a reset.

Bit 7



Reserved: This bit is always read as 0. Do not write 1 to it.

Bits 6 to 2



IRQ5

IRQ5IRQ5

IRQ5 to IRQ1

IRQ1IRQ1

IRQ1 Pins Detected Edge Select (IRQ5EG to IRQ1EG): These bits select

detected edge for interrupts IRQ5 to IRQ1.

Bits 6 to 2

IRQnEG Description

0 Interrupt request generated at falling edge of IRQn pin input (Initial value)

1 Interrupt request generated at rising edge of IRQn pin input

(n = 5 to 1)

Bits 1 and 0



IRQ0

IRQ0IRQ0

IRQ0 Pin Detected Edge Select (IRQ0EG1, IRQ0EG0): These bits select

detected edge for interrupt IRQ0.

Bit 1 Bit 0

IRQ0EG1 IRQ0EG0 Description

0 0 Interrupt request generated at falling edge of IRQ0 pin input (Initial

value)

0 1 Interrupt request generated at rising edge of IRQ0 pin input

1 * Interrupt request generated at both falling and rising edges of IRQ0 pin

input

Note: * Don't care

Rev. 1.0, 02/01, page 108 of 1184

6.2.5 IRQ Status Register (IRQR)

R/(W)*

R/(W)*R/(W)*R/(W)*

IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F

——

Note: * Only 0 can be written, to clear the flag.

Bit :

Initial value :

R/W :

IRQR is an 8-bit read able/writable register th at indicates the status of IRQ5 to IRQ0 interrup t

requests.

IRQR is initialized to H'00 by a reset.

Bits 7 and 6



Reserved: These bits are always read as 0. Do not write 1 to them.

Bits 5 to 0



IRQ5 to IRQ0 Flag s: These bits indicate the status of IRQ5 to IRQ0 interrupt

requests.

Bit n

IRQnF Description

0 [Clearing conditions] (Initial value)

Cleared by reading IRQnF set to 1, then writing 0 in IRQnF

When IRQn interrupt exception handling is executed

1 [Setting conditions]

• When a falling edge occurs in IRQn input while falling edge detection is set

(IRQnEG = 0)

• When a rising edge occurs in IRQn input while rising edge detection is set

(IRQnEG = 0)

• When a falling or rising edge occurs in IRQ0 input while both-edge detection is

set (IRQ0EG1 = 1)

(n = 5 to 0)

Rev. 1.0, 02/01, page 109 of 1184

6.2.6 Port Mode Register 1 (PMR1)

R/W

PMR17 PMR16 PMR15 PMR14 PMR13 PMR12 PMR11 PMR10

R/WR/WR/W

Bit :

Initial value :

R/W :

Port Mode Register 1 (PMR1) controls pin function switching-over of port 1. Switching is

specified for each bit.

PMR1 is an 8-b it r eadable/writable register and is initialized to H'00 by a reset.

Only bits 5 to 0 are explained here. For details, see section 10.3.2, Register Configuration.

Bits 5 to 0



P15/IRQ5

IRQ5IRQ5

IRQ5 to P10/IRQ0

IRQ0IRQ0

IRQ0 pin switching (PMR15 to PMR10): These bits are for

setting the P1n/IRQn pin as the input pin for P1n or as the IRQn pin for external interrupt request

input.

Bit n

PMR1n Description

0 P1n/IRQn pin functions as the P1n input/output pin (Initial value)

1 P1n/IRQn pin functions as the IRQn input/output pin

(n = 5 to 0)

Notes on switching the pin function by PMR1 are as follows:

• When the port is set as the IC input pin or IRQ5 to IRQ0 input pin, the pin level must be high

or low regardless of active mode or power-down mode. Do not set the pin level at medium.

• Switching the pin function of P16/IC or P15/IRQ5 to P10/IRQ0 may be mistak en ly identified

as edge detection and detection signal may be generated. To prevent this, operate as follows:

 Set the interrupt enable/disable f lag to disable before switching the p in function .

 Clear the applicable interrupt request flag to 0 after switching the pin function and

executing another instruction.

Program example

MOV.B R0L,@IENR ⋅⋅⋅⋅⋅⋅ Interrupt disabled

MOV.B R1L,@PMR1 ⋅⋅⋅⋅⋅⋅ Pin function change

NOP ⋅⋅⋅⋅⋅⋅ Optional instruction

BCLR m @IRQR ⋅⋅⋅⋅⋅⋅ Applicable interrupt clear

MOV.B R1L,@IENR ⋅⋅⋅⋅⋅⋅ Interrupt enabled

Rev. 1.0, 02/01, page 110 of 1184

6.3 Interrupt Sources

Interrupt sources comprise external inter r upts (IRQ5 to IRQ0) and internal in ter rupts.

6.3.1 External Interrupts

There are six external interrupt sources; IRQ5 to IRQ0. Of these, IRQ1 to IRQ0 can be used to

restore this chip from standby mode.

• IRQ5 to IRQ0 Interrupts: Interrupts IRQ5 to IRQ0 are requested by an input signal at pins

IRQ5 to IRQ0. Interrupts IRQ5 to IRQ0 have the following features:

(a) Using IEGR, it is possible to select whether an interrupt is requested by a falling edge,

rising edge, or both edges, at pin IRQ0.

(b) Using IEGR, it is possible to select whether an interrupt is requested by a falling edge or

rising edge at pins IRQ5 to IRQ1.

(d) The interrupt control level can be set with ICR.

(e) The status of interrupt requests IRQ5 to IRQ0 is indicated in IRQR. IRQR flags can be

cleared to 0 by software.

Figure 6.2 shows a block diagram of interrupts IRQ5 to IRQ0.

Clear signal

Edge detection

circuit

IRQnEG IRQnF

IRQnE

Note: n = 5 to 0

IRQn interrupt

request

IRQn input

Figure 6.2 Block Diagram of Interrupts IRQ5 to IRQ0

Rev. 1.0, 02/01, page 111 of 1184

Figure 6.3 shows the timing of IRQnF setting.

Internal φ

IRQnF

IRQn

input pin

Figure 6.3 Timing of IRQnF Setting

The vector numbers for IRQ5 to IRQ0 interrupt exception handling are 21 to 26.

Upon detection of IRQ5 to IRQ0 interrupts, the applicable pin is set in the port register 1 (PMR1)

as IRQn pin.

6.3.2 Internal Interrupts

There are 38 sources for internal interrupts from on-chip supporting modules.

• For each on-chip supporting module there are flags that indicate the interrupt request status,

and enable bits that select enabling or disabling of these interrupts. If any one of these is set to

1, an interr upt request is issued to the inter r upt contro ller .

• The interrupt control level can be set by means of ICR.

• The NMI is the highest priority interrupt and is always accepted regardless of the control mode

and CPU interrupt mask bit. In this LSI, NMIs are used as interrupts generated by the

watchdog timer.

Rev. 1.0, 02/01, page 112 of 1184

6.3.3 Interrupt Exception Vector Table

Table 6.4 shows interrup t ex ception handling sour ces, vector addr esses, and interrupt priorities.

For defau lt priorities, the lo wer the vector nu mber, the higher the pr iority.

Priorities among modules can be set by means of ICR. The situation when two or more modules

are set to the same priority, and priorities within a module, are fixed as shown in table 6.4.

Table 6.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities

Priority Interrupt Source Origin of

Interrupt Source Vector

No. Vector Address ICR Remarks

Reset External pin 0 H'0000 to H'0003 

 1 H'0004 to H'0007 

 2 H'0008 to H'000B 

 3 H'000C to H'000F 

 4 H'0010 to H'0013 

Reserved

 5 H'0014 to H'0017 

Direct transiti on Ins tructi on 6 H'0018 to H'001B 

NMI Wat chdog timer 7 H'001C to H'001F 

TRAPA#0 8 H'0020 to H' 0023 

TRAPA#1 9 H'0024 to H' 0027 

TRAPA#2 10 H'0028 to H'002B 

Trap instruc tion

TRAPA#3

Instruction

11 H'002C to H'002F 

12 H'0030 to H'0033

13 H'0034 to H'0037

14 H'0038 to H'003B

High

Low

Reserved 

15 H'003C to H'003F



Rev. 1.0, 02/01, page 113 of 1184

Priority Interrupt Source Origin of

Interrupt Source Vector

No. Vector Address ICR Remarks

#0 16 H'0040 to H'0043

#1 17 H'0044 to H'0047

Address t rap

ATC

18 H'0048 to H'004B



IC P SU 19 H' 004C to H'004F ICRA6

HSW1 Servo ci rcuit 20 H'0050 to H' 0053 ICRA5

IRQ0 21 H'0054 to H'0057 ICRA4

IRQ1 22 H'0058 to H'005B ICRA3

IRQ2 23 H'005C to H'005F

IRQ3 24 H'0060 to H'0063

ICRA2

IRQ4 25 H'0064 to H'0067

IRQ5

External pi n

26 H'0068 to H'006B

ICRA1

External V interrupt Sync separat or 27 H'006C to H'006F ICRA0

OSD V int errupt OSD 28 H'0070 to H'0073

Data sli cer odd field i nterrupt Data s l i cer 29 H'0074 to H' 0077 ICRB7

Data sli cer even fiel d i nterrupt 30 H'0078 to H'007B

Noise int errupt Sync separator 31 H'007C to H'007F ICRB6

Reserved  32 H'0080 to H'0083 

33 H'0084 t o H' 0087

Drum latc h 1 (speed) Servo c ircuit 34 H'0088 t o H'008B ICRB 5

Capstan latch 1 (speed) 35 H' 008C to H'008F

TMAI Timer A 36 H'0090 to H'0093 ICRB4

TMBI Timer B 37 H'0094 to H'0097 ICRB3

High

TMJ1I Timer J 38 H' 0098 to H'009B I CRB 2

TM J 2I 39 H'009C to H'009F

TM R1I Ti m er R 40 H'00A0 to H'00A3 ICRB1

TM R2I 41 H'00A4 to H'00A7

TM R3I 42 H'00A8 to H'00AB

Low TMLI Timer L 43 H'00AC to H'00AF ICRB0

Rev. 1.0, 02/01, page 114 of 1184

Priority Interrupt Source Origin of

Interrupt Source Vector

No. Vector Address ICR Remarks

ICXA* Timer X1* 44 H'00B0 to H'00B3

ICXB* 45 H'00B 4 to H'00B7

ICXC* 46 H'00B8 to H' 00BB

ICXD* 47 H'00BC to H' 00B F

OCX1* 48 H'00C0 to H'00C3

OCX2* 49 H'00C4 to H'00C7

OVFX* 50 H'00C8 t o H' 00CB

ICRC7

VD interrupt s Sync si gnal

detection 51 H'00CC to H' 00CF ICRC6

Reserved  52 H'00D0 to H'00D3

8-bit int erval tim er Wat chdog timer 53 H'00D4 to H'00D7 ICRC5

CTL 54 H'00D8 to H'00DB

Drum latc h 2 (speed) 55 H'00DC to H'00DF

Capstan latch 2 (speed) 56 H' 00E0 to H'00E3

Drum latc h 3 (phase) 57 H'00E4 t o H' 00D7

Capstan latch 3 (phase)

Servo c i rcuit

58 H'00E8 t o H' 00EB

ICRC4

IIC1 IIC1 59 H'00EC to H' 00E F ICRC3

ERI 60 H' 00F0 to H'00F3

RXI 61 H'00F4 to H'00F7

TXI 62 H'00F8 to H'00FB

SCI1

TEI

SCI1

(UART)

63 H'00FC to H'00FF

ICRC2

64 H' 0100 to H'0103 IIC0*

DDCSW*

IIC0*

65 H'0104 to H'0107

ICRC1

A/D conversion end A /D 66 H'0108 to H'010B ICRC0

High

Low HSW2 Servo circuit 67 H'010C to H'010F ICRD7

Note: * Not available in the H8S/2197S or H8S/2196S.

Rev. 1.0, 02/01, page 115 of 1184

6.4 Interrupt Operation

6.4.1 Interrupt Control Modes and Interrupt Operation

Interrupt operations in this LSI differ depending on the interrupt control mode.

The NMI interrupt* and address trap interrupts are accepted at all times except in the reset state.

In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided

for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request.

Interrup t sources in which the enable bits are set to 1 are controlled by the interr upt controller .

Table 6.5 shows the interrupt control modes.

The interrupt controller performs interrupt control according to the interrupt control mode set by

the INTM1 and INTM0 bits in SYSCR, the priorities set in I CR, an d the masking state indicated

by the I and UI bits in the CPU’s CCR.

Note: * In this LSI, the NMI interrupt is generated by the watchdog timer.

Table 6.5 Interrupt Control Modes

SYSCR Interrupt

Control

Mode INTM1 INTM0

Priority Setting

Mask Bits Description

0 0 ICR I Interrupt mask control is

performed by the I bit

Priority can be set with ICR

1 ICR I, UI 3-level interrupt mask control is

performed by the I and UI bits

Priority can be set with ICR

Rev. 1.0, 02/01, page 116 of 1184

Figure 6.4 shows a block diagram of the priority decision circuit.

Interrupt control modes 0 and 1

Interrupt source

Vector number

Interrupt acceptance

control and 3-level

mask control

Default priority

determination

I C R

Figure 6.4 Block Diagram of Interrupt Priority Determination Operation

• Interrupt Acceptance Control and 3-Level Control: In interrupt control modes 0 and 1,

interrupt acceptance control and 3-level mask control is performed by means of the I and UI

bits in CCR, a nd ICR (control level) .

Table 6.6 shows the interrupts selected in each interrupt control mode.

Table 6.6 Interrupts Selected in Each Interrupt Control Mode

Interrupt Mask Bit Interrupt

Control

Mode I UI Selected Interrupts

0 * All interrupts (control level 1 has priority) 0

1 * NMI*1 and address trap interrupts

0 * All interrupts (control level 1 has priority)

0 NMI*1, address trap and control level 1 interrupts

1 NMI*1 and address trap interrupts

Notes: * Don't care

1. In this LSI, the NMI interrupt is generated by the watchdog timer.

• Default Priority Determination : If th e same value is set for ICR, acceptance of multiple

interrupts is enabled, and so only the interrupt source with the highest priority according to the

preset default priorities is selected and has a vecto r number generated.

Interrupt sources with a lower priority than the accepted interrupt source are held pending.

Table 6.7 shows operations and control signal functions in each interrupt control mode.

Rev. 1.0, 02/01, page 117 of 1184

Table 6.7 Operations and Control Sig na l Functions in Each Interrupt Control Mode

Setting Interrupt Acceptance Control,

3-Level Control

Interrupt

Control

Mode INTM1 INTM0 I UI ICR

Default Priority

Determination

0 0 { IM  PR {

1 { IM IM PR {

Legend:

{: Interrupt operation control performed

IM: Used as interrupt mask bit

PR: Sets priority

: Not used

6.4.2 Interrupt Control Mode 0

Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by

the I b it in the CPU’s CCR, and ICR. Interrupts are e nabled w hen the I bit is cleared to 0 , and

disabled when set to 1. Control level 1 interrupt sources have higher priority.

Figure 6.5 shows a flowchart of the interrupt acceptance operation in this case.

• If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an

interrupt r e quest is sent to the interrupt controller.

• When interrupt requests ar e sent to the interrupt controller , a control level 1 interrupt,

according to the control level set in ICR, has priority for selection, and other interrupt requests

are held pending. If a number of interrupt requests with the same control level setting are

generated at the same time, the interrupt request with the highest priority according to the

priority system shown in table 6.4 is selected.

• The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the

I bit is set to 1, only an NMI*1 or an address trap interrupt is accepted, and other interrupt

requests are held pending.

• When an interrupt request is accepted, interrupt exception handling starts after execution of the

current instruction has been completed.

• The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on

the stack shows the address of the first instructio n to be executed after retur ning from the

interrupt handling routine.

• Next, the I bit in CCR is set to 1. This disables all interrupts except NMI* and ad dress trap.

• A vector address is generated for the accepted interrupt, and execution of the interrupt

handling routine starts at the address indicated by the contents of that vector address.

Note: * In this LSI, the NMI interrupt is generated by the watchdog timer.

Rev. 1.0, 02/01, page 118 of 1184

Program execution state

Interrupt

generated?

NMI

Address trap

interrupt?

Control level 1

interrupt?

I C

I = 0

Yes

Yes Yes

Yes

Yes Yes

Save PC and CCR

I ← 1

Read vector address

Branch to interrupt handling routine

I C No

H S W 1H S W 1

H S W 2H S W 2

Hold pending

Figure 6.5 Flowchart of Procedure Up to Interrupt Acceptance in

Interrupt Contro l Mode 0

Rev. 1.0, 02/01, page 119 of 1184

6.4.3 Interrupt Control Mode 1

Three-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts

by means of the I and UI bits in the CPU’s CCR and ICR.

• Control level 0 interrupt requests are enabled when the I bit is cleared to 0, and disabled when

set to 1.

• Control level 1 interrupt r equests are enabled when the I bit o r UI bit is cleared to 0, and

disabled when both the I bit and the UI bit are set to 1.

For example, if the interrupt enable bit for an interrupt request is set to 1, and H'04, H'00, H'00

and H'00 are set in ICRA, ICRB, ICRC and I CRD r e spectively, (i.e. IRQ2 interrupt is set to

control level 1 and o ther interru pts to contro l level 0), the situ ation is as follows:

• When I = 0, all interrupts are enabled

(Priority order: NMI > IRQ2 > IC > HSW1 > ...)

• When I = 1 and UI = 0, only NMI, address trap and IRQ2 interrupts are enabled

• When I = 1 and UI = 1, only NMI and address trap interrupts are enabled

Figure 6.6 shows the state transitions in these cases.

Only NMI, address trap and

IRQ2 interrupts enabled

All interrupts enabled

Exception handling

execution or UI ← 1

Exception handling

execution or

I ← 1, UI ← 1

I ← 0

I ← 1, UI ← 0

UI ← 0

I ← 0

Only NMI and address trap

interrupts enabled

Figure 6.6 Example of State Transitions in Interrupt Control Mode 1

Figure 6.7 shows an operation flowchart of interrupt reception.

Rev. 1.0, 02/01, page 120 of 1184

(1) If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an

interrupt r e quest is sent to the interrupt controller.

(2) When interrupt requests are sen t to the interrupt controller, a control level 1 interrupt,

according to the control level set in ICR, has priority for selection, and other interrupt requests

are held pending. If a number of interrupt requests with the same control level setting are

generated at the same time, the interrupt request with the highest priority according to the

priority system shown in table 6.4 is selected.

(3) The I bit is then referenced. If the I bit is cleared to 0, the UI bit has no effect.

An interrupt request set to interrupt control level 0 is accepted when the I bit is cleared to 0. If

the I bit is set to 1, only NMI* and address trap interrupts are accepted, and other interrupt

requests are held pending.

An interru pt request set to interrupt co ntrol level 1 has priority over an interrupt request set to

interrupt control level 0, and is accepted if the I bit is cleared to 0, or if the I bit is set to 1 and

the UI bit is cleared to 0.

When both the I bit and the UI bit are set to 1, only NMI* and address trap interrupts are

accepted, and other interrupt requests are held pending.

(4) When an interrupt request is accepted, interrupt exception handling starts after execution of the

current instruction has been completed.

(5) The PC a nd CCR are saved to the stack area by interr upt exception handling. The PC saved on

the stack shows the address of the first instructio n to be executed after retur ning from the

interrupt handling routine.

(6) Next, the I and UI bits in CCR are set to 1. This m asks all interrupts except N M I* and addr ess

trap.

(7) A vector address is generated for the accepted interrupt, and execution of the interrupt

handling routine starts at the address indicated by the contents of that vector address.

Note: * In this LSI, the NMI interrupt is generated by the watchdog timer.

Rev. 1.0, 02/01, page 121 of 1184

Program execution state

NMI

I C

Yes

Yes Yes

Yes

Yes Yes

I C No

H S W 1H S W 1

H S W 2

Yes

Interrupt

generated?

Address trap

interrupt?

Control level 1

interrupt?

I = 0 I = 0

UI = 0

Save PC and CCR

I ← 1, UI ← 1

Read vector address

Branch to interrupt handling routine

Hold pending

Figure 6.7 Flowchart of Procedure Up to Interrupt Acceptance in

Interrupt Contro l Mode 1

Rev. 1.0, 02/01, page 122 of 1184

6.4.4 Interrupt Exception Handling Sequence

Figure 6.8 shows the interrupt exception handling sequence. The example shown is for the case

where interrupt control 0 is set in advanced mode, and the program area and stack area are in on-

chip memory.

(1)

(1) Instruction prefetch address (Not executed.

This is the contents of the saved PC, the

return address.)

Saved PC and saved CCR

Vector address

Interrupt handling routine start address (vector address contents)

Interrupt handling routine start address ((13) = (10)(12))

First instruction of interrupt handling routine

(2)(4)

(6)(8)

(10)(12)

(13)

(9)(11)

(14)

(3) (5) (7) (9) (11) (13)

Internal

address bus

Interrupt

request signal

Internal read

signal

Internal

write signal

Internal

data bus (2) (4) (6) (8) (10) (12) (14)

Stack Vector fetch

Interrupt level

determination

Wait for end of

instruction

Interrupt

acceptance

Internal

operation Internal

operation

Instruction

prefetch Interrupt handling routine

instruction prefetch

Instruction code (Not executed.)

(3) Instruction prefetch address (Not executed.)

(5) SP-2

(7) SP-4

Figure 6.8 Interrupt Exception Handling

Rev. 1.0, 02/01, page 123 of 1184

6.4.5 Interrupt Response Times

Table 6.8 shows interrupt response times-the interval between generation of an interrupt request

and execution of the first instruction in the interrupt handling routine. The symbols used in table

6.8 are explained in table 6.9.

Table 6. 8 Inter r upt Response Times

No. Number of States Advanced Mode

1 Interrupt priority determination*1 3

2 Number of wait states until executing instruction ends*2 1 to 19+2⋅SI

3 PC, CCR stack save 2⋅Sk

4 Vector fetch 2⋅SI

5 Instruction fetch*3 2⋅SI

6 Internal processing*4 2

Total (using on-chip memory) 12 to 32

Notes: 1. Two states in case of internal interrupt.

2. Refers to MULXS and DIVXS instruction.

3. Prefetch after interrupt acceptance and interrupt handling routine prefetch.

4. Internal processing after interrupt acceptance and internal processing after vector

fetch.

Table 6.9 Number of States in Interrupt Handling Routine Execution

Object of Access

Symbol Internal Memory

Instruction fetch SI 1

Stack operation SK 1

Rev. 1.0, 02/01, page 124 of 1184

6.5 Usage Notes

6.5.1 Contention between Interrupt Generation and Disabling

When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective

after execution of the instruction.

In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or

MOV, if an interru pt is generated d uring execu tio n of the instruction, the inter rupt concerned will

still be enabled on completion of the in str uction, and so interrup t ex ception han dling for that

interrupt will b e ex ecuted on com pletion of the instruction. However, if there is an interrupt

request of higher prio rity than that in ter r upt, interrup t exception han dling will be execu ted for the

higher-priority interrupt, and the lower-priority interrupt will be ignored.

The same also applies when an interrupt source flag is cleared to 0.

Figure 6.9 shows an example in which the OCIAE bit in timer X1 TIER is cleared to 0.

TIER address

Internal

address bus

Internal

write signal

OCIAE

OCFA

OCIA

interrupt signal

TIER write cycle

by CPU OCIA interrupt

exception handling

Figure 6.9 Contention between Interrupt Generation and Disabling

Rev. 1.0, 02/01, page 125 of 1184

The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while

the interrupt is masked.

6.5. 2 Instructions that Disable Interr upts

Instructions that disab le in terru pts are LDC, ANDC, ORC, and XORC. After any of these

instructions is executed, all interrupts including NMI are disabled and the next instruction is

always executed. Wh en the I bit or UI bit is set by one of these instructions, the new valu e

becomes valid two states after execution of the instruction ends.

6.5.3 Interrupts during Execution of EEPMOV Instruction

Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.

With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer

is not accepted un til the move is completed .

With the EEPMOV.W instru ction, if an in ter rupt requ e st is issued durin g the transfer, interrupt

exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this

case is the address of the next instruction.

Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the

following coding should be used.

L1: EEPMOV.W

MOV.W R4,R4

BNE L1

Rev. 1.0, 02/01, page 126 of 1184

Rev. 1.0, 02/01, page 127 of 1184

Section 7 ROM

7.1 Overview

The H8S/2199R has 128 kbytes or 256 kbytes of on-chip ROM (flash memory or mask ROM), the

H8S/2198R has 112 kbytes, the H8S/2197R and H8S/2197S have 96 kbytes, and the H8S/2196R

and H8S/2196S have 80 kbytes*. The ROM is connected to the CPU by a 16-bit data bus. The

CPU accesses both byte and word data in one state, enabling faster instruction fetches and higher

processing speed.

The flash memory versions of the H8S/2199R can be erased and programmed on-board as well as

with a general-purpose PROM programmer.

Note: * For details on product line-up, refer to section 1, Overview.

7.1.1 Block Diagram

Figure 7.1 shows a block diagram of the ROM.

Internal data bus (upper 8 bits)

Internal data bus (lower 8 bits)

H'000000

H'000002

H'01FFFE

H'000001

H'000003

H'01FFFF

Figure 7.1 ROM Block Diagram (H8S/2199R)

Rev. 1.0, 02/01, page 128 of 1184

7.2 Overview of Flash Memory

7.2.1 Features

The features of the flash memory are summarized below.

• Four flash memo ry operating modes

 Program mode

 Erase mode

 Program-verify mode

 Erase-verify mode

• Programming/erase methods

The flash memory is programmed 128 bytes at a time. Erasing is performed by block erase (in

single-block units). When erasing all blocks, the individual blocks must be erased

sequentially. Block erasing can be performed as required on 4-kbyte, 32-kbyte, and 64-kbyte

blocks. (In OSD ROM, block erasing can be performed on 1-kbyte, 2-kbyte, and 28-kbyte

blocks).

• Programming/erase times

The flash memory programming time is 10 ms (typ.) for simultaneous 128-byte programming,

equivalent to 78 µs (typ.) per byte, and the erase time is 100 ms (typ.) per block.

• Reprogram ming capability

The flash memory can be reprogrammed up to 100 times.

• On-board programming modes

There are two modes in which flash memory can be programmed/erased/verified on-board:

 Boot mode

 User program mode

• Automatic bit r ate adjustment

If data transfer on boot mode, automatic adjustment is possible at host transfer bit rates and

LSI's bit rates.

• Protect modes

There are three protect modes, hardware, software, and error protect, which allow protected

status to be designated for flash memory program/erase/verify operations.

• Programmer mode

Flash memory can be programmed/erased in programmer mode, using a PROM programmer,

as well as in on-board programming mode.

Rev. 1.0, 02/01, page 129 of 1184

7.2.2 Block Diagram

Figure 7.2 shows a block diagram of the flash memory.

Module bus

Bus interface/controller

Flash memory

(256 kbytes)

Operat-

ing

mode

FLMCR1

STCR

FLMCR1

FLMCR2

EBR1

EBR2

: Serial timer control register

: Flash memory control register 1

: Flash memory control register 2

: Erase block register 1

: Erase block register 2

Legend:

Internal address bus

Internal data bus (16 bits)

STCR

FWE pin

Mode pin

FLMCR2

EBR1

Flash memory

(OSD ROM)

(32 kbytes)

EBR2

Figure 7.2 Block Diagram of Flash Memory (H8S/2199R Only)

Rev. 1.0, 02/01, page 130 of 1184

7.2.3 Flash Memory Operating Modes

Mode Transitions

When each mode pin and the FWE pin are set in the reset state and a reset-start is executed, the

MCU enters one of the operating modes shown in figure 7.3. In user mode, flash memory can be

read but not pr ogrammed or erased.

Flash memory can be programmed and erased in boot mode, user program mode, and programmer

mode.

Boot mode

On-board program mode

User

program

mode

User mode

Reset state

Programmer

mode

FWE = 1, MD0 = 0,

P12 = P13 = P14 = 1

MD0 = 0,

P12 = P13 = 1, P14 = 0

RES = 0

FWE = 1

SWE = 1

FWE = 0

SWE = 0

RES = 0

MD1 = 1, FWE = 0

RES = 0

Only make a transition between user mode

and user program mode when the CPU is not

accessing the flash memory.

Note:

Figure 7.3 Flash Memory Mode Transitions

Rev. 1.0, 02/01, page 131 of 1184

On-Board Programming Modes

• Boot mode

<RAM>

<Host>

Programming control

program

SCI

Application

program

(old version)

New application

program

Programming control

program

Programming control

program

<RAM>

<Host>

SCI

Boot program area

<RAM>

<Host>

SCI

Flash memory erase

Program execution state

<RAM>

<Host>

SCI

New application

program

1. Initial state 2. Writing control program transfer

3. Flash memory initialization 4. Writing new application program

Boot program

Application

program

(old version)

Boot program

Boot program

Boot program

Boot program area Programming control

program

The flash memory is in the erased state when the

device is shipped. The description here applies to

the case where the old program version or data is

being rewritten. The user should prepare the

programming control program and new application

program beforehand in the host.

When boot mode is entered, the boot program in

this LSI chip (originally incorporated in the chip) is

started, and SCI communication check is carried

out, and the boot program required for flash memory

erasing is automatically transferred to the RAM boot

program area.

The erase program in the boot program area (in

RAM) is executed, and the flash memory is

initialized (to H'FF). In boot mode, entire flash

memory erasure is performed, without regard to

blocks.

The programming control program transferred from

the host to RAM by SCI communication is executed,

and the new application program in the host is

written into the flash memory.

New application

program

New application

program

Figure 7.4 Boot Mode

Rev. 1.0, 02/01, page 132 of 1184

• User program mode

<RAM>

<Host>

Programming/erase control program

SCI

Boot program

New application

program

<RAM>

<Host>

SCI

<RAM>

<Host>

SCI

Flash memory erase

Boot program

New application

program

Program execution state

<RAM>

<Host>

SCI

Programming/erase

control program

1. Initial state 2. Programming/erase control program transfer

3. Flash memory initialization 4. Writing new application program

FWE assessment program

Transfer program

Application

program

(old version)

FWE assessment program

Transfer program

Programming/erase control program Programming/erase control program

New application

program

Boot program

FWE assessment program

Transfer program

(1) The FWE assessment program that confirms that

the FWE pin has been driven high, and (2) the

program that will transfer the programming/erase

control program from the flash memory to on-chip RAM

should be written into the flash memory by the user

beforehand. (3) The programming/erase control

program should be prepared in the host or in the flash

memory.

When the FWE pin is driven high, user software

confirms this fact, executes the transfer program in the

flash memory, and transfers the programming/erase

control program to RAM.

The programming/erase control program in RAM is

executed, and the flash memory is initialized (to H'FF).

Erasing can be performed in block units, but not in byte

units.

Next, the new application program in the host is written

into the erased flash memory blocks. Do not write to

unerased blocks.

New application

program

Boot program

FWE assessment program

Transfer program

Application

program

(old version)

Figure 7.5 User Program Mode (Example)

Rev. 1.0, 02/01, page 133 of 1184

Differences between Boot Mode and User Program Mode

Boot Mode User Program Mode

Entire memory erase Yes Yes

Block erase No Yes

Programming contr ol program* Program/program-verify Erase/erase-verify

Program/program-verify

Note: * To be provided by the user, in accordance with the recommended algorithm.

Block Configuration

The main ROM area is divided into three 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte

blocks. The OSD ROM area is divided into two 1-kbyte blocks, one 2-kbyte block, and one 28-

kbyte block.

Address H'00000

Address H'3FFFF

256 kbytes

64 kbytes

32 kbytes

Address H'40000

Address H'47FFF

32 kbytes

OSD ROM area

Main ROM area

28 kbytes

2 kbytes

1 kbyte

4 kbytes × 8

Figure 7.6 Flash Memory Block Configuration

Rev. 1.0, 02/01, page 134 of 1184

7.2.4 Pin Configuration

The flash memory is controlled by means of the pins shown in table 7.1.

Table 7.1 Flash Memory Pins

Pin Name Abbreviation I/O Function

Reset RES Input Reset

Flash write enable FWE Input Flash program/erase protection by hardware

Mode 0 MD0 Input Sets this LSI operating mode

Port 12 P12 Input Sets this LSI operating mode when MD0 = 0

Port 13 P13 Input Sets this LSI operating mode when MD0 = 0

Port 14 P14 Input Sets this LSI operating mode when MD0 = 0

Transmit data SO1 Output Serial transmit data outpu t

Receive data SI1 Input Serial receive data input

7.2.5 Register Configuration

Table 7.2 shows the registers used to control the flash memory when enabled.

In order for these registers to be accessed, the FLSHE bit must be set to 1 in STCR.

Table 7.2 Flash Memory Registers

Flash memory control register 1 FLMCR1*5 R/W*2 H'00*3 H'FFF8

Flash memory control register 2 FLMCR2*5 R/W*2 H'00*4 H'FFF9

Erase block regi ster 1 EBR1*5 R/W*2 H'00*4 H'FFFA

Erase block regi ster 2 EBR2*5 R/W*2 H'00*4 H'FFFB

Serial timer control register STCR R/W H'00 H'FFEE

Notes: 1. Lower 16 bits of the address.

2. When the FWE bit in FLMCR1 is not set at 1, writes are disabled.

3. When a high level is input to the FWE pin, the initial value is H'80.

4. When a low level is input to the FWE pin, or if a high level is input and the SWE bit in

FLMCR1 is not set, these registers are initialized to H'00.

5. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit regi sters. Only byte accesses are valid

for these registers, the access requiring 2 states .

Rev. 1.0, 02/01, page 135 of 1184

7.3 Flash Memory Register Descriptions

7.3.1 Flash Memory Control Register 1 (FLMCR1)

FWE

—*

SWE1

R/W

ESU1

R/W

PSU1

R/W

EV1

R/W

PV1

R/W

Bit

Initial value

R/W

Note: * Determined by the state of the FWE pin.

FLMCR1 is an 8-bit register used for flash memory operating mode control. With addresses

H'00000 to H'3FFFF, program-verify mode or erase-verify mode is entered by setting SWE to 1

when FWE = 1, then setting the PV1 bit and EV1 bit. Program mode is entered by setting SWE1

when FWE = 1, th en setting the SWE1 bit and PSU1, and finally setting the P1 bit. With

addresses H'00000 to H'3FFFF, erase mode is entered by setting SWE1 when FWE = 1, then

setting the ESU1 bit, and finally setting the E1 bit. FLMCR1 is initialized by a reset, in standby

mode or watch mode, when a low level is input to the FWE pin, and when a high level is input to

the FWE pin while th e SWE1 bit in FLMCR1 is not set to 1. Its initial value is H'80 when a high

level is input to the FWE pin, and H'00 when a low level is input. When on-chip flash memory is

disabled, a read will r eturn H'00, and wr ites ar e invalid.

Writes to the SWE1 b it in FLMCR1 ar e enabled only when FWE = 1; writes to the ESU1, PSU1,

EV1 and PV1 bits only when FWE = 1 and SWE1 = 1; writes to the E1 bit only when FWE = 1,

SWE1 = 1, and ESU1 = 1; and writes to the P1 bit only when FWE = 1, SWE1 = 1, and PSU1 = 1.

Bit 7



Flash Write Enable (FWE): Sets hardware protection against flash memory

programming/erasing.

Bit 7

FWE Description

0 When a low level is input to the FWE pin (hardware-protected state)

1 When a high level is input to the FWE pin

Rev. 1.0, 02/01, page 136 of 1184

Bit 6



Software Write Enable (SWE): Enables or disables flash memory programming. SWE

should be set before setting bits 5 to 0, bits 7 to 0 in EBR1, and bits 3 to 0 in EBR2.

Bit 6

SWE1 Description

0 Writes are disabled (Initial value)

1 Writes are enabled

[Setting condition]

Setting is available when FWE = 1 is selected

Bit 5



Erase Set-Up 1 ( ESU1): Prepares for erase mode. ESU1 should be set to 1 before setting

the E1 bit in FLMCR1 to 1. Do not set the SWE1, PSU1 , EV1, PV1 , E1, or P1 bit at the same

time.

Bit 5

ESU1 Description

0 Erase set-up clear ed (Initial value)

1 Transition to eras e set-up mode

[Setting condition]

Setting is available when FWE = 1 and SWE1 = 1 are selected

Bit 4



Program Set-Up 1 (PSU1): Prepares for program mode. PSU1 should be set to 1 before

setting the P1 b it in FLMCR1 to 1. Do not set th e SWE1, ESU1, EV1, PV1, E1 or P1 b it at the

same time.

Bit 4

PSU1 Description

0 Program set-up cle ared (Initial value)

1 Transition to program set-up mode

[Setting condition]

Setting is available when FWE = 1 and SWE1 = 1 are selected

Rev. 1.0, 02/01, page 137 of 1184

Bit 3



Erase-Verify (EV1): Selects erase-verify mode transition or clearing. Do not set the

SWE1, ESU1, PSU1, PV1, E1, or P1 bit at the same time.

Bit 3

EV1 Description

0 Erase-verify mode cleared (Initial value)

1 Transition to eras e-verify mode

[Setting condition]

Setting is available when FWE = 1 and SWE1 = 1 are selected

Bit 2



Program-Verify (PV 1): Selects program-verify mode transition or clearing. Do not set

the SWE1, ESU1, PSU1, EV1, E1, or P1 bit at the same time.

Bit 2

PV1 Description

0 Program-verify mode cleared (Initial value)

1 Transition to program-verify mode

[Setting condition]

Setting is available when FWE = 1 and SWE1 = 1 are selected

Bit 1



Erase (E1): Selects erase mode transition or clearing. Do not set the SWE1, ESU1, PSU1,

EV1, PV1, or P1 bit at th e same time.

Bit 1

E1 Description

0 Erase mode cleared (Initial value)

1 Transition to erase mode

[Setting condition]

Setting is available when FWE = 1, SWE1 = 1, and ESU1 = 1 are selected

Bit 0



Program (P1): Selects program mode transition or clearing (target address range :

H'00000 to H'3FFFF). Do not set the SWE1, PSU1, ESU1, EV1, PV1, or E1 bit at the same time.

Bit 0

P1 Description

0 Program mode cleared (Initial value)

1 Transition to program mode

[Setting condition]

Setting is available when FWE = 1, SWE1 = 1, and PSU1 = 1 are selected

Rev. 1.0, 02/01, page 138 of 1184

7.3.2 Flash Memory Control Register 2 (FLMCR2)

FLER

SWE2

R/W

ESU2

R/W

PSU2

R/W

EV2

R/W

PV2

R/W

Bit

Initial value

R/W

FLMCR2 is an 8-bit register used for flash memory operating control mode.

With addresses H'40000 to H'47FFF, program -verify mode and erase-verify mode is entered by

setting SWE2 when FWE (FLMCR1) = 1, then setting the EV2 bit and the PV2 bit. Prog ram mode

is entered by setting SWE2 when FWE (FLMCR1) = 1, then setting th e SWE2 bit and PSU2 bit,

and finally setting the P2 bit.

With addresses H'40000 to H'47FFF, erase mode is entered by setting SWE2 when FWE

(FLMCR1) = 1, th en setting the ESU2 bit , and fina lly setting the E2 bit. FLMCR2 is initialized to

H'00 by a reset, in standby mode or watch mode, when a low level is input to the FWE pin, and

when a high level is input to the FWE pin while the SWE2 bit in FLMCR2 is set to 1. FLER can

be initialized only by a reset.

Writes to the SWE2 b it in the FLMCR2 are en abled only when FWE (FLMCR1) = 1; writes to the

ESU2, PSV2, EV2, and PV2 bits only when FWE (FLMCR1) = 1 and SWE2 = 1; writes to the E2

bit only when FWE (FLMCR1) = 1, SW2 = 1, and ESU2 = 1; writes to the P2 bit only when FWE

(FLMCR1) = 1, SWE2 = 1, and PSU2 = 1.

Bit 7



Flash Memory Error (FLER): Indicates that an error has occurred during an operation on

flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-

protection state.

Bit 7

FLER Description

0 Flash memory is operating normally

Flash memory program/erase protection (error protection) is disabled

[Clearing condition]

Reset (Initial value)

1 An error has occurred during flash memory programming/erasing

Flash memory program/erase protection (error protection) is enabled

[Setting condition]

See section 7.6.3, Error Protection

Rev. 1.0, 02/01, page 139 of 1184

Bit 6



Software Write Enable 2 (SWE2): Enables or disables flash memory programming

(target address range: H'40000 to H'47FFF). SW2 should be set when setting bits 5 to 0 and bits 7

to 4 in EBR2.

Bit 6

SWE2 Description

0 Writes are disabled (Initi al val ue)

1 Writes are enabled

[Setting condition]

Setting is available when FWE=1 is selected

Bit 5



Erase Set-up 2 (ESU2): Prepares for erase mode. (Target address range: H'40000 to

H'47FFF). Do n ot set the PSU2, EV2, PV2, W2, P2 bits at the same time.

Bit 5

ESU2 Description

0 Erase set-up clear ed (Initial value)

1 Transitio n to erase set-up mod e

[Setting condition]

Setting is enabled when FWE=1 and SWE2=1 are selected

Bit 4



Program Set-up 2 (PSU2): Prepares for program mode (Target address rang: H'40000 to

H'47FFF). Do n ot set the ESU2, EV2, PV2, E2, P2 bits at the same tim e.

Bit 4

PSU2 Description

0 Program set-up cle ared (Initial value)

1 Transition to program set-up mode

[Setting condition]

Setting is enabled when FWE=1 and SWE2=1 are selected

Bit 3



Erase-Verify 2 (EV2): Selects erase-verify mode transition or clearing (target address

range : H'40000 to H'47FFF). Do n ot set the ESU2, PSU2, PV2, E2 , P2 bits at the same time.

Bit 3

EV2 Description

0 Erase-verify mode cleared (Initial value)

1 Transition to eras e-verify mode

[Setting condition]

Setting is available when FWE=1 and SWE2=1 are selected

Rev. 1.0, 02/01, page 140 of 1184

Bit 2



Program-Verify 2 (PV2): Selects program-verify mode transition or clearing (target

address ran ge: H'40000 to H'47 FFF) . Do not set the ESU2, PSU2, EV2, E2, and P2 bits at the

same time.

Bit 2

PV2 Description

0 Program-verify mode cleared

1 Transition to program-verify mode

[Setting condition]

Setting is available when FWE=1 and SWE2=1 are selected

Bit 1



Erase 2 (E2): Selects erase mode transition or clearing (target address range: H'40000 to

H'47FFF, do not set the ESU2, PSU2, EV2 , PV2, and P2 bits at the same time.

Bit 1

E2 Description

0 Erase mode cleared

1 Transition to erase mode

[Setting condition]

Setting is available when FWE=1, SWE2=1, and ESU2=1 are selected

Bit 0



Program 2 (P2): Selects program mode transition or clearing (target address range:

H'40000 to H'47FFF). Do not set the ESU2, PSU2, EV2, PV2, and E2 bits at the same time.

Bit 0

P2 Description

0 Program mode cleared

1 Transition to program mode

[Setting condition]

Setting is available when FWE=1, SWE2=1, and PSU2=1 are selected

Rev. 1.0, 02/01, page 141 of 1184

7.3.3 Erase Block Register 1 (EBR1)

EB7

R/W

EB6

R/W

EB5

R/W

EB4

R/W

EB3

R/W

EB0

R/W

EB2

R/W

EB1

R/W

Bit

EBR2

Initial value

R/W

EBR1 is an 8-bit register that specify the flash memo ry erase area block by block.

EBR1 is initialized to H'00 by a reset, in standby mode or watch mode, when a low level is input

to the FWE pin, and when a high level is input to the FWE pin and the SWE1 bit in FLMCR1 is

not set. When a bit in EBR1 is set to 1, the corresponding block can be erased. Other blocks are

erase-protected . Set only one bit in EBR1 and EBR2. More than o ne bit cannot be set. If set, all

bits are cleared to 0.

Table 7.3 shows the flash memory block configuration.

7.3.4 Erase Block Register 2 (EBR2)

EB15

R/W

EB14

R/W

EB13

R/W

EB12

R/W

EB11

R/W

EB8

R/W

EB10

R/W

EB9

R/W

Bit

EBR2

Initial value

R/W

EBR2 is an 8-bit register that specify the flash memory erase area block by block; EBR2 is

initialized to H'00 by a reset, in standby mode or watch mode, and when a low level is input to the

FWE pin. Bits 3 to 0 are initialized to 0 when a high level is input to the FWE pin and the SWE1

in FLMCR1 is not set. Bits7 to 4 are initialized to 0 when the SWE2 in FLMCR2 is not set. When

a bit in EBR2 is set to 1, the corresponding block can be erased. Other blocks are erase-protected.

Set only on e bit in EBR1 and EBR2. More than one b it cannot be set. I f set, all bits are cleared to

The flash memory block configuration is shown in table 7.3.

Rev. 1.0, 02/01, page 142 of 1184

Table 7.3 Flash Memory Erase Blocks

Block (Size) Address

EB0 (4 kbytes) H'000000 to H'000FFF

EB1 (4 kbytes) H'001000 to H'001FFF

EB2 (4 kbytes) H'002000 to H'002FFF

EB3 (4 kbytes) H'003000 to H'003FFF

EB4 (4 kbytes) H'004000 to H'004FFF

EB5 (4 kbytes) H'005000 to H'005FFF

EB6 (4 kbytes) H'006000 to H'006FFF

EB7 (4 kbytes) H'007000 to H'007FFF

EB8 (32 kbytes) H'008000 to H'00F FFF

EB9 (64 kbytes) H'010000 to H'01F FFF

EB10 (64 kbytes) H'020000 to H'02FFFF

EB11 (64 kbytes) H'030000 to H'03FFFF

EB12 (1 kbyte) H'040000 to H'0403FF

EB13 (1 kbyte) H'040400 to H'0407FF

EB14 (2 kbytes) H'040800 to H'040 FFF

EB15 (28 kbytes) H'041000 to H'047FFF

7.3.5 Serial/Timer Control Register (STCR)

—

IICX1

R/W

IICX0

R/W

—

FLSHE

R/W

—

OSROME

R/W

—

Bit

Initial value

R/W

STCR is an 8-b it r ead/write register that controls the I2C bus interface operating mode, on-chip

flash memory (in F-ZTAT versions), and OSD ROM. For details on IIC bus interface, refer to

section 23, I2C Bus Interface. If a module controlled by STCR is not used, do not write 1 to the

correspo nding bit. STCR is initialized to H'00 by a reset.

Bits 6 and 5



I2C Control (IICX1, IICX0): These b its control the operation of the I2C bus

interface. For details, see section 23, I2C Bus Interface.

Rev. 1.0, 02/01, page 143 of 1184

Bit 3



Flash Memory Control Register Enable (FLSHE): Setting the FLSHE bit to 1 enables

read/write access to the flash memory control registers. If FLSHE is cleared to 0, the flash

memory control registers are deselected. In this case, the flash memory contro l register contents

are retained.

Bit 3

FLSHE Description

0 Flash memory control registers deselected (Initial value)

1 Flash memory control registers selected

Bit 2



OSD ROM Enable (OSROME): Controls the OSD character data ROM (OSDROM)

access. When this bit is set to 1, the OSDROM can be accessed by the CPU, and when this bit is

cleared to 0, the OSDROM cannot be accessed by the CPU but accessed by the OSD module.

Before writing to or erasing the OSDROM in the F-ZTAT ver sio n, be sure to set this bit to 1.

Note: During OSD display, the OSDROM cannot be accessed by the CPU. Before accessing the

OSDROM by the CPU, be su re to clear th e OSDON bit in the screen control register to 0

then set the OSROME bit to 1. If the OSROME bit is set to 1 dur ing OSD display, the

character data ROM cannot be accessed correctly by CPU.

Bit 2

OSROME Description

0 OSD ROM is accessed by the OSD (Initial value)

1 OSD ROM is accessed by the CPU

Bits 7, 4, 1 and 0



Reserved: Always read as 0. Do not write 1 to these bits.

Rev. 1.0, 02/01, page 144 of 1184

7.4 On-Board Programming Modes

When pins are set to on-board programming mode, program/erase/verify operations can be

performed on the on-chip flash memory. There are two on-board prog ramming modes: boot mode

and user program mode. The pin settings for transition to each of these modes are shown in table

7.4. For a diagram of the transitions to the various flash memory modes, see figure 7.3.

Table 7.4 Setting On-Board Programming Modes

Mode Pin

Mode Name FWE MD0 P12 P13 P14

Boot mode 1 0 1*2 1*2 1*2

User program mode 1*1 1   

Notes: 1. In user program mode, the FWE pin should not be constantly set to 1. Set FWE to 1 to

make a transition to user program mode before performi ng a program/erase/verify

operation.

2. Can be used as I/O ports after boot mode is initiated.

Rev. 1.0, 02/01, page 145 of 1184

7.4.1 Boot Mode

When boot mode is used, the flash memory programming control program must be prepared in the

host beforehand. The channel 1 SCI to be used is set to asynchronous mode.

When a reset-start is executed after the LSI’s pins have been set to boot mode, the boot program

built into the LSI is started and the programming control program prepared in the host is serially

transmitted to the LSI via th e SCI. In the LSI, the programming control program received via the

SCI is written into the progr ammin g control program area in on- chip RAM. Af ter the transfer is

completed, control branches to the start address of the programming control program area and the

programming control program execution state is entered (flash memory programming is

performed).

The transferred programming control program must therefore include coding that follows the

programming algorithm given later.

Figure 7.7 shows the system configuration in boot mode. Figure 7.8 shows the boot program mode

execution procedure.

SI1

SO1 SCI1

This LSI

Flash memory

Write data reception

Verify data

transmission

Host

On-chip RAM

Figure 7.7 System Configuration in Boot Mode

Rev. 1.0, 02/01, page 146 of 1184

Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is

transmitted as an erase error, and the erase operation and subsequent operations

are halted.

Start

Set pins to boot mode

and execute reset-start

Host transfers data (H'00)

continuously at prescribed bit rate

The LSI measures low period

of H'00 data transmitted by host

The LSI calculates bit rate and

sets value in bit rate register

After bit rate adjustment, the LSI

transmits one H'00 data byte to

host to indicate end of adjustment

Host confirms normal reception

of bit rate adjustment end

indication (H'00), and transmits

one H'55 data byte

After receiving H'55,

LSI transmits one H'AA

data byte to host

Host transmits number

of programming control program

bytes (N), upper byte followed

by lower byte

The LSI transmits received

number of bytes to host as verify

data (echo-back)

n = 1

Host transmits programming control

program sequentially in byte units

The LSI transmits received

programming control program to

host as verify data (echo-back)

Transfer received programming

control program to on-chip RAM

n = N? No

Yes

End of transmission

Check flash memory data, and

if data has already been written,

erase all blocks

After confirming that all flash

memory data has been erased,

The LSI transmits one H'AA

data byte to host

Execute programming control

program transferred to on-chip RAM

n + 1 → n

Figure 7.8 Boot Mode Execution Procedure

Rev. 1.0, 02/01, page 147 of 1184

Automatic SCI Bit Rate Adjustment

Start

bit Stop

bit

D0 D1 D2 D3 D4 D5 D6 D7

Low period (9 bits) measured (H'00 data) High period

(1 or more bits)

Figure 7.9 Automatic SCI Bit Rate Adjustment

When boot mode is initiated, the LSI measures the low period of the asynchronous SCI

communication data (H'00) transmitted continu ously from the host. The SCI transmit/receive

format should be set as follows: 8-bit d ata, 1 stop bit, no parity. The LSI calculates the bit r a te of

the transmission from the host from the measured low period , and transmits one H'00 byte to the

host to indicate the end of bit rate adjustment. The host should confirm that this ad justment end

indication (H'00) has been received normally, and transmit one H'55 byte to the LSI. If reception

cannot be performed normally, initiate boot mode again (reset), and repeat the above operations.

Depending on the host's transmissio n bit rate and the LSI system clock fr e quency, there will be a

discrepancy between the bit rates of the host and the LSI. To ensure correct SCI operation, the

host's transfer bit rate should be set to (4800, 9600, 19200) bps.

Table 7.5 shows typical host transfer bit rates and system clock frequencies for which automatic

adjustment of the LSI’s bit rate is possible. The boot program should be executed within this

system clock range.

Table 7.5 System Clock Frequencies for which Automatic Adjust ment of This LSI Bit

Rate Is Possible

Host Bit Rate (bps) System Clock Frequency

4800 8 MHz to 10 MHz

9600 8 MHz to 10 MHz

19200 8 MHz to 10 MHz

Rev. 1.0, 02/01, page 148 of 1184

On-Chip RA M Area Divisio ns in Boot Mode: In boot mode, the 2048-byte area from

H'FFDFB0 to H'FFE7AF is reserved for use by the boot program, as shown in figure 7.10. The

area to which the programming control program is transferred is H'FFE7B0 to H'FFFFAF (6144

bytes). The boot program area can be used when the programming control program transferred

into RAM enters the execution state. A stack area should be set up as required.

H'FFDFB0

H'FFE7AF

Programming

control program

area

(6144 bytes)

H'FFFFAF

Boot program

area*

(2048 bytes)

Note: * The boot program area cannot be used until a transition is made to the execution

state for the programming control program transferred to RAM. Note that the boot

program reamins stored in this area after a branch is made to the programming

control program.

Figure 7.10 RAM Areas in Boot Mode

Rev. 1.0, 02/01, page 149 of 1184

Notes on Use of Boot Mode:

1. When the LSI comes out of reset in boot mode, it measures the low period of the input at the

SCI's SI1 pin. The reset should end with SI1 pin high. After the reset ends, it takes about 100

states for the LSI to get ready to measure the low period of the SI1 pin input.

2. In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all

flash memory blocks are erased. Boot mode is for use when user program mode is

unavailable, such as the first time on-board programming is performed, or if the program

activated in user program mode is accidentally erased.

3. Interrupts cannot be used while the flash memory is being programmed or erased.

4. The SI1 and SO1 pins should be pulled up on the board.

5. Before branching to the programming control program (H'FFE7B0 in RAM area), the LSI

terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE

and TE bits in SCR to 0), but the adjusted b it rate value remains set in BRR. The transmit data

output pin, SO1, goes to the high-level output state (P21PCR = 1, P21PDR = 1).

The contents of the CPU's internal general registers are undefined at this time, so these

registers must be initialized immediately after branching to the pr ogr a m ming control program.

In particu lar, since the stack pointer (SP) is used im plicitly in subroutine calls, etc., a stack

area must be specified for use by the programming contro l program.

The initial values of other on-chip register s ar e not changed.

6. Boot mode can be entered by making the pin settings shown in table 7.4 and executing a reset-

start.

When the LSI detects the boot mode setting at reset release*, it retains that state internally.

Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting

the FWE pin and mode pins, and executing reset release*. Boot mode can also be cleared by a

WDT overflow reset.

If the mode pin input levels are changed in boot mode, the boot mode state will be maintained

in the microcomputer, and boot mode continued, unless a reset occurs. However, the FWE pin

must not be driven low while the boot program is running or flash memory is being

programmed or erased.

Note: * Mode pin and FWE pin input must satisfy the mode programming setup time (tMDS = 4

states) with respect to the reset release timing.

Rev. 1.0, 02/01, page 150 of 1184

7.4.2 User Program Mode

When set to user program mode, the LSI can program and erase its flash memory by executing a

user program/erase control program. Therefore, on-board reprogramming of the on-chip flash

memory can be carried out by providing on-board means of FWE control and supply of

programming data, and storing a program/erase control program in part of the program area as

necessary.

In this mode, the LSI starts up in mode 1 and applies a high level to the FWE pin.

The flash memory itself cannot be read while the SWE1 bit is set to 1 to perform programming or

erasing, so the control program that performs programming and erasing should be run in on-chip

RAM or external memory.

Figure 7.11 shows the procedure for executing the program/erase control program when

transferred to on-chip RAM.

Clear FWE

FWE = high

Branch to flash memory

application program

Branch to program/erase control

program in RAM area

Execute program/erase control

program (flash memory rewriting)

Transfer program/erase

control program to RAM

MD0 = 1

Reset start

Write the FWE assessment program and

transfer program (and the program/erase

control program if necessary) beforehand

Note: Do not apply a constant high level to the FWE pin. Apply a high level to the FWE pin only

when the flash memory is programmed or erased. Also, while a high level is applied to the

FWE pin, the watchdog timer should be activated to prevent overprogramming or

overerasing due to program runaway, etc.

Figure 7.11 User Program Mode Execution Procedure

Rev. 1.0, 02/01, page 151 of 1184

7.5 Programming/Erasing Flash Memory

In the on-board programming modes, flash memory programming and erasing is performed by

software, using the CPU. There are four flash memory operating modes: program mode, erase

mode, program-verify mode, and erase-verify mode. With addresses H'00000 to H'3FFFF,

transitions to these modes can be made by setting the PSU1, ESU1, P1, E1, PV1 and EV1 bits in

FLMCR1. With addresses H'40000 to H'47FFF, transitions to these modes can be made by setting

the PSU2, ESU2, P2, E2, PV2, and EV2 bits in the FLMCR2.

The flash memory cannot be read while being programmed or erased. Therefore, the program that

controls flash memory programming/erasing (the programming control program) should be

located and executed in on-chip RAM or external memory.

Notes: 1. Operation is not guaranteed if setting/resetting of the SWE1, ESU1, PSU1, EV1, PV1,

E1, and P1 bits in FLMCR1, and the SWE2, ESU2, PSU2, EV2, PV2, E2, and P2 in

FLMCR2, is executed by a program in flash memory.

2. When program ming or erasing, set FWE to 1 (programm ing/erasing will not be

executed if FWE = 0).

3. Perform programming in the erased state. Do not perform additional programming on

previously pro grammed addre s s es .

4. Do not write to addresses H'00000 to H'3FFFF and H'40000 to H'47FFF at the same

time. Otherwise operation cannot be guaranteed.

5. Do not operate the OSD when writing or erasing addresses H'40000 to H'47FFF. Do

not set the OSROME in STCR to 1 before manipulating the flash control register.

7.5.1 Program Mode (n=1 when the target address range is H'00000 to H'3FFFF and

n=2 when the target address range is H'40000 to H'47FFF)

Follow the procedure shown in the program/program-verify flowchart in figure 7.12 to write data

or programs to flash memory. Performing program operations according to this flowchart will

enable data or prog r ams to be written to flash memory without subjecting the device to voltage

stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a

time.

Following the elapse of 1.0 µs o r more after the SWEn bit is set to 1 in flash memory control

data area, and the 128-byte data in the reprogram data area written consecutively to the write

addresses. The lo wer 8 bits o f the start address written to must b e H'00, or H'80. One hundred

and twenty-eight consecutive byte data transfers are performed. The program address and

program data are latched in the flash memory. A 128-byte data transfer must be performed even if

writing fewer than 128 bytes; in this case, H'FF data mu st be written to the extra addresses.

Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc.

Set 6.6 ms as the WDT overflow period. After this, preparation for program mode (program

setup) is carried out by setting the PSUn b it in FLMCRn, and after the elapse of 50 µs or more, the

operating mode is switched to program mode by setting the Pn bit in FLMCRn. The time during

Rev. 1.0, 02/01, page 152 of 1184

which the Pn bit is set is the flash memory programming time. Make a program setting for one

programming operation using the table in the programming flowchart.

7.5.2 Program-Verify Mode (n = 1 when the target address range is H'00000 to H'3FFFF

and n = 2 when the target address range is H'40000 to H'47FFF)

In program-verify mode, th e data written in p r ogra m mod e is read to check wheth e r it has been

correctly written in the flash memory.

After the elapse of a given programming time, the programming mode is exited (the Pn bit in

FLMCRn is cleared, then the PSUn bit is cleared at least 5 µs later). The watchdog tim er is

cleared after the elapse of 5 µs or more, and the operating mode is switched to program-verify

mode by setting the PVn bit in FLMCRn. Before reading in program-verify mode, a dummy write

of H'FF data should be made to the addresses to be read. The dummy write should be executed

after the elapse of 4 µs or more. When the flash memory is read in this state (verify data is read in

16-bit units) , the data at the latched address is read. Wait at least 2 µs after the dummy wr ite

before performing this read operation. Next, the originally written da ta is co mpared with the

verify data, and reprogram data is computed (see figure 7.12) and transferred to the reprogram

data area. After 128 bytes of data have been verified, exit program-verify mode, wait for at least 2

µs, then clear the SWEn bit in FLMCRn. If reprogramming is necessary, set program mode again,

and repeat the program/program-verify sequence as before. However, ensure that the

program/program-verify sequence is not repeated more than 1,000 times on the same bits.

Rev. 1.0, 02/01, page 153 of 1184

Programming pulse apply subroutine

Write pulse application subroutine

Start

Start of programming

Set SWE1 (2) bit in FLMCR(2)

Set PV1(2) bit in FLMCR1(2)

Clear PV1(2) bit in FLMCR1(2)

Clear SWE1(2) bit in FLMCR1(2)

Write pulse additional program pulse 10 µs

Call subroutine

Store 128-byte program data in program

data area and reprogram data area

Write 128-byte program data in RAM reprogram

data area consecutevely to flash memory

Write 128-byte program data in RAM additional

data area consecutively to flash memory

tsswe: W ait 1 µs

tspv: W ait 4 µs

tspvr: W ait 2 µs

tcpv: W ait 2 µs

tcswe: W ait 100 µs

End of programming

Programming pulse 30 µs or 200 µs

H'FF dummy write to verify address

Read verify data

Calculate additional program data

Calculate reprogram data

Complete 128-byte

data verification?

Transfer additional program data to additional program data area

Transfer reprogram data to reprogram data area

Program data= verify data?

Refer to note *6

for the pulse width

6≥n?

n←n+1

6≥n ?

m= 0?

Clear SWE1 (2) bit in FLMCR1(2)

tcwe: W ait 100 µs

Programming Failure

n ≥ 1000?

m= 1

Call subroutine

n= 1

m= 0

Enable WDT

Set PSU1 (2) bit in FLMCR1 (2)

Set P1 (2) bit in FLMCR1 (2)

Clear P1(2) bit in FLMCR1 (2)

Clear PSU1(2) bit in FLMCR1 (2)

tspsu: W ait 50 µs

tcp: W ait 5 µs

tcpsu: Wait 5 µs

Disable WDT

End of subroutine

Note: 6. Programming pulse width

Number of times

of programming Programming

time (z) µs

The programming pulse must be 10 µs in

additional programming

Perform programming after erasing data. Do not perform additional programming to addresses that have already been written to.

Notes: 1. Data transfer is performed by byte transfer. The lower eight bits of the start address must be H'00 or H'80. A 128-byte data transfer must be performed even if writing

fewer than 128 bytes: in this case, H'FF must be written to the extra addresses.

2. Verify data is read in 16-bit (word) units.

3. Even in case of the bit which is already-programmed in the 128-byte programming loop, perform additional programming if the bit fails at the next verify.

4. An area for storing program data (128 bytes), reprogram data (128 bytes), and additional program (128bytes) must be provided in RAM. The contents of the reprogram

and additional program areas are rewritten as programming processes.

5. A 30 µs or 200 µs programming pulse must be applied.

For details on programming pulse, refer to Notes*6.

To perform additional data programming, apply a programming pulse of 10 µs. Reprogram data X' is the reprogram data after program pulse is applied.

Program data storage are

(128 bytes)

Reprogram data storage

area (128 bytes)

Additional program data

storage area (128 bytes)

Reprogram Data Calculation Table Additiona l program data calculation table

Increment address

tsp10 or tsp30 or tsp200:

Wait 10 µs or 30 µs or 200 µs

998

999

1000

200

RAM

Source Data (D)

Reprogram data (X)

Additional program data (Y)

Reprogram data (X')

CommentsVerify data (V)

Verify data (V)

Programming completed

Programming incomplete; reprogram

Still in erased state; no action

Comments

Additional programming performed

Additional programming not performed

Figure 7.12 Program/Program-Verify Flowchart

Rev. 1.0, 02/01, page 154 of 1184

7.5.3 Erase Mode (n = 1 when the target address range is H'00000 to H'3FFFF and n = 2

when the target address range is H'40000 to H'47FFF)

Flash memory erasing should be performed block by block following the procedure shown in the

erase/erase-verify flowchart (single-block erase) shown in figure 7.13.

To perform data or program erasure, make a 1 bit setting for the flash memory area to be erased in

erase block register 1 or 2 (EBR1 or EBR2) at least 1 µs after setting the SWEn bit to 1 in flash

memory control register n (FLMCRn). Next, the watchdog timer is set to prevent overerasing in

the event of program runaway, etc.

Set more than 19.8 ms as the WDT overflow period. After this, preparation for erase mode (erase

setup) is carried out b y setting the ESUn bit in FLMCRn , and af ter a elapse of 100 µs or more, the

operating mode is switched to erase mo de by setting the En bit in FLMCRn. The tim e during

which the En bit is set is the flash memory erase time. Ensure that erase time does not exceed 10

ms.

Note: With flash memory erasing, preprogramming (setting all data in the memory to be erased

to 0) is not necessary before starting the erase procedure.

Rev. 1.0, 02/01, page 155 of 1184

End of erasing

START

Set SWE1 (2) bit in FLMCR1 (2)

Set ESU1 (2) bit in FLMCR1 (2)

Set E1 (2) bit in FLMCR1 (2)

tsswe: Wait 1 µs

tsesu: Wait 100 µs

n = 1

Set EBR1 (2)

Enable WDT

tse: Wait 10 ms

tce: Wait 10 µs

tcesu: Wait 10 µs

tsev: Wait 20 µs

Set block start address to

verify address

tsevr: Wait 2 µs

tcev: Wait 4 µs

Clear E1 (2) bit in FLMCR1 (2)

Clear ESU1 (2) bit in FLMCR1 (2)

Set EV1 (2) bit in FLMCR1 (2)

H'FF dummy write to verify address

Read verify data

Clear EV1 (2) bit in FLMCR1 (2)

tcev: Wait 4 µs

Clear EV1 (2) bit in FLMCR1 (2)

Clear SWE1 (2) bit in FLMCR1 (2)

Disable WDT

Verify data =

all 1?

tcswe: Wait 100 µs tcswe: Wait 100 µs

End of erasing of

all erase blocks?

Erase failure

Clear SWE1 (2) bit in FLMCR1 (2)

n ≥ (N)?

NO NO

YES

Notes: 1.

Increment

address

n←n+1

Last address

of block?

Preprogramming (setting erase block data to all 0) is not necessary.

Verify data is read in 16-bit (word) units.

Set only one bit in EBR. More than two bit cannot be set.

Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially.

For the value of N, see table 31.32, Flash Memory Characteristics.

Figure 7.13 Erase/Erase-Verify Flowchart

Rev. 1.0, 02/01, page 156 of 1184

7.5.4 Erase-Verify Mode (n = 1 when the target address range is H'00000 to H'3FFFF

and n = 2 when the target address range is H'40000 to H'47FFF)

In erase-verify mode, data is read after memory has been erased to check whether it has been

correctly erased.

After the elapse of the erase time, erase mode is exited (the En bit in FLMCRn is cleared, then the

ESUn bit is cleared at least 10 µs later), the watchdog timer is cleared after the elapse of 10 µs or

more, and the operating mode is switched to erase-verify mode by setting the EVn bit in

FLMCRn. Before reading in erase-verify mode, a dummy write of H'FF data should be made to

the addresses to be read. The dummy write should be executed after the elapse of 6.0 µs or more.

When the flash m e m ory is read in this state (verif y data is read in 16-bit units), the data at the

latched add r ess is r ead. Wait at least 2 µs after the dummy write before performing this read

operation. If the read data has been erased (all 1), a dummy write is performed to the next

address, and erase-verify is performed. If the read data has not been erased, set erase mode again,

and repeat the erase/erase-verify sequence in the same way. However, ensure that the erase/erase-

verify sequence is not repeated more than 100 times. When verification is completed, exit erase-

verify mode, and wait for at least 4 µs. If erasure has been completed on all the erase blocks, clear

the SWEn bit in FLMCRn. If there are any unerased blocks, make a 1 bit setting for the flash

memory area to be erased, and repeat the erase/erase-verify sequence in the same way.

Rev. 1.0, 02/01, page 157 of 1184

7.6 Flash Memory Protection

There are three kinds of flash memory prog ram/erase protection: hardware protection, software

protection, and error protection.

7.6.1 Hardware Protection

Hardware protection refers to a state in which programming/erasing of flash memory is forcibly

disabled or aborted. Hardware protection is reset by settings in flash memory control registers 1

and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2). (See table 7.6.)

In error protected state, the FLMCR1, FLMCR2, EBR1, and EBR2 settings are maintained.

Table 7.6 Hardware Protection

Functions

Item Description Program Erase

FWE pin

protection • When a low level is input to the FWE pin, FLMCR1,

FLMCR2 (excluding the FLER bit), EBR1, and EBR2

are initialized, and the program/erase-protected state

is entered

Yes Yes

Reset/standby

protection • In a reset (including a WDT overflow reset) and in

standby mode or watch mode, FLMCR1, FLMCR2,

EBR1, and EBR2 are initialized, and the

program/erase-protected state is entered

• In a reset via the RES pin, the reset state is not

entered unless the RES pin is held low until oscillation

stabilizes after powering on. In the case of a reset

during operation, hold the RES pin low for the RES

pulse width specified in the AC characteristics

Yes Yes

Rev. 1.0, 02/01, page 158 of 1184

7.6.2 Software Protection

Software protection can be implemented by setting the SWE1 bit in FLMCR1 an d SWE2 bit in

FLMCR2 and erase block registers 1 and 2 (EBR1, EBR2). When software protection is in effect,

setting the P1 or E1 bit in flash memory control register 1 (FLMCR1) or P2 or E2 bit in flash

memory control register 2 (FLMCR2) does not cause a transition to program mode or erase mode.

(See table 7.7.)

Table 7.7 Software Protection

Functions

Item Description Program Erase

SWE bit

protection • Clearing the SWE bit to 0 in FLMCR1 sets the

program/erase-protected state for all blocks

(Execute in on-chip RAM or external memory)

Yes Yes

Block

specification

protection

• Erase protection can be set for indivi dua l bloc ks by

settings in erase block registers 1 and 2 (EBR1, EBR2)

• Setting EBR1 and EBR2 to H'00 places all blocks in

the erase-protected state

 Yes

Rev. 1.0, 02/01, page 159 of 1184

7.6.3 Error Protection

In error protection, an error is detected when MCU runaway occurs during flash memory

programming/erasing, or operation is not performed in accordance with the prog ram/erase

algorithm, and the program/erase operation is aborted. Aborting the program/erase operation

prevents damage to the flash memory due to overprogramming or overerasing.

If the MCU malf unctions during f lash memory programm ing/er a sing, the FLER bit is set to 1 in

FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2

settings are retained , b ut program mode or erase mode is aborted at the point at which the error

occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit.

However, PV1, PV2, EV1 and EV2 bit setting is enabled, and a transition can be made to verify

mode.

FLER bit setting conditions are as follows:

• When flash memory is read during programming/erasing (including a vector read or instruction

fetch)

• Immediately after exception handling (excluding a reset) during programming/erasing

• When a SLEEP instruction (including standby) is executed during programming/erasing

Error protection is released only by a reset and in hardware standby mode.

Figure 7.14 shows the flash memory state transition diagram.

: Memory read possible

: Verify-read possible

: Programming possible

: Erasing possible

Legend: : Memory read impossible

: Verify-read impossible

: Programming impossible

: Erasing impossible

RD VF PR ER FLER = 0

Error occurrence

(Sleep instruction)

RES = 0

RD VF PR ER FLER = 0

Program mode

Erase mode Reset

(hardware protection)

RD VF PR ER FLER = 1 RD VF PR ER FLER = 1

Error protection mode Error protection

mode (power-down mode)

Power-down mode

FLMCR1, FLMCR2 (except FLER bit), EBR1, EBR2

initialization state

FLMCR1, FLMCR2,

EBR1, EBR2 initialization

state

Power-down mode release

Figure 7.14 Flash Memory State Transitions

Rev. 1.0, 02/01, page 160 of 1184

7.7 Interrupt Handling when Programming/Erasing Flash Memory

All interrupts are disabled when flash memory is being programmed or erased (when the P1 or E1

bit is set in FLMCR1, or the P2 or E2 bit is set in FLMR2 ) , and while the boot program is

executing in boot mode*1, to give priority to the program or erase operatio n. There are three

reasons fo r this:

• Interrupt during programming or erasing might cause a violation of the programming or

erasing algorithm, with the result that normal operation could not be assured.

• In the interrupt exception handling sequence during programming or erasing, the vector would

not be read correctly*2, possibly resulting in MCU runaway.

• If interrupt occurred during boot program execution, it would not be possible to execute the

normal boot mode sequence.

For these reasons, in on-board programming mode alone there are conditions for disabling

interrupt, as an exception to the general rule. However, this provision does not guarantee normal

erasing and programming or MCU operation. All requests must therefore be disabled inside and

outside the MCU during FWE application. Interrupt is also disabled in the error-protection state

while the P1 or E1 bit remains set in FLMCR1, o r the P2 or E2 bit remains set in FLMCR2 .

Notes: 1. I nterrupt requ ests must be disabled inside and outside th e MCU until data write by the

write control prog ram is complete.

2. The vector may not be read correctly in this case for the following two reasons:

• If flash memory is read while being programmed or erased (while the P or E bit is

set in FLMCR1 or FLMCR2), correct re ad da ta will n ot be obtained (undetermined

values will be r e turned).

• If the interrupt entry in the interrupt vector table has not been programmed yet,

interrupt ex ception handling will not be executed corr ectly.

Rev. 1.0, 02/01, page 161 of 1184

7.8 Flash Memory Programmer Mode

7.8.1 Programmer Mode Setting

Programs and data can be written and erased in programmer mode as well as in the on-board

programming modes. In programmer mode, flash memory read mode, auto-program mode, auto-

erase mode, and status read mode are supported with these device types. In auto-p rogram mode,

auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode,

detailed intern al signals are output after execution of an auto-pro gram or au to-era se o peration.

7.8.2 Socket Adapters and Memory Map

In programmer mode, a socket adapter is moun ted on the PROM programmer. The socket adapter

product codes are listed in table 7.8.

Figure 7.15 shows the memory map in prog rammer mode.

Table 7.8 Socket Adapter Product Codes

Product Codes Package Socket Adapter Product Code

HD64F2199R 112-pin QFP ME2199ESHF1H

(Minato Electronics)

H8S/2199R

H'000000

MCU mode Programmer mode

H'047FFF

H'00000

H'47FFF

On-chip ROM area

Figure 7.15 Memory Map in Programmer Mode

Rev. 1.0, 02/01, page 162 of 1184

7.8.3 Programmer Mode Operation

Table 7.9 shows how the different operating modes are set when using programmer mode, and

table 7.10 lists the commands used in programmer mode. Details of each mode are given below.

• Memory Read Mode: Memory read mode supports byte reads.

• Auto-Program Mode: Auto-program mode supports programming of 128 bytes at a time.

Status polling is used to confirm the end of auto-programming.

• Auto-Erase Mode: Auto-erase mode supports automatic erasing of the entire flash memory.

Status polling is used to confirm the end of auto-erasing.

• Status Read Mode: Status polling is used for auto-programming and auto-erasing, and normal

termination can be confirmed by reading the IO6 signal. In status read mode, error

informatio n is ou tp ut if an error occurs.

Table 7.9 Settings for Each Operating Mode in Programmer Mode

Pin Names

Mode FWE CE

CECE

CE OE

OEOE

OE WE

WEWE

WE IO0 to IO7 A0 to A17

Read H or L L L H Data output Ain

Output disable H or L L H H Hi-z X

Command write H or L*3 L H L Data input Ain*2

Chip disable*1 H or L H X X Hi-z X

Notes: 1. Chip disable is not a stand by s tate; internally, it is an operation state.

2. Ain indicates that there is also address input in auto-program mode.

3. For command writes when making a transition to auto-program or auto-erase mode,

input a high level to the FWE pin.

Table 7.10 Programmer Mode Commands

1st Cycle 2nd Cycle

Command Name Number of

Cycles Mode Address Data Mode Address Data

Memory read mode 1 + n write X H'00 Read RA Dout

Auto-program mode 129 write X H'40 write WA Din

Auto-erase mode 2 write X H'20 write X H'20

Status read mode 2 write X H'71 write X H'71

Notes: 1. In auto-program mode. 129 cycles are required for command writing by a simultaneous

128-byte write.

2. In memory read mode, the number of cycles depends on the number of address write

cycles (n).

Rev. 1.0, 02/01, page 163 of 1184

7.8.4 Memory Read Mode

• After the end of an auto-program, auto-erase, or status read operation, the command wait state

is entered. To read memory contents, a transition mu st be made to memory read mode by

means of a command write before the read is executed.

• Command writes can be performed in memory read mode, just as in the command wait state.

• Once memory read mode has been entered, consecutive reads can be performed.

• After power-on, memory read mode is entered.

Table 7.11 AC Characteristics in Memory Read Mode (1) −

−−

− Preliminary −

−−

−

Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C

Item Symbol Min Max Unit

Command write cycle tnxtc 20  µs

CE hold time tceh 0  ns

CE setup time tces 0  ns

Data hold time tdh 50  ns

Data setup time tds 50  ns

Write pulse width twep 70  ns

WE rise time tr  30 ns

WE fall time tf  30 ns

A18 to A0

IO7 to IO0 H'00

Command write

wep

ceh

nxtc

Note: Data is latched on the rising edge of WE.

ces

Memory read mode

ADDRESS STABLE

DATA

Figure 7.16 Memory Read Mode Timing Waveforms after Command Write

Rev. 1.0, 02/01, page 164 of 1184

Table 7.12 AC Characteristics when Entering Another Mode from Memory Read Mode

−

−−

− Preliminary −

−−

−

Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C

Item Symbol Min Max Unit

Command write cycle tnxtc 20  µs

CE hold time tceh 0  ns

CE setup time tces 0  ns

Data hold time tdh 50  ns

Data setup time tds 50  ns

Write pulse width twep 70  ns

WE rise time tr  30 ns

WE fall time tf  30 ns

A18 to A0

IO7 to IO0 H'XX

Other mode command write

wep

ceh

nxtc

Note: Do not enable WE and OE at the same time.

ces

ADDRESS STABLE

DATA

Figure 7.17 Timing Waveforms when Entering Another Mode from Memory Read Mode

Rev. 1.0, 02/01, page 165 of 1184

Table 7.13 AC Characteristics in Memory Read Mode (2) −

−−

− Preliminary −

−−

−

Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C

Item Symbol Min Max Unit

Access tim e tacc  20 µs

CE output delay time tce  150 ns

OE output delay ti me toe  150 ns

Output disable delay time tdf  100 ns

Data output hold time toh 5  ns

A18 to A0

IO7 to IO0

VIL

VIH

acc

ADDRESS STABLE ADDRESS STABLE

DATA

Figure 7.18 Timing Waveforms for CE

CECE

CE/OE

OEOE

OE Enable State Read

A18 to A0

IO7 to IO0

VIH

tce

tacc

toe

toh toh

tdf

tce

tacc

toe

ADDRESS STABLE ADDRESS STABLE

DATA DATA

tdf

Figure 7.19 Timing Waveforms for CE

CECE

CE/OE

OEOE

OE Clocked Read

Rev. 1.0, 02/01, page 166 of 1184

7.8.5 Auto-Program Mode

AC Characteristics

Table 7.14 AC Characteristics in Auto-Program −

−−

− Preliminary −

−−

−

Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C

Item Symbol Min Max Unit

Command write cycle tnxtc 20  µs

CE hold time tceh 0  ns

CE setup time tces 0  ns

Data hold time tdh 50  ns

Data setup time tds 50  ns

Write pulse width twep 70  ns

Status polling start time twsts 1  ms

Status polling access time tspa  150 ns

Address setup time tas 0  ns

Address hold time tah 60  ns

Memory write time twrite 1 3000 ms

WE rise time tr  30 ns

WE fall time tf  30 ns

Write setup time tpns 100  ns

Write end setup time tpnh 100  ns

Rev. 1.0, 02/01, page 167 of 1184

FWE

A18 to A0

IO7

tnxtc

twsts

spa

tnxtc

tces

tds tdh

twep

tas

pnh

pns

tah

ceh

ADDRESS STABLE

Data transfer

1 byte to 128 bytes

IO6

Programming wait

DATA

IO5 to IO0 H'40 DATA

H'00

tftr

twrite(1 to 3,000 ms)

Programming operation

end identification signal

Programming normal end

identification signal

Figure 7.20 Auto-Program Mode Timing Waveforms

Notes on Use of Auto-Program Mode

• In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out

by executing 128 consecutive byte transfers.

• A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this

case, H'FF data must be wr itten to the extra addresses.

• The lower 8 bits of the transfer address must be H'00 or H'80. If a value other than an effective

address is input, processing will switch to a memory write operation but a write error will be

flagged.

• Memory address transfer is performed in the second cycle (figure 7.20). Do no t perform

transfer after the second cy cle.

• Do not perform a command write during a programming operation.

• Perform one auto-programming operation for a 128-byte block for each address.

Characteristics are not guaranteed for two or more programming operations.

• Confirm normal end of auto-programming by checking IO6. Alternatively, status read mode

can also be used for this purpose (IO7 status polling uses the auto-program operation end

identification pin).

• The status polling I O6 and IO7 pin information is retained until the next co mman d write.

Until the next command write is perfor med, reading is possible b y enabling CE and OE.

Rev. 1.0, 02/01, page 168 of 1184

7.8.6 Auto-Erase Mode

AC Characteristics

Table 7.15 AC Characteristics in Auto-Erase Mode −

−−

− Preliminary −

−−

−

Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C

Item Symbol Min Max Unit

Command write cycle tnxtc 20  µs

CE hold time tceh 0  ns

CE setup time tces 0  ns

Data hold time tdh 50  ns

Data setup time tds 50  ns

Write pulse width twep 70  ns

Status polling start time tests 1  ms

Status polling access time tspa  150 ns

Memory erase time terase 100 40000 ms

WE rise time tr  30 ns

WE fall time tf  30 ns

Erase setup time tens 100  ns

Erase end setup time tenh 100  ns

FWE

A18 to A0

IO5 to IO0

IO6

IO7

WE terase (100 to 40000ms)

tests

tspa

tnxtc

tces tceh

tdh

CLin DLin

tds

twep

tens

H'00

H'20 H'20

tenh

Erase end

identification signal

Erase normal end

identification signal

tftr

Figure 7.21 Auto-Erase Mode Timing Waveforms

Rev. 1.0, 02/01, page 169 of 1184

Notes on Use of Erase-Program Mode

• Auto-erase mode supports only entire memory erasing.

• Do not perform a command write during auto-erasing.

• Confirm normal end of auto-erasing by checking IO6. Alternatively, status read mode can also

be used for this purpose (IO7 status polling uses the auto-erase operation end identification

pin).

• The status polling I O6 and IO7 pin information is retained until the next co mman d write.

Until the next command write is perfor med, reading is possible b y enabling CE and OE.

7.8.7 Status Read Mode

Status read mode is used to identify what type of abnormal end has occurred. Use this mode when

an abnormal end occurs in auto-program mode or auto-erase mode.

The return code is retained until a co mmand write for other than status read mode is performed.

Table 7.16 AC Characteristics in Status Read Mode −

−−

− Preliminary −

−−

−

Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C

Item Symbol Min Max Unit

Command write cycle tnxtc 20  µs

CE hold time tceh 0  ns

CE setup time tces 0  ns

Data hold time tdh 50  ns

Data setup time tds 50  ns

Write pulse width twep 70  ns

OE output delay ti me toe  150 ns

Disable delay time tdf  100 ns

CE output delay time tce  150 ns

WE rise time tr  30 ns

WE fall time tf  30 ns

Rev. 1.0, 02/01, page 170 of 1184

A18 to A0

IO7 to IO0

WE t

ces

nxtc

Note: IO2 and IO3 are undefined.

ces

ceh

wep

DATA

ceh

nxtc

H'71 H'71

Figure 7.22 Status Read Mode Timing Waveforms

Table 7.17 Status Read Mode Return Commands

Pin Name IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0

Attribute Normal end

identification Command

error Programming

error Erase error   Programming

or erase count

exceeded

Effective

address error

Initial value 0 0 0 0 0 0 0 0

Indications Normal

end: 0

Abnormal

end: 1

Command

error: 1

Otherwise: 0

Programming

error: 1

Otherwise: 0

Erase error: 1

Otherwise: 0

  Count

exceeded: 1

Otherwise: 0

Effective

address

error: 1

Otherwise: 0

Note: IO2 and IO3 are undefined.

Rev. 1.0, 02/01, page 171 of 1184

7.8.8 Status Polling

The IO7 status polling flag indicates the operating status in auto-program or auto-erase mode.

The IO6 status polling flag indicates a normal or abnormal end in auto-program or auto-erase

mode.

Table 7.18 Status Polling Output Truth Table

Pin Names Internal Operation

in Progress Abnormal End 



 Normal End

IO7 0 1 0 1

IO6 0 0 1 1

IO0 to IO5 0 0 0 0

Rev. 1.0, 02/01, page 172 of 1184

7.8.9 Programmer Mode Transition Time

Commands cannot be accepted during the oscillation stabilization period or the programmer mode

setup period. After the programmer mode setup time, a transition is made to memory read mode.

Table 7.19 Command Wait State Transition Time Specifications

Item Symbol Min Max Unit

Standby releas e

(oscillation stabilization time) tosc1 10  ms

Programmer mode setup time tbmv 10  ms

VCC hold time tdwn 0  ms

RES

FWE

Memory read

mode

Command wait

state

Command

wait state

Normal/abnormal

end identifica-

tion

Auto-program mode

Auto-erase mode

osc1

bmv

dwn

Note: Except in auto-program mode and auto-erase mode, drive the FWE input pin low.

Don't care

Figure 7.23 Oscillatio n St abilizat ion Time,

Boot Program Transfer Time, and Power Supply Fall Sequence

7.8.10 Notes on Memory Programming

• When programming addresses which have previously been programmed, carry out auto-

erasing before auto-programming.

• When performing programming using programmer mode on a chip that has been

programmed/erased in an on-board programming mode, auto-erasing is recommended before

carrying out auto-pr ogra mmi n g.

Notes: 1. Th e f lash memory is initially in the erased state when the device is shipped by Hitachi.

For other chips for which the erasure history is unknown, it is recommended that auto-

erasing be executed to check and supplemen t the initialization (erase) level.

2. Auto-programming should be performed once only on the same address block.

Rev. 1.0, 02/01, page 173 of 1184

7.9 Note on Switching from F–ZTAT Version to Mask-ROM Version

The mask ROM version does not have the internal registers for flash memory control that are

provided in the F-ZTAT version. Table 7.20 lists the registers that are present in the F-ZTAT

version but not in the mask ROM version. If a register listed in table 7.20 is read in the mask

ROM version, an undefined value will be returned. Therefore, if application software developed

on the F-ZTAT version is switched to a mask ROM version product, it must be modified to ensure

that the registers in table 7.20 have no effect.

Table 7.20 Registers Present in F-ZTAT Version but Absent in Mask ROM Version

Flash memory control register 1 FLMCR1 H'FFF8

Flash memory control register 2 FLMCR2 H'FFF9

Erase block register 1 EBR1 H'FFFA

Erase block register 2 EBR2 H'FFFB

Rev. 1.0, 02/01, page 174 of 1184

Rev. 1.0, 02/01, page 175 of 1184

Section 8 RAM

8.1 Overview

The H8S/2199R, H8S/2198R, H8S/2197R, and H8S/2196R have 4 kbytes, H8S/2197S, and

H8S/2196S have 3 kbytes, and H8S/2199R F-ZTAT version has 8 kbytes of on-ch ip high-speed

static RAM. The on-chip RAM is connected to the CPU by a 16-bit data bus, enabling both byte

data and word data to be accessed in one state. This makes it possible to perform fast word data

transfer.

8.1.1 Block Diagram

Figure 8.1 shows a block diagram of the on-chip RAM.

Internal data bus (upper 8 bits)

Internal data bus (lower 8 bits)

H'FFEFB0

H'FFEFB2

H'FFEFB4

H'FFFFAE

H'FFEFB1

H'FFEFB3

H'FFEFB5

H'FFFFAF

Figure 8.1 Block Diagram of RAM (H8S/2199R)

Rev. 1.0, 02/01, page 176 of 1184

Rev. 1.0, 02/01, page 177 of 1184

Section 9 Clock Pulse Generator

9.1 Overview

This LSI has a built-in clock pulse gen e rator (CPG) that generates th e system clock (φ), the bus

master clock, and internal clocks.

The clock pulse gen erator consists of a system clock oscillator , a duty adjustment circuit, clock

selection circuit, medium-speed clo ck divider, subclock oscillator, and subclock division circuit.

9.1.1 Block Diagram

Figure 9.1 shows a block diagram of the clock pulse generator.

System

clock

oscillator

Duty

adjustment

circuit Clock

selection

circuit

Medium-

speed clock

divider

Subclock

oscillator Subclock

division

circuit

OSC1

OSC2

φ/16, φ/32, φ/64

φw/2, φw/4, φw/8

φ SUB

φ or φ SUB

Timer A

count clock

Internal clock

To supporting modules

Bus master cloc

To CPU

φSUB (φw/2, φw/4, φw/8)

Figure 9.1 Block Diagram of Clock Pulse Generator

9.1.2 Register Configuration

The clock pulse generator is controlled by SBYCR and LPWRCR. Table 9.1 shows the register

configuration.

Table 9.1 CPG Registers

Name Abbreviation R/W Initial Value Address*

Standby control register SBYCR R/W H'00 H'FFEA

Low-power control register LPWRCR R/W H'00 H'FFEB

Note: * Lower 16 bits of the address.

Rev. 1.0, 02/01, page 178 of 1184

9.2 Register Descriptions

9.2.1 Standby Control Register (SBYCR)

SSBY

R/W

STS2

R/W

STS1

R/W

STS0

R/W

—

SCK0

R/W

—

SCK1

R/W

Bit

Initial value

R/W

SBYCR is an 8-bit readable/writable register that performs power-down mode control.

Only bits 0 and 1 are described here. For a description of the other bits, see section 4.2.1, Standby

Control Register (SBYCR). SBYCR is init ialized to H'00 by a r eset.

Bits 1 and 0



System Clock Select 1 and 0 (SCK1, SCK0): These bits select the bus master

clock for high-speed mode and medium-speed mode.

Bit 1 Bit 0

SCK1 SCK0 Description

0 Bus master is in high-speed mode (Initial value) 0

1 Medium-spe ed clo ck is φ/16

0 Medium-spe ed clo ck is φ/32 1

1 Medium-spe ed clo ck is φ/64

Rev. 1.0, 02/01, page 179 of 1184

9.2.2 Low-Power Contro l Register (LPWRCR)

DTON

R/W

LSON

R/W

NESEL

R/W

—

SA0

R/W

—

SA1

R/W

Bit

Initial value

R/W

LPWRCR is an 8-bit readable/writable register that performs power-down mode control.

Only bit 1 and 0 is described here. For a description of the other bits, see section 4.2.2, Low-

Power Control Register (LPWRCR).

LPWRCR is initialized to H'00 by a reset.

Bits 1 and 0



Subactive Mode Clo c k Select (SA1, SA0): Select CPU clock for subactive mode.

In subactive mode, writes are disabled.

Bit 1 Bit 0

SA1 SA0 Description

0 CPU operating clock is φw/8 (Initial value) 0

1 CPU operating clock is φw/4

1 * CPU operating clock is φw/2

Note: * Don't care

Rev. 1.0, 02/01, page 180 of 1184

9.3 Oscillator

Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock.

9.3.1 Connecting a Crystal Resonator

Circuit Configura tion: A crystal resonator can be connected as shown in the example in figure

9.2. An AT-cut parallel-resonance crystal should be used.

OSC1

OSC2 CL2

CL1

CL1 = CL2 = 10 to 22pF

Figure 9.2 Connection of Crystal Resonator (Example)

Crystal Resonator: Figure 9.3 shows the equivalent circuit of the crystal resonator. Use a crystal

resonator that has the characteristics shown in table 9.2 and the same frequency as the system

clock (φ).

OSC1

AT-cut parallel-resonance type

OSC2

Figure 9.3 Crystal Resonator Equivalent Circuit

Table 9.2 Crystal Resonator Parameters

Frequency (MHz) 8 10

RSmax (Ω) 80 60

COmax (pF) 7 7

Rev. 1.0, 02/01, page 181 of 1184

Note on Board Design: When a crystal resonator is connected, the following po ints should be

noted.

Other signal lines should be routed away from the oscillator circuit to prevent induction from

interfering with correct oscillation. See figure 9.4.

When designing the board, place the crystal resonator and its load capacitors as close as possible

to the OSC1 and OSC2 pins.

Signal A Signal B

This LSI

OSC1

OSC2

Avoid

Figure 9.4 Example of Incorrect Board Design

Rev. 1.0, 02/01, page 182 of 1184

9.3.2 External Clock Input

Circuit Configura tion: An external clock signal can be input as shown in the examples in figure

9.5. If the OSC2 pin is left open, make sure that stray capacitance is no more than 10 pF.

In example (b), make sure that the external clock is held high in standby mode, subactive mode,

subsleep mode, and watch mode.

OSC1

OSC2

External clock input

Open

(a) OSC2 pin left open

OSC1

OSC2

External clock input

(b) Inverted-phase clock input at OSC2 pin

Figure 9.5 External Clock Input (Examples)

Rev. 1.0, 02/01, page 183 of 1184

External Clock: The external clock signal should have the same frequency as the system clock

(φ).

Table 9.3 and figure 9.6 show the input conditions for the external clock.

Table 9.3 External Clock Input Conditions

VCC = 4.0 to 5.5 V

Item Symbol Min Max Unit Test Conditions

External clo ck inp ut low

pulse width tEXL 40  ns

External clo ck inp ut high

pulse width tEXH 40  ns

External clock rise time tEXr  10 ns

External clock fall time tEXf  10 ns

Figure 9.6

tEXH tEXL

tEXr tEXf

OSC1

Figure 9.6 External Clock Input Timing

Table 9.4 shows th e external clock ou tput settling delay tim e, and figure 9.7 shows the external

clock ou tput settlin g delay timing. The oscillator and duty adjustm ent circuit hav e a functio n for

adjusting the waveform of the external clock input at the OSC1 pin. When the prescribed clock

signal is input at the OSC1 pin, internal clock signal output is fixed after the elapse of the external

clock ou tput settling delay time (tDEXT). As the clock signal output is not fixed du ring the tDEXT

period, the reset signal should be driven low to maintain the reset state.

Rev. 1.0, 02/01, page 184 of 1184

Table 9.4 External Clock Output Settling Delay Time

Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = AVSS = 0 V

Item Symbol Min Max Unit Notes

External clock outp ut settl ing

delay time tDEXT* 500  µs Figure 9.7

Note: * tDEXT includes 20 tCYC of RES pulse width (tRESW).

tDEXT*

RES

(Internal)

OSC1

VCC 4.0 V

Note: * tDEXT includes 20 tcyc of RES pulse width (tRESW).

Figure 9.7 External Clock Output Settling Delay Timing

Rev. 1.0, 02/01, page 185 of 1184

9.4 Duty Adjustment Circuit

When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit ad justs the duty

cycle of the clock sig nal from the oscillator to ge nerate the system clock (φ).

9.5 Medium-Speed Clock Divider

The medium-speed divider divides the system clock to generate φ/16, φ/32, and φ/64 clocks.

9.6 Bus Master Clock Selection Circuit

The bus master clock selection circuit selects the system clock (φ) or one of the medium-speed

clocks (φ/16, φ/32 or φ/64) to be supplied to the bus master (CPU), according to the settings of bits

SCK2 to SCK0 in SBYCR.

Rev. 1.0, 02/01, page 186 of 1184

9.7 Subclock Oscillator Circuit

9.7.1 Connecting 32.768 kHz Crystal Resonator

When using a subclock, connect a 32.768 kHz crystal resonator to X1 and X2 pins as shown in

figure 9.8.

For precautions on connecting, see Note on Board Design, in section 9.3.1 Connecting a Crystal

Resonator.

X2 C

= C

= 15 pF (Typ)

Figure 9.8 Connecting a 32.768 kHz Crystal Resonator (Example)

Figure 9.9 shows a crystal resonator equivalent circuit.

= 1.5 pF (Typ)

= 14 kΩ (Typ)

= 32.768 kHz

Type: MX38T (Nihon Denpa Kogyo Co., Ltd.)

Note: Values shown are the reference values.

Figure 9.9 32.768 kHz Crystal Resonator Equivalent Circuit

Rev. 1.0, 02/01, page 187 of 1184

9.7.2 When Subclock is not Needed

Connect X1 pin to VCL, and X2 pin should remain open as shown in figure 9.10.

Open

Figure 9.10 Terminal When Subclock is not Needed

9.8 Subclock Waveform Shaping Circuit

To eliminate noise in the subclock input from the X1 pin, this circuit samples the clock using a

clock obtained by dividing the φ clo ck. The sampling frequency is set with the NESEL bit in

LPWRCR. For details, see section 4.2.2, Low-Power Control Register (LPWRCR). The clock is

not sampled in subactive mode, subsleep mode, or watch mode.

9.9 Notes on the Resonator

Resonator characteristics are closely related to the user board design. Perform appropriate

assessment of resonator connection, mask version and F-ZTAT, by referring to the connection

example given in this section. The resonator circuit rate differs depending on the free capacity of

the resona tor and the execution circuit, so consult with the resonato r manufacturer before

determination. Make sure the voltage applied to the resonator pin does not exceed the maximum

rated voltage.

Rev. 1.0, 02/01, page 188 of 1184

Rev. 1.0, 02/01, page 189 of 1184

Section 10 I/O Port

10.1 Overview

10.1.1 Port Functions

This LSI has seven 8-bit I/O ports (including one CMOS high-current port), and one 8-bit input

port. Table 10.1 shows the functions of each port. Each I/O part a port control register (PCR) that

controls an input and output and a port data register (PDR) for storing output data. The input and

output can be controlled in a unit of bit. The pin whose peripheral function is used both as an

alternative function can set the pin function in a unit of bit by a port mode register (PMR).

10.1.2 Port Input

• Reading a Port

 When a general port of PCR = 0 (input) is read, the pin level is read.

 When a general port of PCR = 1 (output) is read, the value of the corresponding PDR bit is

read.

 When the pins (excluding AN7 to AN0 and RPB7 to RP0 pins) set to the peripheral

function are read, the results are as given in items (1) and (2) according to the PCR value.

• Processing Input Pins

The general input port or general I/O port is gated by read signals. Unused pins can be left

open if they are not read. However, if an open pin is read, a feedthrough current may apply

during the read period according to an intermediate level. The read period is about one-state.

Relevant ports: P0, P1, P2, P3, P4, P5, P6, P7, and P8

When an altern ative pin is set to an alternative fun ction other than the general I/O, always set

the pin level to a high or low level. If the pin is left open, a feedthrough current applies

according to an intermediate level, which adversely affects reliability, cau ses malfunctions,

and in the worst case may damage the pin.

Because the PMR is not initialized in low p ower consumption mode, pay atten tion to the pin

input level after the mode has been shifted to the low power consumption mode.

Relevant pins: IC, IRQ0 to IRQ5, SCK1, SI1, SDA1, SCL1, SDA0*, SCL0*, SYNCI*,

FTIA*, FTI B* , FT IC*, FTID*, RPTRG, TMBI, ADTRG, EXCTL, COMP, DPG, EXCAP,

and EXTTRG

Note: * Not available in the H8S/2197S or H8S/2196S.

Rev. 1.0, 02/01, page 190 of 1184

Table 10. 1 Port F unctions

Port Description Pins Alternative Functions

Function

Switching

Port 0 P 07 to P00 input-

only ports P07/AN7 to

P00/AN0 Anal og dat a input channels 7 to 0 PMR0

P17/TMOW Prescalar unit f requency di vi sion clock

output

P16/IC Prescal ar uni t input c apture input

Port 1 P 17 to P10 I/O ports

(Built-in MOS pull-up

transistors)

P15/IRQ5 to

P10/IRQ0 External interrupt reques t input

PMR1

P27/SYNCI Formatless serial clock input*

P26/SCL0 I2C bus interface clock I/O *

P25/SDA0 I2C bus i nterf ace dat a I/O*

STCR

ICCR

P24/SCL1 I2C bus interface clock I/O

P23/SDA1 I2C bus i nterf ace dat a I/O

P22/SCK1 SCI1 clock I/O

P21/SO1 SCI1 transmit data output

Port 2 P 27 to P20 I/O ports

(Built-in MOS pull-up

transistors)

P20/SI1 SCI1 receive data input

SMR

SCR

P37/TMO Timer J timer output

P36/BUZZ Timer J buzzer output

P35/PWM3

P34/PWM2

P33/PWM1

P32/PWM0

8-bit PWM3 output*

8-bit PWM2 output*

8-bit PWM1 output

8-bit PWM0 output

P31/SV2 Servo monitor output

Port 3 P 37 to P30 I/O ports

(Built-in MOS pull-up

transistors)

P30/SV1

PMR3

P47/RPTRG Realtime output port trigger input 

P46/FTOB Timer X output compare B output*

P45/FTOA Timer X output compare A output* TOCR

P44/FTID Timer X input capture D input*

P43/FTIC Timer X input capture C input*

P42/FTIB Timer X input capture B input*

P41/FTIA Timer X input capture A input*



Port 4 P 47 to P40 I/O ports

P40/PWM14 14-bit PWM output* PMR4

Realtime output port P67/RP7/

TMBI Timer B event output

Realtime output port P66/RP6/

ADTRG A/D conversion start external trigger

input

Port 6 P 63 to P60 I/O ports

P65/RP5 to

P60/RP0 Realtime output port

PMR6

PMRA

PPG output P77/PPG7/

RPB to P74 /

PPG4/RP8 Realtime output port

Port 7 P 77 to P70 I/O ports

P73/PPG3 to

P70/PPG0 PP G output

PMR7

PMRB

Rev. 1.0, 02/01, page 191 of 1184

Port Description Pins Alternative Functions

Function

Switching

P87/DPG DPG signal input

P86/EXTTRG External trigger signal input

Pre-amplifier output result signal

input

P85/COMP/B

Color signal output (B)

Pre-amplifier output select signal

input

P84/H.Amp

SW/G

Color signal output (G)

Control signal output for

processing color signals

P83/C.Rotary/

Color signal output (R)

P82/EXCTL External CTL signal input

External capstan signal input

P81/EXCAP/

YBO OSD character position output

Port 8 P 87 to P80 I/O ports

P80/YCO OSD character data output

PMR8

PMRC

Note: This LSI does not have port 5.

* These alternative functions are not available in the H8S/2197S or H8S/2196S.

Rev. 1.0, 02/01, page 192 of 1184

10.1.3 MOS Pull-Up Transistors

The MOS pull-up transistors in ports 1 to 3 can be switched on or off by the MOS pull-up select

registers 1 to 3 (PUR1 to PUR3 ) in units of bits. Settings in PUR1 to PUR3 are valid when the pin

function is set to an input by PCR1 to PCR3. If the pin function is set to an output, the MOS pull-

up transistor is turned off. Figure 10.1 shows the circuit configuration of a pin with a MOS pull-

up transistor.

PUR

STBY

Legend

PCR

PDR

PUR

PCR

PDR

: Low power consumption mode signal

(The pull-up MOS transistor is turned off by the STBY signal in low power

consumption mode except for sleep mode)

: MOS pull-up select register

: Port control register

: Port data register

Input data

Figure 10.1 Circuit Configuration of Pin with MOS Pull-Up Transistor

Rev. 1.0, 02/01, page 193 of 1184

10.2 Port 0

10.2.1 Overview

Port 0 is an 8-bit input-only port. Table 10.2 shows the port 0 configuration.

Port 0 consists of pins that are used both as standard input ports (P07 to P00) and analog input

channels (AN7 to AN0). It is switched by port mode register 0 (PMR0).

Table 10.2 Port 0 Configuratio n

Port Function Alternative Function

P07 (standard input port) AN7 (analog input channel)

P06 (standard input port) AN6 (analog input channel)

P05 (standard input port) AN5 (analog input channel)

P04 (standard input port) AN4 (analog input channel)

P03 (standard input port) AN3 (analog input channel)

P02 (standard input port) AN2 (analog input channel)

P01 (standard input port) AN1 (analog input channel)

Port 0

P00 (standard input port) AN0 (analog input channel)

Rev. 1.0, 02/01, page 194 of 1184

10.2.2 Register Configuration

Table 10.3 shows the port 0 register configuration.

Table 10.3 Port 0 Register Configuration

Name Abbrev. R/W Size Initial Value Address*

Port mode register 0 PMR0 R/W Byte H'00 H'FFCD

Port data register 0 PDR0 R Byte  H'FFC0

Note: * Lower 16 bits of the address.

Port Mode Register 0 (PMR0)

R/W

R/W R/WR/WR/W

6PMR04 PMR03 PMR02 PMR01 PMR00PMR07 PMR06 PMR05

Bit :

Initial value :

R/W :

Port mode register 0 (PMR0) controls switching of each pin function of port 0. The switching is

specified in a unit of bit.

PMR0 is an 8-b it r ead/write enable register. Wh en reset, PMR0 is initialized to H'00.

Bits 7 to 0



P07/AN7 to P00/AN0 Pin Switching (PMR07 to PMR00): PMR07 to PMR00 set

whether the P0n/ANn pin is used as a P0n input pin or an ANn pin for the analog input channel of

an A/D converter.

Bit n

PMR0n Description

0 The P0n/ANn pin functions as a P0n input pin (Initial value)

1 The P0n/ANn pin functions as an ANn input pin

(n = 7 to 0)

Rev. 1.0, 02/01, page 195 of 1184

Port Data Register 0 (PDR0)

57 PDR04 PDR03 PDR02 PDR01 PDR00

PDR07

RRR

PDR06 PDR05

————————

Initial value :

R/W :

Bit :

Port data register 0 (PDR0) reads the port states. When the corresponding bit of PMR0 is 0

(general input port), the pin state is read if PDR0 is read. When the corresponding bit of PMR0 is

1 (analog input ch annel) , 1 is read if PDR0 is read.

PDR0 is an 8-bit read-only register. When PDR0 is reset, its values become undefined.

10.2.3 Pin Functions

This section describes the pin functions of port 0 and their selection methods.

P07/AN7 to P00/AN0: P07/AN7 to P00/AN0 are switched according to the PMR0n bit of PMR0

as shown below.

PMR0n Pin Function

0 P0n input pin

1 ANn input pin

(n = 7 to 0)

10.2.4 Pin States

Table 10.4 shows the pin 0 states in each operation mode.

Table 10.4 P ort 0 Pin St ates

Pins Reset Active Sleep Standby Watch Subactive Subsleep

P07/AN7 to

P00/AN0 High-

impedance High-

impedance

Rev. 1.0, 02/01, page 196 of 1184

10.3 Port 1

10.3.1 Overview

Port 1 is an 8-bit I/O port. Table 10.5 shows the port 1 configuration.

Port 1 consists of pins that are used both as standard I/O ports (P17 to P10) and frequency division

clock ou tput ( T MOW) , input capture input (IC), or external interrupt request inputs (IRQ5 to

IRQ0). It is switched by port mode register 1 (PMR1) and port control register 1 (PCR1).

Port 1 can select the functions of MOS pull-up transistors.

Table 10.5 Port 1 Configuratio n

Port Function Alternative Function

P17 (standard I/O port) TMOW (frequency division clock output)

P16 (standard I/O port) IC (input capture input)

P15 (standard I/O port) IRQ5 (external interrupt request input)

P14 (standard I/O port) IRQ4 (external interrupt request input)

P13 (standard I/O port) IRQ3 (external interrupt request input)

P12 (standard I/O port) IRQ2 (external interrupt request input)

P11 (standard I/O port) IRQ1 (external interrupt request input)

Port 1

P10 (standard I/O port) IRQ0 (external interrupt request input)

10.3.2 Register Configuration

Table 10.6 shows the port 1 register configuration.

Table 10.6 Port 1 Register Configuration

Name Abbrev. R/W Size Initial Value Address*

Port mode register 1 PMR1 R/W Byte H'00 H'FFCE

Port control register 1 PCR1 W Byte H'00 H'FFD1

Port data register 1 PDR1 R/W Byte H'00 H'FFC1

MOS pull-up select

Note: * Lower 16 bits of the address.

Rev. 1.0, 02/01, page 197 of 1184

Port Mode Register 1 (PMR1)

R/W

R/W R/WR/WR/W

6PMR14 PMR13 PMR12 PMR11 PMR10PMR17 PMR16 PMR15

Bit :

Initial value :

R/W :

Port mode register 1 (PMR1) controls switching of each pin function of port 1. The switching is

specified in a unit of bit.

PMR1 is an 8-b it r ead/write enable register. Wh en reset, PMR1 is initialized to H'00.

Note the follo wing items when the pin functions are switch e d by PMR1.

• If port 1 is set to an IC input pin and IRQ5 to IRQ0 by PMR1, the pin level needs be set to the

high or low level regardless of the active mode and low power consumption mode. The pin

level must not be set to an intermediate level.

• When the pin functions of P16/IC and P15/IPQ5 to P10/IRQ0 are switched by PMR1, they are

incorrectly recognized as edge detection according to the state of a pin signal and a detection

signal may be generated. To prevent this, perform the operation in the following procedure.

 Before switching the pin functions, inhibit an interrupt enable flag from being interrupted.

 After having switched the pin functions, clear the relevant interrupt request flag to 0 by a

single instruction.

Program Example:

MOV.B R0L,@IENR ⋅⋅⋅⋅⋅⋅ In terrupt disabled

MOV.B R1L,@PMR1 ⋅⋅⋅⋅⋅⋅ Pin function change

NOP ⋅⋅⋅⋅⋅⋅ Optional instruction

BCLR m @IRQR ⋅⋅⋅⋅⋅⋅ Appli cable interrupt cl ear

MOV.B R1L,@IENR ⋅⋅⋅⋅⋅⋅ In terrupt enabled

Rev. 1.0, 02/01, page 198 of 1184

Bit 7



P17/TMOW Pin Switching (PMR17): PMR17 sets whether the P17/TMOW pin is used

as a P17 I/O pin or a TMOW pin for the frequency division clock output.

Bit 7

PMR17 Description

0 The P17/TMOW pin functions as a P17 I/O pin (Initial value)

1 The P17/TMOW pin functions as a TMOW output pin

Bit 6



P16/IC

ICIC

IC Pin Switching (PMR16): PMR16 sets whether the P16/IC pin as a P16 I/O pin or

an IC pin for the input capture input of the prescalar unit. The IC pin has a built-in noise cancel

circuit. See section 21, Prescalar Unit.

Bit 6

PMR16 Description

0 The P16/IC pin functions as a P16 I/O pin (Initial value)

1 The P16/IC pin functions as an IC input pin

Bits 5 to 0



P15/IRQ5

IRQ5IRQ5

IRQ5 to P10/IRQ0

IRQ0IRQ0

IRQ0 Pin Switching (PMR15 to PMR10): PMR15 to PMR10 set

whether the P1n/IRQn pin is used as a P1n I/O pin or an IRQn p in for the external interrupt

request input.

Bit n

PMR1n Description

0 The P1n/IRQn pin functions as a P1n I/O pin (Initial value)

1 The P1n/IRQn pin functions as an IRQn input pin

(n = 5 to 0)

Port Control Register 1 (PCR1)

W WWW

6PCR14 PCR13 PCR12 PCR11 PCR10PCR17 PCR16 PCR15

Bit :

Initial value :

R/W :

Port control register 1 (PCR1) controls the I/Os of pins P17 to P10 of port 1 in a unit of bit.

When PCR1 is set to 1, the corresponding P17 to P10 pins become output pins, and when it is set

to 0, they become input pins. When the relevant pin is set to a general I/O by PMR1, settings of

PCR1 and PDR1 become valid.

PCR1 is an 8-bit write-only register. When PCR1 is read, 1 is read. When reset, PCR1 is

initialized to H'00 .

Rev. 1.0, 02/01, page 199 of 1184

Bits 7 to 0



P17 to P10 Pin Switching (PCR17 toPCR10)

Bit n

PCR1n Description

0 The P1n pin functions as an input pin (Initial value)

1 The P1n pin functions as an output pin

(n = 7 to 0)

Port Data Register 1 (PDR1)

R/W

R/W R/WR/WR/W

6PDR14 PDR13 PDR12 PDR11 PDR10PDR17 PDR16 PDR15

Bit :

Initial value :

R/W :

Port data register 1 (PDR1) stores the data for the pins P17 to P10 of port 1. When PCR1 is 1

(output), the PDR1 values are directly read if port 1 is read. Accordingly, the pin states are not

affected. When PCR1 is 0 (input), the pin states are read if port 1 is read .

PDR1 is an 8-b it read/ write enable register. When reset, PDR1 is initialized to H'00.

MOS Pull-Up Select Register 1 (PUR1 )

R/W

R/W R/WR/WR/W

6PUR14 PUR13 PUR12 PUR11 PUR10PUR17 PUR16 PUR15

Bit :

Initial value :

R/W :

MOS pull-up selector register 1 (PUR1) controls the on and off of the MOS pull-up transistor of

port 1. Only the pin whose corresponding bit of PCR1 was set to 0 (input) becomes valid. When

the corresponding bit of PCR1 is set to 1 (output), the corresponding bit of PUR1 becomes invalid

and the MOS pull-up transistor is turned off.

PUR1 is an 8-b it read/ write enable register. When reset, PUR1 is initialized to H'00.

Bits 7 to 0



P17 to P10 MOS Pull-Up Control (PCR17 to PCR10)

Bit n

PUR1n Description

0 The P1n pin has no MOS pull-up transistor (Initial value)

1 The P1n pin has a MOS pull-up pin

(n = 7 to 0)

Rev. 1.0, 02/01, page 200 of 1184

10.3.3 Pin Functions

This section describes the port 1 pin functions and their selection methods.

P17/TMOW: P17/TMOW is switched as shown below according to the PMR17 bit in PMR1 and

the PCR17 b it in PCR1.

PMR17 PCR17 Pin Function

0 P17 input pin 0

1 P17 output pin

1 * TMOW output pin

Note: * Don’t care

P16/IC

ICIC

IC: P16/IC is switched as shown below according to the PMR16 bit in PMR1, the NC on/off

bit in prescalar unit contro l/status re gister (PCSR), and the PCR16 bit in PCR1.

PMR16 PCR16 NC on/off Pin Function

0 P16 input pin 0

P16 output pin

0 Noise cancel invalid 1 *

IC input pin

Noise cance l vali d

Note: * Don’t care

P15/IRQ5

IRQ5IRQ5

IRQ5 to P10/IRQ0

IRQ0IRQ0

IRQ0: P15/IRQ15 to P10/IRQ0 are switched as shown belo w according to the

PMR1n bit in PMR1 and the PCR1n bit in PCR1.

PMR1n PCR1n Pin Function

0 P1n input pin 0

1 P1n output pin

1 * IRQn input pin

(n = 5 to 0)

Notes: 1. * Don’t care.

2. The IRQ5 to IRQ0 input pins can select the leading or falling edge as an edge sense

(the IRQ0 pin can select both edges). See section 6.2.4, IRQ Edge Select Register

(IEGR).

3. IRQ1 or IRQ2 can be used as a timer J event input and IRQ3 can be used as a timer R

input capture input. For details , see section 13, Timer J or section 15, Timer R.

Rev. 1.0, 02/01, page 201 of 1184

10.3.4 Pin States

Table 10.7 shows the port 1 pin states in each operation mode.

Table 10.7 P ort 1 Pin St ates

Pins Reset Active Sleep Standby Watch Subactive Subsleep

P17/TMOW

P16/IC

P15/IRQ5

P10/IRQ0

High-

impedance Operation Holding High-

impedance High-

impedance Operation Holding

Note: If the IC input pin and IRQ5 to IRQ0 input pins are set, the pin level need be set to the high

or low level regardless of the active mode and low po wer consumption mode. Note that the

pin level must not reach an intermediate level.

Rev. 1.0, 02/01, page 202 of 1184

10.4 Port 2

10.4.1 Overview

Port 2 is an 8-bit I/O port. Table 10.8 shows the port 2 configuration.

Port 2 consists of pins that are used both as standard I/O ports (P27 to P20) and SCI clock I/O

(SCK1), receive data input (SI1), send data output (SO1), I2C bus interface clock I/O (SCL0,

SCL1), or data I/O (SDA0, SDA1). It is switched by serial mode register (SMR), serial control

Port 2 can select the MOS pull-up function.

Table 10.8 Port 2 Configuratio n

Port Function Alternative Function

P27 (standard I/O port) SYNCI (Formatless serial clock input)

P26 (standard I/O port) SCL0 (I2C bus interface clock I/O)

P25 (standard I/O port) SDA0 (I2C bus interface data I/O)

P24 (standard I/O port) SCL1 (I2C bus interface clock I/O)

P23 (standard I/O port) SDA1 (I2C bus interface data I/O)

P22 (standard I/O port) SCK1 (SCI1 clock I/O)

P21 (standard I/O port) SO1 (SCI1 transmit data output)

Port 2

P20 (standard I/O port) SI1 (SCI1 receiv e data input)

Note: The H8S/2197S and H8S/2196S do not have SYNCI, SCL0, and SDA0 pin functions.

10.4.2 Register Configuration

Table 10.9 shows the port 2 register configuration.

Table 10.9 Port 2 Register Configuration

Name Abbrev. R/W Size Initial Value Address*

Port control register 2 PCR2 W Byte H'00 H'FFD2

Port data register 2 PDR2 R/W Byte H'00 H'FFC2

MOS pull-up select

Note: * Lower 16 bits of the address.

Rev. 1.0, 02/01, page 203 of 1184

Port Control Register 2 (PCR2)

W WWW

6PCR24 PCR23 PCR22 PCR21 PCR20PCR27 PCR26 PCR25

Bit :

Initial value :

R/W :

Port control register 2 (PCR2) controls the I/Os of pins P27 to P20 of port 2 in a unit of bit.

When PCR2 is set to 1, the corresponding P27 to P20 pins become output pins, and when it is set

to 0, they become input pins. When the relevant pin is set to a general I/O, settings of PCR2 and

PDR2 are valid.

PCR2 is an 8-bit write-only register. When PCR2 is read, 1 is read. When reset, PCR2 is

initialized to H'00 .

Bits 7 to 0



P27 to P20 Pin Switching (PCR27 to PCR20)

Bit n

PCR2n Description

0 The P2n pin functions as an input pin (Initial value)

1 The P2n pin functions as an output pin

(n = 7 to 0)

Port Data Register 2 (PDR2)

R/W

R/W R/WR/WR/W

6PDR24 PDR23 PDR22 PDR21 PDR20PDR27 PDR26 PDR25

Bit :

Initial value :

R/W :

Port data register 2 (PDR2) stores the data for the pins P27 to P20 of port 2. When PCR2 is 1

(output), the PDR2 values are directly read if port 2 is read. Accordingly, the pin states are not

affected. When PCR2 is 0 (input), the pin states are read if port 2 is read .

PDR2 is an 8-b it r ead/write enable register. When reset, PDR2 is initialized to H'00.

Rev. 1.0, 02/01, page 204 of 1184

MOS Pull-Up Select Register 2 (PUR2 )

R/W

R/W R/WR/WR/W

6PUR24 PUR23 PUR22 PUR21 PUR20PUR27 PUR26 PUR25

Bit :

Initial value :

R/W :

MOS pull-up selector register 2 (PUR2) controls the ON and OFF of the MOS pull-up transistor

of port 2. Only the pin whose corresponding bit of PCR2 was set to 0 (input) becomes valid. If

the corresponding bit of PCR2 is set to 1 (output), the corresponding bit of PUR2 becomes invalid

and the MOS pull-up transistor is turned off.

PUR2 is an 8-b it r ead/write enable register. When reset, PUR2 is initialized to H'00.

Bits 7 to 0



P27 to P20 Pull-Up MOS Control (PUR27 to PUR20)

Bit n

PUR2n Description

0 The P2n pin has no MOS pull-up transistor (Initial value)

1 The P2n pin has a MOS pull-up transistor

(n = 7 to 0)

Rev. 1.0, 02/01, page 205 of 1184

10.4.3 Pin Functions

This section describes the port 2 pin functions and their selection methods.

P27/SYNCI: P27/SYNCI is switched as shown below according to the PCR27 bit in PCR2.

PCR Pin Function

0 P27 input pin

1 P27 output pin

Notes: Because the SYNCI always functions, the alternative pin need always be set to the high or

low level regardless of active mode or low power consumption mode.

The H8S/2197S and H8S/2196S do not have SYNCI pin function.

P26/SCL0: P26/SCL0 is switched as shown below according to the PCR26 bit in PCR2 and the

ICE bit in the I2C Bus control register 0 (ICCR0).

ICE PCR26 Pin Function

0 P26 input pin 0

1 P26 output pin

1 * SCL0 I/O pin

Notes: * Don’t care

The H8S/2197S and H8S/2196S do not have SCL0 pin function.

P25/SDA0: P25/SDA0 is switched as shown below according to the PCR25 bit in PCR2 and the

ICE bit in the I2C Bus control register 0 (ICCR0).

ICE PCR25 Pin Function

0 P25 input pin 0

1 P25 output pin

1 * SDA0 I/O pin

Notes: * Don’t care

The H8S/2197S and H8S/2196S do not have SDA0 pin function.

Rev. 1.0, 02/01, page 206 of 1184

P24/SCL1: P24/SCL1 is switched as shown below according to the PCR24 bit in PCR2 and the

ICE bit in the I2C Bus control register 1 (ICCR1).

ICE PCR24 Pin Function

0 P24 input pin 0

1 P24 output pin

1 * SCL1 I/O pin

Note: * Don’t care

P23/SDA1: P23/SDA1 is switched as shown below according to the PCR23 bit in PCR2 and the

ICE bit in the I2C Bus control register 1 (ICCR1).

ICE PCR23 Pin Function

0 P23 input pin 0

1 P23 output pin

1 * SDA1 I/O pin

Note: * Don’t care

P22/SCK1: P22/SCK1 is switched as shown below according to the PCR22 bit in PCR2, the C/A

bit in SMR, and the CKE1 and CKE0 bits in SCR.

CKE1 C/A

A CKE0 PCR22 Pin Function

0 P22 input pin 0

1 P22 output pin

SCK1 output pin

1 *

SCK1 input pin

Note: * Don’t care

P21/SO1: P21/SO1 is switched as shown below according to the PCR21 bit in PCR2 and the TE

bit in SCR.

TE PCR21 Pin Function

0 P21 input pin 0

1 P21 output pin

1 * SO1 output pin

Note: * Don’t care

Rev. 1.0, 02/01, page 207 of 1184

P20/SI1: P20/SI1 is switched as shown below according to the PCR20 bit in PCR2 and the RE bit

in SCR.

RE PCR20 Pin Function

0 P20 input pin 0

1 P20 output pin

1 * SI1 input pin

Note: * Don’t care

10.4.4 Pin States

Table 10.10 shows the port 2 pin states in each operation mode.

Table 10.10 Port 2 Pin States

Pins Reset Active Sleep Standby Watch Subactive Subsleep

P27/SYNCI

P26/SCL0

P25/SDA0

P24/SCL1

P23/SDA1

P22/SCK1

P21/SO1

P20/SI1

High-

impedance Operation Holding High-

impedance High-

impedance Operation Holding

Note: Because the SYNCI, SCL0, SDA0, SCL1, and SDA1 always function, the alternative pin

need always be set to the high or low level regardless of active mode or low power

consumption mode.

If the SCK1, and SI1 input pi ns are set, the pin level needs be set to the high or low level

regardless of the active mode and low power consumption mode. Note that the pin level

must not reac h an intermediate level.

Rev. 1.0, 02/01, page 208 of 1184

10.5 Port 3

10.5.1 Overview

Port 3 is an 8-bit I/O port. Table 10.11 shows the port 3 configuration.

Port 3 consists of pins that are used both as standard I/O ports (P37 to P30) and timer J timer

output (TMO), buzzer output (BUZZ), 8-bit PWM outputs (PWM3 to PWM0), SCI2 strobe output

(STRB), or chip select input (CS). It is switched by port mode register 3 (PMR3) and port control

Port 3 can select the MOS pull-up function.

Table 10.11 Port 3 Configuration

Port Function Alternative Function

P37 (standard I/O port) TMO (timer J timer output)

P36 (standard I/O port) BUZZ (timer J buzzer output)

P35 (standard I/O port) PWM3 (8-bit PWM output)

P34 (standard I/O port) PWM2 (8-bit PWM output)

P33 (standard I/O port) PWM1 (8-bit PWM output)

P32 (standard I/O port) PWM0 (8-bit PWM output)

P31 (standard I/O port) SV2 (servo monitor output)

Port 3

P30 (standard I/O port) SV1 (servo monitor output)

Note: The H8S/2197S and H8S/2196S do not have PWM3 and PWM2 pin functions.

10.5.2 Register Configuration

Table 10.12 shows the port 3 register configuration.

Table 10.12 Port 3 Register Configuration

Name Abbrev. R/W Size Initial Value Address*

Port mode register 3 PMR3 R/W Byte H'00 H'FFD0

Port control register 3 PCR3 W Byte H'00 H'FFD3

Port data register 3 PDR3 R/W Byte H'00 H'FFC3

MOS pull-up select

Note: * Lower 16 bits of the address.

Rev. 1.0, 02/01, page 209 of 1184

Port Mode Register 3 (PMR3)

R/W

R/W R/WR/WR/W

6PMR34 PMR33 PMR32 PMR31 PMR30PMR37 PMR36 PMR35

Bit :

Initial value :

R/W :

Port mode register 3 (PMR3) controls switching of each pin function of port 3. The switching is

specified in a unit of bit.

PMR3 is an 8-b it r ead/write enable register. Wh en reset, PMR3 is initialized to H'00.

Bit 7



P37/TMO Pin Switching (PMR37): PMR37 sets whether the P37/TMO pin is used as a

P37 I/O pin or a TMO pin for the timer J output timer.

Bit 7

PMR37 Description

0 The P37/TMO pin functions as a P37 I/O pin (Initial value)

1 The P37/TMO pin functions as a TMO output pin

Notes: If the TMO pin is used for remote control sending, a careless timer output pulse may be

output when the remote control mode is set after the output has been switched to the TMO

output. Perform the switching and setting in the following order.

1. Set the remote control mode.

2. Set the TMJ-1 and 2 counter data of the timer J.

3. Switch the P37/TMO pin to the TMO output pin.

4. Set the ST bit to 1.

Bit 6



P36/BUZZ Pin Switching (PMR36): PMR36 sets whether the P36/BUZZ pin as a P36

I/O pin or an BUZZ pin for the timer J buzzer output. For the selection of the BUZZ output, see

13.2.2, Timer J Control Register (TMJC).

Bit 6

PMR36 Description

0 The P36/BUZZ pin functions as a P36 I/O pin (Initial value)

1 The P36/BUZZ pin functions as a BUZZ output pin

Rev. 1.0, 02/01, page 210 of 1184

Bits 5 to 2



P35/PWM3 to P32/PWM0 Pin Switching (PMR35 to PMR32): PMR35 to PMR32

set whether the P3n/PWMm pin is used as a P3n I/O pin or a PWMm pin for the 8-bit PWM

output.

Bit n

PMR3n Description

0 The P3n/PWMm pin functions as a P3n I/O pin (Initial value)

1 The P3n/PWMm pin functions as a PWMm output pin

(n = 5 to 2, m = 3 to 0)

Note: The H8S/2197S and H8S/2196S do not have PWM3 and PWM2 pin functions.

Bit 1



P31/SV2 Pin Switching (PMR31): PMR31 sets whether the P31/SV2 pin is used as a P31

I/O pin or an SV2 pin for the servo monitor output.

Bit 1

PMR31 Description

0 The P31/SV2 pin functions as a P31 I/O pin (Initial value)

1 The P31/SV2 pin functions as an SV2 output pin

Bit 0



P30/SV1 Pin Switching (PMR30): PMR30 sets whether the P30/SV1 pin is used as a P30

I/O pin or an SV1 pin for servo monitor output.

Bit 0

PMR30 Description

0 The P30/SV1 pin functions as a P30 I/O pin (Initial value)

1 The P30/SV1 pin functions as an SV1 output pin

Rev. 1.0, 02/01, page 211 of 1184

Port Control Register 3 (PCR3)

W WWW

6PCR34 PCR33 PCR32 PCR31 PCR30PCR37 PCR36 PCR35

Bit :

Initial value :

R/W :

Port control register 3 (PCR3) controls the I/Os of pins P37 to P30 of port 3 in a unit of bit.

When PCR3 is set to 1, the corresponding P37 to P30 pins become output pins, and when it is set

to 0, they become input pins. When the relevant pin is set to a general I/O by PMR3, settings of

PCR3 and PDR3 become valid.

PCR3 is an 8-bit write-only register. When PCR3 is read, 1 is read. When reset, PCR3 is

initialized to H'00 .

Bits 7 to 0



Pin 37 to P30 Pin Switching (PCR37 to PCR30)

Bit n

PCR3n Description

0 The P3n pin functions as an input pin (Initial value)

1 The P3n pin functions as an output pin

(n = 7 to 0)

Port Data Register 3 (PDR3)

R/W

R/W R/WR/WR/W

6PDR34 PDR33 PDR32 PDR31 PDR30PDR37 PDR36 PDR35

Bit :

Initial value :

R/W :

Port data register 3 (PDR3) stores the data for the pins P37 to P30 of port 3. When PCR3 is 1

(output), the PDR3 values are directly read if port 3 is read. Accordingly, the pin states are not

affected. When PCR3 is 0 (input), the pin states are read if port 3 is read .

PDR3 is an 8-b it r ead/write enable register. When reset, PDR3 is initialized to H'00.

Rev. 1.0, 02/01, page 212 of 1184

MOS Pull-Up Select Register 3 (PUR3 )

R/W

R/W R/WR/WR/W

6PUR34 PUR33 PUR32 PUR31 PUR30PUR37 PUR36 PUR35

Bit :

Initial value :

R/W :

MOS pull-up selector register 3 (PUR3) controls the ON and OFF of the MOS pull-up transistor

of port 3. Only the pin whose corresponding bit of PCR3 was set to 0 (input) becomes valid. If

the corresponding bit of PCR3 is set to 1 (output), the corresponding bit of PUR3 becomes invalid

and the MOS pull-up transistor is turned off.

PUR3 is an 8-b it r ead/write enable register. When reset, PUR3 is initialized to H'00.

Bits 7 to 0



P37 to P30 MOS Pull-Up Control (PUR37 to PUR30)

Bit n

PCR3n Description

0 The P3n pin has no MOS pull-up transistor (Initial value)

1 The P3n pin has a MOS pull-up transistor

(n = 7 to 0)

10.5.3 Pin Functions

This section describes the port 3 pin functions and their selection methods.

P37/TMO: P37/TMO is switched as shown below according to the PMR37 bit in PMR3 and the

PCR37 bit in PCR3.

PMR37 PCR37 Pin Function

0 P37 input pin 0

1 P37 output pin

1 * TMO output pin

Note: * Don’t care

Rev. 1.0, 02/01, page 213 of 1184

P36/BUZZ: P36/BUZZ is switched as shown below according to the PMR36 bit in PMR3 and the

PCR36 bit in PCR3.

PMR36 PCR36 Pin Function

0 P36 input pin 0

1 P36 output pin

1 * BUZZ output pin

Note: * Don’t care

P35/PWM3: P35/PWM3 is switched as shown below according to the PMR3n bit in PMR3 and

the PCR3n b it in PCR3.

PMR35 PCR35 Pin Function

0 P35 input pin 0

1 P35 output pin

1 * PWM3 output pin

Notes: * Don’t care

The H8S/2197S and H8S/2196S do not have PWM3 pin function.

P34/PMW2: P34/PMW2 is switched as shown below according to the PMR34 bit in PCR3 and

the PCR34 b it in PCR3.

PMR34 PCR34 Pin Function

0 P34 input pin 0

1 P34 output pin

1 * PWM2 output pin

Notes: * Don’t care

The H8S/2197S and H8S/2196S do not have PWM2 pin function.

P33/PWM1: P33/PWM1 is switched as shown below according to the PMR33 bit in PMR3 and

the PCR33 b it in PCR3.

PMR33 PCR33 Pin Function

0 P33 input pin 0

1 P33 output pin

1 * PWM1 input pin

Note: * Don’t care

Rev. 1.0, 02/01, page 214 of 1184

P32/PWM0: P32/PWM0 is switched as shown below according to the PMR32 bit in PMR3 and

the PCR32 b it in PCR.

PMR32 PCR32 Pin Function

0 P32 input pin 0

1 P32 output pin

1 * PWM0 output pin

P31/SV2: P31/SV2 is switched as shown below according to the PMR31 bit in PMR3 and the

PCR31 bit in PCR3.

PMR31 PCR3 Pin Function

0 P31 input pin 0

1 P31 output pin

1 * SV2 output pin

P30/SV1: P30/SV1 is switched as shown below according to the PMR30 bit in PMR3 and the

PCR30 bit in PCR3.

PMR30 PCR30 Pin Function

0 P30 input pin 0

1 P30 output pin

1 * SV1 output pin

Note: * Don’t care

Rev. 1.0, 02/01, page 215 of 1184

10.5.4 Pin States

Table 10.13 shows the port 3 pin states in each operation mode.

Table 10.13 Port 3 Pin States

Pins Reset Active Sleep Standby Watch Subactive Subsleep

P37/TMO

P36/BUZZ

P35/PWM3

P32/PWM0

P31/SV2

P30/SV1

High-

impedance Operation Holding High-

impedance High-

impedance Operation Holding

Rev. 1.0, 02/01, page 216 of 1184

10.6 Port 4

10.6.1 Overview

Port 4 is an 8-bit I/O port. Table 10.14 shows the port 4 configuration.

Port 4 consists of pins that are used both as standard I/O ports (P47 to P40) and output compare

output (FTOA, FTOB), input capture input (FTIA, FTIB, FTIC, FTID) or 14-bit PWM output

(PWM14). It is switched by port mode register 4 (PRM4), timer output compare control register

(TOCR), and port control register 4 (PCR4).

Table 10.14 Port 4 Configuration

Port Function Alternative Function

P47 (standard I/O port) RPTRG (realtime output port trigger input)

P46 (standard I/O port) FTOB (timer X1 output compare output)

P45 (standard I/O port) FTOA (timer X1 output compare output)

P44 (standard I/O port) FTID (timer X1 input capture input)

P43 (standard I/O port) FTIC (timer X1 input capture input)

P42 (standard I/O port) FTIB (timer X1 input capture input)

P41 (standard I/O port) FTIA (timer X1 input capture input)

Port 4

P40 (standard I/O port) PWM14 (14-bit PWM output)

Note: The H8S/2197S and H8S/2196S do not have PWM14, FTIA, FTIB, FTIC, FTID, FTOA, and

FTOB pin functions.

10.6.2 Register Configuration

Table 10.15 shows the port 4 register configuration.

Table 10.15 Port 4 Register Configuration

Name Abbrev. R/W Size Initial Value Address*

Port mode register 4 PMR4 R/W Byte H'7E H'FFDB

Port control register 4 PCR4 W Byte H'00 H'FFD4

Port data register 4 PDR4 R/W Byte H'00 H'FFC4

Note: * Lower 16 bits of the address.

Rev. 1.0, 02/01, page 217 of 1184

Port Mode Register 4 (PMR4)

R/W

6—————PMR47 —

—————R/W —

PMR40

Bit :

Initial value :

R/W :

Port mode register 4 (PMR4) controls switching of the P47/RPTRG pin and the P40/PWM14 pin

function. The switchings of the P46/FTOB and P45/FTOA functions are controlled by TOCR.

See section 16, Timer X1. The FTIA, FTIB, FTIC, and FTID inputs always function.

PMR4 is an 8-b it r ead/write enable register. When reset, PMR4 is initialized to H'7E.

Because the RPTRG input always function, the alternative pin need always be set to the high or

low level regardless of the active mode and low power consumption mode. Note that the pin level

must not reach an intermediate level.

Because the FTIA, FTIB, FTIC, and FTID inputs always function, each input uses the input edge

to the alternative general I/O pins P44, P43, P42, and P41 as input signals.

Bit 7



P47/RPTRG Pin Switching (PMR47): PMR47 sets whether the P47/RPTRG pin is used

as a P40 I/O pin or a RPTRG pin for the realtime outp ut port trigger input.

Bit 7

PMR47 Description

0 The P47/RPTRG pin functions as a P47 I/O pin (Initial value)

1 The P47/RPTRG pin functions as a RPTRG I/O pin

Bits 6 to 1



Reserved Bits: Reserved bits. When the bits are read, 1 is always read. The write

operation is invalid.

Bit 0



P40/PWM14 Pin Switching (PMR40): PMR40 sets whether the P40/PWM14 pin is used

as a P40 I/O pin or a PWM14 pin for the 14-bit PWM square wave output.

Bit 0

PMR40 Description

0 The P40/PWM14 pin functions as a P40 I/O pin (Initial value)

1 The P40/PWM14 pin functions as a PWM14 output pin

Note: The H8S/2197S and H8S/2196S do not have PWM14 pin function.

Rev. 1.0, 02/01, page 218 of 1184

Port Control Register 4 (PCR4)

W WWW

6PCR44 PCR43 PCR42 PCR41 PCR40PCR47 PCR46 PCR45

Bit :

Initial value :

R/W :

Port control register 4 (PCR4) controls the I/Os of pins P47 to P40 of port 4 in a unit of bit.

When PCR4 is set to 1, the corresponding P47 to P40 pins become output pins, and when it is set

to 0, they become input pins. When the relevant pin is set to a general I/O by PMR4, settings of

PCR4 and PDR4 become valid.

PCR4 is an 8-bit write-only register. When PCR4 is read, 1 is read. When reset, PCR4 is

initialized to H'00 .

Bits 7 to 0



P47 to P40 Pin Switching (PCR47 to PCR40)

Bit n

PCR4n Description

0 The P4n pin functions as an input pin (Initial value)

1 The P4n pin functions as an output pin

(n = 7 to 0)

Port Data Register 4 (PDR4)

R/W

R/W R/WR/WR/W

6PDR44 PDR43 PDR42 PDR41 PDR40PDR47 PDR46 PDR45

Bit :

Initial value :

R/W :

Port data register 4 (PDR4) stores the data for the pins P47 to P40 of port 4. When PCR4 is 1

(output), the PDR4 values are directly read if port 4 is read. Accordingly, the pin states are not

affected. When PCR4 is 0 (input), the pin states are read if port 4 is read .

PDR4 is an 8-b it r ead/write enable register. When reset, PDR4 is initialized to H'00.

Rev. 1.0, 02/01, page 219 of 1184

10.6.3 Pin Functions

This section describes the port 4 pin functions and their selection methods.

P47/RPTRG: P47/RPTRG is switched as shown below according to the PMR47 bit in PMR4 and

the PMR47 b it in PMR4 and the PCR47 bit in PCR4.

PMR47 PCR47 Pin Function

0 0 P47 input pin

1 P47 output pin

1 * RPTRG input pin

Note: * Don’t care

P46/FTOB: P46/FTOB is switched as shown below according to the PCR46 bit in PCR4 and the

OEB bit in TOCR.

OEB PCR46 Pin Function

0 P46 input pin 0

1 P46 output pin

1 * FTOB output pin

Notes: * Don’t care

The H8S/2197S and H8S/2196S do not have FTOB pin function.

P45/FTOA: P45/FTOA is switched as shown below according to the PCR45 bit in PCR4 and the

OEA bit in TOCR.

OEA PCR45 Pin Function

0 P45 input pin 0

1 P45 output pin

1 * FTOA output pin

Notes: * Don’t care

The H8S/2197S and H8S/2196S do not have FTOA pin function.

P44/FTID: P44/FTID is switched as shown below according to the PCR44 bit in PCR4.

PCR44 Pin Function

0 P44 input pin

1 P44 output pin

FTID input pin

Note: The H8S/2197S and H8S/2196S do not have FTID pin function.

Rev. 1.0, 02/01, page 220 of 1184

P43/FTIC: P43/FTIC is switched as shown below according to the PCR43 bit in PCR4.

PCR43 Pin Function

0 P43 input pin

1 P43 output pin

FTIC input pin

Note: The H8S/2197S and H8S/2196S do not have FTIC pin function.

P42/FTIB: P42/FTIB is switc hed as shown below according to the PCR42 bit in PCR4.

PCR42 Pin Function

0 P42 input pin

1 P42 output pin

FTIB input pin

Note: The H8S/2197S and H8S/2196S do not have FTIB pin function.

P41/FTIA: P41/FTIA is switched as shown below according to the PCR41 bit in PCR4.

PCR41 Pin Function

0 P41 input pin

1 P41 output pin

FTIA input pin

Note: The H8S/2197S and H8S/2196S do not have FTIA pin function.

P40/PWM14: P40/PWM14 is switched as shown below according to the PMR40 bit in PMR4 and

the PCR40 b it in PCR4.

PMR40 PCR40 Pin Function

0 P40 input pin

1 P40 output pin

1 * PWM14 input pin

Notes: * Don’t care

The H8S/2197S and H8S/2196S do not have PWM14 pin function.

Rev. 1.0, 02/01, page 221 of 1184

10.6.4 Pin States

Table 10.16 shows the port 4 pin states in each operation mode.

Table 10.16 Port 4 Pin States

Pins Reset Active Sleep Standby Watch Subactive Subsleep

P47/RPTRG

P46/FTOB

P45/FTOA

P44/FTID

P43/FTIC

P42/FTIB

P41/FTIA

P40/PWM14

High-

impedance Operation Holding High-

impedance High-

impedance Operation Holding

Note: If the RPTRG input pin is set, the pin level must be set to the high or low level regardless of

the active mode or low power consumption mode. Note that the pin level must not reach an

intermediate le vel.

Because the FTIA, FTIB, FTIC, and FTID inputs always function, the alternative pin need be

set to the high or low level regardless of the active mode and low power consumption

mode.

Rev. 1.0, 02/01, page 222 of 1184

10.7 Port 6

10.7.1 Overview

Port 6 is an 8-bit I/O port. Table 10.17 shows the port 6 configuration. Port 6 is a large current I/O

port.

The sink current is 20 mA maximum (VOL=1.7 V) and four pins can be tu rned on at the same

time. Port 6 consists of p in s that ar e used as large current I/O ports (P6 7 to 60) and realtime output

ports (RP7 to RP0). It is switched by port mode register 6 (PMR6), port mode register A (PMRA),

and port contro l register 6 (PCR6).

The realtime output f unctio n can instantaneously switch the output data by an external or internal

trigger port.

Table 10.17 Port 6 Configuration

Port Function Alternative Function

P67 (large current I/O port) RP7/TMBI (timer B event inpu t)

P66 (large current I/O port) RP6/ADTRG (A/D conversion start external

trigger input)

P65 (large current I/O port) RP5 (realtime output port pin)

P64 (large current I/O port) RP4 (realtime output port pin)

P63 (large current I/O port) RP3 (realtime output port pin)

P62 (large current I/O port) RP2 (realtime output port pin)

P61 (large current I/O port) RP1 (realtime output port pin)

Port 6

P60 (large current I/O port) RP0 (realtime output port pin)

Rev. 1.0, 02/01, page 223 of 1184

10.7.2 Register Configuration

Table 10.18 shows the port 6 register configuration.

Table 10.18 Port 6 Register Configuration

Name Abbrev. R/W Size Initial Value Address*

Port mode register 6 PMR6 R/W Byte H'00 H'FFDD

Port mode register A PMRA R/W Byte H'3F H'FFD9

Port control register 6 PCR6 W Byte H'00 H'FFD6

Port data register 6 PDR6 R/W Byte H'00 H'FFC6

Realtime output trigger

select register 1 RTPSR1 R/W Byte H'00 H'FFE5

Realtime output trigger

edge select registe r RTPEGR*2 R/W Byte H'FC H'FFE4

Port control register slave

6 PCRS6  Byte H'00 

Port data register slave 6 PDRS6  Byte H'00 

Notes: 1. Lower 16 bits of the address.

2. RTPEGR is also used by port 7.

Port Mode Register 6 (PMR6)

R/W

7PMR64 PMR63 PMR62 PMR61 PMR60

R/W

PMR67

R/WR/WR/W

PMR66 PMR65

Bit :

Initial value :

R/W :

Port mode register 6 (PMR6) controls switching of each pin function of port 6. The switching is

specified in u nits of bits.

PMR6 is an 8-b it r ead/write enable register. Wh en reset, PMR6 is initialized to H'00 .

Bits 7 to 0



P67/RP7 to P60/RP0 Pin Switching (PMR67 to PMR60): PMR67 to PMR60 set

whether the P6n/RPn pin is used as a P6n I /O pin or an RPn pin for the realtime output port.

Bit n

PMR6n Description

0 The P6n/RPn pin functions as a P6n I/O pin (Initial value)

1 The P6n/RPn pin functions as an RPn output pin

(n = 7 to 0)

Rev. 1.0, 02/01, page 224 of 1184

Port Mode Register A (PMRA)

—

R/W ——R/W

6—————PMRA7 PMRA6 —

Bit :

Initial value :

R/W :

Port mode register A (PMRA) switches the pin functions in port 6. Switching is specified in a unit

of bit. PMR6 is an 8 -bit r ead /write reg ister.

When reset, PMRA is initialized to H'3F.

Bit 7



P67/RP7/TMBI Pin Switching (PMRA7): PMRA7 can be used as a P6n I/O pin or a

TMBI pin for timer B event input.

Bit 7

PMRA7 Description

0 P67/RP7/TMBI pin functions as a P67/RP7 I/O pin (Initial value)

1 P67/RP7/TMBI pin functions as a TMBI pin

Bit 6



Timer B Event In put Edge Sw itching (PMRA6): PMRA6 selects the TMBI edge sense.

Bit 6

PMRA6 Description

0 Timer B event inpu t detects falling edge

1 Timer B event input detects rising edge

Rev. 1.0, 02/01, page 225 of 1184

Port Control Register 6 (PCR6)

7PCR64 PCR63 PCR62 PCR61 PCR60

PCR67

WWW

PCR66 PCR65

Bit :

Initial value :

R/W :

Port contr ol register 6 (PCR6) selects the general I /O of port 6 and controls the r ealtime output in

a unit of bit tog e ther with PMR6.

When PMR6 = 0, the corresponding P67 to P60 pins become general output pins if PCR6 is set to

1, and they become general input pins if it is set to 0.

When PMR6 = 1, PCR6 controls the correspond ing RP7 to RP0 realtime outp ut pins. For details,

see section 10.7.4, Operation.

PCR6 is an 8-bit write-only register. When PCR6 is read, 1 is read. When reset, PCR6 is

initialized to H'00 .

PMR6 PCR6

Bit n Bit n

PMR6n PCR6n Description

0 The P6n/RPn pin functions as a P6n general I/O input pin

(Initial value)

1 The P6n/RPn pin functions as a P6n general output pin

1 * The P6n/RPn pin functions as an RPn realtime output pin

Note: * Don’t care (n = 7 to 0)

Port Data Register 6 (PDR6)

R/W

7PDR64 PDR63 PDR62 PDR61 PDR60

R/W

PDR67

R/WR/WR/W

PDR66 PDR65

Bit :

Initial value :

R/W :

Port data register 6 (PDR6) stores the data for the pins P67 to P60 of port 6.

For PMR6 = 0, when PCR6 is 1 (output), the PDR6 values are directly read if po rt 6 is read.

Accordingly, the pin states are not affected. When PCR6 is 0 (input), the pin states are read if port

6 is read.

For PMR6 = 1, port 6 becomes a realtime output pin. For details, see section 10 . 7.4, Operation.

PDR6 is an 8-b it r ead/write enable register. When reset, PDR6 is initialized to H'00.

Rev. 1.0, 02/01, page 226 of 1184

Realtime Output Trigger Select Register (RTPSR1)

R/W

7RTPSR14 RTPSR13 RTPSR12 RTPSR11 RTPSR10

R/W

RTPSR17

R/WR/WR/W

RTPSR16 RTPSR15

Bit :

Initial value :

R/W :

The realtime ou tput trigger select register (RTPSR1) sets whether the ex ternal trigger (RPTRG pin

input) or the internal trigger (HSW) is used as an trigger input for the realtime output in a unit of

bit. For the internal trigger HSW, see section 26.4, HSW Timing Generation Circuit.

RTPSR is an 8- bit read/write enable reg ister . When reset, RTPSR is initialized to H'00.

Bits 7 to 0



RP7 to RP0 Trigger Switching

Bit n

RTPSR1n Description

0 Selects the external trigger (RPTRG pin input) as a trigger input (Initial value)

1 Selects the internal trigger (HSW) a trigger input

(n = 7 to 0)

Rev. 1.0, 02/01, page 227 of 1184

Real Time Output Trigger Edge Select Register (RTPEGR)

R/W

7——————

——————

RTPEGR1 RTPEGR0

1R/W

Bit :

Initial value :

R/W :

The realtime output trigger edge select register (RTPEGR) sp ecif ies th e edge sense of the external

or internal tr igger input for the realtime output.

RTPEGR is an 8-b it r ead/write enable register. When reset, RTPEGR i s initialized to H'FC.

Bits 7 to 2



Reserved Bits: Reserved bits. When the bits are read, 1 is always read. The write

operation is invalid.

Bits 1 and 0



Realtime Output Trigger Edge Select (RTPEGR1, RTPEGR0): RTPEGR1 and

RTPEGR0 select the edge sense of the external or internal trigger input for the realtim e output.

Bit 1 Bit 0

RTPEGR1 RTPEGR0

Description

0 Inhibits a trigger input (Initial value) 0

1 Selects the rising edge of a trigger input

0 Selects the falling edge of a trigger input 1

1 Selects both the leading and falling edges of a trigger input

Rev. 1.0, 02/01, page 228 of 1184

10.7.3 Pin Functions

This section describes the port 6 pin functions and their selection methods.

P67/RP7/TMBI: P67/RP7/TMBI is switched as shown below according to the PMRA7 bit in

PMRA, PMR67 bit in PMR6, and PCR67 bit in PCR6.

PMRA7

PMR67

PCR67

Pin Function

Output Value Value When PDR6n

Was Read

0 P67 input pin  P67 pin 0

1 P67 output pin PDR67 PDR67

0 Hi-Z*1,*2

RP7 output pin

PDRS67*2

PDR67

0 P67 pin 1 *

TMBI input pin 

PDR67

Notes: 1. Hi-Z: High impedance

2. When PMR67=1 (realtime output pin), indicates the state after the PCR67 setup value

has been transferred to PCRS67 by a trigger input.

P66/RP6/ADTRG

ADTRGADTRG

ADTRG: P66/RP6/ADTRG is switched as shown below according to the PMR66 bit in

PMR6 and PCR66 bit in PCR6. The ADTRG pin function switching is controlled by the ADTSR.

For details, refer to section 24, A/D converter.

PMR66 PCR66 Pin Function Output Value Value When PDR66 Was Read

0 P66 input pin  P67 pin

1 P66 output pin PDR66 PDR66

0 Hi-Z*1,*2 1

RP6 output pin

PDRS66*2

PDR66

Notes: 1. Hi-Z: High impedance

2. When PMR66=1 (realtime output pin), indicates the state after the PCR66 setup value

has been transferred to PCRS66 by a trigger input.

Rev. 1.0, 02/01, page 229 of 1184

P65/RP5 to P60/RPD: P65/RP5 to P60/RPD are switched below according to the PMRAn bit in

PMRA, PMR6n bit in PMR6, and PCR6n bit in PCR6.

PMR6n PCR6n Pin Function Output Value Value When PDR6n Was Read

0 P6n input pin  P6n pin

1 P6n output pin PDR6n PDR6n

0 RPn output pin Hi-Z*1,*2 1

1 RPn output pin PDRS6n*2

PDR6n

(n = 5 to 0)

Notes: 1. Hi-Z: High impedance

2. When PMR6n=1 (realtime output pin), indicates the state after the PCR6n setup value

has been transferred to PCRS6n by a trigger input.

Rev. 1.0, 02/01, page 230 of 1184

10.7.4 Operation

Port 6 can be used as a realtime ou tput port or general I/O output port by PMR6 . Port 6 functions

as a realtime outpu t port wh en PMR6 = 1 and as a g eneral I /O port when PMR6 = 0. The

operation per po rt 6 function is shown below. (See figure 10.2.)

P6/RP

RTPEGR write

Legend:

PMR6

PCR6

PDR6

PCRS6

PDRS6

RTPSR1

RTPEGR

HSW

RPTRG

: Port mode register 6

: Port control register 6

: Port data register 6

: Port control register slave 6

: Port data register slave 6

: Realtime output trigger select register

: Realtime output trigger edge select register

: Internal trigger signal

: External trigger pin

RTPSR write

RMR6 write

RDR6 write

RCR6 write

RDR6 read

RTPEGR

Selection

circuit

Selection

circuit

Internal data bus

External trigger

RPTRG

Internal trigger

HSW

RTPSR

PMR6

PDR6

PCR6

RDRS6

RCRS6

Figure 10.2 Port 6 Function Block Diagram

Rev. 1.0, 02/01, page 231 of 1184

• Operation of the Realtim e Ou tput Port (PMR6 = 1 )

When PMR6 is 1, it operates as a realtime output port. When a trigger is input, the PDR6 data

is transferre d to PDRS6 and the PCR6 is tr ansferred data to PCRS6, resp ectively. In this case,

when PCRS6 is 1, the PDRS6 data of the corresponding bit is output to the RP pin. When

PCRS6 is 0, the RP pin of the corresponding bit is output to the high-impedance state. In other

words, the pin output state (high or low) or high-impedance state can instantaneously be

switched by a trigger input.

Adversely, when PDR6 is read, the PDR6 values are read regardless of the PCR6 and PCRS6

values.

• Operation of the general I/O port (PMR6 = 0)

When PMR6 is 0, it operates as a general I/O port. When data is written to PDR6, the same

data is also written to PDRS6. Accordingly, because both PDR6 and PDRS6 and both PCR6

and PCRS6 can be handled as one register, respectively, they can be used in the same way as a

normal general I/O port. In other words, if PCR6 is 1, the PDR6 data of the corresponding bit

is output to the P6 pin. If PCR6 is 0, the P6 pin of the corresponding bit becomes an input.

Adversely, assuming that PDR6 is read, the PDR6 values are read when PCR6 is 1 and the pin

values are read when PCR6 is 0.

10.7.5 Pin States

Table 10.19 shows the port 6 pin states in each operation mode.

Table 10.19 Port 6 Pin States

Pins Reset Active Sleep Standby Watch Subactive Subsleep

P67/RP7/TMBI

P66/RP6/ADTRG

P65/RP5

P60/RP0

High-

impedance Operation Holding High-

impedance High-

impedance Operation Holding

Note: If the TMBI and ADTRG input pins are set, the pin level must be set to the high or low level

regardless of the active mode or low power consumption mode. Note that pin level must not

reach an intermediate level.

Rev. 1.0, 02/01, page 232 of 1184

10.8 Port 7

10.8.1 Overview

Port 7 is an 8-bit I/O port. Table 10.20 shows the port 7 configuration.

Port 7 consists of pins that are used both as standard I/O ports (P77 to P70) and HSW timing

generation circuit (programmable pattern generator: PPG) outputs (PPG7 to PPG0). It is switched

by port mode register 7 (PMR7) and port control register 7 (PCR7).

For the programmable generator (PPG), see section 26.4, HSW (Head-switch) Timing Generation

Circuit.

Table 10.20 Port 7 Configuration

Port Function Alternative Function

PPG7 (HSW timing output) P77 (standard I/O port)

RPB (realtime output port)

PPG6 (HSW timing output) P76 (standard I/O port)

RPA (realtime output port)

PPG5 (HSW timing output) P75 (standard I/O port)

RP9 (realtime output port)

PPG4 (HSW timing output) P74 (standard I/O port)

RP8 (realtime output port)

P73 (standard I/O port) PPG3 (HSW timing output)

P72 (standard I/O port) PPG2 (HSW timing output)

P71 (standard I/O port) PPG1 (HSW timing output)

Port 7

P70 (standard I/O port) PPG0 (HSW timing output)

Rev. 1.0, 02/01, page 233 of 1184

10.8.2 Register Configuration

Table 10.21 shows the port 7 register configuration.

Table 10.21 Port 7 Register Configuration

Name Abbrev. R/W Size Initial Value Address*

Port mode register 7 PMR7 R/W Byte H'00 H'FFDE

Port mode register B PMRB R/W Byte H'0F H'FFDA

Port control register 7 PCR7 W Byte H'00 H'FFD7

Port data register 7 PDR7 R/W Byte H'00 H'FFC7

Realtime output trigger

select register 2 RTPSR2 R/W Byte H'0F H'FFE6

Realtime output trigger

edge select registe r RTPEGR R/W Byte H'FC H'FFE4

Port control register slave

7 PCRS7  Byte H'00 

Port data register slave 7 PDRS7  Byte H'00 

Note: * Lower 16 bits of the address.

Rev. 1.0, 02/01, page 234 of 1184

Port Mode Register 7 (PMR7)

R/W

7PMR74 PMR73 PMR72 PMR71 PMR70

R/W

PMR77

R/WR/WR/W

PMR76 PMR75

Bit :

Initial value :

R/W :

Port mode register 7 (PMR7) controls switching of each pin function of port 7. The switching is

specified in a unit of bit.

PMR7 is an 8-b it r ead/write enable register. Wh en reset, PMR7 is initialized to H'00.

Bits 7 to 0



P77/PPG7 to P70/PPG0 Pin Switching (PMR77 to PMR70): PMR77 to PMR70

set whether the P7n/PPGn pin is used as a P7n I/O pin or a PPGn pin for the HSW timing

generation circuit output.

Bit n

PMR7n Description

0 The P7n/PPGn pin functions as a P7n I/O pin (Initial value)

1 The P7n/PPGn pin functions as a PPGn output pin

(n = 7 to 0)

Port Mode Register B (PMRB)

4———PMRB4

———R/W

R/W

R/W —R/W

6—PMRB7 PMRB6 PMRB5

Bit :

Initial value :

R/W :

Port mode register B (PMRB) controls switching of each pin function of port 7. The switching is

specified in a unit of bit.

PMRB is an 8-bit r ead/write enable register. When reset, PMRB is initialized to H'0F.

Rev. 1.0, 02/01, page 235 of 1184

Bits 7 to 4



P77/RP7B to P74/RP8 Pin Switching (PMRB7 to PMRB4): P77/RP7B to

P74/RP8 set whether the P7n/RPm pin is used as a P7n I/O pin or a RPm pin for the realtime

output port. (n= 7 to 4 and m= B, A, 9, or 8)

Bit n

PMRBn Description

0 P7n/RPm pin func tions as a P7n I/O pin (Initial value)

1 P7n/RPm pin func tions as a RPm I/O pin

(n = 7 to 4 and m = B, A, 9, and 8)

Bits 3 to 0



Reserved Bits: Reserved bits. When the bits are read, 1 is always read. The write

operation is invalid.

Port Control Register 7 (PCR7)

7PCR74 PCR73 PCR72 PCR71 PCR70

PCR77

WWW

PCR76 PCR75

Bit :

Initial value :

R/W :

Port control register 7, together with PMRB, enable the general-purpose input/output of port 7 and

controls realtime output in bit units.

For details, refer to section 10.8.4. Operation.

PCR7 is an 8-bit write-only register. When the PCR7 is read, 1 is always read. When reset, PCR7

is initialized to H'00.

Bits 7 to 0



P77 to P70 Pin I/O Switching (PCR77 to PCR70)

PMRB PCR7

Bitn Bitn

PMRBn PCR7n Description

0 P7n/RPm pin functions as a P7n general input pin (Initial Value) 0

1 P7n/RPm pin functions as a P7n general output pin

1 * P7n/RPm pin functions as a RPm realtime output pin

(n = 7 to 4 and m = B, A, 9, and 8)

Note: * Don’t care

Rev. 1.0, 02/01, page 236 of 1184

Port Data Register 7 (PDR7)

R/W

7PDR74 PDR73 PDR72 PDR71 PDR70

R/W

PDR77

R/WR/WR/W

PDR76 PDR75

Bit :

Initial value :

R/W :

Port data register 7 (PDR7) stores the data for the pins P77 to P70 of port 7.

If PCR7 is 1 (output) when PMRB=0, the PDR7 values are directly read when port 7 is read.

Accordingly, the pin states are not affected. When PCR7 is 0 (input), the pin states are read if port

7 is read. When PMRB=1, port 7 pin functio ns as a realtime output pin. For details, ref e r to

section 10.8.4, Operation.

PDR7 is an 8-b it r ead/write enable register. When reset, PDR7 is initialized to H'00.

Realtime Output Trigger Select Register 2 (RTPSR2)

—

R/W

7RTPSR24 ————

R/W

RTPSR27

——R/W

RTPSR26 RTPSR25

Bit :

Initial value :

R/W :

Realtime outpu t tr igger select register (RTPSR2) selects whether to use an external trigger

(RPTRG pin input) or internal trigger (HSW) for the realtime output trigger input by specifying a

unit of bit. For details on internal trigger HSW, refer to section 26.4, HSW (Head-switch) Timing

Generator.

RTPSR2 is an 8 - bit read/write enable reg ister.

When reset, RTPS R2 is initialized to H'0F.

Rev. 1.0, 02/01, page 237 of 1184

Bits 7 to 4



RPB to RP8 Pin Trigger Switching (RTPSR27 to RTPSR24)

Bit7

RTPSR2n Description

0 Selects external trigger (RPTRG pin input) for trigger input (Initial value)

1 Selects inter nal trig ger (HSW) for trigger input

(n = 7 to 4)

Realtime Output Trigger Edge Selection Register (RTPEGR)

R/W

7——————

——————

RTPEGR1 RTPEGR0

1R/W

Bit :

Initial value :

R/W :

The realtime ou tput trigger edge selection register (RTPEGR) specifies the sensed edge(s) of

external or intern al tr igger input fo r realtime o utput.

RTPEGR is an 8-b it readable/writable register. In a reset, RTPEGR is initialized to H'FC.

Bits 7 to 2—Reserved: These bits are always read as 1 and cannot be modified.

Bits 1 and 0—Realtime Output Trigger Edge Select (RTPEGR1, RTPEGR0): These bits

select the sensed edge( s) of external or internal trigger input for realtim e output.

Bit 1 Bit 0

RTPEGR1 RTPEGR0 Description

0 Disab les trigger inpu t (Initi al val ue) 0

1 Selects trigger input rising edge

0 Selects trigger input falling edge 1

1 Selects trigger input rising and falling edges

Rev. 1.0, 02/01, page 238 of 1184

10.8.3 Pin Functions

This section describes the port 7 pin functions and their selection methods.

P77/PPG7/RPB to P74/PPG4/RP8: P77/PPG7/RPB to P74/PPG4/RP8 are switched as shown

below according to the PMRBn bit in PMRB and the PCR7n bit in PCR7.

PMRBn

PMR7n

PCR7n

Pin Function

Output Value Value Returned when

PDR7n is Read

0 P7n input pin  P7n pin 0 0

1 P7n output pin PDR7n PDR7n

0 P7n pin 0 1

PPGn output pin PPGn

PDR7n

0 Hi-Z*1 1 *

RPm output pin

PDRS7n*1

PDR7n

(n = 7 to 4, m = B, A, 9, 8)

Notes: Hi-Z: High impedance

* Don’t care

1. When PMRBn = 1 (realtime output pin), the state indicated is that after the PCR7n set

value has been transferred to PCRS7n by trigger input.

P73/PPG to P70/PPG0: P73/PPG to P70/PPG0 are switched as shown below according to the

PMR7n bit in PMR7 and the PCR7n bit in PCR7.

PMR7n

PCR7n

Pin Function

Output Value Value Returned when PDR7n

is Read

0 P7n input pin  P7n pin

1 P7n output pin PDR7n PDR7n

0 P7n pin 1

PPGn output pin PPGn

PDR7n

(n = 3 to 0)

Rev. 1.0, 02/01, page 239 of 1184

10.8.4 Operation

Port 7 can be used by the PMRB as a realtime o utput port or an I /O port.

Port 7 function s as a realtim e outp ut port when PMRB=1 and functions as an I/O port when

PMRB=0. Figure 10.3 show the block diagram of port 7.

P7/RP

RTPEGR write

RTPSR2 write

PMRA write

PDR7 write

PCR7 write

PDR7 read

RTPEGR

Select

External trigger

RPTRG

Internal

trigger HSW

RTPSR2

PMRB: Port mode register B

PCR7: Port control register 7

PDR7: Port data register 7

PCRS7: Port control register slave 7

PDRS7: Port data register slave 7

Legend: RTPSR2: Realtime output trigger select register

RTPEGR: Realtime output trigger edge select register

HSW: Internal trigger signal

RPTRG: External trigger pin

Internal data bus

PMRB

PDR7

PCR7

PDRS7

PCRS7

Figure 10.3 Block Diagram of Port 7

Rev. 1.0, 02/01, page 240 of 1184

Port 7 functions as follows:

1. Realtime ou tput port function (PMRB=1)

Port function as a realtime output port when PMRB is 1. After a trigger input, the PDR7 data

is transferr ed to PDRS7 and PCR7 da ta is tr ansferred to PCRS7. In th is case, when PCRS7 is

1, the PDRS7 data of the corresponding bit is output from the RP pin. When PCRS7 is 0, the

RP pin of the corr esponding bit enters high-impedance state. In other words, the realtime

output port function can instantaneously switch the pin output state (High or Low) or high-

impedance by a trigger input.

2. I/O port function (PMRB=0)

Port 7 functions as an I/O port when PMRB is 0. After data is written to PDR7, the same data

is written to PDRS7. Af ter data is written to PCR7 , the same da ta is wr itten to PCRS7. Since

PDR and PDRS7, and PCR7 and PCRS7 can be used as one register, the registers can be used

as the I/O ports. In other words, if PCR7 is 1, the PDR7 data of the corresponding bit is output

from the P7 pin. If PCR is 0, the P7 pin of the corresponding bit is an input pin. If PD7 is read,

the PDR7 value is read when PCR7 is 1 and the pin value is read when PCR7 is 0.

10.8.5 Pin States

Table 10.22 shows the port 7 pin states in each operation mode.

Table 10.22 Port 6 Pin States

Pins Reset Active Sleep Standby Watch Subactive Subsleep

P77/PPG7/RPB

P74/PPG4/RP8

P73/PPG3

P70/PPG0

High-

impedance Operation Holding High-

impedance High-

impedance Operation Holding

Rev. 1.0, 02/01, page 241 of 1184

10.9 Port 8

10.9.1 Overview

Port 8 is an 8-bit I/O port. Table 10.23 shows the port 8 configuration.

Port 8 consists of pins that are used both as standard-current I/O ports (P87 to P80) and an external

CTL signal input (EXCTL), a pre-amplifier output result signal input (COMP), color signal

outputs (R, G, and B), a pre-amplifier output selection signal output (H.Amp SW), a control signal

output for processing color signal (C.Rotary), a DPG signal input (DPG), a capstan external sync

signal input (EXCAP), an OSD character display position output (YB0), an OSD character data

output (YC0), and an external reference signal input (EXTTRG). It is switched by port mode

Table 10.23 Port 8 Configuration

Port Function Alternative Function

P87 (standard I/O port) DPG signal input

P86 (standard I/O port) External referenc e signal input

Pre-amplifier output result signal input P85 (standard I/O port)

Color signal output

Pre-amplifier output selection signal output P84 (standard I/O port)

Color signal output

Control signal output for processing color si gnal P83 (standard I/O port)

Color signal output

P82 (standard I/O port) External CTL signal input

Capstan extern al syn c sig nal i nput P81 (standard I/O port)

OSD character display position output

Port 8

P80 (standard I/O port) OSD character data output

Rev. 1.0, 02/01, page 242 of 1184

10.9.2 Register Configuration

Table 10.24 shows the port 8 register configuration.

Table 10.24 Port 8 Register Configuration

Name Abbrev. R/W Size Initial Value Address*

Port mode register 8 PMR8 R/W Byte H'00 H'FFDF

Port mode register C PMRC R/W Byte H'C5 H'FFE0

Port control register 8 PCR8 W Byte H'00 H'FFD8

Port data register 8 PDR8 R/W Byte H'00 H'FFC8

Note: * Lower 16 bits of the address.

Rev. 1.0, 02/01, page 243 of 1184

Port Mode Register 8 (PMR8)

R/W

7PMR84PMR85PMR86PMR87

R/WR/WR/WR/W

PMR83 PMR82 PMR81 PMR80

0R/WR/W

Bit :

Initial value :

R/W :

Port mode register 8 (PMR8) controls switching of each pin function of port 8. The switching is

specified in a unit of bit.

PMR8 is an 8-b it r ead/write enable register. Wh en reset, PMR8 is initialized to H'F0.

If the EXCTL, COMP, DPG and EXTTRG input pins are set, the pin level need always be set to

the high or low level regardless of the active mode and low power consumption mode. Note that

the pin level must not reach an intermediate level.

Bit 7



P87/DPG Pin Switching (PMR87): PMR87 sets whether the P87/DPG pin is used as a

P87 I/O pin or a DPG signal input pin.

Bit 7

PMR87 Description

0 P87/DPG pin functions as a P87 I/O pin

(Drum control signals are input as an ov erlapped signal) (Initial value)

1 P87/DPG pin functions as a DPG input pin

(Drum control signals are input as separate signals)

Bit 6



P86/EXTTRG Pin Switching (PMR86): PMR86 sets whether the P86/EXTTRG pin is

used as a P86 I/O pin or an external trigger signal input pin.

Bit 6

PMR86 Description

0 P86/EXTTRG pin functions as a P86 I/O pin (Initial value)

1 P86/EXTTRG pin functions as a EXTTRG input pin

Bit 5



P85/COMP Pin Switching (PMR85): PMR85 sets whether the P85/COMP pin is used as

a P85 I/O pin or a COMP input pin of the preamplifier output result signal.

Bit 5

PMR85 Description

0 P85/COMP pin functions as a P85 I/O pin (Initial value)

1 P85/COMP pin functions as a COMP input pin

Rev. 1.0, 02/01, page 244 of 1184

Bit 4



P84/H. Amp SW Pin Switching (PMR84): PMR84 sets whether the P84/H.Amp SW pin

is used as a P84 I/O pin or H.Amp SW pin of the preamplifier output select signal output.

Bit 4

PMR84 Description

0 P84/H.Amp SW pin functions as a P84 I/O pin (Initial value)

1 P84/H.Amp SW pin functions as a H.Amp SW output pin

Bit 3



P83/C. Rotary Pin Switching (PMR83): PMR83 sets whether the P83/C. Rotary pin is

used as a P83 I/O pin or a C.Rotary pin of a control signal output for processing color signal.

Bit 3

PMR83 Description

0 P83/C.Rotary pin functions as a P83 I/O pin (Initial value)

1 P83/C.Rotary pin functions as a C.Rotary output pin

Bit 2



P82/EXCTL Pin Switching (PMR82): PMR82 sets whether the P82/EXCTL pin

functions as a P82 I/O pin or a EXCTL input pin of external CTL signal input.

Bit 2

PMR82 Description

0 P82/EXCTL pin functions as a P82 I/O pin (Initial value)

1 P82/EXCTL pin functions as a EXCTL input pin

Bit 1



P81/EXCAP Pin Switching (PMR8 1 ): PMR81 sets whether the P81/EXCAP pin

functions as a P81 I/O pin or a EXCAP pin of capstan external synchronous signal input.

Bit 1

PMR81 Description

0 P81/EXCAP pin functions as a P81 I/O pin (Initial value)

1 P81/EXCAP pin functions as a EXCAP input pin

Bit 0



P80/YCO Pin Switching (PMR80): PMR80 sets whether the P80/YCO pin functions as a

P80 I/O pin or a YCO pin of OSD character data outpu t.

Bit 0

PMR80 Description

0 P80/YCO pin functions as a P80 I/O pin (Initial value)

1 P80/YCO pin functions as a YCO output pin

Rev. 1.0, 02/01, page 245 of 1184

Port Mode Register C (PMRC)

R/W

—

R/W

7PMRC4 PMRC3 — PMRC1 —

—

—R/W—

— PMRC5

Bit :

Initial value :

R/W :

Port mode register C (PMRC) controls switching of each pin function of port 8. The switching is

specified in a unit of a bit.

PMRC is an 8-bit r ead/write enable register. Wh en reset, PMRC is initialized to H'C5.

Bits 7, 6, 2, and 0



Reserved Bits: Reserved bits. When the bits are read, 1 is always read. The

write operation is invalid.

Bit 5



P85/B Pin Switching (PMRC5): PMRC5 sets whether to use the P85/B pin as a P85 I/O

pin or a B pin of the OSD color signal output.

Bit 5

PMRC5 Description

0 P85/B pin functions as a P85 pin (Initial value)

1 P85/B pin functions as a B output pin

Bit 4



P84/G Pin Switching (PMRC4): PMRC4 sets whether to use the P84/G pin as a P84 I/O

pin or a G pin of the OSD color signal output.

Bit 4

PMRC4 Description

0 P84/G pin functions as a P84 I/O pin (Initial value)

1 P84/G pin functions as a G output pin

Bit 3



P83/R Pin Switching (PMRC3): PMRC3 sets whether to use the P83/R pin as a P83 I/O

pin or a R pin of the OSD color signal output.

Bit 3

PMRC3 Description

0 P83/R pin functions as a P83 I/O pin (Initial value)

1 P83/R pin functions as a R output pin

Rev. 1.0, 02/01, page 246 of 1184

Bit 1



P81/YBO Pin Switching (PMRC1): PMRC1 sets whether to use the P81/YBO pin as a

P81 I/O pin or a YBO pin of the OSD character disp lay position output.

Bit7

PMR1 Description

0 P81/YBO pin functions as a P81 I/O pin (Initial value)

1 P81/YBO pin functions as a YBO output pin

Port Control Register 8 (PCR8)

7PCR84 PCR83 PCR82 PCR81 PCR80

PCR87

WWW

PCR86 PCR85

Bit :

Initial value :

R/W :

Port control register 8 (PCR8) controls I/O of pins P87 to P80 of port 8. The I/O is specified in a

unit of bit.

When PCR8 is set to 1, the corresponding P87 to P80 pins become output pins, and when it is set

to 0, they become input pins.

When the pins are set as general I/O pins, the settings of PCR8 and PDR8 become valid.

PCR8 is an 8 - bit write-only register. Wh en PCR8 is read, 1 is r ead. When reset PCR8 is initialized

to H'00.

Bits 7 to 0



P87 to P80 Pin I/O Switching

Bit n

PCR8n Description

0 P8n pin functions as an input pin (Initial value)

1 P8n pin functions as an output pin

(n = 7 to 0)

Rev. 1.0, 02/01, page 247 of 1184

Port Data Register 8 (PDR8)

R/W

7PDR84 PDR83 PDR82 PDR81 PDR80

R/W

PDR87

R/WR/WR/W

PDR86 PDR85

Bit :

Initial value :

R/W :

Port data register 8 (PDR8) stores the data of pins P87 to P80 port 8. When PCR is 1 (output), the

pin states are read is port 8 is read. Accordingly, the pin states are not affected. When PCR8 is 0

(input), the pin states are read it port 8 is read.

PDR8 is an 8-b it r ead/write enable register. When reset, PDR8 is initialized to H'00.

Rev. 1.0, 02/01, page 248 of 1184

10.9.3 Pin Functio ns

This section describes the port 8 pin functions and their selection methods.

P87/DPG: P87/DPG is switched as shown below according to the PMR87 bit in PMR8 and

PCR87 bit in PCR8.

PMR87 PCR87 Pin Function

0 P87 input pin

1 P87 output pin

1 * DPG input pin

Note: * Don’t care

P86/EXTTRG: P86/EXTTRG is switched as shown below according to the PMR86 bit in PMR8

and PCR86 bit in PCR8.

PMR86 PCR86 Pin Function

0 P86 input pin

1 P86 output pin

1 * EXTTRG input pin

Note: * Don’t care

P85/COMP/B: P85/COMP/B is switched as shown below according to the PMR85 bit in PMR8,

PMRC5 bit in PMRC, and PCR85 bit in PCR8.

PMRC5 PMR85 PCR85 Pin Function

0 P85 input pin

0 0

1 P85 output pin

* 1 * COMP input pin

1 0 * B output pin

Note: * Don’t care

Rev. 1.0, 02/01, page 249 of 1184

P84/H.Amp SW/G: P84/H.Amp SW/G is switched as shown below according to the PMR84 bit

in PMR, PMRC4 bit in PMRC, and PCR84 bit in PCR8.

PMRC4 PMR84 PCR84 Pin Function

0 P84 input pin

0 0

1 P84 output pin

* 1 * H.Amp SW output pin

1 0 * G output pin

Note: * Don’t care

P83/C.Rotary/R: P83/C.Rotary/R is switched as shown below according to the PMR83bit in

PMR8, PMRC3 bit in PMRC, and PCR83 bit in PCR8.

PMRC3 PMR83 PCR83 Pin Function

0 P83 input pin

0 0

1 P83 output pin

* 1 * C.Rotary output pin

1 0 * R output pin

Note: * Don’t care

P82/EXCTL: P82/EXCTL is switched as shown below according to the PMR82 bit in PMR8 and

PCR82 bit in PCR8.

PMR82 PCR82 Pin Function

0 P82 input pin

1 P82 output pin

1 * EXCTL input pin

Note: * Don’t care

P81/EXCAP/YBO: P81/EXCAP/YBO is switched as shown below according to the PMR81 bit

in PMR8, PMRC1 bit in PMRC, and PCR81 bit in PCR8 .

PMRC1 PMR81 PCR81 Pin Function

0 P81 input pin

0 0

1 P81 output pin

* 1 * EXCAP output pin

1 0 * YBO output pin

Note: * Don’t care

Rev. 1.0, 02/01, page 250 of 1184

P80/YCO: P80/YCO is switched as shown below according to the PMR80 bit in PMR8 and

PCR80 bit in PCR

PMR80 PCR80 Pin Function

0 P80 input pin

1 P80 output pin

1 * YCO output pin

Note: * Don’t care

10.9.4 Pin States

Table 10.25 shows the port 8 pin states in each operation mode.

Table 10.25 Port 8 Pin States

Pins Reset Active Sleep Standby Watch Subactive Subsleep

P87/DPG

P86/EXTTRG

P85/COMP/B

P84/H.Amp SW/G

P83/C.Rotary/R

P82/EXCTL

P81/EXCAP/YB0

P80/YCO

High-

impedance Operation Holding High-

impedance High-

impedance Operation Holding

Notes: 1. If the EXCTL, COMP, DPG, and EXTTRG input pins are set, the pin level need always

be set to the high or low level regardless of the active mode and low power

consumption mode. Note that the pin level must not reach an intermediate level.

2. As the DPG always functions, a high or low pin level must be input to the multiplexed

pins regardless of whether active mode or power-down mode is in effect.

Rev. 1.0, 02/01, page 251 of 1184

Section 11 Timer A

11.1 Overview

Timer A is an 8-bit interval timer. It can be used as a clock timer when connected to a 32.768 kHz

crystal oscillator.

11.1.1 Features

Features of timer A are as follows:

• Choices of eight different types of internal clocks (φ/16384, φ/8192, φ/4096, φ/1024, φ/512,

φ/256, φ/64 and φ/16) are available for your selection.

• Four different overflowing cycles (1s, 0.5s, 0.25s and 0.03125s) are selectable as a clock timer.

(When using a 32.768 kHz crystal oscillator.)

• Requests for interrupt will be outp ut when the counter overflows.

Rev. 1.0, 02/01, page 252 of 1184

11.1.2 Block Diagram

Figure 11.1 shows a block diagram of timer A.

Legend:

TMA

32 kHz

Crystal oscillator

Overflowing of

the interval

timer

System

clock

φw

φw/128

φ/16384, φ/8192,

φ/4096, φ/1024,

φ/512, φ/256,

φ/64, φ/16

TCA

: Timer mode register A

: Timer counter A

Note: * Selectable only when the prescaler W output (φw/128) is

working as the input clock to the TCA.

Prescaler S

(PSS) Interrupting

circuit

Prescaler unit

Prescaler W

(PSW)

TCA

1/4 TMA

Interrupt

requests

Internal data bus

÷8*

÷64*

÷128*

÷256*

Figure 11.1 Block Diagram of Timer A

11.1.3 Register Configuration

Table 11.1 shows the register configuration of timer A.

Table 11.1 Register Co nf iguration

Name Abbrev. R/W Size Initial Value Address*

Timer mode register A TMA R/W Byte H'30 H'FFBA

Timer counter A TCA R Byte H'00 H'FFBB

Note: * Lower 16 bits of the address.

Rev. 1.0, 02/01, page 253 of 1184

11.2 Register Descriptions

11.2.1 Timer Mode Register A (TMA)

R/W

5——

——

R/WR/WR/W

TMAIE

R/(W)*

TMAOV TMA3 TMA2 TMA1 TMA0

Note: * Only 0 can be written to clear the flag.

Bit :

Initial value :

R/W :

The timer mode register A (TMA) works to control the interrupts of timer A and to select the input

clock.

TMA is an 8-bit read/write register. When reset, the TMA will be initialized to H'30.

Bit 7



Timer A Overflow Flag (TMAOV): This is a status flag indicating the fact that the TCA

is overflowing (H'FF → H'00).

Bit 7

TMAOV Description

0 [Clearing conditions] (Initial value)

When 0 is written to the TMAOV flag after reading the TMAOV flag under the status

where TMAOV = 1

1 [Setting conditions]

When the TCA overflows

Bit 6



Enabling Interrupt of the Timer A (TMAIE): This bit works to permit/prohibit

occurrence of interrupt of the Timer A (TMAI) when the TCA overflows and when the TMAOV

of the TMA is set to 1 .

Bit 6

TMAIE Description

0 Prohibits occurrence of interrupt of the Timer A (TMAI) (Initial value)

1 Permits occurrence of interrupt of the Timer A (TMAI)

Bits 5 and 4



Reserved: These bits cannot be modified and are always read as 1.

Rev. 1.0, 02/01, page 254 of 1184

Bit 3



Selection of the Clock Source and Prescaler (TMA3): This bit works to select the PSS

or PSW as the clock source for the Timer A.

Bit 3

TMA3 Description

0 Selects the PSS as the clock source for the Ti mer A (Initial value)

1 Selects the PSW as the clock source for the Timer A

Bits 2 to 0



Clock Selection ( TMA2 t o TMA0): These bits work to select the clo ck to input to

the TCA. In combination with the TMA3 bit, the choices are as follows:

Bit 3 Bit 2 Bit 1 Bit 0

TMA3 TMA2 TMA1 TMA0 Prescaler Division Ratio (Interval Timer)

or Overflow Cycle (Time Base) Operation

Mode

0 PSS, φ/16384 (Initial value) 0

1 PSS, φ/8192

0 PSS, φ/4096

1 PSS, φ/1024

0 PSS, φ/512 0

1 PSS, φ/256

0 PSS, φ/64

1 PSS, φ/16

Interval

timer mode

0 1s 0

1 0.5s

0 0.25s

1 0.03125s

0 0

Works to clear the PSW and TCA to H'00

Clock time

base mode

Note: φ = f osc

Rev. 1.0, 02/01, page 255 of 1184

11.2.2 Timer Counter A (TCA)

4567

TCA3

TCA4

TCA5

TCA6

TCA7 TCA2 TCA1 TCA0

Bit :

Initial value :

R/W :

The timer counter A (TCA) is an 8-bit up-counter that counts up on inputs from the internal clock.

The inputting clock can be selected by TMA3 to TMA0 bits of th e TMA

When the TCA overflows, th e TMAOV bit of th e TMA is set to 1.

The TCA can be cleared by setting the TMA3 and TMA2 bits of the TMA to 11.

The TCA is always readable. When reset, the TCA will be initialized into H'00.

11.2.3 Module Stop Control Register (MSTPCR)

MSTP15

R/W

MSTPCRH

MSTP14

R/W

MSTP13

R/W

MSTP12

R/W

MSTP11

R/W

MSTP10

R/W

MSTP9

R/W

MSTP8

R/W

MSTP7

R/W

MSTP6

R/W

MSTP5

R/W

MSTP4

R/W

MSTP3

R/W

MSTP2

R/W

MSTP1

R/W

MSTP0

R/W

MSTPCRL

Initial value :

R/W :

Bit :

The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode.

When the MSTP15 bit is set to 1, th e Timer A stops its operation at th e ending point of the bus

cycle to shift to the module stop mode. For more information, see section 4.5, Module Stop

Mode. When reset, the MSTPCR will be initialized into H'FFFF.

Bit 7



Module Stop ( MSTP1 5): This bit works to designate the module stop mode for the Timer

MSTPCRH

Bit 7

MSTP15 Description

0 Cancels the module stop mode of the Timer A

1 Sets the module stop mode of the Timer A (Initial value)

Rev. 1.0, 02/01, page 256 of 1184

11.3 Operation

Timer A is an 8-bit interval timer. It can be used as a clock timer when connected to a 32.768 kHz

crystal oscillator.

11.3.1 Operation as the Interval Timer

When the TMA3 b it of th e TMA is cleared to 0, timer A works as an 8-bit interval timer.

After reset, the TCA is cleared to H'00 and as the TMA3 bit is cleared to 0, the Timer A continues

counting up as the in terval counter without interrupts right after resetting.

As the operation clock for timer A, selection can be made from eight different types of internal

clocks being output from the PSS by the TMA2 to T M A0 bits of the TMA.

When the clock signal is input after the reading of the TCA reaches H'FF, timer A overflows and

the TMAOV bit of the TMA will be set to 1 . An interrupt occurs when the TMAIE bit of the

TMA is 1.

When overflowing occurs, the reading of the TCA returns to H'00 before resuming counting up.

Consequently, it works as the interval timer to produce ov erflow outputs periodically at every 256

input clocks.

11.3.2 Operation as Clock Timer

When the TMA3 b it of th e TMA is set to 1, timer A work s as a time base f or the clock.

As the overflow cycles for timer A, selection can be made from four different types by counting

the clock being ou tput from the PSW by the TMA1 bit and TMA0 bit of the TMA.

11.3.3 Initializing the Counts

When the TMA3 an d TMA2 bits are set to 11, the PSW and TCA will be cleared to H'00 to come

to a stop.

At this state, writing 1 0 to the TMA3 bit and TMA2 bit m akes timer A start countin g from H'00 in

the time base mode for clocks.

After clearing the PSW and TCA using the TMA3 and TMA2 bits, writing 00 or 01 to the TMA3

bit and TMA2 bit to m ake timer A start counting from H'00 in the interval timer mod e . However,

the period to the first count is not constant, since the PSS is not cleared.

Rev. 1.0, 02/01, page 257 of 1184

Section 12 Timer B

12.1 Overview

Timer B is an 8-bit up-counter. Timer B is equipped with two different types of functions namely,

the interval function and the auto reloading function.

12.1.1 Features

• Seven different types of internal clocks (φ/16384, φ/4096, φ/1024, φ/512, φ/128, φ/32 and φ/8)

or an of external clock can be selected.

• When the counter overflows, a interrupt request will be issued.

12.1.2 Block Diagram

Figure 12.1 shows a block diagram of timer B.

Legend:

TMB

φ/16384

φ/4096

φ/1024

φ/512

φ/128

φ/32

φ/8

TMBI

TCB : Timer mode register B

: Timer counter B

TLB

TMBI : Timer re-loading register B

: Event input terminal of the Timer B

Re-loading

Clock sources

Overflowing

Timer B

Interrupt requests

Internal data bus

TCB

TMB

TLB

Interrupting

circuit

Figure 12.1 Block Diagram of Timer B

Rev. 1.0, 02/01, page 258 of 1184

12.1.3 Pin Configuration

Table 12.1 shows the pin configuration of timer B.

Table 12. 1 Pin Configuration

Name Abbrev. I/O Function

Event inputs to timer B TMBI Input Event input pin for inputs to the TCB

12.1.4 Register Configuration

Table 12.2 shows the register configuration of timer B.

The TCB and TLB are b eing allocated to the same address. Reading or writing determin es the

accessing register.

Table 12.2 Register Co nf iguration

Name Abbrev. R/W Size Initial Value Address*

Timer mode register B TMB R/W Byte H'18 H'D110

Timer counter B TCB R Byte H'00 H'D111

Timer load register B TLB W Byte H'00 H'D111

Port mode register A PMRA R/W Byte H'3F H'FFD9

Note: * Lower 16 bits of the address.

Rev. 1.0, 02/01, page 259 of 1184

12.2 Register Descriptions

12.2.1 Timer Mode Register B (TMB)

R/W

——

R/WR/W

TMBIE

R/(W)*

TMBIF

R/W

TMB17 TMB12 TMB11 TMB10

Note: * Only 0 can be written to clear the flag.

Bit :

Initial value :

R/W :

The TMB is an 8-b it r e ad/write r egister which works to co ntrol the interrupts, to select th e auto

reloading function and to select the input clock.

When reset, the TMB is initialized to H'1 8.

Bit 7



Selecting the Auto Reloading Function (TMB17): This bit works to select the auto

reloading function of the Timer B.

Bit 7

TMB17 Description

0 Selects the interval function (Initial value)

1 Selects the auto reloading function

Bit 6



Interrupt Requesting Flag for the Timer B (TMBIF): This is an interrupt requesting

flag for the Timer B. It indicates the fact that the TCB is overflowing.

Bit 6

TMBIF Description

0 [Clearing conditions] (Initial value)

When 0 is written after reading 1

1 [Setting conditions]

When the TCB overflows

Rev. 1.0, 02/01, page 260 of 1184

Bit 5



Enabling Interrupt of the Timer B (TMBIE): This bit works to permit/prohibit

occurrence of interrupt of timer B when the TCB overflows and when the TMBIF is set to 1.

Bit 5

TMBIE Description

0 Prohibits interrupt of timer B (Initial value)

1 Permits interrupt of timer B

Bits 4 and 3



Reserved: These bits cannot be modified and are always read as 1.

Bits 2 to 0



Clock Selection (TMB12 to TMB10): These bits work to select the clock to input to

the TCB. Selection of th e rising edge or the falling edge is work ab le with the external event

inputs.

Bit 2 Bit 1 Bit 0

TMB12 TMB11 TMB10 Descriptions

0 0 0 Internal clock: Counts at φ/16384 (Initial value)

0 0 1 Internal clock: Counts at φ/4096

0 1 0 Internal clock: Counts at φ/1024

0 1 1 Internal clock: Counts at φ/512

1 0 0 Internal clock: Counts at φ/128

1 0 1 Internal clock: Counts at φ/32

1 1 0 Internal clock: Counts at φ/8

1 1 1 Counts at the rising edge and the falling edge of external

event inputs (TMBI)*

Note: * The edge selection for the external event inputs is made by setting the PMRA6 of the port

mode register A (PMRA). See section 12.2.4, Port Mode Register A (PMRA).

Rev. 1.0, 02/01, page 261 of 1184

12.2.2 Timer Counter B (TCB)

345

TCB15

TCB14

TCB13

TCB16

TCB17 TCB12 TCB11 TCB10

Bit :

Initial value :

R/W :

The TCB is an 8-bit readable register which works to count up by the internal clock inputs and

external event inputs. The input clock can be selected by the TMB12 to TMB10 of the TMB.

When the TCB overflows (H'FF → H'00 or H'FF → TLB setting), a interrupt request of the Timer

B will be issued.

When reset, the TCB is initialized to H'00.

12.2.3 Timer Load Register B (TLB)

345

TLB15

TLB14

TLB13

TLB16

TLB17 TLB12 TLB11 TLB10

Bit :

Initial value :

R/W :

The TLB is an 8-b it wr ite only reg ister which works to set the re loading value of the TCB.

When the reloading value is set to the TLB, th e value will be simultane ously loaded to th e TCB

and the TCB starts counting up from the set value. Also, during an auto reload ing operation, when

the TCB overf lo ws, the value of the TLB will be loaded to the TCB. Consequently, the

overflowing cycle can be set within the range of 1 to 256 input clocks.

When reset, the TLB is in itialized to H'00.

Rev. 1.0, 02/01, page 262 of 1184

12.2.4 Port Mode Register A (PMRA)

—

567

——PMRA6PMRA7

—

——R/WR/W

—

——

1100

Bit :

Initial value :

R/W :

The port mode register A (PMRA) works to changeover the pin functions of the port 6 and to

designate the edge sense of the event inputs of timer B (TMBI).

The PMRA is an 8-b it r ead /write reg ister . When reset, the PMRA will be initialized to H'3F.

See section 10.7, Port 6 for other information than bit 6.

Bit 6



Selecting the Edge s of the Ev ent Inputs to the Timer B (PMRA6) : This bit works to

select the input edge sense of the TMBI pins.

Bit 6

PMRA6 Description

0 Detects the falling edge of the event inputs to the Timer B (Initial value)

1 Detects the rising edge of the event inputs to the Timer B

Rev. 1.0, 02/01, page 263 of 1184

12.2.5 Module Stop Control Register (MSTPCR)

MSTP15

R/W

MSTPCRH

MSTP14

R/W

MSTP13

R/W

MSTP12

R/W

MSTP11

R/W

MSTP10

R/W

MSTP9

R/W

MSTP8

R/W

MSTP7

R/W

MSTP6

R/W

MSTP5

R/W

MSTP4

R/W

MSTP3

R/W

MSTP2

R/W

MSTP1

R/W

MSTP0

R/W

MSTPCRL

Initial value :

R/W :

Bit :

The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode.

When the MSTP14 bit is set to 1, the Timer B stops its operation at the ending point of the bu s

cycle to shift to the module stop mode. For more information, see section 4.5, Module stop mode.

When reset, the MSTPCR is initialized to H'FFFF.

Bit 6



Module Stop ( MSTP1 4): This bit works to designate the module stop mode for the Timer

MSTPCRH

Bit 6

MSTP14 Description

0 Cancels the module stop mode of the Timer B

1 Sets the module stop mode of the Timer B (Initial value)

Rev. 1.0, 02/01, page 264 of 1184

12.3 Operation

12.3.1 Operation as the Interval Timer

When the TMB17 bit of the TMB is set to 0, timer B works as an 8-bit interval timer.

When reset, since the TCB is cleared to H'00 and as the TMB17 bit is cleared to 0, timer B

continues counting up as the interval timer without interrupts right after resetting.

As the clock source for timer B, selection can be made from seven different types of internal

clocks being output from the prescaler unit by th e TMB12 to TMB10 bits of the TMB or an

external clock through the TMBI input pin can be chosen instead.

When the clock signal is input after the reading of the TCB reaches H'FF, timer B overflows and

the TMBIF bit of the TMB will be set to 1. At th is time, when the TMBIE bit of the TMB is 1,

interrupt occurs.

When overflowing occurs, the reading of the TCB returns to H'00 before resuming counting up.

When a value is set to the TLB while the interval timer is in oper ation, the value which has been

set to the TLB will be loaded to the TCB simultaneously.

12.3.2 Operation as the Auto Reload Timer

When the TMB17 of the TMB is set to 1, the Tim er B works as an 8-bit auto reload timer.

When a reload value is set in the TLB, the value is loaded onto the TCB at the sam e tim e, and the

TCB starts counting up from the value.

When the clock signal is input after the reading of the TCB reaches H'FF, timer B overflows and

the TLB value is loaded onto the TCB, then the TCB co n tinues counting up fro m the loaded value.

Accordingly, overflow interval can be set within the range of 1 to 256 clocks depending on the

TLB value.

Clock source and interrupts in the auto reload operation are th e same as those in the interval

operation . When the TLB value is re-set while the auto r e load timer is in o peration, the value

which has been set to the TLB will be loaded onto the TCB simultaneously.

12.3.3 Event Counter

Timer B works as an event counter using the TMBI pin as th e event input pin. When the TMB12

to TMB10 are set to 111, the external event will be selected as the clock source and the TCB

counts up at the leading edge or the trailing edge of the TMBI pin inputs.

Rev. 1.0, 02/01, page 265 of 1184

Section 13 Timer J

13.1 Overview

Timer J consists of twin counters. It carries different operation modes such as reloading and event

counting.

13.1.1 Features

Timer J consists of an 8-bit reloading timer and an 8 -bit/1 6-bit selectable reloading timer . It has

various functions as listed below. The two timers can be used separately, or they can be connected

together to oper a te as a sin gle timer.

• Reloading timers

• Event counters

• Remote-controlled transmissio ns

• Takeup/Supply reel pulse division

13.1.2 Block Diagram

Figure 13.1 is a block diagram of timer J. Timer J consists of two reload timers namely, TMJ-1

and TMJ-2.

Rev. 1.0, 02/01, page 266 of 1184

Legend:

TCJ

Note: * At the Low level under the timer mode.

TLJ

: Timer counter J

: Timer load register J

TCK

TLK

: Timer counter K

: Timer load register K

TMO

REMOout

: TMJ-1 timer output

: TMJ-2 toggle output

(Remote controller

transmission data)

BUZZ

Reloading register

(Burst/space

width register

PS22, 21,20

EXN

: Buzzer output

TGL : TMJ-2 toggle flag

PS22, 21,20

: TMJ-2 input clock selection

: Starting the remote controlled operation

PS11,10 : TMJ-1 input clock selection

8/16

T/R

EXN

: 8-bit/16-bit operation changeover

: Timer output/Remote controller output changeover

: Expansion function switching

Internal data bus

Edge

detection

Toggle

T/R

Down-counter

(8/16-bit)

BUZZ

Output

Control

Monitor

Output

Control

Toggle

Reloading

8/16

PS11,10

Down-

counter (8-bit)

Under

flow Under-

flow

TCJ

TMJ-1 TMJ-2 TCK

PB/REC-CTL

DVCTL

TCA7

φ/4096

φ/8192

TGL

REMOout

TMO

BUZZ

Clock sources

IRQ2

φ/64

φ/128

φ/1024

φ/2048

φ/16384

Clock sources

IRQ1

φ/4

φ/256

φ/512

Synchronization

TLJ

Reloading

TLK

TMJ-1

Interrupting circuit Interrupt request

by the TMJ1I

Interrupt request

by the TMJ2I

TMJ-2

Interrupting circuit

Figure 13.1 Block Diagram of timer J

Rev. 1.0, 02/01, page 267 of 1184

13.1.3 Pin Configuration

Table 13.1 shows the pin configuration of timer J.

Table 13. 1 Pin Configuration

Name Abbrev. I/O Function

Event input pin IRQ1 Input Event inputs to the TMJ-1

Event input pin IRQ2 Input Event inputs to the TMJ-2

13.1.4 Register Configuration

Table 13.2 shows the register configuration of timer J.

The TCJ and TLJ or the TCK and TLK are being allocated to the same address respectively.

Reading or writing determines the accessing register.

Table 13.2 Register Co nf iguration

Name Abbrev. R/W Size Initial Value Address*2

Timer mode register J TMJ R/W Byte H'00 H'D13A

Timer J control register TMJC R/W Byte H'09 H'D13B

Timer J status register TMJS R/(W)*1 Byte H'3F H'D13C

Timer counter J TCJ R Byte H'FF H'D139

Timer counter K TCK R Byte H'FF H'D138

Timer load register J TLJ W Byte H'FF H'D139

Timer load register K TLK W Byte H'FF H'D138

Notes: 1. Only 0 can be written to clear the flag.

2. Lower 16 bits of the address.

Rev. 1.0, 02/01, page 268 of 1184

13.2 Register Descriptions

13.2.1 Timer Mode Register J (TMJ)

R/W

R/WR/WR/W

R/W

PS10

R/W

PS11 8/16 PS21 PS20 TGL T/R

Bit :

Initial value :

R/W :

The timer mode register J (TMJ) works to select the inputting clock for the TMJ-1 and TMJ-2 and

to set the operation mode.

The TMJ is an 8-b it r egister an d bit 1 is for read only. All the remaining bits are applicab le to

read/write.

When reset, the TMJ is initialized to H'0 0.

Under all other modes than the remo te contr olling mode, writing into the TMJ works to initialize

the counters (TCJ and TCK) to H'FF.

Bits 7 and 6



Selecting the Inputting Clock to the TMJ-1 (PS11, PS10): These bits work to

select the clock to input to the TMJ-1. When the external clock is selected, the counted edge

(rising or falling) can also be selected.

Bit 7 Bit 6

PS11 PS10 Description

0 Counting by the PSS, φ/512 (Initial value) 0

1 Counting by the PSS, φ/256

0 Counting by the PSS, φ/4 1

1 Counting at the risi ng edge or the falling edge of the external clock

inputs (IRQ1)*

Note: * The edge selection for the external clock inputs is made by setting the IRQ edge select

When using an external clock under the remote controlling mode, set the opposite edge

with the IRQ1 and the IRQ2 when using an external clock under the remote controlling

mode. (When IRQ1 falling, select IRQ2 rising and when IRQ1 rising, select IRQ2 falling)

Rev. 1.0, 02/01, page 269 of 1184

Bit 5



Starting the Remote Controlled Operation (ST): This bit work s to start the remote

controlled operat ions .

When this b it is set to 1, clock signa l is supplied to the TMJ-1 to start signa l tr ansmissions.

When this bit is cleared to 0, clock supply stops to discontinue the operation. The ST bit will be

valid under the remote controlling mode, namely, when bit 0 (T/R bit) is 1 and bit 4 (8/16 bit) is 0.

Under other modes than the remote controlling mode, it will be fixe d to 0. When a shift to the low

power consumption mode is made during r emote controlled operation, the ST bit will be cleared to

0. When resuming operation after returning to the active mode, write 1.

Bit 5

ST Description

0 Works to stop clock signal supply to the TMJ-1 under the remote controlling mode

(Initial value)

1 Works to supply clock signal to the TMJ-1 under the remote controlling mode

Bit 4



Switching Over Between 8-bit/16-bit Operations (8/16): This bit works to choose if

using timer J as two units of 8-bit timer/counter or if using it as a single unit of 16-bit

timer/counter. Even under 16-bit operations, TMJ1I interrupt requests from the TMJ-1 will be

valid.

Bit 4

8/16 Description

0 Makes the TMJ-1 and TMJ-2 operate separately (Initial value)

1 Makes the TMJ-1 and TMJ-2 operate altogether as 16-bit timer/counter

Bits 3 and 2



Selecting the Inputting Clock for the TMJ-2 (PS21, PS20): These bits, together

with the PS22 bit in the timer J control re gister (TMJC), work to select the clock for the TMJ-2.

When the exter n al clock is selected, the counted edge (rising or falling) can also be selected. For

details, refer to section 13.2.2, Timer J Control Register ( TMJC).

Bit 1



TMJ-2 Toggle Flag (TGL): This flag indicates the toggled status of the underflowing

with the TMJ-2. Reading only is workable.

It will be cleared to 0 under the low p o wer consumption mode.

Bit 1

TGL Description

0 The toggle output of the TMJ-2 is 0 (Initial value)

1 The toggle output of the TMJ-2 is 1

Rev. 1.0, 02/01, page 270 of 1184

Bit 0



Switching Over Bet ween Timer Output/Remote Controlling Output (T/R): This bit

works to select if using the timer outputs from the TMJ-1 as the output signal through the TMO

pin or if using the toggle outputs (remote controlled transmission data) from the TMJ-2 as the

output signal through the TMO pin.

Bit 0

T/R Description

0 Timer outputs from the TMJ-1 (Initial value)

1 Toggle outputs from the TMJ-2 (remote controlled transmission data)

Selecting the Operation Mode

The operating m ode of tim er J is determined by bit 3 (EXN) of the timer J contr ol register (TMJC)

and bits 4 (8/16) and 0 (T/R) of the timer mode register J (TMJ).

TMJC TMJ

Bit 3 Bit 4 Bit 0

EXN 8/16 T/R Description

0 0 0 8-bit timer + 16-bit timer

1 Remote-controlling mode (TMJ-2 works as a 16-bit timer)

1 * 24-bit timer

1 0 0 Two 8-bit timers (Initial value)

1 Remote-controlling mode (TMJ-2 works as an 8-bit timer)

1 * 16-bit timer

Note: * Don’t care

Writing to the TMJ in timer mode initializes the counters (TCJ and TCK) (H'FF). Consequently,

write to the relo ading registers (TLJ an TLK) after finish in g settings with th e TMJ.

Under the remote contro lling mode, although the TLJ and the TLK will not be initialized even

when writing is m a de into the TMJ, follow the seque nce listed below when starting a r emote

controlling operat i o n:

1. Make setting to the remote controlling mode with the TMJ.

2. Write the data in to the TLJ and TLK.

3. Start the remote controlled operation by use of the TMJ. (ST bit = 1).

Even under 16-bit o perations, TMJ1I interrup t requ e sts f r om the TMJ-1 will be valid.

Rev. 1.0, 02/01, page 271 of 1184

13.2.2 Timer J Control Register (TMJC)

R/W

3PS22EXN

R/W

R/WR/W

MON1

R/W

BUZZ0

R/W

BUZZ1 MON0 TMJ2IE TMJ1IE

Bit :

Initial value :

R/W :

The timer J contro l register (TMJC) works to select the buzzer output frequency and to control

permissio n/proh ibition of interrupts.

The TMJC is an 8-bit r ead/write register.

When reset, the TMJC is initialized to H'09.

Bits 7 and 6



Selecting the Buzzer Output (BUZZ1, BUZZ0): These bits work to select if

using the buzzer outputs as the output signal through the BUZZ pin or if using the monitor signals

as the output signal through the BUZZ pin.

When setting is made to the mon itor signals, choose th e monitor signal using the MON1 bit and

MON0 bit.

Bit 7 Bit 6

BUZZ1 BUZZ0 Description Frequency when

φφ

φ = 10 MHz

0 φ/4096 (Initial val ue) 2.44 kHz 0

1 φ/8192 1.22 kHz

0 Works to output monitor signals 1

1 Works to output BUZZ signals from timer J

Rev. 1.0, 02/01, page 272 of 1184

Bits 5 and 4



Selecting the Monitor Signals (MON1, MON0): These bits work to select the

type of signals being output through the BUZZ pin for monitoring purpose. These settings are

valid only when the BUZZ1 and BUZZ0 bits are being set to 10.

When PB-CTL or REC-CTL is chosen, signa l duties will be output as th ey are.

In case of DVCTL signals, signals from the CTL dividing circuit will be toggled before being

output. Signal wav ef orm s divided by the CTL dividing cir cuit into n-divisions will fur ther be

divided into halves. (Namely, 2n divisions, 50% duty waveform).

In case of TCA7, Bit 7 of the counter of the Timer A will be output. (50% duty)

When prescaler W is being used with the Timer A, 1 Hz outputs are available.

Bit 5 Bit 4

MON1 MON0 Description

0 PB or REC-CTL (Initial value) 0

1 DVCTL

1 * Outputs TCA7

Note: * Don't care.

Bit 3



Expansion Function Control Bit (EXN): This bit enables or disables the expansion

function of TMJ-2. When the expansion function is enabled, TMJ-2 works as a 16-bit counter, and

further input clock sources and types can be selected.

Bit 3

EXN Description

0 Enables the TMJ-2 expansion function

1 Disables the TMJ-2 expansion function (Initial value)

Bit 2



Enabling Interrupt of the TMJ2I (TMJ2IE): This bit works to permit/prohibit

occurrence of TMJ2I interrupt of the TMJS in 1-set of the TMJ2I.

Bit 2

TMJ2IE Description

0 Prohibits occurrence of TMJ2I interrupt (Initial value)

1 Permits occurrence of TMJ2I interrupt

Rev. 1.0, 02/01, page 273 of 1184

Bit 1



Enabling Interrupt of the TMJ1I (TMJ1IE): This bit works to permit/prohibit

occurrence of TMJ1I interrupt of the TMJS in 1-set of the TMJ1I.

Bit 1

TMJ1IE Description

0 Prohibits occurrence of TMJ1I interrupt (Initial value)

1 Permits occurrence of TMJ1I interrupt

Bit 0



TMJ-2 Input Clock Selection (PS22): This bit, together with the PS21 and PS20 bits of

the timer mode register J (TMJ), selects the TMJ-2 input clock source.

TMJC TMJ

Bit 3 Bit 0 Bit 3 Bit 2

EXN PS22 PS21 PS20 Description

0 1 0 0 PSS; count at φ/128

1 PSS; count at φ/64

1 0 Count at TMJ-1 underflow

1 External clock (IRQ2); count at rising or falling edge*1

0 * * Reserved

1 1 0 0 PSS; count at φ/16384 (Initial value)

1 PSS; count at φ/2048

1 0 Count at TMJ-1 underflow

1 External clock (IRQ2); count at rising or falling edge*1

0 0 0 PSS; count at φ/1024

1 PSS; count at φ/1024

1 0 Count at TMJ-1 underflow

1 External clock (IRQ2); count at rising or falling edge*1

Notes: * Don't care

1. The external clock edge can be selected by the IRQ edge select register (IEGR). For

details, refer to section 6.2.4, IRQ Edge Select Registers (IEGR).

Rev. 1.0, 02/01, page 274 of 1184

13.2.3 Timer J Status Register (TMJS)

012345

——————

R/(W)*

TMJ1I

R/(W)*

TMJ2I

111111

Note: * Only 0 can be written to clear the flag.

Bit :

Initial value :

R/W :

The timer J status register (TMJS) works to indicate issuance of the interrupt request of timer J.

The TMJS is an 8-b it r ead/write register. When reset, the TMJS is initialized to H'3F.

Bit 7



TMJ2I Interrupt Requesting Flag (TMJ2I): This is the TMJ2I interrupt requesting flag.

This flag is set out when the TMJ-2 underflows.

Bit 7

TMJ2I Description

0 [Clearing conditions] (Initial value)

When 0 is written after reading 1

1 [Setting conditions]

When the TMJ-2 underflows

Bit 6



TMJ1I Interrupt Requesting Flag (TMJ1I): This is the TMJ1I inter r upt requesting flag.

This flag is set out when the TMJ-1 underflows.

TMJ1I interr upt requests will also be made und er a 16-bit operation.

Bit 6

TMJ1I Description

0 [Clearing conditions] (Initial value)

When 0 is written after reading 1

1 [Setting conditions]

When the TMJ-1 underflows

Bits 5 to 0



Reserved: These bits cannot be modified and are always read as 1.

Rev. 1.0, 02/01, page 275 of 1184

13.2.4 Timer Counter J (TCJ)

RRR

TDR15

TDR16

TDR17 TDR14 TDR13 TDR12 TDR11 TDR10

Bit :

Initial value :

R/W :

The timer counter J (TCJ) is an 8-bit readable down-counter which works to count down by the

internal clock inputs or external clock inputs. The inputting clock can be selected by the PS11 and

PS10 bits of the TMJ. TCJ values can be readout always. Nonetheless, when the EXN bit in

TMJC and the 8/1 6 bit in TMJ are both set to 1, (means when setting is made to 16- bit operation),

reading is possible under the word command only.

At this time, the TCK of the TMJ-2 can be read by the upper 8 bits and the TCJ can be read by the

lower 8 bits. When the EXN bit in TMJC is 0, TCJ can be read only in byte units.

When the TCJ underflows (H'00 → Reloading value), regardless of the operation mode setting of

the 8/16 bit, the TMJ1I bit of the TMJS will be set to 1 bit. The TCJ and TLJ are being allocated

to the same add ress.

When reset, the TCJ is initialized to H'FF.

13.2.5 Timer Counter K (TCK)

RRR

TDR25

TDR26

TDR27 TDR24 TDR23 TDR22 TDR21 TDR20

Bit :

Initial value :

R/W :

The timer counter K (TCK) is an 8-bit or a 16-bit readable down-counter which works to count

down by the in ternal cloc k inputs or external clock inputs. The inputtin g clock can be selected by

the EXN and PS2 bits of the TMIC, and the PS21 and PS20 bits of the TMJ. TCK values can be

readout always. Nonetheless, when the EXN bit in TMJC and the 8/16 bit in TMJ are both set to

1, (means when setting is made to 16-bit operation), reading is possible under the word command

only.

At this time, the TCK can be read by the upper 8 bits and the TCJ of the TMJ-1 can be read by the

lower 8 bits. Wh en the EXN bit in TMJC is 0, TCK works as a 16-bit counter and can be read only

in word units.

When the TCK underflows (H'00 → Reloading valu e) , the TMJ2I b it of the TMJS will be set to 1.

The TCK and TLK are being allocated to the same address.

When reset, the TCK is initialized to H'FF.

Rev. 1.0, 02/01, page 276 of 1184

13.2.6 Timer Load Register J (TLJ)

WWW

TLR15

TLR16

TLR17 TLR14 TLR13 TLR12 TLR11 TLR10

Bit :

Initial value :

R/W :

The timer load register J ( TLJ) is an 8-bit write only register which work s to set the reloading

value of the TCJ.

When the reloading value is set to the TLJ, the value will be simultaneously loaded to the TCJ and

the TCJ starts counting down from the set value. Also, during an auto reloading operation, when

the TCJ underflows, the value of the TLJ will be loaded to the TCJ. Consequently, the

underflowing cycle can be set within the range of 1 to 256 input clocks. Nonetheless, when the

EXN bit in TMJC and the 8/16 bit in TMJ are both set to 1, (means when setting is m ade to 16-bit

operation), writing is possible under the word command only.

At this time, the upper 8 bits can be written into the TLK of the TMJ-2 and the lower 8 bits can be

written into th e TLJ. When the EXN bit in TMJC is 0, TLJ can b e wr itten to only in byte units; an

8-bit relo ad value is written to TLJ.

The TLJ and TCJ are being allocated to the same address.

When reset, the TLJ is in itialized to H'FF.

13.2.7 Timer Load Register K (TLK)

WWW

TLR25

TLR26

TLR27 TLR24 TLR23 TLR22 TLR21 TLR20

Bit :

Initial value :

R/W :

The timer load register K ( T LK) is an 8-bit or a 16-bit write only r egister wh ich works to set the

reloading value of th e TCK.

When the reloading value is set to the TLK, the value will be simultaneously lo aded to the TCK

and the TCK starts counting down from the set value. Also, during an auto reloading operation,

when the TCK underflows, the value of the TLK will be loaded to the TCK. Consequently, the

underflowing cycle can be set within the range of 1 to 256 input clocks. Nonetheless, when the

EXN bit in TMJC and the 8/16 bit in TMJ are both set to 1, (means when setting is m ade to 16-bit

operation), writing is possible under the word command only. At this time, the upper 8 bits can be

written into th e TLK and th e lower 8 bits can be written into the TLJ of the TMJ-1. When the

EXN bit in TMJC is 0, TLK can be written to only in word units; a 16- bit reload value is written

to TLK. The TLK and TCK are being allocated to the same address.

When reset, the TLK is in itialized to H'FF.

Rev. 1.0, 02/01, page 277 of 1184

13.2.8 Module Stop Control Register (MSTPCR)

MSTP15

R/W

MSTPCRH

MSTP14

R/W

MSTP13

R/W

MSTP12

R/W

MSTP11

R/W

MSTP10

R/W

MSTP9

R/W

MSTP8

R/W

MSTP7

R/W

MSTP6

R/W

MSTP5

R/W

MSTP4

R/W

MSTP3

R/W

MSTP2

R/W

MSTP1

R/W

MSTP0

R/W

MSTPCRL

Initial value :

R/W :

Bit :

The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode.

When the MSTP13 bit is set to 1, timer J stops its operation at the ending point of the bus cycle to

shift to the module stop mode. For more information, see section 4.5, Module Stop Mode.

When reset, the MSTPCR is initialized to H'FFFF.

Bit 5



Module Stop ( MSTP1 3): This bit works to designate the module stop mode for the Timer

MSTPCRH

Bit 5

MSTP13 Description

0 Cancels the module stop mode of timer J

1 Sets the module stop mode of timer J (Initial value)

Rev. 1.0, 02/01, page 278 of 1184

13.3 Operation

13.3.1 8-bit Reload Timer (TMJ-1)

The TMJ-1 is an 8-bit reload timer. As the clock source, dividing clock or edge signals through

the IRQ1 pin are being used. By selecting the edge signals through the IRQ1 pin, it can also be

used as an event counter. While it is working as an event counter, its reloading function is

workable simultaneously. When data are wr itten into the reloading register, these data will be

written into the counters (event counter, timer coun ter) simultaneously. Also, when the event

counter underflows, the event counter value is reset to the reload register value, and a TMJ1I

interrupt reque st o ccurs. Every time the counter underflows, the output level toggles. This outp ut

can be used as a buzzer or the carrier frequency at remote-controlled transmission by selecting an

appropriate divided clock.

The TMJ-1 and TMJ-2, in combination, can be used as a 16-bit or a 24-bit reload timer.

Nonetheless, when they are being used, in combination, as a 16-bit timer, word command only is

valid and the TCK works as the down counter for the upper 8 bits and the TCJ works as the down

counter for the lower 8 bits, means a reloading register of total 16 bits.

When data are wr itten into a 16-bit reload ing r egister, th e sam e data will be written into the 16-bit

down counter.

Also, when the 16-bit down counter underflow signals, the data of the 16-bit reloading register

will be reloaded into the down counter. When the EXN bit of TMJC is set to 0, the expansion

function of TMJ-2 is enabled, that is, TMJ-2 works as a 16-bit reloading timer, and it can be

connected to TMJ-1 to be a 24-bit reloading timer. In this case, TCK works as the upper 16-bit

part and TCJ works as the lower 8-bit part of a 24-bit down counter, and TLK works as the upper

16-bit part and TLJ works as the lower 8-bit part of a 24-bit reloading register.

Even when they are making a 16-bit or a 24-bit operation, the TMJ1I interrupt requests of the

TMJ-1 and BUZZER outputs are effective. In case these functions are not necessary, make them

invalid by programming.

The TMJ-1 and TMJ-2, in combination, can be used for remote controlled data transmission.

Regarding the remote controlled data transmission, see section 13.3.3, Remote Controlled Data

Transmission.

13.3.2 8-bit Reload Timer (TMJ-2)

The TMJ-2 is an 8-bit or a 16-bit down-counting reload timer. As the clock source, dividing

clock, edge signals through the IRQ2 pin or the underflow signals from the TMJ-1 are being used.

By selecting the edge signals through the IRQ2 pin, it can also be used as an event counter. While

it is working as an event counter, its reloading function is workable simultaneously.

When data are wr itten into the reloading register, these data will be written into the counter

simultaneously. Also, when the counter underflows, reloading will be made to the data counter of

the reloading r egister.

When the counter underflows, TMJ2I interrupt requests will be issued.

The TMJ-2 and TMJ-1, in combination, can be used as a 16-bit or a 24-bit reload timer. For more

Rev. 1.0, 02/01, page 279 of 1184

information on the 16-bit or 24-bit reload timer , see section 13.3.1, 8-bit Reload Timer (TMJ-1).

The TMJ-2 and TMJ-1, in combination, can be operated by remote controlled data transmission.

Regarding the remote controlled data transmission, see section 13.3.3, Remote Controlled Data

Transmission.

13.3.3 Remote Controlled Data Transmission

The Timer J is capable of making remote controlled data transmission. The carrier frequencies for

the remote controlled data transmission can be generated by the TMJ-1 and the burst width

duration and the space width duration can be setup by the TMJ-2.

The data having been written into the reloading register TMJ-1 and into the burst/space duration

controlled data transmission starts. (Remote controlled data transmission starting bit (ST) ← 1)

While remote controlled data tr ansmission is being made, the contents of the burst/space duration

Even when a writing is made to the burst/space duration register while remote controlled data

transmission is being made, reloading operation will not be made until an underflow signal is

issued. The TMJ-2 issues TMJ2I interrupt requests by the underflow signals. The TMJ-1

performs normal reloading operation (including the TMJ1I interrupt requests).

Figure 13.2 shows the output waveform for the remote controlled data transmission function.

When a shift to the low power consumption mode is ef fected while remote controlled data

transmission is being mad e, the ST bit will be cleared to 0. When resu ming the remote controlled

data transmissio n after returning to the active mode, write 1.

Burst width Space width Burst width

TMJ-2 toggle output

= 1 TMJ-2 toggle output

= 0 TMJ-2 toggle

output = 1

Setting the

space width Setting the

burst width Setting the

space width

ST bit ← 1 Underflow Underflow Underflow

TMJ-1 can generate

the carrier frequencies

Remote controlled data

transmission outputs

Setting the remote

controlled mode

Setting the burst width

Figure 13.2 Remote Controlled Data Transmission Output Waveform

Rev. 1.0, 02/01, page 280 of 1184

TMJ-1

UDF

TMO

(BUZZ)

TMJ-2

UDF

REMOout

TMO

Remote controlled data

transmission output

Figure 13.3 Timer Output Timing

Rev. 1.0, 02/01, page 281 of 1184

When the Timer J is set to the remote controlled oper ation mode, since the start bit ( ST) is bein g

set or cleared in synchronization with the inputting clock to the TMJ-2, a delay upto a cycle of the

inputting clock at the maximum occurs, namely, after the ST bit has been set to 1 until the remote

controlled data transmission starts. Consequently, when the TLK is updated during the period

after setting th e ST bit to 1 until the next cycle of the inputting clock comes, the initial burst width

will be changed as shown in figure 13.4.

Therefore, when making remote controlled data transmission, determine 1/0 of the TGL bit at the

time of the first burst width control operation without fail. (Or, set the space width to the TLK

after waiting for a cycle of the inputting clock.)

After that, operations can be continued by interrupts.

Similarly, pay attention to the control works when ending remote controlled data transmission.

Example:

1) Set the burst width with the TLK.

2) ST bit ← 1.

3) Execute the procedure 4) if the TGL flag = 1.

4) Set the space width with the TLK under the status where the TGL flag = 1.

5) Make TMJ-2 interrupt.

6) Set the burst width with the TLK.

n) After making TMJ-2 interrupt, make setting of the ST ← 0 under the status where the TGL

flag = 0.

The period during which the

space width settig can be

made. (S)

Delay

Interrupt

TLK setting

(Burst width)

(B)

Burst width

according to (B) Space width

according to (S)

Stopping the remote controlled

data transmission

TGL flag

Inputting clock

to the TMJ-2

ST ← 0

Delay

ST ← 1

Remote controlled data

transmission starts here.

If an updating is made with the

TLK during this period, the burst

width will be changed.

Figure 13.4 Controls of the Remote Controlled Data Transmission

Rev. 1.0, 02/01, page 282 of 1184

13.3.4 TMJ-2 Expansion Function

The TMJ-2 expansion function is enabled by setting the EXN bit in the timer J co n trol re gister

(TMJC) to 0. This function makes TMJ-2, which usually wo rks as an 8-bit counter, work as a 16-

bit counter. When this function is selected, timer counter K (TCK) and timer load register K

(TLK) must be accessed as follows:

TCK Re ad: To read TCK, use the word-length MOV instruction. In this case, the upper 8 bits of

TCK are read out to the lower byte of the on-chip data bus, and the lower 8 bits are read out to the

upper byte of the on-chip data bus. That is, when MOV.W @TCK, Rn is executed, the lower 8

bits of TCK are stored in RnH and the upper 8 bits are stored in RnL.

TLK Write: To write to TLK, use the word-leng th MOV instru ction. In this case, the upper 8 b its

are written to the lo wer byte of TLK, and the lower 8 bits are written to th e upp er byte of TLK.

That is, when MOV.W Rn, @ TLK is executed, the RnH d a ta is written to the lower byte of TLK,

and the RnL data is written to the upper byte of TLK.

Rev. 1.0, 02/01, page 283 of 1184

Section 14 Timer L

14.1 Overview

Timer L is an 8-bit up/down counter using the control pulses or the CFG division signals as the

clock source.

14.1.1 Features

Features of timer L are as follows:

• Two types of internal clocks (φ/128 and φ/64), DVCFG2 (CFG division signal 2), PB and

REC-CTL (control pulses) are available for your selection.

— When the PB-CTL is not available, such as when reproducing un-recorded tapes, tape

count can be made by the DVCFG2.

— Selection of the rising edge or the falling edge is workable with the CTL pulse counting.

• Interrupts occur when the co unter overflows or underflows and at occurrences of compare

match clear.

• Capable to switch over between the up-counting and down-counting functions with the

counter.

Rev. 1.0, 02/01, page 284 of 1184

14.1.2 Block Diagram

Figure 14.1 shows a block diagram of timer L.

Legend:

Internal data bus

DVCFG2 : Division signal 2 of the CFG

PB and REC-CTL : Control pluses necessary when making

reproduction and storage

LMR : Timer L mode register

LTC : Linear time counter

RCR : Reload/compare match register

OVF : Overflow

UDF : Underflow

LMR

LTC

RCR

Comparator

Write

OVF/UDF

Reloading

Match clear

Interrupt request

Interrupting

circuit

DVCFG2

PB and

REC-CTL

Internal clock

φ/128

φ/64

Read

Figure 14.1 Block Diagram of Timer L

Rev. 1.0, 02/01, page 285 of 1184

14.1.3 Register Configuration

Table 14.1 shows the register configuration of timer L. The linear time counter (LTC) and the

reload compare patch register (RCR) are being allocated to the same address.

Reading or writing determines the accessing register.

Table 14.1 Register Co nf iguration

Name Abbrev. R/W Size Initial Value Address*

Timer L mode register LMR R/W Byte H'30 H'D112

Linear time counter LTC R Byte H'00 H'D113

Reload/compare match

Note: * Lower 16 bits of the address.

Rev. 1.0, 02/01, page 286 of 1184

14.2 Register Descriptions

14.2.1 Timer L Mode Register (LMR)

R/W

——

R/WR/WR/W

LMIE

R /(W)*

LMIF LMR3 LMR2 LMR1 LMR0

Note: * Only 0 can be written to clear the flag.

Bit :

Initial value :

R/W :

The timer L mode register A (LMR) is an 8 - bit read/write register which wo rks to control the

interrupts, to select between up-counting and down-counting and to select the clock source. When

reset, the LMR is initialized to H'30.

Bit 7



Timer L Interrupt Requesting Flag (LMIF): This is the Timer L interrupt requesting

flag. It indicates occurrence of overflow or underflow of the LTC or occurrence of compare

match clear.

Bit 7

LMIF Description

0 [Clearing conditions] (Initial value)

When 0 is written after reading 1

1 [Setting conditions]

When the LTC overflows, underflows or when compare match clear has occurred

Bit 6



Enabling Interrupt of the Timer L (LMIE): When the LTC overflows, underflows or

when comp are match clear has occurred, then LMIF is set to 1 , th is bit works to permit/prohib it

the occurrence of an interrupt of timer L.

Bit 6

LMIE Description

0 Prohibits occurrence of interrupt of Timer L (Initial value)

1 Permits occurrence of interrupt of Timer L

Bits 5 and 4



Reserved: These bits cannot be modified and are always read as 1.

Bit 3



Up-Count/Dow n- Count Cont rol (LMR3): This b it is for selection if timer L is to be

controlled to the up-counting function or down-counting function.

Rev. 1.0, 02/01, page 287 of 1184

1. When Controlled to the Up-Counting Function

 When any other values than H'00 are input to the RCR, the LTC will b e cleared to H'00

before star ting counting up. When the LTC value and the RCR value match , the LTC will

be cleared to H'00. Also, interrupt requests will be issued by the match sig nal. (Compare

match clear function)

 When H' 00 is set to the RCR, the counter makes 8-bit interval timer operation to issue a

interrupt request when overflowing occurs. (Interval timer function)

2. When Controlled to the Down-Counting Function

 When a value is set to the RCR, the set valu e is r e loaded to the LTC and coun ting down

starts from that value. When the LTC underflows, the value of the RCR will be reloaded to

the LTC. Also, when the LTC underflows, a interrupt request will be issued. (Auto reload

timer fun ction)

Bit 3

LMR3 Description

0 Controlling to the up-counting function (Initial value)

1 Controlling to the down-counting func tion

Bits 2 to 0



Clock Selection ( LMR2 t o LMR0): The bits LMR2 to LMR0 work to select the

clock to input to timer L. Selection of the leading edge or the trailing edge is workab le for

counting by the PB and the REC-CTL.

Bit 2 Bit 1 Bit 0

LMR2 LMR1 LMR0 Description

0 Counts at the rising edge of the PB and REC-CTL

(Initial value)

1 Counts at the falling edge of the PB and REC-CTL

1 * Counts the DVCFG2

0 * Counts at φ/128 of the internal clock 1

1 * Counts at φ/64 of the internal clock

Note: * Don't care.

Rev. 1.0, 02/01, page 288 of 1184

14.2.2 Linear Time Counter (LTC)

456

RRRR

LTC6

LTC5

LTC4

LTC7 LTC3 LTC2 LTC1 LTC0

Bit :

Initial value :

R/W :

The linear time counter (LTC) is a readable 8-bit up/down-counter. The inputting clock can be

selected by the LMR2 to LMR0 bits of the LMR.

When reset, the LTC is in itialized to H'00.

14.2.3 Reload/Compare Match Register (RCR)

456

WWWW

RCR6

RCR5

RCR4

RCR7 RCR3 RCR2 RCR1 RCR0

Bit :

Initial value :

R/W :

The reload/compare match register (RCR) is an 8-bit wr ite only r e g ister .

When timer L is be ing controlled to the up-counting function, when a comp are match value is set

to the RCR, the LTC will be cleared at the same time and the LTC will then start counting up from

the initial value (H'00).

While, when the Timer L is being controlled to the down-counting function, when a reloading

value is set to the RCR, the same value will be loaded to the LTC at the same time and the LTC

will then start counting up fr om said value. Also, when the LTC underflows, the value of the RCR

will be reloaded to the LTC.

When reset, the RCR is initialized to H'00 .

Rev. 1.0, 02/01, page 289 of 1184

14.2.4 Module Stop Control Register (MSTPCR)

MSTP15

R/W

MSTPCRH

MSTP14

R/W

MSTP13

R/W

MSTP12

R/W

MSTP11

R/W

MSTP10

R/W

MSTP9

R/W

MSTP8

R/W

MSTP7

R/W

MSTP6

R/W

MSTP5

R/W

MSTP4

R/W

MSTP3

R/W

MSTP2

R/W

MSTP1

R/W

MSTP0

R/W

MSTPCRL

Bit :

Initial value :

R/W :

The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode.

When the MSTP12 bit is set to 1, timer L stops its operation at the ending point of the bus cycle to

shift to the module stop mode. For more information, see section 4.5, Module Stop Mode.

When reset, the MSTPCR is initialized to H'FFFF.

Bit 4



Module Stop ( MSTP1 2): This bit works to designate the module stop mode for timer L.

MSTPCRH

Bit 4

MSTP12 Description

0 Cancels the module stop mode of timer L

1 Sets the module stop mode of timer L (Initial value)

Rev. 1.0, 02/01, page 290 of 1184

14.3 Operation

Timer L is an 8-bit up/down counter.

The inputting cloc k for Timer L can be selected by the LMR2 to LMR0 bits of the LMR from the

choices of the internal clock (φ/128 and φ/64), DVCDG2, PB and REC-CTL.

Timer L is provided with three different types of operation modes, namely, the compare match

clear mode when controlled to the up-counting function, the auto reloading mode when controlled

to the down-co unting function and th e interval timer mode.

Respective operation modes and operation methods will be explained below.

14.3.1 Compare Match Clear Operation

When the LMR3 b it of the LMR is cleared to 0, timer L will be controlled to the up-counting

function.

When any other values than H'00 ar e wr itten into the RCR, the LT C will be cleared to H'00

simultaneously before starting counting up.

Figure 14.2 shows RCR writing and LTC clearing timing. When the LTC value and the RCR

value match ( compare match), the LTC readings will be cleared to H'00 to resume counting from

H'00.

Figure 14.3 indicated on the next page shows the co mpare match clear timing.

RCR

LTC

Write signal

1 state

H' 00

Figure 14.2 RCR Writing and L TC Clearing Timing Cha rt

Rev. 1.0, 02/01, page 291 of 1184

LTC

RCR

NH' 00N-1

Interrupt

request

Count-up

signal

Compare match

clear signal

PB-CTL

Figure 14.3 Compare Match Clearing Timing Chart

(In case the rising edge of the PB-CTL is selected)

14.3.2 Auto-Reload Operation

When 1 is written in bit LMR3 of LMR, LTC enters down-counting control mode.

When a reload value is written in RCR, LTC i s reloaded with the same value and starts counting

down from that value. Figure 14-4 shows the timing of the writing and reloading of RCR.

At underflow, LTC is reloaded with the RCR value. Figure 14-5 shows the reload timing.

1 state

Write

signal

RCR

LTC

Figure 14-4 Timing of Writing a nd Reloading of RCR

Rev. 1.0, 02/01, page 292 of 1184

PB-CTL

RCR

LTC

H'00

H'01 N

Count-down

signal

Interrupt

request

Reload

underflow

Figure 14-5 Reload Timing (Rising Edge of PB-CTL Selected)

14.3.3 Interval Timer Operation

When bit LMR3 is cleared to 0 in LMR, the timer L enters up-counting control mode.

If H'00 is written in RCR, compare-m atch operations are not carried out. The counter functions as

an interval timer (up-counter).

14.3.4 Interrupt Request

The timer L generates an interrupt request when any of the following occurs:

• Compare-match clear under up-counting control

• Underflow under down-counting control

• Overflow or underflow when the reload/compare-match register (RCR) value is H'00

Rev. 1.0, 02/01, page 293 of 1184

14.4 Typical Usage

Figure 14-6 shows a typical usage of the timer L.

H'FF

Value written

in RCR

H'00

***

LTC = RCR

Compare match clear Underflow

(reload) Underflow

(reload)

Value other than H'00

written in RCR under

up-counting control Down-counting control

(1 written in bit LMR3)

(Rewind, reverse, etc.)

(Record, playback,

fast-forward, etc.)

Notation

A downward-pointing arrow indicates an interrupt request.

Figure 14-6 Typical Usage of Linear Time Counter

14.5 Reload Timer Interrupt Request Signal

The timer counters with reload registers generate an underflow or overflow in the last cycle before

being decremented or incremented. The underflow or overflow generates a reload signal and an

interrupt request signal.

If the value in the reload register is rewritten at the same time as the underflow or overflow (at the

reload timin g ), an in terru pt request is generated and the counter is relo ad ed at the same time.

When rewriting the reload value in order to avoid an inter rupt, leave an ample timing margin

around the write to the reload register.

Rev. 1.0, 02/01, page 294 of 1184

Figure 14-7 shows a sample timing diagram of contention between an underflow and the rewriting

of the reload register.

1 Bus

cycle

Write

Reload

Counter

UDF

H'01 H'00 H'nn H'nn-1

IRR

H'zz H'nn

Reload: disabled by write

Notation

Write:

Reload:

UDF:

IRR:

Reload register rewrite signal

Reload signal

Counter underflow

Interrupt request signal

Figure 14-7 Contention between Reload Timer Underflow and

Rewriting of Reload Register

Rev. 1.0, 02/01, page 295 of 1184

Section 15 Timer R

15.1 Overview

Timer R consists of triple 8-bit down-counters. It carries VCR mode identification function and

slow tracking function in addition to the reloading function and event counter function.

15.1.1 Features

The Timer R consists of triple 8-bit r eloading timers. By combinin g the functions of three units of

reloading timers/counters and by combining three units of timers, it can be used for the following

applications:

• Applications making use of the functions of three units of reloading timers.

• For identif ication of the VCR mod e .

• For reel controls.

• For acceleration and braking of the capstan motor when being applied to intermittent

movements.

• Slow tracking mono-multi applications.

15.1.2 Block Diagram

Timer R consists of th ree units of reload timer counters, namely, two units of reload timer

counters equipped with capturing function (TMRU-1 and TMRU-2) and a unit of reload timer

counter (TMRU-3).

Figure 15.1 is a block diagram of timer R.

Rev. 1.0, 02/01, page 296 of 1184

Notes:

Internal bus

Clock sources

DVCTL

CFG↑

Clock

selection

(2 bits)

Reloading register

(8 bits)

Down-counter

(8 bits)

Capture register

(8 bits)

TMRI2

Interrupt request

TMRI1

Interrupt

request

TMRI3

Interrupt

request

TMRU-1

TMRCP1 *2

Under

flow

TMRU-3 Underflow

TMRL3

PS31,30

External signals

IRQ3

φ /1024

φ /2048

φ /4096

Clock source

φ /64

φ /128

φ /256

Clock sources

φ /4

φ /256

φ /512

Down-counter

(8 bits)

Latch

clock

selection

Clock

selection

(2 bits)

Resetting

Available/

Not

available

CP/

SLM

SLW

CAPF

Capture register

(8 bits)

Down-counter

(8 bits)

Reloading register

(8 bits)

Acceleration/

braking

Reloading

Available/

not

available

Reloading

clock

selection

Reloading register

(8 bits)

RLD/

CAP

Clock

selection

(2 bits)

CPS

LAT PS21,20

CLR2

Res

TMRCP2

Under

flowTMRU-2 CFG mask F/F

Acceleration

braking

AC/BR

TMRL2

RLD

RLCK

TMRL1PS11,10

Interrupting circuit

1. When the DVCTL is being used as the clock source, reloading will be made when the counter underflows and when

the dividing clock is being used as the clock source, reloading will be made by the DVCTL.

2. When the LAT bit = 0, the capture signal against the TMRU-1 will not be output.

Figure 15.1 Block Diagram of Timer R

Rev. 1.0, 02/01, page 297 of 1184

15.1.3 Pin Configuration

Table 15.1 shows the pin configuration of timer R.

Table 15. 1 Pin Configuration

Name Abbrev. I/O Function

Input capture inputti ng pin IRQ3 Input Input capture inputting for the Timer R

15.1.4 Register Configuration

Table 15.2 shows the register configuration of timer R.

Table 15.2 Register Co nf iguration

Name Abbrev. R/W Size Initial Value Address

Timer R mode register 1 TMRM1 R/W Byte H'00 H'D118

Timer R mode register 2 TMRM2 R/W Byte H'00 H'D119

Timer R control/status

Timer R capture register 1 TMRCP1 R Byte H'FF H'D11A

Timer R capture register 2 TMRCP2 R Byte H'FF H'D11B

Timer R load register 1 TMRL1 W Byte H'FF H'D11C

Timer R load register 2 TMRL2 W Byte H'FF H'D11D

Timer R load register 3 TMRL3 W Byte H'FF H'D11E

Note: Memories of respective registers will be preserved even under the low power consumption

mode. Nonetheless, the CAPF flag and SLW flag of the TMRM2 will be cleared to 0.

Rev. 1.0, 02/01, page 298 of 1184

15.2 Register Descriptions

15.2.1 Timer R Mode Register 1 (TMRM1)

R/W

R/WR/WR/W

RLD

R/W

AC/BR

R/W

CLR2 RLCK PS21 PS20 RLD/CAP CPS

Bit :

Initial value :

R/W :

The timer R mode register 1 (TMRM1) works to control the acceleration and braking processes

and to select the in putting clock for the TMRU-2. This is an 8-bit read/write register.

When reset, the TMRM1 is initialized to H'00 .

Bit 7



Selecting Clearing/Not Clearing of TMRU-2 (CLR2): This bit is used for selecting if

the TMRU-2 counter reading is to be cleared or not as it is captured.

Bit 7

CLR2 Description

0 TMRU-2 counter reading is not to be cleared as soon as it is captured. (Initial value)

1 TMRU-2 counter reading is to be cleared as soon as it is captured

Bit 6



Acceleration/Braking Processing (AC/BR): This bit works to control occurrences of

interrupt requests to detect completion of acceleration or braking while the capstan motor is

making in termitten t r evolutions.

For more information, see section 15.3.6, Acceleration and Braking Processes of the Capstan

Motor.

Bit 6

AC/BR Description

0 Braking (Initial value)

1 Acceleration

Rev. 1.0, 02/01, page 299 of 1184

Bit 5



Using/Not Using the TMRU-2 for Reloading (RLD): This bit is used for selecting if the

TMRU-2 reload function is to be turned on or not.

Bit 5

RLD Description

0 Not using the TMRU-2 as the reload timer (Initial value)

1 Using the TMRU-2 as the reload timer

Bit 4



Reloading Timing for the TMRU-2 (RLCK): This bit works to select if th e TMRU-2 is

reloading by the CFG or by underflowing of the TMRU-2 counter. This choice is valid only when

the bit 5 (RLD) is being set to 1.

Bit 4

RLCK Description

0 Reloading at the rising edge of the CFG (Initial value)

1 Reloading by underflowing of the TMR U-2

Bits 3 and 2



Clock Source for the TMRU-2 (PS21, PS20): These bits work to select the

inputting clock to the TMRU-2.

Bit 3 Bit 2

PS21 PS20 Description

0 Counting by underflowing of the TMRU-1 (Initial value) 0

1 Counting by the PSS, φ/256

0 Counting by the PSS, φ/128 1

1 Counting by the PSS, φ/64

Bit 1



Operation Mode of the TMRU-1 (RLD/CAP): This bit works to select if the operation

mode of the TMRU-1 is reload timer mode or capture timer mode.

Under the capture timer mode, reloading operation will not be made. Also, the counter reading

will be cleared as soon as captu re has been made.

Bit 1

RLD/CAP Description

0 The TMRU-1 works as the reloading timer (Initial value)

1 The TMRU-1 works as the capture timer

Rev. 1.0, 02/01, page 300 of 1184

Bit 0



Capture Signals of the TMRU-1 (CPS): In combination with the LAT bit (Bit 7) of the

TMR2, this bit wor ks to select the captur e sig nals of the TMRU-1. This bit becomes valid when

the LAT bit is bein g set to 1. It will also become va lid when the RLD/CAP bit (Bit 1) is being set

to 1. Nonetheless, it will be invalid wh en the RLD/CAP bit (Bit 1) is being set to 0.

Bit 0

CPS Description

0 Capture signals at the rising edge of the CFG (Initial value)

1 Capture signals at the edge of the IRQ3

15.2.2 Timer R Mode Register 2 (TMRM2)

R/(W)*

R/W

R/(W)*R/WR/W

PS10

R/W

PS11

R/W

LAT PS31 PS30 CP/SLM CAPF SLW

Bit :

Initial value :

R/W :

The timer R mode register 2 (TMRM2) is an 8-bit read/write register which works to identify the

operation mode and to control the slow tracking processing.

When reset, the TMRM2 is initialized to H'00 .

Note: * The CAPF bit and the SLW bit, respectively, works to latch the inter rupt causes and

writing 0 only is valid. Consequen tly, when these bits are being set to 1, respectiv e

interrupt requests will no t b e issued. Th erefore, it is necessary to check these bits

during the course of the interrupt processing routine to have them cleared.

Also, priority is given to the set and, when an interrup t cause occur while the a clearing

command (BCLR, MOV, etc.) is being executed, th e CAPF bit and the SLW bit will

not be cleared respectively and it thus becomes necessary to pay attention to the

clearing timing.

Rev. 1.0, 02/01, page 301 of 1184

Bit 7



Capture Signals of the TMRU-2 (LAT): In combination with the CPS bit (Bit 0) of the

TMRM1, this bit wo r ks to select the captur e signals of the TMRU-2.

TMRM2 TMRM1

Bit 7 Bit 0

LAT CPS Description

0 * Captures when the TMRU-3 underflows (Initial value)

0 Captures at the rising edge of the CFG 1

1 Captures at the edge of the IRQ3

Note: * Don't care.

Bits 6 and 5



Clock Source for the TMRU-1 (PS11, PS10): These bits work to select the

inputting clock to the TMRU-1.

Bit 6 Bit 5

PS11 PS10 Description

0 Counting at the rising edge of the CFG (Initial value) 0

1 Counting by the PSS, φ/4

0 Counting by the PSS, φ/256 1

1 Counting by the PSS, φ/512

Bits 4 and 3



Clock Source for the TMRU-3 (PS31, PS30): These bits work to select the

inputting clock to the TMRU-3.

Bit 4 Bit 3

PS31 PS30 Description

0 Counting at the rising edge of the DVCTL from the dividing circuit.

(Initial value)

1 Counting by the PSS, φ/4096

0 Counting by the PSS, φ/2048 1

1 Counting by the PSS, φ/1024

Rev. 1.0, 02/01, page 302 of 1184

Bit 2



Interrupt Causes (CP/SLM): This bit works to select the interrupt causes for the TMRI3.

Bit 2

CP/SLM Description

0 Makes interrupt requests upon the capture signals of the TMRU-2 valid (Initial value)

1 Makes interrupt requests upon ending of the slow tracking mono-multi valid

Bit 1



Capture Signal Flag (CAPF): This is a flag being set out by th e capture signal of the

TMRU-2. Although both reading/writing are possible, 0 only is valid for writing.

Also, priority is being given to the set and, when the capture signal and writing 0 occur

simultaneo usly, this flag bit remains being set to 1 and the interrupt requ e st will not be issued and

it is necessary to be attentive about this fact.

When the CP/SLM bit (bit 2) is being set to 1, this CAPF bit should always be set to 0.

The CAPF flag is cleared to 0 under the low power consumption mode.

Bit 1

CAPF Description

0 [Clearing conditi ons ] (Initial val ue)

When 0 is written after reading 1

1 [Setting conditions]

At occurrences of the TMRU-2 capture signals while the CP/SLM bit is set to 0

Bit 0



Slow Tracking Mono- mult i Flag (SLW): This is a flag being set out when the slow

tracking mono-multi processing ends. Although both reading/writing are possible, 0 only is valid

for writing.

Also, prior ity is being given to the set and, when ending of the slow tracking mono-multi

processing and writing 0 occur simultaneously, this flag bit remains being set to 1 and the interrupt

request will not be issued and it is necessary to be attentive about this fact.

When the CP/SLM bit (bit 2) is being set to 0, this SLW bit should always be set to 0.

The SLW flag is cleared to 0 under the low power consumption mode.

Bit 0

SLW Description

0 [Clearing conditi ons ] (Initial val ue)

When 0 is written after reading 1

1 [Setting conditions]

When the slow tracking mono-multi processing ends while the CP/SLM bit is set to 1

Rev. 1.0, 02/01, page 303 of 1184

15.2.3 Timer R Control/Status Register (TMRCS)

1——

——

R/(W)*

R/(W)*R/W

TMRI1E

R/W

TMRI2E

R/W

TMRI3E TMRI3 TMRI2 TMRI1

Note: * Only 0 can be written to clear the flag.

Bit :

Initial value :

R/W :

The timer R control/status register (TMRCS) works to control the interrupts of timer R.

The TMRCS is an 8-b it r ead/write register. When reset, the TMRCS is initialized to H'0 3.

Bit 7



Enabling the TMRI3 Inter rupt (TMRI3E) : This bit works to permit/pro hibit occurrence

of the TMRI3 interrupt when an interrupt cause being selected by the CP/SLM bit of th e TMRM2

has occurred, such as occurrences of the TMRU-2 capture signals or when the slow tracking

mono-multi processing ends, and the TMRI3 has been set to 1.

Bit 7

TMRI3E Description

0 Prohibits occurrences of TMRI3 interrupts (Initial value)

1 Permits occurrences of TMRI3 interrupts

Bit 6



Enabling the TMRI2 Inter rupt (TMRI2E) : This bit works to permit/pro hibit occurrence

of the TMRI2 interrupt when the TMRI2 has been set to 1 by issuance of the underflow signal of

the TMRU-2 or by endin g of the slow tracking mono-mu lti pro cessing.

Bit 6

TMRI2E Description

0 Prohibits occurrences of TMRI2 interrupts (Initial value)

1 Permits occurrences of TMRI2 interrupts

Rev. 1.0, 02/01, page 304 of 1184

Bit 5



Enabling the TMRI1 Interrupt (TMRI1E): This bit works to permit/pro hibit occurrence

of the TMRI1 interrupt when the TMRI1 has been set to 1 by issuance of the underflow signal of

the TMRU-1.

Bit 5

TMRI1E Description

0 Prohibits occurrences of TMRI1 interrupts (Initial value)

1 Permits occurrences of TMRI1 interrupts

Bit 4



TMRI3 Interrupt Requesting Flag (TMRI3): This is the TMRI3 interrupt requesting

flag.

It indicates occurrence of an interrupt cause being selected by the CP/SLM bit of the TMRM2,

such as occur r ences of the TMRU-2 capture signa ls or ending of the slow trackin g mono-multi

processing.

Bit 4

TMRI3 Description

0 [Clearing conditions] (Initial value)

When 0 is written after reading 1

1 [Setting conditions]

At occurrence of the interrupt cause being selected by the CP/SLM bit of the TMRM2

Bit 3



TMRI2 Interrupt Requesting Flag (TMRI2): This is the TMRI2 interrupt requesting

flag.

It indicates occurrences of the TMRU-2 underflow signals or ending of the acceleration/braking

processing of the capstan motor.

Bit 3

TMRI2 Description

0 [Clearing conditions] (Initial value)

When 0 is written after reading 1

1 [Setting conditions]

At occurrences of the TMRU-2 underflow signals or ending of the acceleration

/braking proces sin g of the capstan motor

Rev. 1.0, 02/01, page 305 of 1184

Bit 2



TMRI1 Interrupt Requesting Flag (TMRI1): This is the TMRI1 interrupt requesting

flag.

It indicates occurrences of the TMRU-1 underflow signals.

Bit 2

TMRI1 Description

0 [Clearing conditions] (Initial value)

When 0 is written after reading 1.

1 [Setting conditions]

When the TMRU-1 underfl ows.

Bits 1 and 0



Reserved: These bits cannot be modified and are always read as 1.

15.2.4 Timer R Capture Register 1 (TMRCP1)

TMRC17

TMRC16

TMRC15

TMRC14

TMRC13

TMRC12

TMRC11

TMRC10

Bit :

Initial value :

R/W :

The timer R capture register 1 (TMRCP1) works to store the captured data of the TMRU-1.

During the course of the capturing operation, the TMRU-1 counter readings are captured by the

TMRCP1 at the CFG edge or the IRQ3 edge. The capturing operation of the TMRU-1 is

performed using 16 bits, in combination with the capturing operation of the TMRU-2.

The TMRCP1 is an 8- bit read only register. When r e set, the TMRCS is initialized to H'FF.

Notes: 1. When the TMRCP1 is readout while the capture signal is being received, the reading

data become unstable. Pay attention to the timing for reading out.

2. When a shift to th e low power consumption mode is m a de while the capturing

operating is in progress, the counter reading becomes unstable. After returning to the

active mode, always write H'FF into the TMRL1 to initialize the counter.

Rev. 1.0, 02/01, page 306 of 1184

15.2.5 Timer R Capture Register 2 (TMRCP2)

TMRC27

TMRC26

TMRC25

TMRC24

TMRC23

TMRC22

TMRC21

TMRC20

Bit :

Initial value :

R/W :

The timer R capture register 2 (TMRCP2) works to store the capture data of the TMRU-2. At

each CFG edge, IRQ3 edge, or at occurrence of underflow of the TMRU-3, the TMRU-2 counter

readings are captured by the TMRCP2.

The TMRCP2 is an 8- bit read only register. When reset, the TMRCS will be initialized in to H'FF.

Notes: 1. When the TMRCP2 is readout while the capture signal is being received, the reading

data become unstable. Pay attention to the timing for reading out.

2. When a shift to the low power consumption mode is made, the counter reading

becomes un stab le. Af ter retu rning to the active mode, always write H'FF into the

TMRL2 to initialize the counter.

15.2.6 Timer R Load Register 1 (TMRL1)

TMR17

TMR16

TMR15

TMR14

TMR13

TMR12

TMR11

TMR10

Bit :

Initial value :

R/W :

The timer R load r egister 1 (TMRL1) is an 8-bit write-only register which wor ks to set the load

value of the TMRU-1.

When a load v a lue is set to the TMRL1, the same v alue will be set to the TMRU-1 counter

simultaneou sly and the counter starts counting down from the set valu e. Also, when the counter

underflows during the course of the reload timer operation, the TMRL1 value will be set to the

counter.

When reset, the TMRL1 is initialized to H'FF.

Rev. 1.0, 02/01, page 307 of 1184

15.2.7 Timer R Load Register 2 (TMRL2)

TMR27

TMR26

TMR25

TMR24

TMR23

TMR22

TMR21

TMR20

Bit :

Initial value :

R/W :

The timer R load r egister 2 ( TMRL2) is an 8-bit write only register which works to set th e load

value of the TMRU-2.

When a load v a lue is set to the TMRL2, the same v alue will be set to the TMRU-2 counter

simultaneou sly and the counter starts counting down from the set valu e. Also, when the counter

underflows or a CFG edge is detected during the course of the reload timer operation, the TMRL2

value will be set to the counter.

When reset, the TMRL2 is initialized to H'FF.

15.2.8 Timer R Load Register 3 (TMRL3)

TMR37

TMR36

TMR35

TMR34

TMR33

TMR32

TMR31

TMR30

Bit :

Initial value :

R/W :

The timer R load r egister 3 ( TMRL3) is an 8-bit write only register which works to set th e load

value of the TMRU-3.

When a load v a lue is set to the TMRL3, the same v alue will be set to the TMRU-3 counter

simultaneou sly and the counter starts counting down from the set valu e. Also, when the counter

underflows or a DVCTL edge is detected, the TMRL2 value will be set to the counter. (Reloading

will be made b y the underflowing signals wh en the DVCTL signal is selected as the clock source,

and reloading will be made by the DVCTL signals when the dividing clock is selected as the clock

source.)

When reset, the TMRL3 is initialized to H'FF.

Rev. 1.0, 02/01, page 308 of 1184

15.2.9 Module Stop Control Register (MSTPCR)

MSTP15

R/W

MSTPCRH

MSTP14

R/W

MSTP13

R/W

MSTP12

R/W

MSTP11

R/W

MSTP10

R/W

MSTP9

R/W

MSTP8

R/W

MSTP7

R/W

MSTP6

R/W

MSTP5

R/W

MSTP4

R/W

MSTP3

R/W

MSTP2

R/W

MSTP1

R/W

MSTP0

R/W

MSTPCRL

Bit :

Initial value :

R/W :

The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode.

When the MSTP11 bit is set to 1, tim er R stops its operation at th e ending point of the bus cycle to

shift to the module stop mode. For more information, see section 4.5, Module Stop Mode.

When reset, the MSTPCR is initialized to H'FFFF.

Bit 3



Module Stop ( MSTP1 1): This bit works to designate the module stop mode for the Timer

MSTPCRH

Bit 3

MSTP11 Description

0 Cancels the module stop mode of timer R

1 Sets the module stop mode of timer R (Initial value)

Rev. 1.0, 02/01, page 309 of 1184

15.3 Operation

15.3.1 Reloa d Timer Counter Equipped with Capturing Functi on TMRU-1

TMRU-1 is a reload timer counter equipped with capturing function. It consists of an 8-bit down-

counter, a reloading register and a capture register.

The clock source can be selected from among the leading edge of the CFG signals and three types

of dividing clocks. It is also selectable whether using it as a reload counter or as a capture counter.

Even when the capturing function is selected, the counter readings can be updated by writing the

values into the reloading register.

When the counter underflows, the TMRI1 interrupt request will be issued.

The initial values of the TMRU-1 counter, reloading register and capturing register are all H'FF.

• Operation of the Reload Timer

When a value is written into to the relo ading register, the same value will be wr itten into the

counter simultaneously. Also, when the counter underflows, the reloading register value will

be reloaded to the counter. The TMRU-1 is a dividing circuit for the CFG. In combination

with the TMRU-2 and TMRU-3, it can also b e used for the mod e identification purpose.

• Capturing Operation

Capturing operation is carried out in combination with the TMRU-2 using the combined 16

bits. It can be so programmed that the coun ter may be cleared by the capture signal. The CFG

edges or IRQ3 edges are used as the capture signals. It is possible to issue the TMRI3

interrupt request by the capture signal.

In addition to th e capturing function being wo rked out in combination with th e TMRU-2, the

TMRU-1 can be used as a 16-bit CFG counter. Selecting the IRQ3 as the capture signal, the

CFG within the duration of the reel pulse being input into the IRQ3 pin can be counted by the

TMRU-1.

Rev. 1.0, 02/01, page 310 of 1184

15.3.2 Reload Timer Count er Equipped with Capturing Function TMRU- 2

TMRU-2 is a reload timer counter equipped with capturing function. It consists of an 8-bit down-

counter, a reloading register and a capture register.

The clock source can be selected from among the undedrflowing signal of the TMRU-1 and three

types of dividing clocks. Also, although the reloading function is workable during its capturing

operation , equ ippin g or not o f the reloading f unction is selectable. Even when with out-reloading-

function is chosen, the counter reading can be updated by writing the values to the reloading

When the counter underflows, the TMRI2 interrupt request will be issued.

The initial values of the TMRU-2 counter, reloading register and capturing register are all H'FF.

• Operation of the Reload Timer

When a value is written into to the relo ading register, the same value will be wr itten into the

counter, simultaneously. Also, when the counter underflows or when a CFG edge is detected,

the reloading register value will be reloaded to the counter.

The TMRU-2 can make acceleration and braking work for the capstan motor using the reload

timer oper a tion.

• Capturing Operation

Using the capture signals, the counter reading can be latched into the capturing register. As the

capture signal, you can choose from among edges of the CFG, edges of the IRQ3 or the

underflow signals of the TMRU-3. It is possible to issue the TMRI3 interrupt request by the

capture sign a l.

The capturing function (stopping the reloading function) of the TMRU-2, in combination with

the TMRU-1 and TMRU-3, can also be used for the mode identification purpose.

15.3.3 Reload Counter Timer TMRU-3

The reload counter timer TMRU-3 consists of an 8-bit down-counter and a reloading register. Its

clock source can be selected from between the undedrflowing signal of the counter and the edges

of the DVCTL sign a ls. ( Whe n the DVCTL signal is selected as the clock source, reloading will be

effected by the underflowing signals and when the dividing clock is selected as the clock source,

reloading will be effected by the DVCTL signals.) The reloadin g signal works to reload the

reloading register value into the counter. Also, when a value is written into to the reloading

The initial values of the counter and the reload ing r egister ar e H'FF.

The underflowing signals can be used as the capturing signal for the TMRU-2.

The TMRU-3 can also be used as a dividing circuit for the DVCTL. Also, in combination with

the TMRU-1 and TMRU-2 (capturing function), the TMRU-3 can be used for the mode

identification purpose. Since the divided signals of the DVCTL are being used as the clock

source, CTL signals (DVCTL) conforming to the double speed can be input when making

Rev. 1.0, 02/01, page 311 of 1184

searches. These DVCTL signals can also be used for phase controls of the capstan motor.

Also, by selecting the dividing clock as the clock source, it is possible to make a delay with the

edges of the DVCTL to provide the slow tr acking mono-multi function.

15.3.4 Mode Identification

When mak in g mode identification (2 /4/6 identification) of the SP/LP/EP modes of reproducing

tapes, the TMRU-1 (CFG dividing circuit), TMRU-2 (capturing function/without reloading

function) and TMRU-3 (DVCTL dividing circuit) of timer R should be used.

Timer R will becom e to the aforemention ed status after a reset.

Under the aforementioned status, the divided CFG should be written into the reloading register of

the TMRU-1 and divided DVCTL should be written into the reloading register of the TMRU-3.

When the TMRU-3 underflows, the counter value of the TMRU-2 is captured. Such capturing

As aforementioned, the Timer R can work to count the number of the CFG corresponding to n

times of DVCTL's or to identify the mode being searched .

For register settings, see section 15.5.1, Mode Identification.

15.3.5 Reeling Controls

CFG counts can be captured by making 16-bit capturing operation combining the TMRU-1 and

TMRU-2. Choosing the IRQ3 as the capture signal and counting the CFG within the duration of

the reel pulse being input through the IRQ3 pin affect reeling controls. For r egister settings, see

section 15.5.2, Reeling Controls.

15.3.6 Acceleration and Braking Processes of the Capstan Motor

When mak ing intermittent move ments such as th ose for slow reproductio ns or for still

reproductions, it is necessary to conduct quick accelerations and abrupt stoppings of the capstan

motor. The acceleration and braking processes functions to check if the revolution of a capstan

motor has reached the prescribed rate when accelerated or braked. For this purpose, the TMRU-2

(reloading function) should be used.

When making accelerations:

• Set the AC/BR bit of the TMRM1 to acceleration (set to 1). Also, use the rising edge of the

CFG as the reloading signal.

• Set the prescribed time on the CFG frequency to determine if the acceleration has been

finished, into the reloading register.

• The TMRU-2 will work to down-count the reloading data.

• In case the acceleration has not been finished (in case the CFG signal is not input even when

the prescribed time has elapsed = underflowing of down-counting has occurred), such

Rev. 1.0, 02/01, page 312 of 1184

underflowing works to set to CFG mask F/F (masking movement) and the reload timer will be

cleared by the CFG.

• When the acceleration has been finished (when the CFG signal is input before the prescribed

time has elapsed = reloading movement has been made before the down counter underflows),

an interrupt request will be issued because of the CFG.

When making breaking:

• Set the AC/BR bit of the TMRM1 to braking (clear to 0). Also, use the rising edge of the CFG

as the reloading signal.

• Set the prescribed time on the CFG frequency to determine if the braking has been finished,

into the reloading register.

• The TMRU-2 will work to down-count the reloading data.

• If the braking has not finished (when the CFG signal is input before the prescribed time has

elapsed and reloading movement has been made before the down counter underflows), the

reload timer mov e m ent will continue.

• When the acceleration has finished (when the CFG signal is not input even when the

prescribed time has elapsed and underflowing of down-counting has occurred), interrupt

request will be issued because of the underflowing signal.

The acceleration and braking processes should be employed when making special reproductions,

in combination with the slow tracking mon o-m ulti function outlined in section 15.3.7.

For register settings, see section 15.5.4, Acceleration and Braking Processes of the Capstan Motor.

15.3 .7 Slow Tracking Mono -Multi Function

When perf orm ing slow reproductions or still reproductions, the braking timing for the capstan

motor is determined by use of the edge of the DVCTL signal. The slow track ing m ono -multi

function works to measure the time from the rising edge of the DVCTL signal down to the desired

point to issue the interrupt request. In actual programming, this interrupt should be used to

activate the brake of the capstan motor. The TMRU-3 should be used to perform time

measurements for the slow tracking mono-multi function. Also, the braking process can be made

using the TMRU-2. Figure 15.2 shows the time series movements when a slow reproduction is

being performed.

For register settin gs, see section 15.5.3, Slow Track ing Mono - Multi Function.

Rev. 1.0, 02/01, page 313 of 1184

HSW

FG acceleration detection

Compensation for vertical vibrations

(Supplementary V-pulse)

DVCTL↑Interrupt

Reloading

Reverse

rotation

Frame feeds

Compensation for

horizontal vibrations Compensation for

horizontal vibrations

Braking

process

Acceleration

process

Slow tracking

delay

C.Rotary

H.AmpSW

Accelerating the

capstan motor

Braking the

drum motor

Slow tracking

mono-multi

Braking the

capstan motor

Servo

Hi-Z

Legend:

Hi-Z : High impedance state

In case of 4-head SP mode.

In case of 2-head application, H.AmpSW and

C.Rotary should be "Low".

FG stopping detection

Forward

rotation

Figure 15.2 Time Series Movements when a Slow Reproduction

Is Being Performed

Rev. 1.0, 02/01, page 314 of 1184

15.4 Interrupt Cause

In timer R, bits TMRI1 to TMRI3 of th e timer R control/status register cause interrupts. Th e

following are descriptions of the interrupts.

1. Interrupts caused by th e underflowing of the TMRU-1 (TMRI1)

These interru pts will constitute the timing for reloading with the TMRU- 1.

2. Interrupts caused by the underf lowing of the TMRU-2 or by an end of the acceleration or

braking process (TMRI2)

When interr upts occur at the reload timing of the TMRU-2, clear the AC/BR

(acceleration/braking) bit of the timer R mode register 1 (TMRM1) to 0.

3. Interrupts caused by th e capture signals of the TMRU-2 and by ending the slow tracking

mono-multi process (TMRI3)

Since these two interru pt causes are constituting the OR, it becomes necessary to determine

which interrupt cause is occurring using the software.

Respective interr upt causes are being set to the CAPF flag or the SLW flag of the timer R

mode register 2 (TMRM2), have the software determine which.

Since the CAPF flag and the SLW flag will no t b e clear ed automatically, program the software

to clear them. (Writing 0 only is valid for these flags.) Unless these flags are cleared,

detection of the next cause becomes unworkable. Also, if the CP/SLM bit is changed leaving

these flags unc lear ed as they are, these flags will get cleared.

Rev. 1.0, 02/01, page 315 of 1184

15.5 Settings for Respective Functions

15.5.1 Mode Identification

When mak in g mode identification (2 /4/6 identification) of the SP/LP/EP modes of reproducing

tapes, the TMRU-1 (CFG dividing circuit), TMRU-2 (capturing function/without reloading

function) and TMRU-3 (DVCTL dividing circuit) of the timer R should be used.

Timer R will be initialized to this mode identification status after a reset.

Under this status, the divided CFG should be written into the reloading register of the TMRU-1

and divided DVCTL should be written into the reloading register of the TMRU-3. When the

TMRU-3 underflows, the counter value of the TMRU-2 is captured. Such capturing register value

represents the number of the CFG within the DVCTL cycle.

Thus, timer R can work to count the number of the CFG corresponding to n times of DVCTL's or

to identify th e mode being searched.

Settings

• Setting the timer R mode register 1 (TMRM1)

 CLR2 bit (bit 7 ) = 1: Works to clear after m a king the TMRU-2 capture.

 RLD bit (bit 5) = 0: Sets the TMRU-3 without reloading function.

 PS21 and PS20 (bits 3 and 2) = (0 and 0): The underflowing signals of the TMRU-1 are to

be used as the clock source for the TMRU-2.

 RLD/CAP bit (bit 1 ) = 0: The TMRU-1 has been set to make the reload timer operation.

• Setting the timer R mode register 2 (TMRM2)

 LAT bit (bit 7) = 0: The underflowing signals of the TMRU-3 are to be used as the capture

signal for the TMRU-2.

 PS11 and PS10 (bits 6 and 5) = (0 and 0): The leading edge of the CFG signal is to be used

as the clock source for the TMRU-1.

 PS31 and PS30 (bits 4 and 3) = (0 and 0): The leading edge of the DVCTL signal is to be

used as the clock source for the TMRU-3.

 CP/SLM bit (bit 2) = 0: The capture signal is to work to issue the TMRI3 interrupt request.

• Setting the timer R load register 1 (TMRL1)

 Set the dividing value fo r the CFG. The set value should become (n − 1) when divided by

• Setting the timer R load register 3 (TMRL3)

 Set the dividing value for the DVCTL. The set value should become (n − 1) when divided

by n.

Rev. 1.0, 02/01, page 316 of 1184

15.5.2 Reeling Controls

CFG counts can be captured by making 16-bit capturing operation combining the TMRU-1 and

TMRU-2. By choosing the IRQ3 as the capture signal, and by counting the CFG within the

duration of the reel pulse being input through the IRQ3 pin, reeling controls, etc. can be effected.

Settings

• Setting P13/IRQ3 pin as the IRQ3 pin

 Set the PMR13 bit (bit 3) of the port mode register 1 (PMR1) to 1. See section 10.3.2, Port

Mode Register (PMR1).

• Setting the timer R mode register 1 (TMRM1)

 CLR2 bit (bit 7 ) = 1: Works to clear after m a king the TMRU-2 capture.

 PS21 and PS20 (bits 3 and 2) = (0 and 0): The underflowing signals of the TMRU-1 are to

be used as the clock source for the TMRU-2.

 RLD/CAP bit (bit 1 ) = 1: The TMRU-1 has been set to make the capturing operation.

 CPS bit (bit 0) = 1: The edge of the IRQ3 signa l is to be used as the capture signal fo r the

TMRU-1 and TMRU-2.

• Setting the timer R mode register 2 (TMRM2)

 LAT bit (bit 7) = 1: The edge of the I RQ3 signal is to be used as the captu r e signal f or the

TMRU-1 and TMRU-2.

 PS11 and PS10 (bits 6 and 5) = (0 and 0): The rising edge of the CFG signal is to be used

as the clock source for the TMRU-1.

 CP/SLM bit (bit 2) = 0: The capture signal is to work to issue the TMRI 3 interrupt request.

15.5 .3 Slow Tracking Mono -Multi Function

When perf orm ing slow reproductions or still reproductions, the braking timing for the capstan

motor is determined by use of the edge of the DVCTL signal. The slow track ing m ono -multi

function works to measure the time from the leading edge of the DVCTL signal down to the

desired point to issue the interrupt request. In actual programming, this interrupt should be used to

activate the brake of the capstan motor. The TMRU-3 should be used to perform time

measurements for the slow tracking mono-multi function. Also, the braking process can be made

using the TMRU-2.

Rev. 1.0, 02/01, page 317 of 1184

Settings

• Setting the timer R mode register 2 (TMRM2)

 PS31 and PS30 (bits 4 and 3) = Other than (0, 0): The dividing clock is to be used as the

clock source for the TMRU-3.

 CP/SLM bit (bit 2) = 1: The slow tracking delay sig nal is to work to issue the TMRI3

interrupt request.

• Setting the timer R load register 3 (TMRL3)

 Set the slow tracking delay value. When th e delay count is n, the set value should be

(n - 1).

 Regarding the delaying duration, see figure 15.2.

15.5.4 Acceleration and Braking Processes of the Capstan Motor

When mak ing intermittent move ments such as th ose for slow reproductio ns or for still

reproductions, it is necessary to conduct quick accelerations and abrupt stoppings of the capstan

motor. The acceleration and braking processes will function to check if the revolution of a capstan

motor has reached the prescribed rate when accelerated or braked. For this purpose, the TMRU-2

(reloading function) should be used.

The acceleration and braking processes should be employed when making special reproductions,

in combination with the slow tracking mon o-m ulti function.

Settings for the acceleration process

• Setting the timer R mode register 1 (TMRM1)

 AC/BR bit (bit 6) = 1: Acceleration process

 RLD bit (bit 5) = 1 : The TMRU-2 is to be used as the reload timer.

 RLCK bit (bit 4) = 0: The TMRU-2 is to reload at the rising edge of the CFG.

 PS21 and PS20 (bits 3 and 2) = Other than (0, 0): The dividing clock is to be used as the

clock source for the TMRU-2.

• Setting the timer R load register 2 (TMRL2)

 Set the count reading for the duration until the acceleration pr ocess finishes. When the

count is n, the set value should be (n − 1).

 Regarding the duration until the acceleration process finish es, see fig ure 15.2.

Settings for the braking process

• Setting the timer R mode register 1 (TMRM1)

 AC/BR bit (bit 6) = 0: Braking process

 RLD bit (bit 5) = 1 : The TMRU-2 is to be used as the reload timer.

 RLCK bit (bit 4) = 0: The TMRU-2 is to reload at the rising edge of the CFG.

Rev. 1.0, 02/01, page 318 of 1184

 PS21 and PS20 (bits 3 and 2) = Other than (0, 0): The dividing clock is to be used as the

clock source for the TMRU-2.

• Setting the timer R load register 2 (TMRL2)

 Set the count reading for the duration until the braking process finishes. When the count is

n, the set valu e should be (n - 1).

 Regarding the duration until the br aking process finishes, see figure 15.2.

Rev. 1.0, 02/01, page 319 of 1184

Section 16 Timer X1

Note: The Timer X1 is not (incorporated in) provided for the H8S/2197S and H8S/2196S.

16.1 Overview

Timer X1 is capable of outputting two different types of independent waveforms using a 16-bit

free running counter (FRC) as the basic means and it is also applicable to measurements of the

durations of input pulses and the cycles external clocks.

16.1.1 Features

Timer X1 has the following features:

• Four different types of counter inputting clocks.

Three different types of internal clocks (φ/4, φ/16 and φ/64) and the DVCFG.

• Two independent output comparing functions

Capable of outputting two different types of independent waveforms.

• Four independent input capturing functions

The rising edge or falling edge can be selected for use. The buffer operation can also be

designated.

• Counter clearing designation is workable.

The counter readings can be cleared by compare match A.

• Seven types of interrupt causes

Comparing match × 2 causes, input capture × 4 causes and overflow × 1 cause are available for

use and they can make respective interrupt requests independently.

Rev. 1.0, 02/01, page 320 of 1184

16.1.2 Block Diagram

Figure 16.1 shows a block diagram of the Timer X1.

Internal data bus

Legend:

TIER

ICRA

ICRB

ICRC

ICRD

TCRX

OCRB

Comparison circuit

FRC

Comparison circuit

OCRA

TOCR

TCSRX

TIER

Input

capture

control

Output comparing output

Interrupt

request × 7

FTOA

FTOB

FTIA*

(HSW)

FTIB*

(VD)

FTIC*

(DVCTL)

FTID*

(NHSW)

(DVCFG)

φ / 4

φ / 16

φ / 64

TCSRX

FRC

OCRA

OCRB

TCRX

TOCR

ICRA

ICRB

ICRC

ICRD

: Timer interrupt enabling register

: Timer control/status register X

: Free running counter

: Output comparing register A

: Output comparing register B

: Timer control register X

: Output comparing control register

: Input capture register A

: Input capture register B

: Input capture register C

: Input capture register D ÊÊ

Note: * stands for the external terminal.

( ) stands for the internal signal.

Figure 16.1 Block Diagram of Timer X1

Rev. 1.0, 02/01, page 321 of 1184

16.1.3 Pin Configuration

Table 16.1 shows the pin configuration of timer X1.

Table 16. 1 Pin Configuration

Name Abbrev. I/O Function

Output comparing A output-pin FTOA Output Output pin for the output comparing A

Output comparing B output-pin FTOB Output Output pin for the output comparing B

Input capture A input-pin FTIA Input Input-pin for the input capture A

Input capture B input-pin FTIB Input Input-pin for the input capture B

Input capture C input-pin FTIC Input Input-pin for the input capture C

Input capture D input-pin FTID Input Input-pin for the input capture D

Rev. 1.0, 02/01, page 322 of 1184

16.1.4 Register Configuration

Table 16.2 shows the register configuration of timer X1.

Table 16.2 Register Co nf iguration

Name Abbrev. R/W Initial Value Address*3

Timer interrupt enabling register TIER R/W H'00 H'D100

Timer control/status register X TCSRX R/ (W)*1 H'00 H'D101

Free running counter H FRCH R/W H'00 H'D102

Free running counter L FRCL R/W H'00 H'D103

Output comparing register AH OCRAH R/W H'FF H'D104*2

Output comparing register AL OCRAL R/W H'FF H'D105*2

Output comparing register BH OCRBH R/W H'FF H'D104*2

Output comparing register BL OCRBL R/W H'FF H'D105*2

Timer control register X TCRX R/W H'00 H'D106

Timer output compari ng contr ol register TOCR R/W H'00 H'D 107

Input capture register AH ICRAH R H'00 H'D108

Input capture register AL ICRAL R H'00 H'D109

Input capture register BH ICRBH R H'00 H'D10A

Input capture register BL ICRBL R H'00 H'D10B

Input capture register CH ICRCH R H'00 H'D10C

Input capture register CL ICRCL R H'00 H'D10D

Input capture register DH ICRDH R H'00 H'D10E

Input capture register DL ICRDL R H'00 H'D10F

Notes: 1. Only 0 can be written to clear the flag for Bits 7 to 1. Bit 0 is readable/writable.

2. The addresses of the OCRA and OCRB are the same. Changeover between them are

to be made by use of the TOCR bit and OCRS bit.

3. Lower 16 bits of the address.

Rev. 1.0, 02/01, page 323 of 1184

16.2 Register Descriptions

16.2.1 Free Running Counter (FRC)

Free running counter H (FRCH)

Free running counter L (FRCL)

R/W

R/WR/WR/W

R/W R/W

R/W

FRC

FRCH FRCL

R/WR/WR/WR/W

R/W

Bit :

Initial value :

R/W :

The FRC is a 16-b it r ead/write up-counter which counts up by the inputting internal clo c k/external

clock. The inpu tting clo c k is to be selected from the CKS1 and CKS0 o f the TCRX.

By the setting of the CCLRA bit of the TCSRX, the FRC can be cleared by comparing match A.

When the FRC o verflows (H'FFFF → H'0000), the OVF of the TCSRX will be set to 1.

At this time, when th e OVI E of th e TI ER is being set to 1, an interru pt request will be issued to the

CPU.

Reading/writing can be made from and to the FRC through the CPU at 8-bit or 16-bit.

The FRC is initialized to H'0000 when reset or under the standby mode, watch mode, subsleep

mode, module stop mode or subactive mode.

Rev. 1.0, 02/01, page 324 of 1184

16.2.2 Output Comparing Registers A and B (OCRA and OCRB)

Output comparing register AH and BH (OCRAH and OCRBH)

Output comparing register AL and BL (OCRAL and OCRBL)

R/W

R/WR/WR/W

R/W R/W

R/W

OCRA, OCRB

OCRAH, OCRBH OCRAL, OCRBL

R/WR/WR/WR/W

R/W

Bit :

Initial value :

R/W :

The OCR consists of twin 16-bit read/write registers (OCRA and OCRB). The contents of the

OCR are always being compared with the FRC and, when the value of these two match, the OCFA

and OCRB of the TCSRX will be set to 1. A t this time, if the OCIAE a nd OCIB of the TIER are

being set to 1, an interrupt request will be issued to the CPU.

When performing compare matching, if the OEA and OEB of the TOCR are set to 1, the level

value set to the OLVLA and OLVLB of the TOCR will be ou tp ut through the FTOA and FTOB

pins. After resetting, 0 will be output through the FTOA and FTOB pins un til the first compare

matching occurs.

Reading/writing can be made from and to the OCR through the CPU at 8-bit or 16-bit.

The OCR is cleared to H'FFFF when reset or under the standby mode, watch mode, subsleep

mode, module stop mode or subactive mode.

Rev. 1.0, 02/01, page 325 of 1184

16.2.3 Input Capture Registers A throug h D (ICRA through ICRD)

Input capture register AH to DH (ICRAH to ICRDH)

Input capture register AL to DL (ICRAL to ICRDL)

RRR

ICRA, ICRB, ICRC, ICRD

ICRAH, ICRBH, ICRCH, ICRDH ICRAL, ICRBL, ICRCL, ICRDL

RRRR

Bit :

Initial value :

R/W :

The ICR consists of four 16-bit read-only registers (ICRA through ICRD).

When the falling edge of the input capture input signal is detected, the value is transferred to the

ICRA through ICRD. The ICFA through ICFD of the TCSRX are set to 1 simultaneously. If the

IDIAE through IDIDE of the TCRX are all set to 1, an interru pt request will be issued to the CPU.

The edge of the input signal can be selected by setting the IEDGA through IEDGD of the TCRX.

The ICRC and ICRD can also be used as the buffer register, of the ICRA and ICRB, respectively

by setting the BUFEA and BUFEB of the TCRX to perform buffer operations. Figure 16.2 shows

the connections necessary when using the ICRC as the buffer register of th e ICRA. (BUFEA = 1)

When the ICRC is used as the buffer of th e ICRA, by setting IEDGA ≠ IEDGC, both of the rising

and falling edges can be designated fo r use. In case of IEDGA = IEDGC, either one of the rising

edge or the falling edge only is usable. Regarding selection of the input signal edge, see table

16.3.

Note: Transf er ence from the FRC to the ICR will be performed regar dless of the value of the

ICF.

Rev. 1.0, 02/01, page 326 of 1184

Edge detection and

capture signal

generating circuit.

BUFEAIEDGA

FTIA

IEDGC

ICRC ICRA FRC

Figure 16.2 Buffer Operation (Example)

Table 16.3 Input Sig nal Edge Selection when Making Buffer Operatio n

IEDGA IEDGC Selection of the Input Signal Edge

0 Captures at the falling edge of the input capture input A (Initial value) 0

Captures at both rising and falling edges of the input capture input A

1 Captures at the rising edg e of the input capture inp ut A

Reading can be made from the ICR through the CPU at 8-bit or 16 -bit.

For stable input capturing operation, maintain the pulse duration of the input capture input signals

at 1.5 system clock (φ) or more in case of single edge capturing and at 2.5 system clock (φ) or

more in case of both edge capturing.

The ICR is initialized to H'0000 when reset or under the standby mode, watch mode, subsleep

mode, module stop mode or subactive mode.

Rev. 1.0, 02/01, page 327 of 1184

16.2.4 Timer Interrupt Enabling Register (TIER)

R/W

R/WR/WR/W

ICICE

R/W

ICIBE

R/W

ICIAE ICIDE OCIAE OCIBE OVIE ICSA

Bit :

Initial value :

R/W :

The TIER is an 8-bit read/write register that controls permission/prohibition of interrupt requests.

The TIER is initialized to H'00 when reset or under the standby mode, watch mode, subsleep

mode, module stop mode or subactive mode.

Bit 7



Enabling the Input Capture Interrupt A (ICIAE): This bit works to permit/prohibit

interrupt requests (ICIA) by the ICFA when the ICFA of the TCSRX is being set to 1.

Bit 7

ICIAE Description

0 Prohibits interrupt requests (ICIA) by the ICFA (Initial value)

1 Permits interrupt requests (ICIA) by the ICFA

Bit 6



Enabling the Input Capture Interrupt B (ICIBE): This bit works to permit/prohibit

interrupt requests (ICIB) by the ICFB when the ICFB of the TCSRX is being set to 1.

Bit 6

ICIBE Description

0 Prohibits interrupt requests (ICIB) by the ICFB (Initial value)

1 Permits interrupt requests (ICIB) by the ICFB

Bit 5



Enabling the Input Capture Interrupt C (ICICE): This bit works to permit/prohibit

interrupt requests (ICIC) by the ICFC when the ICFC of the TCSRX is being set to 1.

Bit 5

ICICE Description

0 Prohibits interrupt requests (ICIC) by the ICFC (Initial value)

1 Permits interrupt requests (ICIC) by the ICFC

Rev. 1.0, 02/01, page 328 of 1184

Bit 4



Enabling the Input Capture Interrupt D (ICIDE): This bit works to permit/prohibit

interrupt requests (ICID) by the ICFD when the ICFD of the TCSRX is being set to 1.

Bit 4

ICIDE Description

0 Prohibits interrupt requests (ICID) by the ICFD (Initial value)

1 Permits interrupt requests (ICID) by the ICFD

Bit 3



Enabling the Output Compar ing Interrupt A (OCIAE): This bit works to

permit/prohibit interrupt re quests (OCIA) by the OCFA when the OCFA of the TCSRX is bein g

set to 1.

Bit 3

OCIAE Description

0 Prohibits interrupt requests (OCIA) by the OCFA (Initial value)

1 Permits interrupt requests (OCIA) by the OCFA

Bit 2



Enabling the Output Comparing Interrupt B (OCIBE): This bit works to

permit/prohibit interrupt r e quests (OCIB) by th e OCFB when the OCFB of the TCSRX is being

set to 1.

Bit 2

OCIBE Description

0 Prohibits interrupt requests (OCIB) by the OCFB (Initial value)

1 Permits interrupt requests (OCIB) by the OCFB

Bit 1



Enabling the Timer Overflow Interrupt (OVIE): This bit works to p ermit/prohibit

interrupt requests (FOVI) by the OVF when the OVF of the TCSRX is being set to 1.

Bit 1

OVIE Description

0 Prohibits interrupt requests (FOVI) by the OVF (Initial value)

1 Permits interrupt requests (FOVI) by the OVF

Rev. 1.0, 02/01, page 329 of 1184

Bit 0



Selecting the Input Capture A Signals (ICSA): This bit works to select the input capture

A signals.

Bit 0

ICSA Description

0 Selects the FTIA pin for inputting of the input capture A signals (Initial value)

1 Selects the HSW for inputting of the input capture A signals

Rev. 1.0, 02/01, page 330 of 1184

16.2.5 Timer Control/Status Register X (TCSRX)

R/WR/(W)*

ICFB

R/(W)*

ICFA

R/(W)*

ICFD

R/(W)*

ICFC

R/(W)*

OCFB

R/(W)*

OCFA CCLRA

R/(W)*

OVF

Note: * Only 0 can be written to clear the flag for Bits 7 to 1.

Bit :

Initial value :

R/W :

The TCSRX is an 8-bit register which works to select counter clearing timing and to control

respective interrupt requesting signals. The TCSRX is initialized to H'00 when reset or under the

standby mode, watch mode, subsleep mode, module stop mode or subactive mode.

Meanwhile, as for the timing, see section 16.3, Operation.

The FTIA through FTID pins are for fixed inputs inside the LSI under the low power consumption

mode excluding the sleep mode. Consequently, when such shifts as active mode → low power

consumption mode → active mode are made, wrong edges may be detected depending on the pin

status or on the type of the detecting edge.

To avoid such erro r, clear the interrupt requesting flag once immediately after shifting to the

active mode from the low power consumption mode.

Bit 7



Input Capture Flag A (ICFA): This is a status flag indicating the fact that the value of

the FRC has been transferred to the ICRA by the input capture signals.

When the BUFEA of the TCRX is being set to 1, the ICFA indicates the status that the FRC value

has been transferred to the ICRA by the input capture signals and that the ICRA value befo re

being updated has been transferred to the ICRC.

This flag should be cleared by use of of the software. Such setting should only be made by use of

the hardware. It is not possible to make this setting using a software.

Bit 7

ICFA Description

0 [Clearing conditions] (Initial value)

When 0 is written into the ICFA after reading the ICFA under the setting of ICFA = 1

1 [Setting conditions]

When the value of the FRC has been transferred to the ICRA by the input capture

signals

Rev. 1.0, 02/01, page 331 of 1184

Bit 6



Input Capture Fla g B (ICFB): This status flag indicates the fact that the value of the

FRC has been tr ansfer red to the ICRB by the input capture signals.

When the BUFEB of the TCRX is being set to 1, the ICFB indicates the status that the FRC value

has been transferred to the ICRB by the input capture signals and that the ICRB value befo re being

updated has been transferred to the ICRC.

This flag should be cleared by use of the software. Such setting should only be made by use of the

hardware. It is not possible to make this setting using a software.

Bit 6

ICFB Description

0 [Clearing conditions] (Initial value)

When 0 is written into the ICFB after reading the ICFB under the setting of ICFB = 1

1 [Setting conditions]

When the value of the FRC has been transferred to the ICRB by the input capture

signals

Bit 5



Input Capture Flag C (ICFC): This status flag indicates the fact that the value of the

FRC has been tr ansfer red to the ICRC by the input capture signals.

When an input capture signal occurs while the BUFEA of the TCRX is being set to 1, although the

ICFC will be set out, data tr ansference to th e ICRC will not be performed.

Therefore, in buffer operation, the ICFC can be used as an external interrupt by setting the ICICE

bit to 1.

This flag should be cleared by use of the software. Such setting should only be made by use of the

hardware. It is not possible to make this setting using a software.

Bit 5

ICFC Description

0 [Clearing conditions] (Initial value)

When 0 is written into the ICFC after reading the ICFC under the setting of ICFC = 1

1 [Setting conditions]

When the input capture signal has occurred

Rev. 1.0, 02/01, page 332 of 1184

Bit 4



Input Capture Flag D (ICFD): This status flag indicates the fact that the value of the

FRC has been transferred to the ICRD by the input capture signals.

When an input capture signal occurs while the BUFEB of the TCRX is being set to 1, although the

ICFD will be set out, data tr ansference to the I CRD will not be performed.

Therefore, in buffer operation, the ICFD can be used as an external interrupt by setting the ICIDE

bit to 1.

This flag should be cleared by use of the software. Such setting should only be made by use of the

hardware. It is not possible to make this setting using a software.

Bit 4

ICFD Description

0 [Clearing conditions] (Initial value)

When 0 is written into the ICFD after reading the ICFD under the setting of ICFD = 1

1 [Setting conditions]

When the input capture signal has occurred

Bit 3



Output Comparing Flag A (OCFA): This status flag indicates the fact that the FRC and

the OCRA have come to a comparing match.

This flag should be cleared by use of the software. Such setting should only be made by use of the

hardware. It is not possible to make this setting using a software.

Bit 3

OCFA Description

0 [Clearing conditions] (Initial value)

When 0 is written into the OCFA after reading the OCFA under the setting of OCFA =

1 [Setting conditions]

When the FRC and the OCRA have come to the comparing match

Rev. 1.0, 02/01, page 333 of 1184

Bit 2



Output Comparing Flag B (OCFB): This status flag indicates the fact that the FRC and

the OCRB have come to a comparing match.

This flag should be cleared by use of the software. Such setting should only be made by use of the

hardware. It is not possible to make this setting using a software.

Bit 2

OCFB Description

0 [Clearing conditions] (Initial value)

When 0 is written into the OCFB after reading the OCFB under the setting of OCFB =

1 [Setting conditions]

When the FRC and the OCRB have come to the comparing match

Bit 1



Timer Over Flow (OVF): This is a status flag indicating the fact that the FRC

overflowed. (H'FFFF → H'0000).

This flag should be cleared by use of the software. Such setting should only be made by use of the

hardware. It is not possible to make this setting using a software.

Bit 1

OVF Description

0 [Clearing conditions] (Initial value)

When 0 is written into the OVF after reading the OVF under the setting of OVF = 1

1 [Setting conditions]

When the FRC value has become H'FFFF → H'0000

Bit 0



Counter Clearing (CCLRA): This bit works to select if or not to clear the FRC by

occurrence of comparing match A (matching signal of the FRC and OCRA).

Bit 0

CCLRA Description

0 Prohibits clearing of the FRC by occurrence of comparing match A (Initial value)

1 Permits clearing of the FRC by occurrence of comparing match A

Rev. 1.0, 02/01, page 334 of 1184

16.2.6 Timer Control Register X (TCRX)

R/WR/W

IEDGB

R/W

IEDGA

R/W

IEDGD

R/W

IEDGC

R/W

BUFEB

R/W

BUFEA CKS0

R/W

CKS1

Bit :

Initial value :

R/W :

The TCRX is an 8-bit read/write register that selects the input capture signal edge, designates the

buffer operation, and selects the in putting clock for the FRC.

The TCRX is initialized to H'00 when reset or under the standby mode, watch mode, subsleep

mode, module stop mode or subactive mode.

Bit 7



Input Capture S ignal Edge Selection A ( IEDG A): This bit works to select the risin g

edge or falling edge of the input capture signal A (FTIA).

Bit 7

IEDGA Description

0 Captures the falling edge of the input capture signal A (Initial value)

1 Captures the rising edge of the input capture signal A

Bit 6



Input Capture S ignal Edge Selectio n B (IEDGB): This bit works to select the rising

edge or falling edge of the input capture signal B (FTIB).

Bit 6

IEDGB Description

0 Captures the falling edge of the input capture signal B (Initial value)

1 Captures the rising edge of the input capture signal B

Bit 5



Input Capture S ignal Edge Selection C ( IEDG C): This bit works to select the risin g

edge or falling edge of the input capture signal C (FTIC). However, when the DVCTL has been

selected as the signal for the input capture signal edge selection C, this bit will not influence the

operation.

Bit 5

IEDGC Description

0 Captures the falling edge of the input capture signal C (Initial value)

1 Captures the rising edge of the input capture signal C

Rev. 1.0, 02/01, page 335 of 1184

Bit 4



Input Capture S ignal Edge Selection D ( IEDG D): This bit works to select the risin g

edge or falling edge of the input capture signal D (FTID).

Bit 4

IEDGD Description

0 Captures the falling edge of the input capture signal D (Initial value)

1 Captures the rising edge of the input capture signal D

Bit 3



Buffer Enabling A (BUF EA ): This bit works to select whethe r or not to use the ICRC as

the buffer register for the ICRA.

Bit 3

BUFEA Description

0 Not using the ICRC as the buffer register for the ICRA (Initial value)

1 Usi ng the ICRC as the buffer register for the ICRA

Bit 2



Buffer Enabling B (BUFEB): This bit wor ks to select whether or not to use the ICRD as

the buffer register for the ICRB.

Bit 2

BUFEB Description

0 Not using the ICRD as the buffer register for the ICRB (Initial value)

1 Usi ng the ICRD as the buffer register for the ICRB

Bits 1 and 0



Clock Select (CKS1, CKS0): These bits work to select the inputting clo c k to the

FRC from among three types of internal clocks and the DVCFG.

The DVCFG is the edge detecting pulse selected by the CFG dividing timer.

Bit 1 Bit 0

CKS1 CKS0 Description

0 0 Internal clock: Counts at φ/4 (Initial value)

0 1 Internal clock: Counts at φ/16

1 0 Internal clock: Counts at φ/64

1 1 DVCFG: The edge detecting pulse selected by the CFG dividing timer

Rev. 1.0, 02/01, page 336 of 1184

16.2.7 Timer Output Comparing Control Register (TOCR)

R/W R/W

ICSC

R/W

ICSB

R/W

OCRS

R/W

ICSD

R/W

OEB

R/W

OEA OLVLB

R/W

OLVLA

Bit :

Initial value :

R/W :

The TOCR is an 8-bit read/write register that select input capture signals and output comparing

output level, permits output comparing outputs, and controls switching over of the access of the

OCRA and OCRB. See section 16.2.4, Timer Interrupt Enabling Register (TIER) regarding the

input capture inputs A.

The TOCR is initialized to H'00 when reset or under the standby mode, watch mode, subsleep

mode, module stop mode or subactive mode.

Bit 7



Selecting the Input Capture B Signals (ICSB): This bit works to select the input capture

B signals.

Bit 7

ICSB Description

0 Selects the FTIB pin for inputting of the input capture B signals (Initial value)

1 Selects the VD as the input capture B signals

Bit 6



Selecting the Input Capture C Signals (ICSC): This bit works to select the input capture

C signals. The DVCTL is the edge detecting pulse selected by the CTL dividing timer.

Bit 6

ICSC Description

0 Selects the FTIC pin for inputting of the input capture C signal s (Initial value)

1 Selects the DVCTL as the input capture C signals

Bit 5



Selecting the Input Capture D Signals (ICSD): This bit works to select the input capture

D signals.

Bit 5

ICSD Description

0 Selects the FTID pin for inputting of the input capture D signal s (Initial value)

1 Selects the NHSW as the input capture D signals

Rev. 1.0, 02/01, page 337 of 1184

Bit 4



Selecting the Output Comparing Register (OCRS): The addresses of the OCRA and

OCRB are the same. The OCRS works to control which register to choose when reading/writing

this address. The choice will n ot influence the operation of the OCRA and OCRB.

Bit 4

OCRS Description

0 Selects the OCRA register (Initial value)

1 Selects the OCRB register

Bit 3



Enabling the Output A (OEA): This bit wor ks to control the output comparing A signals.

Bit 3

OEA Description

0 Prohibits the output comparing A signal outputs (Initial value)

1 Permits the output comparing A signal outputs

Bit 2



Enabling the Output B (OEB): This bit wor ks to control the output comparing B signals.

Bit 2

OEB Description

0 Prohibits the output comparing B signal outputs (Initial value)

1 Permits the output comparing B signal outputs

Bit 1



Output Level A (OLVLA): This bit works to select the output level to output through the

FTOA pin by use of the comparing match A (matching signal between the FRC and OCRA).

Bit 1

OLVLA Description

0 Low level (Initial value)

1 High level

Rev. 1.0, 02/01, page 338 of 1184

Bit 0



Output Level B (OLVLB): This bit works to select the output level to ou tput through th e

FTOB pin by use of the comparing match B (matching signal between the FRC and OCRB).

Bit 0

OLVLB Description

0 Low level (Initial value)

1 High level

16.2.8 Module Stop Control Register (MSTPCR)

MSTP15

R/W

MSTPCRH

MSTP14

R/W

MSTP13

R/W

MSTP12

R/W

MSTP11

R/W

MSTP10

R/W

MSTP9

R/W

MSTP8

R/W

MSTP7

R/W

MSTP6

R/W

MSTP5

R/W

MSTP4

R/W

MSTP3

R/W

MSTP2

R/W

MSTP1

R/W

MSTP0

R/W

MSTPCRL

Initial value :

R/W :

Bit :

The MSTPCR consists of twin 8-bit read/write registers that control the module stop mode.

When the MSTP10 bit is set to 1, the Timer X1 stops its operation at the ending point of the bus

cycle to shift to the module stop mode. For more information, see section 4.5, Module Stop

Mode.

When reset, the MSTPCR is initialized to H'FFFF.

Bit 2



Module Stop ( MSTP1 0): This bit works to designate the module stop mode for timer X1.

MSTPCRH

Bit 2

MSTP10 Description

0 Cancels the module stop mode of the Timer X1

1 Sets the module stop mode of the Timer X1 (Initial value)

Rev. 1.0, 02/01, page 339 of 1184

16.3 Operation

16.3.1 Operation of Timer X1

• Output Comparing Operation

Right after resetting, the FRC is initialized to H'0000 to start counting up. The inputting clock

can be selected from among three different types of internal clocks or the external clock by

setting the CKS1 and CKS0 of the TCRX.

The contents of the FRC are always being compared with the OCRA and OCRB and, when

the value of these two match, the level set by th e the OLVLA and OLVLB of the TOCR is

output through the FTOA pin and FTOB pin.

After resetting , 0 will be output through th e FTOA and FTOB pins u ntil the first comp are

matching occurs.

Also, when the CCLRA of the TCSRX is being set to 1, th e FRC will be clear ed to H'0000

when the comparing match A occurs.

• Input Capturing Operation

Right after resetting, the FRC is initialized to H'0000 to start counting up. The inputting clock

can be selected from among three different types of internal clocks or the external clock by

setting the CKS1 and CKS0 of the TCRX.

The inputs are transferred to the IEDGA through IEDGD of the TCRX through the FTIA

through FTID pins and, at the same time, the ICFA through ICFD of the TCSRX are set to 1.

At this time, if the ICIAE through ICIED of the TIER are being set to 1, due interrupt request

will be issued to the CPU.

When the BUFEA a nd BUFEB of the TCRX ar e set to 1, the ICRC and ICRD wo rk as the

buffer register, respectively, of the ICRA and ICRB. When the edge selected by setting the

IEDGA through IEDGD of the TCRX is input through the FTIA and FTIB pins, the value at

the time of the FRC is transferred to the ICRA and ICRB and, at the same time, the values of

the ICRA a nd ICRB b efore updating are transferred to the ICRC a nd ICRD. A t this time,

when the ICFA and ICFB are being set to 1 and if the ICIAE and ICIBE of the TIER are being

set to 1, du e interr upt r e quest will be issued to th e CPU.

Rev. 1.0, 02/01, page 340 of 1184

16.3.2 Counting Timing of the FRC

The FRC is counted up by the inputting clock. By setting the CKS1 and CKS0 of the TCRX, the

inputting clock can be selected from among three different types of clocks (φ/4, φ/16 and φ/64)

and the DVCFG.

• Internal Clock Operation

By setting the CKS1 and CKS0 bits of the TCRX, three types of internal clocks (φ/4, φ/16 and

φ/64), generated by dividing the system clock (φ) can be selected. Figure 16.3 shows the

timing chart.

FRC

Internal clock

FRC input

clock

NN-1 N+1

Figure 16.3 Count Timing for Internal Clock Operation

• DVCFG Clock Operation

By setting the CKS1 and CKS0 bits of the TCRX to 1, DVCFG clock input can be selected.

The DVCFG clock makes counting by use of the edge detecting pulse being selected by the

CFG dividing timer.

Figure 16.4 shows the timing chart.

FRC

CFG

FRC input

clock

NN+1

DVCFG

Figure 16.4 Count Timing for CFG Clock Operation

Rev. 1.0, 02/01, page 341 of 1184

16.3.3 Output Comparing Signal Outputting Timing

When a comparing match occurs, the output level having been set by the OLVL of the TOCR is

output through the output comparing signal outputting pins (FTOA and FTOB).

Figure 16.5 shows the timin g chart fo r the output comparing signal outputting A.

FRC

OLVLA

FTOA

Output comparing

signal outputting

A pin

↓ Clearing*

N+1

Comparing match

signal

OCRA

Note: * Execution of the command is to be designated by the software.

Figure 16.5 Output Comparing Signal Outputting A Timing

16.3.4 FRC Clearing Timing

The FRC can be cleared when the comparing match A occurs. Figure 16.6 shows the timing chart.

FRC

Comparing match

A signal

NH' 0000

Figure16.6 Clearing Timing by Occurrence of the Comparing Match A

Rev. 1.0, 02/01, page 342 of 1184

16.3 .5 Input Capture Signal Inputting Timing

• Input Capture Signal Inputting Timing

As for the input capture signal inputting, rising or falling edge is selected by settings of the

IEDGA through IEDGD bits of the TCRX.

Figure 16.7 shows the timing chart when the rising edge is selected (IEDGA through IEDGD =

1).

Input capture signal

inputting pin

Input capture signal

Figure 16.7 Input Capture Signal Input ting Timing ( under normal state)

• Input Capture Signal Inputting Timing when Making Buffer Operation

Buffer operation can be made using the ICRA or ICRD as the buffer of the ICRA or ICRB.

Figure 16.8 shows the input capture signal inputting timing chart in case both of the rising and

falling edges are designated (IEDGA = 1 and IEDGC = 0, or IEDGA = 0 and IEDGC = 1),

using the ICRC as the buffer register for the ICRA (BUFEA = 1).

Input capture

signal

FTIA

FRC

ICRA

ICRC

nn+1 N

Figure 16.8 Input Capture Signal Inp ut t ing Timing Chart Under the Buffer Mode

(under normal state)

Rev. 1.0, 02/01, page 343 of 1184

Even when the ICRC or ICRD is used as the b uffer re gister, the input capture flag will be set up

corresponding to the designated edge change of respective input capture signals.

For example, when using the ICRC as the buffer register for the ICRA, when an edge change

having been designated by the IEDGC bit is detected with the input capture signals C and if the

ICIEC bit is du ly set, an interrupt re quest will be issued.

However, in this case, the FRC value will n ot be transferred to th e I CRC.

16.3.6 Input Capture Flag ( ICF A through ICFD) Setting Up Timing

The input capture signal works to set the ICFA through ICFD to 1 and, simultaneously, the FRC

value is transferred to the corresponding ICRA through ICRD. Figure 16.9 shows the timing

chart.

Input capture

signal

ICFA to ICFD

ICRA to ICRD

FRC

Figure 16.9 ICFA through ICFD Setting Up Timing

Rev. 1.0, 02/01, page 344 of 1184

16.3.7 Output Comparing Flag (OCFA and OCFB) Setting Up Timing

The OCFA and OCFB are being set to 1 by the co mparing match signal being output when the

values of the OCRA, OCRB and FRC match. The comparing match signal is generated at the last

state of the value match (the timing of the FRC's updating the matching count reading).

After the values of the OCRA, OCRB and FRC match, up until the count up clock signal is

generated , the comparing match signal will not be issued. Figure 16.10 sho ws the OCFA and

OCFB setting timing chart.

Comparing match

signal

OCFA, OCFB

OCRA, OCRB

FRC N

N+1

Figure 16.10 OCF Setting Up Timing

16.3.8 Overflow Flag (CVF) Setting Up Timing

The OVF is set to when the FRC over flows (H'FFFF → H'0000). Figure 16.11 shows the timing

chart.

Overflowing

signal

FRC H'FFFF H'0000

OVF

Figure 16.11 OVF Setting Up Timing

Rev. 1.0, 02/01, page 345 of 1184

16.4 Operation Mode of Timer X1

Table 16.4 indicated below shows the operation mode of Timer X1.

Table 16.4 Operation Mode of Timer X1

Operation

Mode Reset Active Sleep Watch Subactive Standby Subsleep

Module

Stop

FRC Reset Functions Functions Reset Reset Reset Reset Reset

OCRA, OCRB Reset Functions Functions Reset Reset Reset Reset Reset

ICRA to ICRD Reset Functions Functions Reset Reset Reset Reset Reset

TIER Reset Functions Functions Reset Reset Reset Reset Reset

TCRX Reset Functions Functions Reset Reset Reset Reset Reset

TOCR Reset Functions Functions Reset Reset Reset Reset Reset

TCSRX Reset Functions Functions Reset Reset Reset Reset Reset

Rev. 1.0, 02/01, page 346 of 1184

16.5 Interrupt Causes

Total seven interrupt causes exist with Timer X1, namely, ICIA through ICID, OCIA, OCIB and

FOVI. Table 16.5 lists the contents of interrup t cau ses. Interr upt requests can be permitted or

prohibited by setting interrupt enabling bits of the TIER. Also, independent vector addresses are

allocated to respective interrupt causes.

Table 16.5 Interrupt Causes of Timer X1

Abbreviations of the Interrupt Causes Priority Degree Contents

ICIA Interrupt request by the ICFA

ICIB Interrupt request by the ICFB

ICIC Interrupt request by the ICFC

ICID Interrupt request by the ICFD

OCIA Interrupt request by the OCFA

OCIB Interrupt request by the OCFB

FOVI Interrupt request by the OVF

High

Low

Rev. 1.0, 02/01, page 347 of 1184

16.6 Exemplary Uses of Timer X1

Figure 16.12 shows an example of outputting at optional phase difference of the pulses of the 50%

duty. For this setting, follow the procedures listed below.

1. Set the CCLRA bit of the TCSRX to 1.

2. Each time a comparing match occurs, the OLVIA bit and the OLVLB bit are reversed by use

of the software.

H'FFFF

OCRA

OCRB

H'0000

FTOA

FTOB

Clearing the

counter

FRC

Figure 16.12 Pulse Outputting Example

Rev. 1.0, 02/01, page 348 of 1184

16.7 Precautions when Using Timer X1

Pay great attention to the fact that the following competition s and operations occur during

operation of timer X1.

16.7.1 Competition between Writing and Clearing with the FRC

When a counter clearing signal is issued under the T2 state where the FRC is under the writing

cycle, writing in to the FRC will not be eff ected and the prio rity will b e given to clearing of the

FRC.

Figure 16.13 shows the timing chart.

Address FRC address

Internal writing

signal

Counter clearing

signal

FRC N H'0000

T1 T2

Writing cycle with the FRC

Figure 16.13 Competition between Writing and Clearing with the FRC

Rev. 1.0, 02/01, page 349 of 1184

16.7.2 Competition between Writing and Co unting Up with the FRC

When a counting up cause occurs under the T2 state where the FRC is under the writing cycle, the

counting up will not be effected and the priority will be given to count writin g.

Figure 16.14 shows the timing chart.

Address

FRC address

Internal writing

signal

Inputting clock

to the FRC

Writing data

FRC N M

T1 T2

Writing cycle with the FRC

Figure 16.14 Competition between Writing and Counting Up with the FRC

Rev. 1.0, 02/01, page 350 of 1184

16.7.3 Competition between Writing and Comparing Match with the OCR

When a comparing match occurs under the T2 state where the OCRA and OCRB are under the

writing cycle, th e prio rity will be given to writing of th e OCR and th e comparing match signa l will

be prohibited.

Figure 16.15 shows the timing chart.

Address OCR address

Internal writing

signal

Comparing match

signal

FRC

Writing data

Will be prohibited

OCR N M

NN+1

T1 T2

Writing cycle with the OCR

Figure 16.15 Competition between Writing and Comparing Match with the OCR

Rev. 1.0, 02/01, page 351 of 1184

16.7.4 Changing Over the Internal Clocks and Counter Operations

Depending on the timing of changing over the internal clocks, the FRC may count up. Table 16.6

shows the relations between the timing of changing over the internal clocks (Re-writing of the

CKS1 and CKS0) and the FRC operations.

When using an internal clock, the counting clock is being generated detecting the falling edge of

the internal clock dividing the system clock (φ). For this reason, like Item No. 3 of table 16.6,

count clock signals are issued deeming the timing before the changeover as the falling edge to

have the FRC to count up.

Also, when changing over between an internal clock and the external clock, the FRC may count

up.

Table 16.6 Changing Over the Internal Clocks and the FRC Operation

No. Rewriting Timing for

the CKS1 and CKS0 FRC Operation

1 Low → low level

changeover

Clock before

the changeover

Clock after

the changeover

Count

clock

FRC

Rewriting of the CKS1 and CKS0

NN+1

2 Low → High level

changeover

Clock before

the changeover

Clock after

the changeover

Count

clock

FRC

Rewriting of the CKS1 and CKS0

N N+1 N+2

Rev. 1.0, 02/01, page 352 of 1184

No. Rewriting Timing for

the CKS1 and CKS0 FRC Operation

3 High → low level

changeover

Clock before

the changeover

Clock after

the changeover

Count

clock

FRC

Rewriting of the CKS1 and CKS0

N+1 N+2

4 High → high level

changeover

Clock before

the changeover

Clock after

the changeover

Count

clock

FRC

Rewriting of the CKS1 and CKS0

N N+1 N+2

Note: * The count clock signals are issued determining the changeover timi ng as the falling edge to

have the FRC to count up.

Rev. 1.0, 02/01, page 353 of 1184

Section 17 Watchdog Timer (WDT)

17.1 Overview

This LSI has an on-chip watchdog timer with one channel (WDT) for monitoring system

operation. The WDT outputs an overflow signal if a sy stem crash prevents the CPU from writing

to the timer counter, allowing it to overflow. At the same time, the WDT can also g e n erate an

internal reset sig nal or internal NMI interrupt signal.

When this watchdog function is not needed, the WDT can be used as an interval timer. In interval

timer mode, an interval timer interrupt is generated each time the counter overflows.

17.1.1 Features

WDT features are listed below.

• Switchable between watchdog timer mode and interval timer mode

 WOVI interrupt generation in interval timer mode

• Internal reset or internal interrupt generated when the timer counter overflows

 Choice of internal reset or NMI interrupt generation in watchdog timer mode

• Choice of 8 counter input clocks

 Maximum WDT interval: system clock period × 131072 × 256

Rev. 1.0, 02/01, page 354 of 1184

17.1.2 Block Diagram

Figure 17.1 shows block diagram of WDT.

Overflow

Interrupt

control

Reset

control

WOVI

(Interrupt request signal)

Internal reset signal*

WTCNT WTCSR

φ / 2

φ / 64

φ / 128

φ / 512

φ / 2048

φ / 8192

φ / 32768

φ / 131072

Clock Clock

select

Internal clock

source

Bus

interface

Module bus

WTCSR

WTCNT

Note: * The internal reset signal can be generated by means of a register setting.

: Timer control/status register

: Timer counter

Internal bus

WDT

Legend:

Internal NMI

interrupt request signal

Figure 17.1 Block Diagram of WDT

Rev. 1.0, 02/01, page 355 of 1184

17.1.3 Register Configuration

The WDT has two registers, as described in table 17.1. These registers control clock selection,

WDT mode switching, the reset signal, etc.

Table 17.1 WDT Registers

Address*1

Name Abbrev. R/W Initial Value Write*2 Read

Watchdog timer

control/status register WTCSR R/ (W)*3 H'00 H'FFBC H'FFBC

Watchdog timer coun ter WTCNT R/W H'00 H'FFBC H'FFBD

System control regi ster SYSCR R/W H'09 H'FFE8 H'FFE8

Notes: 1. Lower 16 bits of the address.

2. For details of write operations, see section 17.2.4, Notes on Register Access.

3. Only 0 can be written in bit 7, to clear the flag.

Rev. 1.0, 02/01, page 356 of 1184

17.2 Register Descriptions

17.2.1 Watchdog Timer Counter (WTCNT)

R/W

Bit :

Initial value :

R/W :

TCNT is an 8-bit readable/writable* up-counter.

When the TME bit is set to 1 in WTCSR, WTCNT starts countin g pulses generated fro m the

internal clock source selected by bits CKS2 to CKS0 in WTCSR. When the count overflows

(changes from H'FF to H'00), the OVF flag in WTCSR is set to 1.

WTCNT is initialized to H'0 0 by a reset, or when the TME bit is cleared to 0.

Note: * WTCNT is write-protected b y a password to prevent accidental overwriting. For

details see section 17.2.4, Notes on Register Access.

17.2.2 Watchdog Timer Control/Status Register (WTCSR)

OVF

R/(W)*

WT/IT

R/W

TME

R/W

—

RST/NMI

R/W

CKS0

R/W

CKS2

R/W

CKS1

R/W

Note: * Only 0 can be written to clear the flag.

Bit :

Initial value :

R/W :

WTCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to

be input to WTCNT, and the timer mode.

WTCSR is initialized to H'00 by a r e set.

Note: * WTCSR is write-protected by a password to prevent accidental overwriting. For

details see section 17.2.4, Notes on Register Access.

Rev. 1.0, 02/01, page 357 of 1184

Bit 7



Overflow Flag (OVF): A status flag that indicates that WTCNT has overflowed from

H'FF to H'00.

Bit 7

OVF Description

0 [Clearing conditions] (Initial value)

1. Write 0 in the TME bit

2. Read WTCSR when OVF = 1*, then write 0 in OVF

1 [Setting condition]

When WTCNT overflows (changes from H'FF to H'00)

When internal reset request generation is selected in watchdog timer mode, OVF is

cleared automatically by the internal reset

Note: * When OVF is polled and the interval timer interrupt is disabled, OVF=1 must be read at

least twice.

Bit 6



Timer Mode Select (WT/IT

ITIT

IT): Selects whether the WDT is used as a watchdog timer or

interval timer. If used as an interval timer, the WDT generates an interv al tim er interrupt request

(WOVI) when TCNT overflows. If used as a watchdog timer, the WDT generates a reset or NMI

interrupt when TCNT overflows.

Bit 6

WT/IT

ITIT

IT Description

0 Interval timer mode: Sends the CPU an interval ti mer interrupt request (WOVI) when

WTCNT overflows (Initial value)

1 Watchdog timer mode: Sends the CPU a reset or NMI interrupt request when

WTCNT overflows

Bit 5



Timer Enable (TME): Selects whether WTCNT runs or is halted.

Bit 5

TME Description

0 WTCNT is initialized to H'00 and halted (Initial value)

1 WTCNT counts

Bit 4



Reserved: This bit should not be set to 1.

Rev. 1.0, 02/01, page 358 of 1184

Bit 3



Reset or NMI (RST/NMI

NMINMI

NMI): Specifies whether an internal reset or NMI interrupt is

requested on WTCNT overflow in watchdog timer mode.

Bit 3

RST/NMI

NMINMI

NMI Description

0 An NMI interrupt request is generated (Initial value)

1 An internal reset request is generated

Bits 2 to 0



Clock Select 2 to 0 (CKS2 to CKS0): These bits select an internal clock source,

obtained by dividing the system clock (φ) for input to WTCNT.

WDT Input Clock Selection

Bit 2 Bit 1 Bit 0 Description

CSK2 CSK1 CSK0 Clock Overflow Period* (when φ

φφ

φ = 10 MHz)

0 φ/2 (Initial

value) 51.2 µs 0

1 φ/64 1.6 ms

0 φ/128 3.3 ms

1 φ/512 13.1 ms

0 φ/2048 52.4 ms 0

1 φ/8192 209.7 ms

0 φ/32768 838.9 ms

1 φ/131072 3.36 s

Note: * The overflow period is the time from when WTCNT starts counting up from H'00 until

overflow occurs.

Rev. 1.0, 02/01, page 359 of 1184

17.2.3 System Control Register (SYSCR)

—

INTM1

INTM0

R/W

XRST

—

Bit :

Initial value :

R/W :

Only bit 3 is described here. For details on functions not related to the watchdog timer, see

sections 3.2.2 and 6.2.1, System Control Register (SYSCR), and the descriptions of the relevant

modules.

Bit 3



External Reset (XRST): Indicates the reset source. When the watchdog timer is used, a

reset can be generated by watchdog timer overflow in addition to external reset input. XRST is a

read-only bit. It is set to 1 by an external reset, and cleared to 0 by watchdog timer overflow.

Bit 3

XRST Description

0 Reset is generated by watchdog timer overflow

1 Reset is generated by external reset input (Initial value)

Rev. 1.0, 02/01, page 360 of 1184

17.2.4 Notes on Register Access

The watchdog timer's WTCNT and WTCSR registers differ from other registers in being more

difficult to write to. The procedures for writing to and reading these registers are given below.

• Writing to WTCNT and WTCSR

These registers mu st be written to by a word tran sf er instruction. They cannot be written to

with byte tran sfer instructions.

Figure 17.2 shows the form at of data written to WTCNT and WTCSR. WTCNT and WTCSR

both have the same write address. For a write to WTCNT, the upper byte of the written word

must contain H'5A and the lower byte must contain the write data. For a write to WTCSR, the

upper byte of the written word must contain H'A5 and the lower byte must contain the write

data. This transf er s the write data from the lower byte to WTCNT or WTCSR.

Address : H'FFBC

H'5A Write data

15 8 7 0

H'A5 Write data

15 8 7 0

Figure 17.2 Format of Data Written to WTCNT and WTCSR

• Reading WTCNT and WTCSR

These registers are read in the same way as other registers. The read addresses are H'FFBC for

WTCSR, and H'FFBD for WTCNT.

Rev. 1.0, 02/01, page 361 of 1184

17.3 Operation

17.3.1 Watchdog Timer Operation

To use the WDT as a watchdog timer, set the WT/IT and TME bits in WTCSR to 1. So ftware

must prevent WTCNT overflows by rewriting the WTCNT value (normally by writing H'00)

before overflow occurs. This ensures that WTCNT does not overflow while the system is

operating normally. If WTCNT overflows without being rewritten because of a system crash or

other error, the chip is reset, or an NMI interrupt is generated, for 518 system clock periods (518

φ). This is illustrated in figure 17.3.

An internal reset request from the watchdog timer and reset input from the RES pin are handled

via the same vector. The reset source can be identified from the value of the XRST bit in SYSCR.

If a reset caused by an input signal from the RES pin and a reset caused by WDT overflow occur

simultaneously, the RES pin reset has priority, and the XRST bit in SYSCR is set to 1.

WTCNT value

H'00 Time

H'FF

WT/IT=1

TME=1 H'00 written

to WTCNT WT/IT=1

TME=1 H'00 written

to WTCNT

518 system clock period

Internal reset

signal

WT/IT

TME

Legend:

Overflow

Internal reset

generated

OVF=1*

: Timer mode select bit

: Timer enable bit

Note: * Cleared to 0 by an internal reset when OVF is set to 1. XRST is cleared to 0.

Figure 17.3 Operation in Watchdog Timer Mode (when Reset)

Rev. 1.0, 02/01, page 362 of 1184

17.3.2 Interval Timer Operation

To use the WDT as an interval timer, clear the WT/IT bit in WTCSR to 0 and set the TME bit to

1. An interval timer interrupt (WOVI) is generated each time WTCNT overflows, provided that

the WDT is operating as an interval timer, as shown in figure 17.4. This function can be used to

generate interrupt requests at regular intervals.

WTCNT value

H'00 Time

H'FF

WT/IT=0

TME=1 WOVI

Overflow Overflow Overflow Overflow

WOVI : Interval timer interrupt request generation

WOVI WOVI WOVI

Figure 17.4 Operation in Interval Timer Mode

Rev. 1.0, 02/01, page 363 of 1184

17.3.3 Timing of Setting of Overflow Flag (OVF)

The OVF bit in WTCS R is set to 1 if WTCNT overflows during interval timer opera tion. At the

same time, an interval timer interrupt (WOVI) is requ e sted. This timing is sh own in figure 17.5.

If NMI request generation is selected in watchdog timer mode, when WTCNT overflows the OVF

bit in WTCSR is set to 1 and at the sam e time an NMI interrupt is r e quested.

WTCNT H'FF H'00

Overflow signal

(internal signal)

OVF

Figure 17.5 Timing of OVF Setting

Rev. 1.0, 02/01, page 364 of 1184

17.4 Interrupts

During interval tim er mode operation, an overflow gen erates an in terval timer interrupt (WOVI).

The interval tim er interrupt is r equested whenever the OVF flag is set to 1 in WTCSR. OVF must

be cleared to 0 in the interrupt handling routine. When NMI interrupt request generation is

selected in watchdog timer mode, an overflow generates an NMI interrupt request.

17.5 Usage Notes

17.5.1 Contention between Watchdog Timer Counter (WTCNT) Write and Increment

If a timer counter clock pulse is generated during the T2 state of a WTCNT write cycle, the write

takes priority and the timer counter is not incremented. Figure 17.6 shows this operation.

Internal address

Internal φ

Internal write

signal

WTCNT input

clock

WTCNT NM

WTCNT write cycle

Counter write data

Figure 17.6 Contention between WTCNT Write and Increment

Rev. 1.0, 02/01, page 365 of 1184

17.5.2 Changing Value of CKS2 to CKS0

If bits CKS2 to CKS0 in WTCSR are written to while the WDT is ope r ating, errors could occur in

the incrementation. Software must stop the watch dog timer (by clearing the TME bit to 0) before

changing the value of bits CKS2 to CKS0.

17.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode

If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is

operating, correct operation cannot be guaranteed. Software must stop the watchdog timer (by

clearing the TME bit to 0) befo re switching the mode.

Rev. 1.0, 02/01, page 366 of 1184

Rev. 1.0, 02/01, page 367 of 1184

Section 18 8-Bit PWM

18.1 Overview

The 8-bit PWM incorporates 4 channels of the duty control method (H8S/2197S and H8S/2196S:

2 channels). Its outputs can be used to control a reel motor or loading motor.

18.1.1 Features

• Conversion period: 256-state

• Duty control me th od

18.1.2 Block Diagram

Figure 18.1 shows a block diagram of the 8-bit PWM (1 channel).

PWMn

OVF

Match signal

Legend:

PWRn

PW8CR: 8-bit PWM data register n

: 8-bit PWM control register

PWMn

OVF

Notes: n=3 to 0 (H8S/2197S and H8S/2196S: n=1 and 0)

: 8-bit PWM square-wave output pin n

: Overflow signal from FRC lower 8-bit

PWRn

Free-running counter (FRC)

Comparator

PW8CR

Polarity

specification

Internal data bus

Figure 18.1 Block Diagram of 8-Bit PWM (1 channel)

Rev. 1.0, 02/01, page 368 of 1184

18.1.3 Pin Configuration

Table 18.1 shows the 8-bit PWM pin configuration.

Table 18. 1 Pin Configuration

Name Abbrev. I/O Function

8-bit PWM square-wave output pin 0 PWM0 Output 8-bit PWM square-wave output 0

8-bit PWM square-wave output pin 1 PWM1 Output 8-bit PWM square-wave output 1

8-bit PWM square-wave output pin 2 PWM2 Output 8-bit PWM square-wave output 2

8-bit PWM square-wave output pin 3 PWM3 Output 8-bit PWM square-wave output 3

18.1.4 Register Configuration

Table 18.2 shows the 8-bit PWM register configuration.

Table 18.2 8-Bit PWM Registers

Name Abbrev. R/W Size Initial Value Address*

8-bit PWM data register 0 PWR0 W Byte H'00 H'D126

8-bit PWM data register 1 PWR1 W Byte H'00 H'D127

8-bit PWM data register 2 PWR2 W Byte H'00 H'D128

8-bit PWM data register 3 PWR3 W Byte H'00 H'D129

8-bit PWM control register PW8CR R/W Byte H'F0 H'D12A

Port mode register 3 PMR3 R/W Byte H'00 H'FFD0

Note: * Lower 16 bits of the address.

Rev. 1.0, 02/01, page 369 of 1184

18.2 Register Descriptions

18.2.1 8-bit PWM Data Registers 0, 1, 2 and 3 (PWR0, PWR1, PWR2, PWR3)

PWR0

7PW04 PW03 PW02 PW01 PW00

PW07

WWW

PW06 PW05

Bit :

Initial value :

R/W :

PWR1

7PW14 PW13 PW12 PW11 PW10

PW17

WWW

PW16 PW15

Bit :

Initial value :

R/W :

PWR2

7PW24 PW23 PW22 PW21 PW20

PW27

WWW

PW26 PW25

Bit :

Initial value :

R/W :

PWR3

7PW34 PW33 PW32 PW31 PW30

PW37

WWW

PW36 PW35

Bit :

Initial value :

R/W :

8-bit PWM data registers 0, 1, 2 and 3 (PWR0, PWR1, PWR2, PWR3) control the duty cycle at 8-

bit PWM pins. The data written in PWR0, PWR1, PWR2 and PWR3 correspond to the high-level

width of one PWM output waveform cycle (256 states).

When data is set in PWR0, PWR1, PWR2 and PWR3, the co ntents of the data are latch ed in the

PWM waveform generators, updating the PWM waveform generation data.

PWR0, PWR1, PWR2 and PWR3 are 8-bit write-only registers. When read, all bits are always

read as 1.

PWR0, PWR1, PWR2 and PWR3 are initialized to H'00 by a reset.

Note: The H8S/2197S and H8S/2196S do no t have PWR2 and PWR3.

Rev. 1.0, 02/01, page 370 of 1184

18.2.2 8-bit PWM Control Register (PW8CR)

R/W

4567 ————

————

PWC3 PWC2 PWC1 PWC0

R/WR/W

1111

Bit :

Initial value :

R/W :

The 8-bit PWM co ntrol register (PW8CR) is an 8-bit read able/writab le r egister that controls PW M

functions. PW8CR is initialized to H'00 by a reset.

Bits 7 to 4



Reserved: These bits cannot be modified and are always read as 1.

Bits 3 to 0



Output Polarity Select (PWC3 t o PWC0): These bits select the output polarity of

PWMn pin between positive or negative (reverse) .

Bit n

PWCn Description

0 PWMn pin output has positive polarity (Initial value)

1 PWMn pin output has negative polarity

Notes: n=3 to 0 (H8S/2197S and H8S/2196S: n=1 and 0).

Rev. 1.0, 02/01, page 371 of 1184

18.2.3 Port Mode Register 3 (PMR3)

R/W

7PMR34 PMR33 PMR32 PMR31 PMR30

R/W

PMR37

R/W R/WR/W

PMR36 PMR35

Bit :

Initial value :

R/W :

The port mode register 3 (PMR3) controls function switching of each pin in the port 3. Switching

is specified for each bit.

The PMR3 is a 8-b it r eadable/writable register and is initialized to H'00 by a reset.

For bits other than 5 to 2, see section 10.5, Port 3.

Bits 5 to 2



P35/PWM3 to P32/PWM0 Pin Switching (PMR35 to PMR32): These bits set

whether the P3n/PWMn pin is used as I/O pin or it is used as 8-bit PWM output PWMm pin.

Bit n

PMR3n Description

0 P3n/PMWm pin functions as P3n I/O pin (Initial value)

1 P3n/PMWm pin functions as PWMm output pin

Notes: n=5 to 2, m=3 to 0. The H8S/2197S and H8S/2196S do not have PWM2 and PWM3 pin

functions.

Rev. 1.0, 02/01, page 372 of 1184

18.2.4 Module Stop Control Register (MSTPCR)

MSTP15

R/W

MSTPCRH

MSTP14

R/W

MSTP13

R/W

MSTP12

R/W

MSTP11

R/W

MSTP10

R/W

MSTP9

R/W

MSTP8

R/W

MSTP7

R/W

MSTP6

R/W

MSTP5

R/W

MSTP4

R/W

MSTP3

R/W

MSTP2

R/W

MSTP1

R/W

MSTP0

R/W

MSTPCRL

Bit :

Initial value :

R/W :

The MSTPCR consists of two 8-bit readable/writable registers that control module stop mode.

When MSTP4 bit is set to 1, the 8-bit PWM stops its operation upon completion of the bus cycle

and transits to the module stop mode. For details, see section 4.5, Module Stop Mode.

The MSTPCR is initialized to H'FFFF by a reset.

Bit 4



Module Stop ( MSTP4 ): This bit sets the module stop mode of the 8 -bit PWM.

MSTPCRL

Bit 4

MSTP4 Description

0 8-bit PWM module stop mode is released

1 8-bit PWM module stop mode is set (Initial value)

Rev. 1.0, 02/01, page 373 of 1184

18.3 8-Bit PWM Operation

The 8-bit PWM outputs PWM pulses having a cycle length of 256 states and a pulse width

determined by the data registers (PWR).

The output PWM pulse can be converted to a DC voltage through integration in a low-pass filter.

Figure 18.2 shows the output waveform example of 8-bit PWM. The pulse width (Twidth) can be

obtained by the following expression:

Twidth = (1/φ) × (PWR setting value)

T width

Pulse width

T width

Pulse cycle

(256 states)

T width

Pulse width

T width

Pulse cycle

(256 states)

H'00

PWRn setting

value

H'FFFRC lower

8-bit value

PWRn pin

output (Positive

polarity)

(n=3 to 0)

(Negative

polarity)

Figure 18.2 8-bit PWM Output Waveform (Example)

Rev. 1.0, 02/01, page 374 of 1184

Rev. 1.0, 02/01, page 375 of 1184

Section 19 12-Bit PWM

19.1 Overview

The 12-bit PWM incorporates 2 channels of the pulse pitch control method and functions as the

drum and capstan motor controller.

19.1.1 Features

Two on-chip 12-bit PWM signal generators are provided to control motors. These PWMs use the

pulse-pitch control method (periodically overriding part of the output). This reduces low-

frequency components in the pulse output, enabling a quick response without increasing the clock

frequency. The pitch of the PWM signal is modified in response to error data (representing lead

or lag in relation to a preset speed and phase).

Rev. 1.0, 02/01, page 376 of 1184

19.1.2 Block Diagram

Figure 19.1 shows a block diagram of the 12-bit PWM (1 channel). The PWM signal is generated

by combining quantizing pulses from a 12-bit pulse generator with quantizing pulses derived from

the contents of a data register. Low-frequency components are reduced because the two

quantizing pulses have different frequencies. The error data is represented by an unsigned 12-bit

binary number.

Internal data bus

Legend:

Note: * Refer to section 26, Servo Circuit.

CAPPWM

DRMPWM

CAPPWM

φ/2

φ/4

φ/8

φ/16

φ/32

φ/64

φ/128

DRMPWM : Capstan mix pin

: Drum mix pin

PWM control register

Digital filter

circuit

Error data

PTON

PWM data register

Output control circuit

Pulse generator

Counter

DFUCR*

CP/DP

Figure 19.1 Block Diagram of 12-Bit PWM (1 channel)

Rev. 1.0, 02/01, page 377 of 1184

19.1.3 Pin Configuration

Table 19.1 shows the 12-bit PWM pin configuration.

Table 19. 1 Pin Configuration

Name Abbrev. I/O Function

Capstan mix CAPPWM

Drum mix DRMPWM

Output 12-bit PWM square-wave output

19.1.4 Register Configuration

Table 19.2 shows the 12-bit PWM register configuration.

Table 19.2 12-Bit PWM Registers

Name Abbrev. R/W Size Initial Value Address*

CPWCR W Byte H'42 H'D07B 12-bit PWM control register

DPWCR W Byte H'42 H'D07A

CPWDR R/W Word H'F000 H'D07C 12-bit PWM data register

DPWDR R/W Word H'F000 H'D078

Note: * Lower 16 bits of the address.

Rev. 1.0, 02/01, page 378 of 1184

19.2 Register Descriptions

19.2.1 1 2-Bit PWM Control Registers (CPWCR, DPWCR)

CPWCR

7CH/L CSF/DF CCK2 CCK1 CCK0

CPOL

WWW

CDC CHiZ

Bit :

Initial value :

R/W :

DPWCR

7DH/L DSF/DF DCK2 DCK1 DCK0

DPOL

WWW

DDC DHiZ

Bit :

Initial value :

R/W :

CPWCR is the PWM output control register for the capstan motor. DPWCR is the PWM output

control register for the drum motor. Both are 8-bit writable registers.

CPWCR and DPWCR are initialized to H'42 by a reset, or when in a power-down state except for

active medium-speed mode.

Bit 7



Polarity Invert (POL): This bit can invert the polarity of th e modulated PWM signal for

noise suppression and other purposes. This bit is invalid when fixed output is selected (when bit

DC is set to 1 ) .

Bit 7

POL Description

0 Output with positive polarity (Initial value)

1 Output with inverted polarity

Bit 6



Output Select (DC): Selects either PWM modulated output, or fixed output controlled by

the pin output bits (bits 5 and 4).

Rev. 1.0, 02/01, page 379 of 1184

Bits 5 and 4



PWM Pin Output (H iZ, H/L): When b it DC is set to 1, the 12-bit PWM output

pins (CAPPWM, DRMPWM) output a value determined by the HiZ and H/L bits. The output is

not affected by bit POL.

In power-down modes, the 12-bit PWM circuit and pin statuses are retained. Before making a

transition to a power-down mode, first set bits 6 (DC), 5 (HiZ), and 4 (H/L) of the 12-bit PWM

control registers (CPWCR and DPWCR) to select a fixed output level. Choose one of the

following settings:

Bit 6 Bit 5 Bit 4

DC HiZ H/L Output state

0 Low output (Initial value) 0

1 High output

1 * High-impedance

0 * * Modulation signal out put

Note: * Don't care

Bit 3



Output Data Select (SF/DF): Selects whether the data to be converted to PWM output is

taken from the data register or from th e digital f ilter circuit.

Bit 3

SF/DF Description

0 Modulation by error data from the digital filter circuit (Initial value)

1 Modulation by error data written in the data register

Note: When PWMs output data from the digital filter circuit, the data consisting of the speed and

phase filtering results are modulated by PWMs and output from the CAPPWM and

DRMPWM pins. However, it is possible to output only drum phase filter results from

CAPPWM pin and only capstan phase filter result from DRMPWM pin, by DFUCR settings

of the digital filter circuit. See section 26.11, Digital Filters.

Rev. 1.0, 02/01, page 380 of 1184

Bits 2 to 0



Carrier Frequency Select (CK2 to CK0): Selects the carrier frequency of th e PWM

modulated signal. Do not set them to 111.

Bit 2 Bit 1 Bit 0

CK2 CK1 CK0 Description

0 φ2 0

1 φ4

0 φ8 (Initial value)

1 φ16

0 φ32 0

1 φ64

0 φ128

1 (Do not set)

Rev. 1.0, 02/01, page 381 of 1184

19.2.2 12-Bit PWM Data Registers (DPWDR, CPWDR)

CPWDR

R/W

CPWDR1

R/W

CPWDR0

R/W

CPWDR3

R/W

CPWDR2

R/W

CPWDR5

R/W

CPWDR4

R/W

CPWDR7

R/W

CPWDR6

R/W

CPWDR9

R/W

CPWDR8

R/W

CPWDR11

R/W

CPWDR10

————

Bit :

Initial value :

R/W :

DPWDR

R/W

DPWDR1

R/W

DPWDR0

R/W

DPWDR3

R/W

DPWDR2

R/W

DPWDR5

R/W

DPWDR4

R/W

DPWDR7

R/W

DPWDR6

R/W

DPWDR9

R/W

DPWDR8

R/W

DPWDR11

R/W

DPWDR10

————

———

—

Bit :

Initial value :

R/W :

The 12-bit PWM data registers (DPWDR and CPWDR) are 12-bit readable/writable registers

in which the data to be converted to PWM output is written.

The data in these registers is converted to PWM output only when bit SF/DF of the

corresponding control register is set to 1. When the SF/DF bit is 0, the error data from the

digital filter circuit is written in the data register, and then modulated by PWM. At this time,

the error data from th e digital filter circu it can be monitored by reading the data register.

These registers can be accessed by word only, and cannot be accessed by byte. Byte access

gives unassured results.

Both registers are initialized to H'F000 by a reset or in a power-down state except for active

medium speed mode.

Rev. 1.0, 02/01, page 382 of 1184

19.2.3 Module Stop Control Register (MSTPCR)

MSTP15

R/W

MSTPCRH

MSTP14

R/W

MSTP13

R/W

MSTP12

R/W

MSTP11

R/W

MSTP10

R/W

MSTP9

R/W

MSTP8

R/W

MSTP7

R/W

MSTP6

R/W

MSTP5

R/W

MSTP4

R/W

MSTP3

R/W

MSTP2

R/W

MSTP1

R/W

MSTP0

R/W

MSTPCRL

Bit :

Initial value :

R/W :

The MSTPCR consists of two 8-bit readable/writable registers that control module stop mode.

When MSTP1 bit is set to 1, the 12-bit PWM stops its operation upon completion of the bus cycle

and transits to the module stop mode. For details, see section 4.5, Module Stop Mode.

The MSTPCR is initialized to H'FFFF by a reset.

Bit 1



Module Stop ( MSTP1 ): This bit sets the module stop mode of the 12-bit PWM.

MSTPCRL

Bit 1

MSTP1 Description

0 12-bit PWM and servo cir cuit m odule stop mode is relea se d

1 12-bit PWM and servo cir cuit m odule stop mode is set (Initial value)

Rev. 1.0, 02/01, page 383 of 1184

19.3 Operation

19.3.1 Output Waveform

The PWM signal generator combines the error data with the output from an internal pulse

generator to produce a pulse-width modulated signal.

When Vcc/2 is set as the reference value, the following conditions apply:

1. When the motor is running at the correct speed and phase, the PWM signal is output with a

50% duty cycle.

2. When the motor is running behind the correct speed or phase, it is corrected by periodically

holding part of the PWM signal low. The part held low depends on the size of the error.

3. When the motor is running ahead of the correct speed or phase, it is corrected by periodically

holding part of the PWM signal high. The part held high depends on the size of the error.

When the motor is running at the correct speed and phase, the error data is a 12-bit value

representing 1/2 (1000 0000 0000), and the PWM output has the same frequency as the selected

division clock.

After the error data has been converted into a PWM signal, the PWM signal can be smoothed into

a DC voltage by an external low-pass filter (LPF). The sm ooth e er r or d a ta can be used to control

the motor .

Figure 19.2 shows sample waveform outputs.

The 12-bit PWM pin outpu ts a low-level signal upon reset, in power-down mode or at module-

stop.

Rev. 1.0, 02/01, page 384 of 1184

Counter

Pulse Generator

PWM data register

C10

C11

C12

C13

Corresponds to Pwr3=1

Corresponds to Pwr2=1

Corresponds to Pwr1=1

Corresponds to Pwr0=1

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Pwr3 2 1 0 "L"

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12

Figure 19.2 Sample Waveform Output by 12-Bit PWM (4 Bits)

Rev. 1.0, 02/01, page 385 of 1184

Section 20 14-Bit PWM

Note: The 14-Bit PWM is not (incorporated in) provided for the H8S/2197S and H8S/2196S.

20.1 Overview

The 14-bit PWM is a pulse division type PWM that can be used for electronic tuner control, etc.

20.1.1 Features

Features of the 14-bit PWM are given below:

• Choice of two conversion periods

A conversion period of 32768/φ with a minimum modulation width of 2/φ, or a conversion

period of 16384/φ with a minimum modulation width of 1/φ, can be selected.

• Pulse division method for less ripple

Rev. 1.0, 02/01, page 386 of 1184

20.1.2 Block Diagram

Figure 20.1 shows a block diagram of the 14-bit PWM.

Legend:

PWCR

φ/4

φ/2

PWDRL

: PWM control register

: PWM data register L

PWDRU

PWM14

: PWM data register U

: PWM14 output pin

Internal data bus

PWCR

PWDRL

PWDRU

PWM waveform

generator PWM14

Figure 20.1 Block Diagram of 14-Bit PWM

20.1.3 Pin Configuration

Table 20.1 shows the 14-bit PWM pin configuration.

Table 20. 1 Pin Configuration

Name Abbrev. I/O Function

PWM 14-bit square-wave outp ut pin PWM14* Output 14-bit PWM square-wav e output

Note: * This pin also functions as P40 general I/O pin. When using this pin, set the pin function by

the port mode register 4 (PMR4). For details, see section 10.6, Port 4.

Rev. 1.0, 02/01, page 387 of 1184

20.1.4 Register Configuration

Table 20.2 shows the 14-bit PWM register configuration.

Table 20.2 14-Bit PWM Registers

Name Abbrev. R/W Size Initial Value Address*

PWM control register PWCR R/W Byte H'FE H'D122

PWM data register U PWDRU W Byte H'C0 H'D121

PWM data register L PWDRL W Byte H'00 H'D120

Note: * Lower 16 bits of the address.

Rev. 1.0, 02/01, page 388 of 1184

20.2 Register Descriptions

20.2.1 PWM Control Register (PWCR)

7———————

——————— R/W

PWCR0

Bit :

Initial value :

R/W :

The PWM contro l r e gister (PWCR) is an 8-b it r ead/write register that contr ols the 14-bit PWM

functions. PWCR is initialized to H'FE by a reset.

Bits 7 to 1



Reserved: These bits cannot be modified and are always read as 1.

Bit 0



Clock Select (PWCR0): Selects the clock supplied to the 14-bit PWM.

Bit 0

PWCR0 Description

0 The input clock is φ/2 (tφ = 2/φ) (Initial value)

The conversion period is 16384/φ, with a minimum modulation width of 1/φ

1 The input clock is φ/4 (tφ = 4/φ)

The conversion period is 32768/φ, with a minimum modulation width of 2/φ

Note: t/φ: Period of PWM clock input

Rev. 1.0, 02/01, page 389 of 1184

20.2.2 PWM Data Registers U and L (PWDRU, PWDRL)

PWDRU

7——

—— W

PWDRU0

PWDRU1

PWDRU2

PWDRU3

PWDRU4

PWDRU5

Bit :

Initial value :

R/W :

PWDRL

PWDRL0

PWDRL1

PWDRL2

PWDRL3

PWDRL4

PWDRL5

PWDRL6

PWDRL7

Bit :

Initial value :

R/W :

PWM data registers U and L (PWDRU and PWDRL) indicate high level width in one PWN

waveform cycle.

PWDRU and PWDRL form a 14-bit write-only register, with the upper 6 bits assigned to PWDRU

and the lower 8 b its to PWDRL. The value written in PWDRU and PWDRL g iv e s the total high-

level width of one PWM waveform cycle. Both PWDRU and PWDRL are accessible by byte

access only. Word access gives unassured results.

When 14- bit data is written in PWDRU and PWDRL, the contents are latched in the PWM

waveform generator and the PWM waveform generation data is updated. When writing the 14-bit

data, follow these steps:

1. Write the lo wer 8 bits to PWDRL.

2. Write the upper 6 bits to PWDRU.

Write the data fir st to PWDRL and then to PWDRU.

PWDRU and PWDRL are write-only registers. When read, all bits always read 1.

PWDRU and PWDRL are initialized to H'C000 by a reset.

Rev. 1.0, 02/01, page 390 of 1184

20.2.3 Module Stop Control Register (MSTPCR)

MSTP15

R/W

MSTPCRH

MSTP14

R/W

MSTP13

R/W

MSTP12

R/W

MSTP11

R/W

MSTP10

R/W

MSTP9

R/W

MSTP8

R/W

MSTP7

R/W

MSTP6

R/W

MSTP5

R/W

MSTP4

R/W

MSTP3

R/W

MSTP2

R/W

MSTP1

R/W

MSTP0

R/W

MSTPCRL

Bit :

Initial value :

R/W :

The module stop control register (MSTPCR) consists of two 8-bit readable/writable registers that

control the module stop mode functions.

When the MSTP5 b it is set to 1, the 14-bit PWM operation stops at the end of the bus cycle and a

transition is made to module stop mode. For details, see section 4.5, Module Stop Mode.

MSTPCR is initialized to H'FFFF by a reset.

Bit 5



Module Stop ( MSTP5 ): Specifies the module stop mode of the 14-bit PWM.

MSTPCRL

Bit 5

MSTP5 Description

0 14-bit PWM module stop mode is released

1 14-bit PWM module stop mode is set (Initial value)

Rev. 1.0, 02/01, page 391 of 1184

20.3 14-Bit PWM Operation

When using the 14-bit PWM, set the r e gisters in this sequence:

1. Set bit PWM40 to 1 in port mode register 4 (PMR4) so that pin P40/PWM14 is designated for

PWM output.

2. Set bit PWCR0 in the PWM control register (PWCR) to select a conversion period of either

32768/φ (PWCR0 = 1) or 16384/φ (PWCR0 = 0).

3. Set the output waveform data in PWM data registers U and L (PWDRU, PWDRL). Be sure to

write byte data f ir st to PWDRL and then to PWDRU. Wh en the data is written in PWDRU,

the contents of these registers are latched in the PWM waveform generator, and the PWM

waveform generation data is updated in synchronization with internal signals.

One conversion period consists of 64 pulses, as shown in figure 20.2. The total high-level width

during this period (TH) corresponds to the data in PWDRU and PWDRL. This relation can be

expressed as follows:

H = (data value in PWDRU and PWDRL + 64) × tφ/2

where to is the p e r iod of PWM cloc k input: 2/φ (bit PWCR0 = 0) or 4/φ (bit PWCR0 = 1).

If the data valu e in PWDRU and PWDRL is fr om H'3FC0 to H'3FFF, the PWM output stays high.

When the data value is H'0000, TH is calculated as follows:

H = 64 × tφ/2 = 32 ⋅ tφ

t H64t H63t H3t H2t H1

T H = t H1 + t H2 + t H3 + ... + t H64

t f1 = t f2 = t f3 = ... = t f64

t f1 t f2 t f63 t f64

1 conversion period

Figure 20.2 Waveform Output by 14-Bit PWM

Rev. 1.0, 02/01, page 392 of 1184

Rev. 1.0, 02/01, page 393 of 1184

Section 21 Prescalar Unit

21.1 Overview

The prescalar unit (PSU) has a 18-bit free running counter (FRC) that uses φ as a clock source and

a 5-bit counter that uses φW as a clock source.

21.1.1 Features

• Prescalar S (PSS)

Generates frequency division clocks that are input to peripheral functions.

• Prescalar W (PSW)

When a timer A is used as a clock time base, the PSW frequency-divides subclocks and

generates input clocks.

• Stable oscillation wait time count

During the return from the low power consumption mode excluding the sleep mode, the FRC

counts the stable oscillation wait time.

• 8-bit PWM

The lower 8 bits of the FRC is used as 8-bit PWM cycle and duty cycle generation counters.

(Conversion cycle: 256 states)

• 8-bit input cap ture by IC pins

Catches the 8 b its of 215 to 28 of the FRC according to the edge of the IC pin for remote control

receiving.

• Frequency division clock output

Can output the frequency division clock for the system clock or the frequency division clock

for the subclock from the frequency division clock output pin (TMOW).

Rev. 1.0, 02/01, page 394 of 1184

21.1.2 Block Diagram

Figure 21.1 shows a block diagram of the prescalar unit.

PWM3

ICR1

PCSR

18-bit free running counter (FRC)

φw/128

Prescalar W

φ/131072 to φ/2

Prescalar S

Internal data bus

MSB LSB

φw/4

φw/8

φw/16

φw/32

φ/32 φ/16 φ/8 φ/4

Interrupt

request

5-bit counter

IC pin

Stable oscillation

wait time count output

TMOW

MSB LSB

8 bits

6 bits 8 bits

PWM2

PWM1

PWM0

Legend:

ICR1

PCSR : Input capture register 1

: Prescalar unit control/status register

TMOW : Input capture input pin

: Frequency division clock output pin

Figure 21.1 Block Diagram of Prescalar Unit

Rev. 1.0, 02/01, page 395 of 1184

21.1.3 Pin Configuration

Table 21.1 shows the pin configuration of the prescalar unit.

Table 21. 1 Pin Configuration

Name Abbrev. I/O Function

Input capture input IC Input Prescalar unit input capture input pin

Frequency division clock

output TMOW Output Prescalar unit frequency division clock

output pin

21.1.4 Register Configuration

Table 21.2 shows the register configuration of the prescalar unit.

Table 21.2 Register Co nf iguration

Name Abbrev. R/W Size Initial Value Address*

Input capture regi ster 1 ICR1 R Byte H'00 H'D12C

Prescalar unit

control/status register PCSR R/W Byte H'08 H'D12D

Note: * Lower 16 bits of the address.

Rev. 1.0, 02/01, page 396 of 1184

21.2 Registers

21.2.1 Input Ca pt ure Register 1 (ICR1)

7ICR14 ICR13 ICR12 ICR11 ICR10

ICR17

RRR

ICR16 ICR15

Bit :

Initial value :

R/W :

Input capture register 1 (ICR1) captures 8-bit data of 215 to 28 of the FRC according to the edge of

the IC pin.

ICR1 is an 8-bit read-only register. The write operation becomes invalid. The ICR1 values are

undefined until the first capture is generated after the mode has been set to the standby mode,

watch mode, subactiv e mode, and subsleeve mode. When reset, ICR1 is initialized to H'0 0.

21.2.2 Prescalar Unit Control/Status Register (PCSR)

R/W

—

R/W

R/WR/W

ICEG

R/W

ICIE

R/(W)*

ICIF NCon/off DCS2 DCS1 DCS0

Note: * Only 0 can be written to clear the flag.

Bit :

Initial value :

R/W :

The prescalar unit control/status register (PCSR) controls the input capture function and selects the

frequency division clock that is output from the TMOW pin.

PCSR is an 8-b it r ead/write enable register. When reset, PCSR is initialized to H'08.

Bit 7



Input Capture Int errupt Flag (ICIF): Input capture inter r upt request flag. This indicates

that the input capture was performed according to the edge of the IC pin.

Bit 7

ICIF Description

0 [Clear condition] (Initial value)

When 0 is written after 1 has been read

1 [Set condition]

When the input capture was performed according to the edge of the IC pi n

Rev. 1.0, 02/01, page 397 of 1184

Bit 6



Input Capture Interrupt Enable ( ICIE): When ICIF was set to 1 by the input capture

according to the edge of the IC pin, ICIE enables and disables the generation of an input capture

interrupt.

Bit 6

ICIE Description

0 Disables the generation of an input capture interrupt (Initial value)

1 Enables the generation of an input capture interrupt

Bit 5



IC

ICIC

IC Pin Edge Select (ICEG): ICEG selects the input edge sense of the IC pin.

Bit 5

ICEG Description

0 Detects the falling edge of the IC pin input (Initial value)

1 Detects the rising edge of the IC pin input

Bit 4



Noise Cancel ON/OFF (NCon/off): NCon/off selects enable/disable of the noise cancel

function of the IC pin. For the noise cancel function, see section 21.3, Noise Cancel Circuit.

Bit 4

NCon/off Description

0 Disables the noise cancel func tion of the IC pin (Initial value)

1 Enables the noise cancel function of the IC pin

Bit 3



Reserved: This bit cannot be modified and is always read as 1.

Rev. 1.0, 02/01, page 398 of 1184

Bits 2 to 0



Frequency Division Clock Output Select (DCS2 to DCS0): DCS2 to DCS0 select

eight types of frequency division clocks that are output from the TMOW pin.

Bit 2 Bit 1 Bit 0

DCS2 DCS1 DCS0 Description

0 Outputs PSS, φ/32 (Initial value) 0

1 Outputs PSS, φ/16

0 Outputs PSS, φ/8

1 Outputs PSS, φ/4

0 Outputs PSW, φW/32 0

1 Outputs PSW, φW/16

0 Outputs PSW, φW/8

1 Outputs PSW, φW/4

Rev. 1.0, 02/01, page 399 of 1184

21.2.3 Port Mode Register 1 (PMR1)

PMR17

R/W

PMR16

R/W

PMR15

R/W

PMR14

R/W

PMR13

R/W

PMR10

R/W

PMR12

R/W

PMR11

R/W

Bit :

Initial value :

R/W :

The port mode register 1 (PMR1) controls switching of each pin function of port 1. The switching

is specified in a u nit of bit.

PMR1 is an 8-b it r ead/write enable register. Wh en reset, PMR1 is initialized to H'00 . For details,

refer to Port Mode Register 1 in section 10.3.2 Register Configuration.

Bit 7



P17/TMOW Pin Switching (PMR17): PMR17 sets whether the P17/TMOW pin is used

as a P17 I/O pin or a TMOW pin for division clock output.

Bit 7

PMR17 Description

0 The P17/TMOW pin functions as a P17 I/O pin (Initial value)

1 The P17/TMOW pin functions as a TMOW output function

Bit 6



P16/IC

ICIC

IC Pin Switching (PMR16): PMR16 sets whether the P16/IC pin is used as a P16 I/O

pin or an IC pin for the input capture input of the prescalar unit.

Bit 6

PMR16 Description

0 The P16/IC pin functions as a P16 I/O pin (Initial value)

1 The P16/IC pin functions as an IC input function

Rev. 1.0, 02/01, page 400 of 1184

21.3 Noise Cancel Circuit

The IC pin has a built-in a noise cancel circuit. The circuit can b e u sed for noise protection such

as remote control receiving. The noise cancel circuit samples the input values of the IC pin twice

at an interval of 256 states. If the input values are different, they are assumed to be noise.

The IC pin can specify enable/disable of the noise cancel function according to the bit 4

(NCon/off) of the prescalar unit control/status register (PCSR).

21.4 Operation

21.4.1 Prescalar S (PSS)

The PSS is a 17- bit counter that u ses th e system clock (φ=fosc) as an input clock and generates the

frequency division clocks (φ/131072 to φ/2) of the peripheral function. The low-order 17 bits of

the 18-bit free running counter (FRC) correspond to the PSS. The FRC is incremented by one

clock. The PSS outpu t is sh ared by the timer and serial communication interface (SCI), and the

frequency division ratio can independently b e set by each built-in peripheral function.

When reset, the FRC is initialized to H'00000, and starts increment after reset has been released.

Because the system clock oscillator is stopped in standby mode, watch mode, subactive mode, and

subsleep mode, the PSS operation is also stopped. In this case, the FCR is also initialized to

H'00000.

The FRC cannot be read and written from the CPU.

Rev. 1.0, 02/01, page 401 of 1184

21.4.2 Prescalar W (PSW)

PSW is a counter that uses the subclock as an input clock. The PSW also generates the input

clock of the timer A. In this case, the timer A f unctions as a clock time base.

When reset, the PSW is initialized to H'00, and starts in cr ement af ter r e set has been released.

Even if the mode has been shifted to the standby mode*, watch mode*, subactive mode*, and

subsleep mode*, the PSW continues the operation as long as the clocks are supplied by the X1 and

X2 pins.

The PSW can also be initialized to H'00 by setting the TMA3 and TMA2 bits of the timer mode

Note: * When the timer A is in module stop mode, the op eration is stopped.

Figure 2 1.2 shows the su pply of the clocks to the periphera l function by th e PSS and PSW.

φ/131072 to φ/2

φTimer

SCI

OSC1 fosc

OSC2

φw/128

φw/4

φwTimer A

Prescalar S

X1 (fx)

X2 CPU

ROM

RAM

TMOW pin

Peripheral register

I/O port

Intermediate

speed clock

frequency divider

Prescalar W

System clock

selection

Subclock

frequency

dividers

(1/2, 1/4, and 1/8)

Subclock

oscillator

System

clock

oscillator

System

clock

duty

correction

circuit

Figure 21.2 Clock Supply

21.4.3 Stable Oscillat ion Wait Time Co unt

For the count o f the stable o scillatio n stable wait time dur ing the return from the lo w power

consumption mode excluding the sleep mode, see section 4, Power-Down State.

Rev. 1.0, 02/01, page 402 of 1184

21.4.4 8-bit PWM

This 8-bit PWM controls the duty control PWM signal in the conversion cycle 256 states. It

counts the cycle and the duty cycle at 27 to 20 of the FRC. It can be used for controlling reel

motors and loading motors. For details, see sectio n 18, 8-Bit PWM.

21.4 .5 8- bit Input Capture Using IC

ICIC

IC Pin

This function catches the 8-bit data of 215 to 28 of the FRC according to the edge of the IC pin. It

can be used for remote control receiving.

For the edge of the IC pin, the rising and falling edges can be selected.

The IC pin has a built-in noise cancel cir c u it. See section 21.3, Noise Cancel Circu it.

An interrupt request is generated due to the input capture using the IC pin.

Note: Rewriting th e ICEG bit, NCon/off b it, or PMR1 6 bit is incorrectly reco gnized as edge

detection according to the combinations between the state and detection edge of the IC pin

and the ICIF bit may be set after up to 384φ seconds.

21.4.6 Frequency Division Clock Output

The frequency division clock can be output from the TMOW pin. For the frequency division

clock, eight types of clocks can be selected according to the DCS2 to DCS0 bits in PCSR.

The clock in which the system clock was frequency-divided is output in active mode and sleep

mode and the clock in which the subclock was frequency-divided is output in active mode*, sleep

mode*, and subactive mode.

Note: * When timer A is in module stop mode, no clock is output.

Rev. 1.0, 02/01, page 403 of 1184

Section 22 Serial Communication Interface 1 (SCI1)

22.1 Overview

The serial communication interface (SCI) can handle both asynchronous and clocked synchronous

serial communication. A function is also provided for serial communication between processors

(multipr ocessor commun ication f unction).

22.1.1 Features

SCI1 features are listed below.

• Choice of asynchronous or synchronous serial communication mode

 Asynchronous mode

• Serial data communication is executed using an asynchronous system in which

synchronization is achieved ch aracter by character

Serial data communication can be carried out with standard asynchronous

communication chips such as a Universal Asynchronous Receiver/Transmitter (UART)

or Asynchronous Communication Interface Adapter (ACIA)

• A multipro cessor communication function is provided that enables serial data

communication with a number of processors

• Choice of 12 serial data transfer formats

Data length: 7 or 8 bits

Stop bit length: 1 or 2 bits

Parity: Even, odd, or none

Multiprocessor bit: 1 or 0

• Receive error detection: Parity, overrun, and framing errors

• Break detection: Break can be detected by reading the SI1 pin level directly in case of a

framing error

 Clock synchronous mode

• Serial data communication is synchronized with a clock

Serial data communication can be carried out with other chips that have a synchronous

communication function

• One serial data transfer format

Data length: 8 bits

• Receive error detection: Overrun errors detected

Rev. 1.0, 02/01, page 404 of 1184

• Full-duplex communication capability

 The transmitter and receiver are mutually independent, enabling transmission and reception

to be executed simultaneously

 Double-buffering is used in both the transmitter and the receiver, enabling continuous

transmission and continuous reception of serial data

• Built-in bau d rate generator allows any b it r a te to be selected

• Choice of serial clock source: internal clock from baud rate generator or ex ternal clock from

SCK1 pin

• Four interrupt sources

 Four interrupt sources (transmit-data-empty, transmit-end, receive-data-full, and receive

error) that can issue requests independently

Rev. 1.0, 02/01, page 405 of 1184

22.1.2 Block Diagram

Figure 22.1 shows a block diagram of the SCI.

SI1

SO1

SCK1

Clock

External clock

φ/4

φ/16

φ/64

TEI

TXI

RXI

ERI

RSR1

RDR1

TSR1

TDR1

SMR1

SCR1

SSR1

SCMR1

BRR1

: Receive shift register 1

: Receive data register 1

: Transmit shift register 1

: Transmit data register 1

: Serial mode register 1

: Serial control register 1

: Serial status register 1

: Serial interface mode register 1

: Bit rate register 1

SCMR1

SSR1

SCR1

SMR1

Transmission/

reception

control

Baud rate

generator

BRR1

Module data bus

Bus interface

Internal data bus

RDR1

TSR1RSR1

Parity generation

Parity check

Legend:

TDR1

Figure 22.1 Block Diagram of SCI

Rev. 1.0, 02/01, page 406 of 1184

22.1.3 Pin Configuration

Table 22.1 shows the serial pins used by the SCI.

Table 22.1 SCI P i ns

Channel Pin Name Symbol I/O Function

Serial clock pin 1 SCK1 I/O SCI1 clock input/output

Receive data pin 1 SI1 Input SCI1 receive data input

Transmit data pin 1 SO1 Output SCI1 transmit data output

22.1.4 Register Configuration

The SCI1 has the internal registers shown in table 22.2. These registers are used to specify

asynchronous mode or synchronous mode, the data format, and the bit rate, and to control the

transmitter/receiver.

Table 22.2 SCI Registers

Channel Name Abbrev. R/W Initial Value Address*1

Serial mode register 1 SMR1 R/W H'00 H'D148

Bit rate register 1 BRR1 R/W H'FF H'D149

Serial control register 1 SCR1 R/W H'00 H'D14A

Transmit data register 1 TDR1 R/W H'FF H'D14B

Serial status register 1 SSR1 R/(W)*2 H'84 H'D14C

Receive dat a register 1 RDR1 R H'00 H'D14D

Serial interface mode register 1 SCMR1 R/W H'F2 H'D14E

MSTPCRH R/W H'FF H'FFEC Common Module stop control register

MSTPCRL R/W H'FF H'FFED

Notes: 1. Lower 16 bits of the address.

2. Only 0 can be written, to clear flags.

Rev. 1.0, 02/01, page 407 of 1184

22.2 Register Descriptions

22.2.1 Receive Shift Register 1 (RSR1)

—

Bit :

R/W :

RSR1 is a register used to receive serial data.

The SCI sets serial data input from the SI1 pin in RSR1 in the order received, starting with the

LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is

transferre d to RDR automatically.

RSR1 cannot be directly read or written to by the CPU.

22.2.2 Receive Data Register 1 (RDR1)

Bit :

Initial value :

R/W :

RDR1 is a register that stores received serial data.

When the SCI has received one byte of serial data, it transfers the received serial data from RSR1

to RDR1 where it is stored, and completes the receive operation. After this, RSR1 is receive-

enabled.

Since RSR1 and RDR1 function as a double buffer in this way, continuous receive operations can

be performed.

RDR1 is a read-only register, and cannot b e wr itten to by the CPU.

RDR1 is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode,

subsleep mode, and module stop mode.

Rev. 1.0, 02/01, page 408 of 1184

22.2.3 Transmit Shift Register 1 (TSR1)

—

Bit :

R/W :

TSR1 is a register u sed to transmit serial data.

To perform serial data transmission, the SCI first tran sf ers transmit data f rom TDR1 to TSR1, then

sends the data to the SO1 pin starting with th e LSB ( bit 0).

When transm ission of one byte is completed, the next tr ansmit data is transferred fro m TDR1 to

TSR1, and tran smission started, automatically. However, data transfer f r om TDR1 to TSR1 is not

performed if the TDRE bit in SSR1 is set to 1 .

TSR1 cannot be directly read or written to by the CPU.

22.2.4 Transmit Data Register 1 (TDR1)

R/W

Bit :

Initial value :

R/W :

TDR1 is an 8-bit register that stores data for serial transmission.

When the SCI detects that TSR is empty, it transfers the transmit data written in TDR1 to TSR1

and starts serial transmission. Continuous serial transmission can be carried out by writing the

next transmit data to TDR1 during serial transmission of the data in TSR1.

TDR1 can be read or wr itten to by the CPU at all times.

TDR1 is initialized to H'FF by a reset, and in standby mode, watch mode, subactive mode,

subsleep mode, and module stop mode.

Rev. 1.0, 02/01, page 409 of 1184

22.2.5 Serial Mode Register 1 (SMR1)

C/A

R/W

CHR

R/W

O/E

R/W

STOP

R/W

CKS0

R/W

CKS1

R/W

Bit :

Initial value :

R/W :

SMR1 is an 8-bit register used to set the SCI's serial transfer format and select the baud rate

generator clock source.

SMR1 can be read or wr itten to by the CPU at all times.

SMR1 is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode,

subsleep mode, and module stop mode.

Bit 7



Communication Mode (C/A

A): Selects asynchronous mode or clock synchronous mode as

the SCI operating mode.

Bit 7

C/A

A Description

0 Asynchronous mode (Initial value)

1 Clock synchronous mode

Bit 6



Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode.

In synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting.

Bit 6

CHR Description

0 8-bit data (Initial value)

1 7-bit data*

Note: * When 7-bit data is selected, the MSB (bit 7) of TDR1 is not transmitted, and LSB-first/MSB-

first select ion is not availa ble .

Rev. 1.0, 02/01, page 410 of 1184

Bit 5



Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is

performed in tran smission, and parity bit checking in reception. In synchronous mode, or when a

multipro cessor format is used, parity bit addition and checking is n ot performed, regard less of the

PE bit setting.

Bit 5

PE Description

0 Parity bit addition and checking disabled (Initial value)

1 Parity bit addition and checking enabled*

Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to

transmit data before transmission. In reception, the parity bit is checked for the parity (even

or odd) specified by the O/E bit.

Bit 4



Parity Mode (O/E

E): Selects either even or odd parity for use in parity add ition and

checking.

The O/E bit setting is only valid when the PE bit is set to 1 , enabling parity bit addition and

checking, in asynchronous mode. The O/E bit setting is invalid in synchronous mode, when parity

bit addition and checking is disabled in asynchronous mode, and when a multiprocessor format is

used.

Bit 4

O/E

E Description

0 Even parity*1 (Initial value)

1 Odd parity*2

Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total

number of 1 bi ts in the transmit character plus the parity bit is even. In reception, a

check is performed to see if the total number of 1 bits in the receive character pl us the

parity bit is even.

2. When odd parity is set, parity bit addition is performed in transmission so that the total

number of 1 bi ts in the transmit character plus the parity bit is odd. In reception, a

check is performed to see if the total number of 1 bits in the receive character pl us the

parity bit is odd.

Rev. 1.0, 02/01, page 411 of 1184

Bit 3



Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode.

The STOP bit setting is only valid in asynchronous mode. If synchronous mode is set the STOP

bit setting is invalid since stop bits are not added.

Bit 3

STOP Description

0 1 stop bit*1 (Initial value)

1 2 stop bits*2

Notes: 1. In transmission, a single 1 bit (stop bit) is added to the end of a transmit character

before it is sent.

2. In transmission, two 1 bits (stop bits) are added to the end of a transmit character

before it is sent.

In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second

stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit o f the next transmit

character.

Bit 2



Multiprocessor Mode (MP): Selects multipro cessor form at. When multiprocessor format

is selected, the PE bit and O/E bit p a r ity settings are invalid. The MP bit setting is only valid in

asynchronous mode; it is invalid in synchronous mode.

For details of the multiprocessor communicatio n function, see section 22 . 3.3 , Multiprocessor

Communication Function.

Bit 2

MP Description

0 Multiprocessor function disabled (Initial value)

1 Multiprocessor format selected

Rev. 1.0, 02/01, page 412 of 1184

Bits 1 and 0



Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the

baud rate generator. The clock source can be selected from φ, φ/4, φ/16, and φ/64, according to

the setting of bits CKS1 and CKS0.

For the relatio n between the clock source, the bit r ate register settin g, and the baud rate, see

section 22.2.8, Bit Rate Register 1.

Bit 1 Bit 0

CKS1 CKS0 Description

0 φ clock (Initial value) 0

1 φ/4 clock

0 φ/16 clock 1

1 φ/64 clock

22.2.6 Serial Control Register 1 (SCR1)

TIE

R/W

RIE

R/W

MPIE

R/W

CKE0

R/W

TEIE

R/W

CKE1

R/W

Bit :

Initial value :

R/W :

SCR1 is a register that performs enabling or disabling of SCI transfer operations, serial clock

output in asyn chronous mode, and interrupt requests, and selection of the serial clock source.

SCR1 can be r e ad or written to by the CPU at all times.

SCR1 is initialized to H'00 by a reset, and in standby mode, watch mod e, subactive mode,

subsleep mode, and module stop mode.

Bit 7



Transmit Interrupt Enable (TIE): Enab les or disables transmit-d a ta- e mpty interrup t

(TXI) request generation when serial transmit data is transf erred from TDR1 to TSR1 and the

TDRE flag in SSR1 is set to 1.

Bit 7

TIE Description

0 Transmit-data-empty interrupt (TXI) request disab led * (Initial value)

1 Transmit-data-empty interrupt (TXI) request enable d

Note: * TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then

clearing it to 0, or cl earing the TIE bit to 0.

Rev. 1.0, 02/01, page 413 of 1184

Bit 6



Receive Interrupt Enable (RIE): Enables or disables receive-data-full interrupt (RXI)

request and receive-error interrupt (ERI) request generation when serial receive data is transferred

from RSR1 to RDR1 and the RDRF flag in SSR1 is set to 1.

Bit 6

RIE Description

0 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request

disabled* (Initial value)

1 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request

enabled

Note: * RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF,

FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0.

Bit 5



Transm it Enable (TE): E nables or disables the start of serial tr a nsmission by the SCI.

Bit 5

TE Description

0 Transmission disabled*1 (Initial value)

1 Transmission enabled*2

Notes: 1. The TDRE flag in SSR1 is fixed at 1.

2. In this state, serial transmission is started when transmit data is written to TDR1 and the

TDRE flag in SSR1 is cleared to 0.

SMR1 setting must be performed to decide the transmission format before setting the

TE bit to 1.

Bit 4



Receive Enable (RE): Enables or disables the start of serial reception by the SCI.

Bit 4

RE Description

0 Reception disabled*1 (Initial value)

1 Reception enabled*2

Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which

retain their states.

2. Serial reception is started in this state when a start bit is detected in asynchronous

mode or serial clock input is detected in synchronous mode.

SMR1 setting mu st be performed to decide the reception format before setting the RE

bit to 1.

Rev. 1.0, 02/01, page 414 of 1184

Bit 3



Multiprocessor Interrupt Enable (MPIE): Enables or disables mu ltiprocessor interr upts.

The MPIE bit setting is only valid in asynchronous mode when receiving with the MP bit in

SMR1 set to 1.

The MPIE bit setting is invalid in clock synchronous mode or when the MP bit is cleared to 0.

Bit 3

MPIE Description

0 Multiprocessor interrupts disabled (normal reception performed) (Initial value)

[Clearing cond iti ons ]

1. When the MPIE bit is cleared to 0

2. When data with MPB = 1 is received

1 Multiprocessor interrupts enabled*

Receive interrupt (RXI) requests, receive-error in terrupt (ERI) requests, and setting of

the RDRF, FER, and ORER flags in SSR1 are disabled until data with the

multiprocessor bit set to 1 is received.

Note: * When receive data including MPB = 0 is received, receive data transfer from RSR1 to

RDR1, receive error detec tion, and setting of the RDRF, FER, and ORER flags in SSR1 , is

not performed. When receive data with MPB = 1 is received, the MPB bit in SSR1 is set to

1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts

(when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled.

Bit 2



Transmit End Interr upt Enable (TEIE) : Enables or disables transmit-end interrupt

(TEI) request generation if th ere is no valid transmit d a ta in TDR when the MSB is transmitted.

Bit 2

TEIE Description

0 Transmit-end interrupt (TEI) request disabled* (Initial value)

1 Transmit-end interrupt (TEI) request enabled*

Note: * TEI cancellation can be performed by reading 1 from the TDRE flag in SSR1, then clearing

it to 0 and cl earing the TEND flag to 0, or clearing the TEIE bit to 0.

Rev. 1.0, 02/01, page 415 of 1184

Bits 1 and 0



Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock

source and enable or disable clock output from the SCK pin. The combination of the CKE1 and

CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or

the serial clock input pin.

The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in

asynchronous mode. The CKE0 bit setting is invalid in synchronous mode, and in the case of

external clock operation (CKE1 = 1). Note that the SCI's operating mode must be decided using

SMR1 before setting the CKE1 and CKE0 bits.

For details of clock source selection, see table 22.9 in section 22.3, Operation.

Bit 1 Bit 0

CKE1 CKE0 Description

Asynchronous mode Internal clock/SCK1 pin functions as I/O

port*1

Clock synchronous

mode Internal clock/SC K1 pi n functions as seri al

clock outp ut*1

Asynchronous mode Internal clock/SCK1 pin functions as clock

output*2

Clock synchronous

mode Internal clock/SC K1 pi n functions as seri al

clock outp ut

Asynchronous mode External clock/SCK1 pin functions as clock

input*3

Clock synchronous

mode External clock/SC K1 pin functions as serial

clock inp ut

Asynchronous mode External clock/SCK1 pin functions as clock

input*3

Clock synchronous

mode External clock/SC K1 pin functions as serial

clock inp ut

Notes: 1. Initial value.

2. Outputs a clock of the same frequency as the bit rate.

3. Input s a clock with a frequen c y 16 times the bit rate.

Rev. 1.0, 02/01, page 416 of 1184

22.2.7 Serial Status Register 1 (SSR1)

TDRE

R/(W)*

RDRF

R/(W)*

ORER

R/(W)*

FER

R/(W)*

PER

R/(W)*

MPBT

R/W

TEND

MPB

Note: * Only 0 can be written to clear the flag.

Bit :

Initial value :

R/W :

SSR1 is an 8-bit register containing status flags that indicate the operating status of the SCI, and

multiprocessor bits.

SSR1 can be read or written to by the CPU at all times. However, 1 cannot be written to flags

TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be

read as 1 beforehand. The TEND flag and MPB flag are read -only flags and cannot be modified.

SSR1 is initialized to H'84 by a reset, and in standby mode, watch mode, subactive mode, subsleep

mode, and module stop mode.

Bit 7



Transmit Data Register Empty (TDRE): Indicates that data has been transferred from

TDR1 to TSR1 and the next serial data can be written to TDR1.

Bit 7

TDRE Description

0 [Clearing conditions]

When 0 is written in TDRE after reading TDRE = 1

1 [Setting conditions] (Initial value)

1. When the TE bi t in SCR is 0

2. When data is transferred from TDR1 to TSR1 and data can be written to TDR1

Bit 6



Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR1.

Bit 6

RDRF Description

0 [Clearing conditions] (Initial value)

When 0 is written in RDRF after reading RDRF = 1

1 [Setting conditions]

When serial reception ends normally and receive data is transferred from RSR to

RDR

Note: RDR1 and the RDRF flag are not affected and retain their previous values when an error is

detected during reception or when the RE bit in SCR1 is cleared to 0.

If reception of the next data is completed while the RDRF flag is still set to 1, an overrun

error will occur and the receive data will be lost.

Rev. 1.0, 02/01, page 417 of 1184

Bit 5



Overrun Error (ORER): Indicates that an overrun error occurred du ring reception,

causing abnormal termination.

Bit 5

ORER Description

0 [Clearing conditions] (Initial value) *1

When 0 is written in ORER after reading ORER = 1*1

1 [Setting conditions]

When the next serial reception is completed while RDRF = 1*2

Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR1 is

cleared to 0.

2. The receive data prior to the overrun error is retained in RDR1, and the data received

subsequently is lost. Also, subsequent serial reception cannot be continued while the

ORER flag is set to 1. In synchronous mode, serial transmission cannot be continued,

either.

Bit 4



Framing Error (FER): Indicates that a framing error occurred during reception in

asynchronous mode, causing abnormal termination.

Bit 4

FER Description

0 [Clearing conditions] (Initial value)

When 0 is written in FER after reading FER = 1*1

1 [Setting conditions]

When the SCI checks the stop bit at the end of the receive data when reception ends,

and the stop bit is 0*2

Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR1 is

cleared to 0.

2. In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit

is not checked. If a framing error occurs, the receive data is transferred to RDR1 but

the RDRF flag is not set. Also, subsequent serial reception cannot be continued while

the FER flag is set to 1. In synchronous mode, serial transmission cannot be

continued, either.

Rev. 1.0, 02/01, page 418 of 1184

Bit 3



Parity Error (PER): Indicates that a parity error occurred during reception using parity

addition in asynchronous mode, causing abnormal termination.

Bit 4

PER Description

0 [Clearing conditions] (Initial value)

When 0 is written in PER after reading PER = 1*1

1 [Setting conditions]

When, in reception, the number of 1 bits in the receive data plus the parity bit does

not match the parity setting (even or odd) specified by the O/E bit in SMR1*2

Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR1 is

cleared to 0.

2. If a parity error occurs, the receive data is transferred to RDR1 but the RDRF flag is not

set. Also, subsequent serial reception cannot be continued while the PER flag is set to

1. In synchronous mode, serial transmission cannot be continued, either.

Bit 2



Transmit End ( TEND): I ndicates that there is no valid data in TDR when the last bit of

the transmit character is sent, and transmission has been ended.

The TEND flag is read-only and cannot be modified.

Bit 2

TEND Description

0 [Clearing conditions]

When 0 is written in TDRE after reading TDRE = 1

1 [Setting conditions] (Initial value)

1. When the TE bit in SCR1 is 0

2. When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit characte r

Bit 1



Multiprocessor Bit (MPB): When reception is performed using a multiprocesso r format

in asynchronous mode, MPB stores the multiprocessor bit in the receive data.

MPB is a read-only bit, and cannot be modified.

Bit 1

MPB Description

0 [Clearing conditions] (Initial val ue) *

When data with a 0 multiproce ssor bit is rec eiv ed

1 [Setting conditions]

When data with a 1 multiproce ssor bit is rec eiv ed

Note: * Retains its previous state when the RE bit in SCR1 is cleared to 0 with multiprocessor

format.

Rev. 1.0, 02/01, page 419 of 1184

Bit 0



Multiprocessor Bit Transfer (MPBT): When transmission is performed using a

multipro cessor format in asynchronous mod e, MPBT stores the multipro cessor bit to be added to

the transmit d a ta.

The MPBT bit setting is invalid when a multip rocessor format is not used , when not transmitting,

and in synchronous mode.

Bit 0

MPBT Description

0 Data with a 0 multiprocessor bit is transmitted (Initial value)

1 Data with a 1 multiprocessor bit is transmitted

22.2.8 Bit Rate Register 1 (BRR1)

R/W

Bit :

Initial value :

R/W :

BRR1 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate

generator operating clock selected by bits CKS1 and CKS0 in SMR.

BRR1 can be r ead or written to by the CPU at all times.

BRR1 is initialized to H'FF by a reset, and in standby mode, watch mode, subactive mode,

subsleep mode, and module stop mode.

Table 22.3 shows sample BRR1 settings in asynchronous mode, and table 22.4 shows sample

BRR1 settings in synchronous mode.

Rev. 1.0, 02/01, page 420 of 1184

Table 22.3 BRR1 Settings for Various Bit Rates (Asynchronous Mode)

Operating Frequency φ

φφ

φ (MHz)

2 2.097152 2.4576 3

Bit Rate

(bits/s) n N Error

(%) n N Error

(%)

110 1 141 0.03 1 148 −0.04 1 174 −0.26 1 212 0.03

150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16

300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16

600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16

1200 0 51 0.16 0 54 −0.70 0 63 0.00 0 77 0.16

2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16

4800 0 12 0.16 0 13 −2.48 0 15 0.00 0 19 −2.34

9600    0 6 −2.48 0 7 0.00 0 9 −2.34

19200       0 3 0.00 0 4 −2.34

31250 0 1 0.00    0   0 2 0.00

38400       0 1 0.00   

Operating Frequency φ

φφ

φ (MHz)

3.6864 4 4.9152 5

Bit Rate

(bits/s) n N Error

(%) n N Error

(%)

110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 −0.25

150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16

300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16

600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16

1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16

2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16

4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 −1.36

9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73

19200 0 5 0.00    0 7 0.00 0 7 1.73

31250    0 3 0.00 0 4 −1.70 0 4 0.00

38400 0 2 0.00    0 3 0.00 0 3 1.73

Rev. 1.0, 02/01, page 421 of 1184

Operating Frequency φ

φφ

φ (MHz)

6 6.144 7.3728 8

Bit Rate

(bits/s) n N Error

(%) n N Error

(%)

110 2 106 −0.44 2 108 0.08 2 130 −0.07 2 141 0.03

150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16

300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16

600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16

1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16

2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16

4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16

9600 0 19 −2.34 0 19 0.00 0 23 0.00 0 25 0.16

19200 0 9 −2.34 0 9 0.00 0 11 0.00 0 12 0.16

31250 0 5 0.00 0 5 2.40    0 7 0.00

38400 0 4 −2.34 0 4 0.00 0 5 0.00   

Operating Frequency φ

φφ

φ (MHz)

9.8304 10

Bit Rate

(bits/s) n N Error

(%) n N Error

(%)

110 2 174 −0.26 2 177 −0.25

150 2 127 0.00 2 129 0.16

300 1 255 0.00 2 64 0.16

600 1 127 0.00 1 129 0.16

1200 0 255 0.00 1 64 0.16

2400 0 127 0.00 0 129 0.16

4800 0 63 0.00 0 64 0.16

9600 0 31 0.00 0 32 −1.36

19200 0 15 0.00 0 15 1.73

31250 0 9 −1.70 0 9 0.00

38400 0 7 0.00 0 7 1.73

Rev. 1.0, 02/01, page 422 of 1184

Table 22.4 BRR1 Settings for Various Bit Rates (Synchronous Mode)

Operating Frequency φ

φφ

φ (MHz)

2 4 8 10

Bit Rate

(bits/s) n N n N n N n N

110 3 70  

250 2 124 2 249 3 124  

500 1 249 2 124 2 249  

1 k 1 124 1 249 2 124  

2.5 k 0 199 1 99 1 199 1 249

5 k 0 99 0 199 1 99 1 124

10 k 0 49 0 99 0 199 0 249

25 k 0 19 0 39 0 79 0 99

50 k 0 9 0 19 0 39 0 49

100 k 0 4 0 9 0 19 0 24

250 k 0 1 0 3 0 7 0 9

500 k 0 0* 0 1 0 3 0 4

1 M 0 0* 0 1

2.5 M 0 0*

5 M

Note: As far as possib le, the sett ing shou ld be made so that the err or is no more than 1%.

Legend:

Blank: Cannot be set.

—: Can be set, but there will be a degree of error.

*: Continuous transfer is not possible.

Rev. 1.0, 02/01, page 423 of 1184

The BRR1 setting is found from the following equations.

• Asynchronous mode:

N = φ × 106 − 1

64 × 22n−1 × B

• Synchronous mode:

N = φ × 106 − 1

8 × 22n−1 × B

Where

B: Bit rate (bits/s)

N: BRR1 setting for baud rate generator (0 ≤ N ≤ 255)

φ: Operating frequency (MHz)

n: Baud rate generator input clock (n = 0 to 3)

(See the table below for th e relation between n and the clock.)

SMR1 Setting

n Clock CKS1 CKS0

0 φ 0 0

1 φ/4 0 1

2 φ/16 1 0

3 φ/64 1 1

The bit rate error in asynchronous mode is found from the following equation:

Error (%) = { φ × 106 − 1 } × 100

(N + 1) × B × 64 × 22n − 1

Table 22.5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 22.6

and 22.7 show the maximum bit rates with external clock input.

Rev. 1.0, 02/01, page 424 of 1184

Table 22. 5 Maximum Bit Rate f or Each Frequency ( A synchronous Mode)

φφ

φ (MHz) Maximum Bit Rate (bits/s) n N

2 62500 0 0

2.097152 65536 0 0

2.4576 76800 0 0

3 93750 0 0

3.6864 115200 0 0

4 125000 0 0

4.9152 153600 0 0

5 156250 0 0

6 187500 0 0

6.144 192000 0 0

7.3728 230400 0 0

8 250000 0 0

9.8304 307200 0 0

10 312500 0 0

Rev. 1.0, 02/01, page 425 of 1184

Table 22.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode)

φφ

φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s)

2 0.5000 31250

2.097152 0.5243 32768

2.4576 0.6144 38400

3 0.7500 46875

3.6864 0.9216 57600

4 1.0000 62500

4.9152 1.2288 76800

5 1.2500 78125

6 1.5000 93750

6.144 1.5360 96000

7.3728 1.8432 115200

8 2.0000 125000

9.8304 2.4576 153600

10 2.5000 156250

Table 22.7 Maximum Bit Rate with External Clock Input (Synchronous Mode)

φφ

φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s)

2 0.3333 333333.3

4 0.6667 666666.7

6 1.0000 1000000.0

8 1.3333 1333333.3

10 1.6667 1666666.7

Rev. 1.0, 02/01, page 426 of 1184

22.2.9 Serial Interface Mode Register 1 (SCMR1)

—

SDIR

R/W

SMIF

R/W

SINV

R/W

—

Bit :

Initial value :

R/W :

SCMR1 is an 8 - bit readable/writable register used to select SCI fun ctions.

SCMR1 is initialized to H'F2 by a reset, and in standby mode, watch mode, subactiv e mode,

subsleep mode, and module stop mode.

Bits 7 to 4



Reserved: These bits cannot be modified and are always read as 1.

Bit 3



Data Transfer Direction (SDIR): Selects the serial/parallel conversion format.

Bit 3

SDIR Description

0 TDR contents are transmitted LSB-first (Initial value)

Receive data is stored in RDR1 LSB-first

1 TDR contents are transmitted MSB-first

Receive data is stored in RDR1 MSB-first

Bit 2



Data Invert (SINV): Specifies inversion of th e data logic level. The SINV bit does not

affect the log ic level of the parity bit(s): p arity bit inversion req uires inversio n of the O/E bit in

SMR1.

Bit 2

SINV Description

0 TDR1 contents are transmitted without modification (Initial value)

Receive data is stored in RDR1 wi thout modification

1 TDR1 contents are inverted before being transmitted

Receive data is stored in RDR1 in inverted form

Bit 1



Reserved: This bit cannot be modified and is always read as 1.

Bit 0



Reserved: 1 should not be written in this bit.

Rev. 1.0, 02/01, page 427 of 1184

22.2.10 Module Stop Control Register (MSTPCR)

R/W

MSTPCRH MSTPCRL

MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0

Bit :

Initial value :

R/W :

MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.

When bit MSTP8 is set to 1, SCI1 o peration stops at the en d of the bus cycle and a transition is

made to module stop mode. For details, see section 4.5, Module Stop Mode.

MSTPCR is initialized to H'FFFF by a reset.

Bit 0



Module Stop ( MSTP8 ): Specifies the SCI1 module stop mode.

MSTPCRH

Bit 0

MSTP8 Description

0 SCI1 module stop mode is cleared

1 SCI1 module stop mode is set (Initial value)

Rev. 1.0, 02/01, page 428 of 1184

22.3 Operation

22.3.1 Overview

The SCI can carry out serial communication in two modes: asynchronous mode in which

synchronization is achieved character by character, and synchronous mode in which

synchronization is achieved with clock pulses.

Selection of asynchronous or synchronous mode and the transmission format is made using SMR1

as shown in table 22.8. The SCI clock is determined by a combination of the C/A bit in SMR1

and the CKE1 and CKE0 bits in SCR1, as shown in table 22.9.

• Asynchronous Mode

 Data length: Choice of 7 or 8 bits

 Choice of p a rity addition, multiprocessor bit addition, and addition of 1 or 2 stop b its ( the

combination of these parameters determines the transfer format and character length)

 Detection of framing, parity, and overrun errors, and breaks, during reception

 Choice of internal or external clock as SCI clock source

• When internal clock is selected:

The SCI operates on the baud rate generator clock and a clock with the same frequency

as the bit rate can b e output

• When external clock is selected:

A clock with a fr equency of 16 times the bit rate must be input (the built-in baud rate

generator is not used)

• Clock Synchronous Mode

 Transfer format: Fixed 8-bit data

 Detection of overrun errors during reception

 Choice of internal or external clock as SCI clock source

• When internal clock is selected:

The SCI operates on the baud rate generator clock and a serial clock is output off-chip

• When external clock is selected:

The built-in bau d rate generator is not used, and the SCI operates on th e input serial

clock

Rev. 1.0, 02/01, page 429 of 1184

Table 22.8 SMR1 Settings and Seria l Transfer Fo rmat Selection

SMR1 Settings SCI Transfer Format

Bit 7 Bit 6 Bit 2 Bit 5 Bit 3

C/A

A CHR MP PE STOP

Mode Data

Length Multiproc-

essor Bit Parity

Bit Stop Bit

Length

0 1 bit 0

2 bits

0 1 bit

8-bit

data

Yes

2 bits

0 1 bit 0

2 bits

0 1 bit

Asynchro-

nous mode

7-bit

data

Yes

2 bits

 0 1 bit

 1

8-bit

data 2 bits

 0 1 bit

 1

Asynchro-

nous mode

(multi-

processor

format) 7-bit

data

Yes

2 bits

1     Clock

synchronous

mode

8-bit

data No

Table 22.9 SMR1 and SCR1 Settings and SCI Clock Source Selection

SMR1 SCR1 Setting

Bit 7 Bit 1 Bit 0 SCI Transfer Clock

C/A

A CKE1 CKE0

Mode Clock Source SCK Pin Function

0 SCI does not use SCK pin 0

Internal

Outputs clock with same frequency

as bit rate

Asynchronous

mode

External Inputs clock with frequency of 16

times the bit rate

0 0

Internal Outputs serial cloc k

Clock

synchronous

mode External Inputs serial clock

Rev. 1.0, 02/01, page 430 of 1184

22.3.2 Operation in Asynchronous Mode

In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the

start of communication and followed by one or two stop bits indicating the end of communication.

Serial communication is thus carried out with synchronization established on a character-by-

character basis.

Inside the SCI, the tran smitter and receiv er are independent units, en ab ling full-duplex

communication. Both th e transmitter and the receiv er also have a doub le-buffered structure, so

that data can be read or written during transmission or reception, enabling continuous data

transfer.

Figure 22.2 shows the general format for asynchronous serial communication.

In asynchronous serial communication, the transmission line is usually held in the mark state (high

level). The SCI monitors the transmission line, and when it goes to the space state (low level),

recognizes a start bit and starts serial communication.

One serial communication character consists of a star t bit (low level), followed by data (in LSB-

first order) , a par ity bit ( high or low level), and finally one or two stop bits (high leve l) .

In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in

reception. The SCI samples the data on the 8th pulse of a clock with a frequency of 16 times the

length of one bit, so that the transfer data is latched at the center of each bit.

LSB

Start

bit

MSB

Idle state

(mark state)

Stop

bit(s)

Transmit/receive data

D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1

Serial

data Parity

bit

1 bit 1 or 2 bits7 or 8 bits 1 bit,

or none

One unit of transfer data (character or frame)

Figure 22.2 Data Format in Asynchronous Communication

(Example with 8-Bit Data, Parity, Two Stop Bits)

Rev. 1.0, 02/01, page 431 of 1184

• Data Transfer Format

Table 22.10 shows the data transfer formats that can be used in asynchronous mode. Any of

12 transfer formats can be selected by settings in SMR1.

Table 22.10 Serial Transfer Formats (Asynchronous Mode)

—

S 8-bit data

STOP

S 7-bit data

STOP

S 8-bit data

STOP STOP

S 8-bit data P

STOP

S 7-bit data

STOP

S 8-bit data

MPB STOP

S 8-bit data

MPB STOPSTOP

S 7-bit data

STOPMPB

S 7-bit data

STOPMPB STOP

S 7-bit data

STOPSTOP

CHR

STOP

SMR1 Settings

123456789101112

Serial Transfer Format and Frame Length

STOP

S 8-bit data P

STOP

S 7-bit data

STOP

Legend:

STOP

MPB

: Start bit

: Stop bit

: Parity bit

: Multiprocessor bit

Rev. 1.0, 02/01, page 432 of 1184

• Clock

Either an internal clock generated by the built-in baud rate generator or an external clock input

at the SCK pin can b e selected as the SCI's serial clock, accordin g to the setting of the C/A bit

in SMR1 and the CKE1 and CKE0 bits in SCR1. For details of SCI clock source selection, see

table 22.9.

When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit

rate used.

When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The

frequen cy of the clock output in this case is equal to th e bit rate, and the phase is such that the

rising edge of the clock is at the center of each transmit data bit, as shown in figure 22.3.

1 frame

D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1

Figure 22.3 Relation between Output Clock and Transfer Data Phase

(Asynchrono us Mo de)

Rev. 1.0, 02/01, page 433 of 1184

• Data Transfer Operations

 SCI Initialization (Asynchr onous Mode)

Before transmitting an d receiving data, first clear the TE and RE bits in SCR1 to 0, then

initialize the SCI as described belo w.

When the operating mode, tran sfer format, etc., is changed, the TE and RE bits must be

cleared to 0 before making the change using the following procedure. When the TE bit is

cleared to 0, the TDRE flag is set to 1 an d TSR1 is initialized. Note th at clear ing the RE

bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the

contents of RDR1.

When an external clock is used the clock should not be stopped during operation, includ ing

initialization, since operation is uncertain .

Figure 22 .4 sh ows a sample SCI initialization flo wchart.

Wait

Start initialization

Set data transfer format

in SMR1 and SCMR1

[1]

Set CKE1 and CKE0 bits in SCR1

(TE, RE bits 0)

Yes

Set value in BRR1

Clear TE and RE bits in SCR1 to 0

[2]

[3]

Set TE and RE bits in SCR1 to 1,

and set RIE, TIE, TEIE,

and MPIE bits [4]

1-bit interval elapsed?

Set the clock selection in SCR1.

Be sure to clear bits RIE, TIE, TEIE, and

MPIE, and bits TE and RE, to 0.

When the clock is selected in

asynchronous mode, it is output

immediately after SCR1 settings are made.

Set the data transfer format in SMR1 and

SCMR1.

Write a value corresponding to the bit rate

to BRR1. This is not necessary if an

external clock is used.

Wait at least one bit interval, then set the

TE bit or RE bit in SCR1 to 1. Also set the

RIE, TIE, TEIE, and MPIE bits.

Setting the TE and RE bits enables the

SO1 and SI1 pins to be used.

[1]

[2]

[3]

[4]

Figure 22.4 Sample SCI Initialization Flowchart

Rev. 1.0, 02/01, page 434 of 1184

 Serial Data Transmission (Asynchronous Mode)

Figure 22.5 shows a sample flowchart for serial transmission.

The following procedure should be used for serial data tran smission.

< End >

[1]

Yes

Initialization

Start transmission

Read TDRE flag in SSR1 [1]

Write transmit data to TDR1 and

clear TDRE flag in SSR to 0

Yes

Read TEND flag in SSR1

[3]

Yes

[4]

Clear PDR to 0

and set PCR to 1

Clear TE bit in SCR1 to 0

TDRE=1

All data transmitted?

TEND=1

Break output?

SCI initialization:

The SO1 pin is automatically designated as

the transmit data output pin.

SCI status check and transmit data write:

Read SSR and check that the TDRE flag is

set to 1, then write transmit data to TDR1

and clear the TDRE flag to 0.

Serial transmission continuation procedure:

To continue serial transmission, read 1

from the TDRE flag to confirm that writing is

possible, then write data to TDR1, and then

clear the TDRE flag to 0.

Break output at the end of serial

transmission:

To output a break in serial transmission, set

PCR for the port corresponding to the SO1

pin to 1, clear PDR to 0, then clear the TE

bit in SCR1 to 0.

[1]

[2]

[3]

[4]

Figure 22.5 Sample Serial Transmission Flowchart

Rev. 1.0, 02/01, page 435 of 1184

In serial transmission, the SCI operates as described below.

1. The SCI mo nitors the TDRE flag in SSR1, an d if it is 0, recognizes that data h as been written

to TDR1, and transfers the data from TDR1 to TSR1.

2. After tran sferring data from TDR1 to TSR1, the SCI sets the TDRE flag to 1 and star ts

transmission.

If the TIE bit is set to 1 at this time, a transmit d ata empty interrupt ( T XI) is g enerated.

The serial transmit data is sent from the SO1 pin in the following order.

a. Start bit:

One 0-bit is o utput.

b. Transmit data:

8-bit or 7-bit data is output in LSB-first order.

c. Parity bit or multipro cessor bit:

One parity bit (even or odd parity), or one multiprocessor bit is ou tp ut.

A format in which neither a parity bit nor a mu ltiprocessor bit is output can also be

selected.

d. Stop bit(s):

One or two 1-bits (stop bits) are output.

e. Mark state:

1 is output continuously u ntil the start bit that starts the n e xt transmission is sent.

3. The SCI checks the TDRE flag at the timing for sending the stop bit.

If the TDRE flag is clear ed to 0, the data is transferred from TDR1 to TSR1 , the stop bit is

sent, and then serial transmission of the next frame is started.

If the TDRE flag is set to 1, the TEND flag in SSR1 is set to 1 , the stop bit is sent, and th en the

mark state is enter ed in which 1 is output contin uou sly . If the TEIE bit in SCR1 is set to 1 at

this time, a TEI interr upt r e quest is gener a ted.

Rev. 1.0, 02/01, page 436 of 1184

Figure 22.6 shows an ex ample of the operation for transmission in asynchronous mode.

TDRE

TEND

1 frame

D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1

1 1

Data

Start

bit Parity

bit Stop

bit Start

bit Data

Parity

bit Stop

bit

TXI interrupt

request

generated

Data written to TDR1 and

TDRE flag cleared to 0

in TXI interrupt handling

routine

TEI interrupt request

generated

Idle state

(mark state)

TXI interrupt request

generated

Figure 22.6 Example of Operation in Transmission in Asynchronous Mode

(Example with 8-Bit Data, Pa rity, One Stop Bit)

Rev. 1.0, 02/01, page 437 of 1184

 Serial Data Reception (Asynchronous Mode)

Figures 22.7 and 22.8 show sample flowcharts for serial reception.

The following procedure should be used for serial data reception.

Yes

< End >

[1]

Initialization

Start reception

[2]

Yes

Read RDRF flag in SSR1 [4]

[5]

Clear RE bit in SCR1 to 0

Read ORER, PER,

FER flags in SSR1

Error handling

(Continued on next page)

[3]

Read receive data in RDR1, and clear

RDRF flag in SSR1 to 0

Yes

PER∨FER∨ORER=1

RDRF=1

All data received?

SCI initialization:

The SI1 pin is automatically designated as

the receive data input pin.

Receive error handling and break

detection:

If a receive error occurs, read the ORER,

PER, and FER flags in SSR to identify the

error. After performing the appropriate

error handling, ensure that the PERE, PER,

and FER flags are all cleared to 0.

Reception cannot be resumed if any of

these flags are set to 1. In the case of a

framing error, a break can be detected by

reading the value of the input port

corresponding to the SI1 pin.

SCI status check and receive data read:

Read SSR and check that RDRF = 1, then

read the receive data in RDR1 and clear

the RDRF flag to 0. Transition of the RDRF

flag from 0 to 1 can also be identified by an

RXI interrupt.

Serial reception continuation procedure:

To continue serial reception, before the

stop bit for the current frame is received,

read the RDRF flag, read RDR1, and clear

the RDRF flag to 0.

[1]

[2][3]

[4]

[5]

Figure 22.7 Sample Serial Reception Data Flowchart (1)

Rev. 1.0, 02/01, page 438 of 1184

< End >

[3]

Error handling

Parity error handling

Yes

Clear ORER, PER, and FER

flags in SSR1 to 0

Yes

Framing error handling

Yes

Overrun error handling

ORER=1

FER=1

Break?

PER=1

Clear RE bit in SCR1 to 0

Figure 22.8 Sample Serial Reception Data Flowchart (2)

Rev. 1.0, 02/01, page 439 of 1184

In serial reception, the SCI operates as described below.

1. The SCI monitors the transmissio n line, and if a 0 stop bit is d e tected, performs internal

synchronization and starts reception.

2. The received data is stored in RSR1 in LSB-to-MSB order.

3. The parity bit and stop bit are received.

After receiving these bits, the SCI carries out the following checks.

a. Parity check:

The SCI checks whether the number of 1 bits in the receive data agrees with the parity

(even or odd) set in the O/E bit in SMR1.

b. Stop bit check:

The SCI checks whether the stop bit is 1.

If there are two stop b its, only the first is checked.

c. Status check:

The SCI checks whether the RDRF flag is 0, indicating that the receive data can be

transferre d from RSR1 to RDR1.

If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored

in RDR1.

If a receive error* is detected in the error check, the operation is as shown in table 22.11.

4. If the RIE bit in SCR1 is set to 1 when the RDRF flag changes to 1, a receive-data-full

interrupt (RXI) request is generated.

Also, if the RIE b it in SCR1 is set to 1 when the ORER, PER, or FER f lag changes to 1, a

receive-error interrupt (ERI) request is generated.

Note: * Subsequent receive operations cannot be performed when a receive error has occurred.

Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be

cleared to 0.

Table 22.11 Receive Errors and Conditions for Occurrence

Receive Error Abbrev. Occurrence Condition Data Transfer

Overrun error ORER When the next data reception is

completed while the RDRF flag

in SSR1 is set to 1

Receive data is not tran sferre d

from RSR1 to RDR1

Framing error FER When the stop bit is 0 Receive data is transferred from

RSR1 to RDR1

Parity error PER When the received data differs

from the parity (even or odd) set

in SMR1

Receive data is transferre d from

RSR1 to RDR1

Rev. 1.0, 02/01, page 440 of 1184

Figure 22.9 shows an example of the operation for reception in asynchronous mode.

RDRF

FER

1 frame

D0 D1 D7 0/1 1 0 D0 D1 D7 0/1

1 1

Data

Start

bit Parity

bit Stop

bit Start

bit

Data

Parity

bit Stop

bit

ERI interrupt request

generated by framing

error

Idle state

(mark state)

RDR1 data read

and RDRF flag

cleared to 0 in

RXI interrupt

handling routine

RXI interrupt

request

generation

Figure 22.9 Example of SCI Operation in Reception

(Example with 8-Bit Data, Pa rity, One Stop Bit)

22.3.3 Multiprocessor Communication Function

The multipr ocessor communication fu nction performs serial commu nication using a

multipro cessor format, in which a multiprocessor bit is ad ded to the transfer da ta, in asynchronous

mode. Use of this function enables data transfer to be performed among a number of processors

sharin g transm ission lines.

When multipro cesso r communication is carried out, each receiving station is addr essed by a

unique ID code.

The serial communication cycle consists of two compon ent cycles: an ID transmission cycle

which specifies the receiv in g station, and a data transmission cycle. The multiprocesso r bit is used

to differentiate between the ID transmission cycle and the data transmission cycle.

The transmitting statio n first sends the ID of the receiving station with which it wants to perform

serial communication as data with a 1 mu ltiprocessor bit added. I t then sen ds transmit data as data

with a 0 multiprocessor bit added.

The receiving station sk ips the data until data with a 1 multiprocessor bit is sent.

When data with a 1 multiprocessor bit is received, the receiving station compares that d a ta with its

own ID. The station whose ID matches then receives the data sent next. Stations whose ID does

not match continue to skip the data until data with a 1 multiprocessor bit is again received. In this

way, data communication is carried out among a number of processors.

Figure 22 .10 shows an example of inter -processor communication using a multiprocessor format.

Rev. 1.0, 02/01, page 441 of 1184

1. Data Transfer Format

There are four data transfer formats.

When a multiprocessor format is specified, the parity bit specification is invalid.

For details, see table 2 2.10.

2. Clock

See the section on asynchronous mode.

Transmitting

station

Receiving

station A

(ID=01)

Receiving

station B

(ID=02)

Receiving

station C

(ID=03)

Receiving

station D

(ID=04)

Serial communication line

Serial

data

ID transmission cycle:

receiving station

specification

Data transmission cycle:

data transmission to

receiving station

specified by ID

(MPB=1) (MPB=0)

H'01 H'AA

Legend:

MPB : Multiprocessor bit

Figure 22.10 Example of Inter-Processor Communication Using Multiprocessor Format

(Transmission of Data H'AA to Receiving Statio n A)

3. Data Transfer Operations

a. Multip rocessor Serial Data Transmission

Figure 22.11 shows a sam ple flowchart for multipr ocessor serial data tran smission.

The followin g procedure should be used for multip rocessor serial data transmission.

Rev. 1.0, 02/01, page 442 of 1184

< End >

[1]

Yes

Initialization

Start transmission

Read TDRE flag in SSR1 [2]

Write transmit data to TDR1

and set MPBT bit in SSR1

Yes

Read TEND flag in SSR1

[3]

Yes

[4]

Clear PDR to 0 and set PCR to 1

Clear TE bit in SCR1 to 0

TDRE=1

Transmission end?

TEND=1

Break output?

Clear TDRE flag to 0

SCI initialization:

The SO1 pin is automatically designated as

the transmit data output pin.

SCI status check and transmit data write:

Read SSR and check that the TDRE flag is

set to 1, then write transmit data to TDR1.

Set the MPBT bit in SSR1 to 0 or 1.

Finally, clear the TDRE flag to 0.

Serial transmission continuation procedure:

To continue serial transmission, be sure to

read 1 from the TDRE flag to confirm that

writing is possible, then write data to TDR1,

and then clear the TDRE flag to 0.

Break output at the end of serial

transmission:

To output a break in serial transmission, set

the port PCR to 1, clear PDR to 0, then

clear the TE bit in SCR1 to 0.

[1]

[2]

[3]

[4]

Figure 22.11 Sample Multiprocessor Serial Transmission Flowchart

Rev. 1.0, 02/01, page 443 of 1184

In serial transmission, the SCI operates as described below.

1. The SCI mo nitors the TDRE flag in SSR1, an d if it is 0, recognizes that data h as been written

to TDR1, and transfers the data from TDR1 to TSR1.

2. After tran sferring data from TDR1 to TSR1, the SCI sets the TDRE flag to 1 and star ts

transmission.

If the TIE bit is set to 1 at this time, a transmit-data-empty interrup t ( T XI) is ge nerated.

The serial transmit data is sent from the SO2 pin in the following order.

a. Start bit:

One 0-bit is o utput.

b. Transmit data:

8-bit or 7-bit data is output in LSB-first order.

c. Multiprocessor bit

One multipr ocessor bit (MPBT value) is output.

d. Stop bit(s):

One or two 1-bits (stop bits) are output.

e. Mark state:

1 is output continuously u ntil the start bit that starts the n e xt transmission is sent.

3. The SCI checks the TDRE flag at the timing for sending the stop bit.

If the TDRE flag is clear ed to 0, data is transferred from TDR1 to TSR1, the stop bit is sent,

and then serial transmission of the next frame is started.

If the TDRE flag is set to 1, the TEND flag in SSR1 is set to 1 , the stop bit is sent, and th en the

mark state is enter ed in which 1 is output contin uou sly . If the TEIE bit in SCR1 is set to 1 at

this time, a transm it- end interrupt (TEI) request is generated.

Rev. 1.0, 02/01, page 444 of 1184

Figure 22.12 shows an example of SCI operation f or tr ansmission using a m ultiprocessor format.

TDRE

TEND

1 frame

D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1

1Data Data

TXI interrupt

request

general

Data written to TDR1 and

TDRE flag cleared to 0

in TXI interrupt handling

routine

TEI interrupt

request

generated

Idle state

(mark state)

TXI interrupt request

generated

Start

bit

Multi-

processor

bit Stop

bit Start

bit Stop

bit 1

Multi-

processor

bit

Figure 22.12 Example of SCI Operation in Transmission

(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)

b. Multiprocessor Serial Data Reception

Figure 22.13 sh ows sample flowcharts for multiprocessor serial reception.

The following procedur e should be used for multiprocessor serial data reception.

Rev. 1.0, 02/01, page 445 of 1184

Yes

< End >

[1]

Initialization

Start reception

Yes

[4]

Clear RE bit in SCR1 to 0

Error handling

(Continued on

next page)

[5]

Yes

FER∨ORER=1

RDRF=1

All data received?

Set MPIE bit in SCR1 to 1 [2]

Read ORER and FER flags in SSR1

Read RDRF flag in SSR1 [3]

Read receive data in RDR1

Yes

This station's ID?

Read ORER and FER flags in SSR1

Yes

Read RDRF flag in SSR1

Yes

FER∨ORER=1

Read receive data in RDR1

RDRF=1

SCI initialization:

The SI1 pin is automatically designated as

the receive data input pin.

ID reception cycle:

Set the MPIE bit in SCR1 to 1.

SCI status check, ID reception and

comparison:

Read SSR and check that the RDRF flag is

set to 1, then read the receive data in

RDR1 and compare it with this station's ID.

If the data is not this station's ID, set the

MPIE bit to 1 again, and clear the RDRF

flag to 0.

If the data is this station's ID, clear the

RDRF flag to 0.

SCI status check and data reception:

Read SSR1 and check that the RDRF flag

is set to 1, then read the data in RDR1.

Receive error handling and break

detectioon:

If a receive error occurs, read the ORER

and FER flags in SSR1 to identify the error.

After performing the appropriate error

handling, ensure that the ORER and FER

flags are both cleared to 0.

Reception cannot be resumed if either of

these flags is set to 1.

In the case of a framing error, a break can

be detected by reading the SI1 in value.

[1]

[2]

[3]

[4]

[5]

Figure 22.13 Sample Multiprocessor Serial Reception Flowchart (1)

Rev. 1.0, 02/01, page 446 of 1184

< End >

Error handling

Yes

Clear ORER, PER, and FER

flags in SSR1 to 0

Yes

Framing error handling

Overrun error handling

ORER=1

FER=1

Break?

Clear RE bit in SCR1 to 0

[5]

Figure 22.14 Sample Multiprocessor Serial Reception Flowchart (2)

Rev. 1.0, 02/01, page 447 of 1184

Figure 22.15 shows an examp le of SCI operation for multiprocessor format reception.

MPIE

RDR1

value

0D0D1 D71 1 0D0D1 D7 01

Data (ID1)

Start

bit MPB Stop

bit Start

bit Data (Data 1) MPB Stop

bit

RXI interrupt

request (multi-

processor

interrupt)

generated

Idle state

(mark state)

RDRF

RDR1 data read

and RDRF flag

cleared to 0 in

RXI interrupt

handling routine

If not this station's

ID, MPIE bit is set

to 1 again

RXI interrupt request

is not generated, and

RDR1 retains its state

ID1

(a) Data does not match station's ID

MPIE

RDR1

value

0D0D1 D71 1 0D0D1 D7 01

Data (ID2)

Start

bit

MPB

Stop

bit Start

bit Data (Data 2) MPB Stop

bit

RXI interrupt

request (multi-

processor

interrupt)

generated

Idle state

(mark state)

RDRF

RDR1 data read and

RDRF flag cleared

to 0 in RXI interrupt

handling routine

Matches this station's

ID, so reception continues,

and data is received in RXI

interrupt handling routine

MPIE bit set

to 1 again

ID2

(b) Data matches station's ID

Data2ID1

MPIE=0

Figure 22.15 Example of SCI Operation in Reception

(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)

Rev. 1.0, 02/01, page 448 of 1184

22.3.4 Operation in Synchronous Mode

In synchronous mod e, data is transmitted or received in synchronization with clock pulses, making

it suitable for high-speed serial communication.

Inside the SCI, the tran smitter and receiv er are independent units, en ab ling full-duplex

communication by use of a common clock. Both the transmitter and the receiver also have a

double-buffered structure, so th at data can be read or written during transmission or reception,

enabling continuous data transfer.

Figure 22.16 shows the general format for synchronous serial communication.

Don't

care

Don't

care

One unit of transfer data (character or frame)

Bit 0

Serial

data

Synchronous

clock

Bit 1 Bit 3 Bit 4 Bit 5

LSB MSB

Bit 2 Bit 6 Bit 7

Note: * High except in continuous transfer

Figure 22.16 Data Format in Synchronous Communication

In synchronous serial communication, data on the transmission line is output from one falling edge

of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock.

In synchronous serial communication, one character consists of data output starting with the LSB

and ending with the MSB. After the MSB is output, the transmission line holds the MSB state.

In synchronous mode, the SCI receives data in synchronization with the rising edge of the serial

clock.

• Data Transfer Format

A fixed 8-bit data format is used.

No parity or m ultiprocessor bits are added.

• Clock

Either an internal clock gene r ated by the built-in baud rate generator or an extern al ser ial clock

input at the SCK pin can be selected, according to the setting of the C/A bit in SMR1 and the

CKE1 and CKE0 bits in SCR1. For details on SCI clock source selection, see table 22.9.

When the SCI is operated on an internal clock, the serial clock is output from the SCK pin.

Eight serial clock pulses are output in the transfer of one character, and when no transfer is

performed the clock is fixed high. When only receive operations are performed, however, the

serial clock is outp ut until an overrun error occurs or the RE bit is cleared to 0 . To perform

receive operations in units of one character, select an external clock as the clock source.

• Data Transfer Operations

Rev. 1.0, 02/01, page 449 of 1184

 SCI Initialization (Synchronous Mode)

Before transmitting an d receiving data, first clear the TE and RE bits in SCR1 to 0, then

initialize the SCI as described belo w.

When the operating mode, tran sfer format, etc., is changed, the TE and RE bits must be

cleared to 0 before making the change using the following procedure. When the TE bit is

cleared to 0, the TDRE flag is set to 1 an d TSR1 is initialized. Note th at clear ing the RE

bit to 0 does not change the settings of the RDRF, PER, FER, and ORER flags, or the

contents of RDR1.

Figure 22.17 shows a samp le SCI initialization flo wchart.

Wait

Note: For simultaneous data transmit and receive operations, the TE and RE bits must be cleared

to 0 or set to 1 simultaneously.

Start initialization

Set data transfer format

in SMR1 and SCMR

Yes

Set value in BRR1

Clear TE and RE bits in SCR1 to 0

[2]

[3]

Set TE and RE bits in SCR1 to 1,

and set RIE, TIE, TEIE, and MPIE

bits [4]

1-bit interval elapsed?

Set CKE1 and CKE0 bits in

SCR1 (TE, RE bits 0) [1]

Set the clock selection in SCR1. Be sure to

clear bits RIE, TIE, TEIE, and MPIE, TE

and RE, to 0.

Set the data transfer format in SMR1 and

SCMR1.

Write a value corresponding to the bit rate

to BRR1. This is not necessary if an

external clock is used.

Wait at least one bit interval, then set the

TE bit or RE bit in SCR1 to 1.

Also set the RIE, TIE, TEIE, and MPIE bits.

Setting the TE and RE bits enables the

SO1 and SI1 pins to be used.

[1]

[2]

[3]

[4]

Figure 22.17 Sa mple SCI Initializatio n Flowchart

Rev. 1.0, 02/01, page 450 of 1184

 Serial Data Transmission (Synchronous Mode)

Figure 22.18 shows a sample flowchart for serial transmission.

The following procedure should be used for serial data tran smission.

< End >

[1]

Yes

Initialization

Start transmission

Read TDRE flag in SSR1 [2]

Write transmit data to TDR1 and

clear TDRE flag in SSR1 to 0

Yes

Read TEND flag in SSR1

[3]

Clear TE bit in

SCR1 to 0

TDRE=1

All data transmitted?

TEND=1

SCI initialization:

The SO1 pin is automatically designated as

the transmit data output pin.

SCI status check and transmit data write:

Read SSR1 and check that the TDRE flag

is set to 1, then write transmit data to TDR1

and clear the TDRE flag to 0.

Serial transmission continuation procedure:

To continue serial transmission, be sure to

read 1 from the TDRE flag to confirm that

writing is possible, then write data to TDR1,

and then clear the TDRE flag to 0.

[1]

[2]

[3]

Figure 22.18 Sample Serial Transmission Flowchart

Rev. 1.0, 02/01, page 451 of 1184

In serial transmission, the SCI operates as described below.

1. The SCI mo nitors the TDRE flag in SSR1, an d if it is 0, recognizes that data h as been written

to TDR1, and transfers the data from TDR1 to TSR1.

2. After tran sferring data from TDR1 to TSR1, the SCI sets the TDRE flag to 1 and star ts

transmission . I f the TIE bit is set to 1 at this tim e, a tr ansmit-data-empty interrupt (TXI) is

generated.

When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an

external clock has been specified, data is output synchronized with the input clock.

The serial transmit data is sent from the SO1 pin starting with the LSB (bit 0) and ending with

the MSB (bit 7) .

3. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7).

If the TDRE flag is cleared to 0, data is transferred from TDR1 to TSR1, and serial

transmission of the next frame is started.

If the TDRE flag is set to 1, the TEND flag in SSR1 is set to 1 , the MSB (bit 7) is sent, and the

SO1 pin m aintains its state.

If the TEIE bit in SCR1 is set to 1 at this time, a transmit-end in ter r upt ( TEI) r equest is

generated.

4. After completion of serial transmission, the SCK pin is held in a constant state.

Figure 22.19 shows an example of SCI operation in transmission.

Transfer

direction

Bit 0

Serial

data

Synchronous

clock

1 frame

TDRE

TEND

Data written to TDR1

and TDRE flag cleared

to 0 in TXI interrupt

handling routine

TXI interrupt

request

generated

Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7

TXI interrupt

request

generated

TEI interrupt

request

generated

Figure 22.19 Example of SCI Operation in Transmission

Rev. 1.0, 02/01, page 452 of 1184

 Serial Data Reception (Synchronous Mode)

Figure 22.20 shows a sample flowchart for serial reception.

The following procedure should be used for serial data reception.

When changing the operating mode from asynchronous to synchronous, be sure to check

that the ORER, PER, and FER flags are all cleared to 0.

The RDRF flag will no t be set if the FER or PER f lag is set to 1, and neither tran smit nor

receive operations will be po ssible.

Rev. 1.0, 02/01, page 453 of 1184

Yes

< End >

[1]

Initialization

Start reception

[2]

Yes

Read RDRF flag in SSR1 [4]

[5]

Clear RE bit in SCR1 to 0

Error handling

(Continued below)

[3]

Read receive data in RDR1,

and clear RDRF flag in SSR1 to 0

Yes

ORER=1

RDRF=1

All data received?

Read ORER flag in SSR1

< End >

Error handling

Clear ORER flag in

SSR1 to 0

Overrun error handling

[3]

SCI initialization:

The SI1 pin is automatically designated as

the receive data input pin.

Receive error handling:

IF a receive error occurs, read the ORER

flag in SSR1, and after performing the

appropriate error handling, clear the ORER

flag to 0. Transfer cannot be resumed if

the ORER flag is set to 1.

SCI status check and receive data read:

Read SSR1 and check that the RDRF flag

is set to 1, then read the receive data in

RDR1 and clear the RDRF flag to 0.

Transition of the RDRF flag from 0 to 1 can

also be identified by and RXI interrupt.

Serial reception continuation procedure:

To continue serial reception, before the

MSB (bit 7) of the current frame is received,

finish reading the RDRF flag, reading

RDR1, and clearing the RDRF flag to 0.

[1]

[2][3]

[4]

[5]

Figure 22.20 Sample Serial Reception Flowchart

Rev. 1.0, 02/01, page 454 of 1184

In serial reception, the SCI operates as described below.

1. The SCI performs internal initialization in synchronization with serial clock input or output.

2. The received data is stored in RSR1 in LSB-to-MSB order.

After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be

transferre d from RSR1 to RDR1.

If this check is passed, the RDRF flag is set to 1, and the receive data is sto red in RDR1. If a

receive error is detected in the error check, the operation is as shown in table 22.11.

Neither transmit nor receive operations can be performed subsequently when a receive error

has been found in the error check.

3. If the RIE bit in SCR1 is set to 1 when the RDRF flag changes to 1, a receive-data-full

interrupt (RXI) request is generated.

Also, if the RIE bit in SCR1 is set to 1 when the ORER flag changes to 1, a receive-error

interrupt (ERI) request is generated.

Figure 22.21 shows an example of SCI operation in reception.

Bit 7

Serial

data

Synchronous

clock

1 frame

RDRF

ORER

ERI interrupt request

generated by

overrun error

RXI interrupt

request

generated

RDR1 data read and

RDRF flag cleared to 0

in RXI interrupt

handling routine

RXI interrupt

request

generated

Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7

Figure 22.21 Example of SCI Operation in Reception

Rev. 1.0, 02/01, page 455 of 1184

 Simultaneous Serial Data Transmission and Reception (Synchronous Mode)

Figure 22.22 shows a sample flowchart for simultaneous serial transmit and receive

operations.

The following procedure should be used for simultaneous serial data transmit and receive

operations.

Yes

< End >

[1]

Initialization

Start transfer

[5]

Error handling

[3]

Read receive data in RDR1, and

clear RDRF flag in SSR1 to 0

Yes

ORER=1

All data received?

[2]

Read TDRE flag in SSR1

Yes

TDRE=1

Write transmit data to TDR1 and

clear TDRE flag in SSR1 to 0

Yes

RDR=1

Read ORER flag in SSR1

[4]

Read RDRF flag in SSR1

Clear TE and RE

bits in SCR1 to 0

Note: When switching from transmit or receive operation

to simultaneous transmit and receive operations, first

clear the TE bit and RE bit to 0, then set both these

bits to 1 simultaneously.

SCI initialization:

The SO1 pin is designated as the transmit

data output pin, and the SI1 pin is

designated as the receive data input pin,

enabling simultaneous transmit and receive

operations.

SCI status check and transmit data write:

Read SSR1 and check that the TDRE flag

is set to 1, then write transmit data to TDR1

and clear the TDRE flag to 0.

Transition of the TDRE flag from 0 to 1 can

also be identified by a TXI interrupt.

Receive error handling:

If a receive error occurs, read the ORER

flag in SSR1, and after performing the

appropriate error handling, clear the ORER

flag to 0. Transmission/reception cannot

be resumed if the ORER flag is set to 1.

SCI status check and receive data read:

Read SSR1 and check that the RDRF flag

is set to 1, then read the receive data in

RDR1 and clear the RDRF flag to 0.

Transition of the RDRF flag from 0 to 1 can

also be identified by an RXI interrupt.

Serial transmission/reception continuation

procedure:

To continue serial transmission/reception,

before the MSB (bit 7) of the current frame

is received, finish reading the RDRF flag,

reading RDR1, and clearing the RDRF flag

to 0. Also before the MSB (bit 7) of the

current frame is transmitted, read 1 from

the TDRE flag to confirm that writing is

possible, then write data to TDR1 and clear

the TDRE flag to 0.

[1]

[2]

[3]

[4]

[5]

Figure 22.22 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations

Rev. 1.0, 02/01, page 456 of 1184

22.4 SCI Interrupts

The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt

(ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI)

request. Table 22. 12 shows the interrupt sour ces and their relative priorities. I ndividual interrupt

sources can be enabled or disabled with the TIE, RI E, and TEIE bits in SCR1. Each kind of

interrupt r equ est is sent to the interrupt controller independently.

When the TDRE flag in SSR1 is set to 1, a TXI interrupt request is generated. When the TEND

flag in SSR1 is set to 1, a TEI interrupt request is generated.

When the RDRF flag in SSR1 is set to 1, an RXI interrupt request is gener a ted. When the ORER,

PER, or FER flag in SSR1 is set to 1, an ERI interrupt requ est is gen e r a ted.

Table 22.12 SCI Interrupt Sources

Channel Interrupt Source Description Priority

ERI Interrupt by receive error (ORER, FER, or PER)

RXI Interrupt by receive data register full (RDRF)

TXI Interrupt by transmit data register empty (TDRE)

TEI Interrupt by transmit end (TEND)

High

Low

The TEI interrupt is requested when th e TEND f lag is set to 1 wh ile the TEIE bit is set to 1. The

TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a

TXI interrupt are requested simultaneously, th e TXI interrupt will have priority for acceptance,

and the TDRE flag and TEND flag may be cleared. Note that the TEI interrupt will not be

accepted in this case.

Rev. 1.0, 02/01, page 457 of 1184

22.5 Usage Notes

The following points should be noted when using the SCI.

• Relation between Wr ites to TDR1 and th e TDRE Flag

The TDRE flag in SSR1 is a status flag that indicates that transmit data has been transferred

from TDR1 to TSR1. When the SCI tran sf ers data from TDR1 to TSR1, the TDRE flag is set

to 1.

Data can be written to TDR1 regardless of the state of the TDRE flag. However, if new data is

written to TDR1 wh en the TDRE flag is cleared to 0, the data stored in TDR1 will be lost since

it has not yet been transferred to TSR1. It is ther ef ore essential to check that th e TDRE flag is

set to 1 before wr iting transmit data to TDR1.

• Operation when Multiple Receive Errors Occur Simultaneously

If a number of receive errors occur at the same time, the state of the status flags in SSR1 is as

shown in table 22.13. If there is an overrun error, data is not transferred from RSR1 to RDR1,

and the receive data is lost.

Table 22.13 State of SSR1 Status Flags and Transfer of Receive Data

SSR1 Status Flags Receive Data Transfer

RDRF ORER FER PER RSR1 to RDR1 Receive Error Status

1 1 0 0 X Overrun error

0 0 1 0 Framing error

0 0 0 1 Parity error

1 1 1 0 X Overrun error + framing error

1 1 0 1 X Overrun error + parity error

0 0 1 1 Framing error + parity error

1 1 1 1 X Overrun error + framing error +

parity error

Notes: : Receive data is transferred from RSR1 to RDR1.

X: Receive data is not transferred from RSR1 to RDR1.

Rev. 1.0, 02/01, page 458 of 1184

• Break Detection and Processing

When framing error (FER) detection is performed, a break can be detected by reading the SI1

pin value directly. In a break, the input from the SI1 pin becomes all 0s, and so the FER flag is

set, and the parity error flag (PER) may also be set.

Note that, since the SCI continues the receive operation after receiving a break, even if the

FER flag is cleared to 0, it will be set to 1 ag ain.

• Sending a Break

The SO1 pin has a dual function as an I/O port whose direction (input or output) is determined

by DR and DDR. This can be used to send a break.

Between serial transmission initializatio n and setting o f the TE bit to 1, the mark state is

replaced by the value of PDR (the p in does not function as the SO1 pin until the TE bit is set to

1). Consequently, PCR and PDR for the port corresponding to the SO1 pin are first set to 1.

To send a break during serial transmission, first clear PDR to 0, then clear the TE bit to 0.

When the TE bit is clear ed to 0, the transmitter is initialized regardless of the current

transmission state, the SO1 pin becomes an I/O port, and 0 is output from the SO1 pin.

• Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)

Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1,

even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before

starting transmissio n.

Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0.

• Receive Data Sampling Timing and Reception Margin in Asynchronous Mode

In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the

transfer rate.

In reception, the SCI samples th e falling edge of the start bit using th e b a sic clo c k, and

performs internal synchronization. Receive data is latched internally at the rising edge of the

8th pulse o f the b asic clock. This is illustrated in fig ure 22.23.

Rev. 1.0, 02/01, page 459 of 1184

Internal basic

clock

16 clocks

8 clocks

Receive data

Synchronization

sampling timing

Start bit D0 D1

Data sampling

timing

15 0 7 15 00 7

Figure 22.23 Receive Data Sampling Timing in Asynchronous Mode

Thus the reception margin in asynchronous mode is given by formula (1) below.

M = | (0.5 – 1

2N ) – (L – 0.5) F – | D – 0.5 |

N (1 + F) | × 100%

... Formula (1)

Where M : Reception margin (%)

N : Ratio of bit rate to clock (N = 16)

D : Clock duty (D = 0 to 1.0)

L : Frame length (L = 9 to 12)

F : Absolute value of clock rate deviation

Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin of 46.875% is given by

formula (2) below.

When D = 0.5 and F = 0,

M = (0.5 – 1

2 × 16 ) × 100%

= 46.875% ... Formula (2)

However, this is only the computed value, and a margin of 20% to 30% should be allowed in

system design.

Rev. 1.0, 02/01, page 460 of 1184

• Operation in Case of Mode Transition

 Transmission

Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module

stop mode, standby mode, watch mode, subactive mode, or subsleep mode transition.

TSR1, TDR1, and SSR1 are reset. The output pin states in module stop mode, standby

mode, watch mode, subactive mode, or subsleep mode depend on the port settings, and

becomes high-level output after the relevant mode is cleared. If a transition is made during

transmission, the data being transmitted will be undefined. When transmitting without

changing the transmit mode after the relevant mode is cleared, transmission can be started

by setting TE to 1 again, and performing the following sequence: SSR1 read Æ TDR1

write Æ TDRE clearance. To transmit with a different transmit mode after clearing the

relevant mode, th e pro cedur e must be started again from initialization . Figure 22.24 shows

a sample flowchart for mode transition during transmission. Port pin states are shown in

figures 22.25 and 22.26.

 Reception

Receive operation should be stopped (by clearing RE to 0) before making a module stop

mode, standby mode, watch mode, subactive mode, or subsleep mode transition. RSR1,

RDR1, and SSR1 are reset. If a transition is made without stopping operation, the data

being received will be invalid. To continue receiving without changing the reception mode

after the relevant mode is cleared, set RE to 1 before starting reception. To receive with a

different receive mode, the procedure must be started again from initialization.

Figure 22.27 shows a sample flowchart for mode transition during reception.

Rev. 1.0, 02/01, page 461 of 1184

Read TEND flag in SSR1

TE= 0

Transition to standby

mode, etc.

Exit from standby

mode, etc.

Change

operating mode? No

All data

transmitted?

TEND = 1

Yes

[1]

[3]

[2]

TE= 1Initialization

[1] Data being transmitted is interrupted.

After exiting software standby mode,

etc., normal CPU transmission is

possible by setting TE to 1, reading

SSR1, writing TDR1, and clearing

TDRE to 0.

[2] If TIE and TEIE are set to 1, clear

them to 0 in the same way.

[3] Includes module stop mode, watch

mode, subactive mode, and subsleep

mode.

Figure 22.24 Sample Flowchart for Mode Transition during Transmission

Rev. 1.0, 02/01, page 462 of 1184

SCK1 output pin

TE bit

SO1 output pin Port input/output High outputPort input/output High output Start Stop

Start of transmission End of

transmission

Port input/output

SCI TxD output Port SCI TxD

output

Port

Transition

to standby Exit from

standby

Figure 22.25 Asynchronous Transmi ssion Using Internal Clock

Port input/output

Last TxD bit held

High output*Port input/output Marking output

Port input/output

SCI TxD output PortPort

Note: * Initialized by software standby.

SCK1 output pin

TE bit

SO1 output pin

SCI TxD

output

Start of transmission End of

transmission Transition

to standby Exit from

standby

Figure 22.26 Synchronous Transmission Using Internal Clock

Rev. 1.0, 02/01, page 463 of 1184

RE= 0

Transition to standby

mode, etc.

Read receive data in RDR1

Read RDRF flag in SSR1

Exit from standby

mode, etc.

Change

operating mode? No

RDRF= 1

Yes

No [1]

[2]

[1]

[2]

RE= 1Initialization

Receive data being received

becomes invalid.

Includes module stop mode,

watch mode, subactive mode,

and subsleep mode.

Figure 22.27 Sample Flowchart for Mode Transition during Reception

Rev. 1.0, 02/01, page 464 of 1184

Rev. 1.0, 02/01, page 465 of 1184

Section 23 I2C Bus Interface (IIC)

23.1 Overview

This LSI incorporates a 2-channel I2C bus interface (H8S/2197S and H8S/2196S: 1 channel).

The I2C bus interf ace confor ms to an d provides a sub set of the Philips I2C bus (inter-IC bus)

interface functions. The register configuration that controls the I2C bus differs partly from the

Philips con f iguration, however.

Each I2C bus interface channel uses only one data line (SDA) and one clock line (SCL) to transfer

data, saving board and connector space.

23.1.1 Features

• Selection of addressing format or non-addressing format

 I2C bus format: addressing format with acknowledge bit, for master/slave operation

 Serial format: non-addressing format without acknowledge bit, for master operation only

• Conforms to Philip s I2C bus interface (I2C bus format)

• Two ways of setting slave address (I2C bus format)

• Start and stop conditions generated automatically in master mode (I2C bus format)

• Selection of acknowledge output levels when receiving (I2C bus format)

• Automatic loading of acknowledge bit when transmitting (I2C bus format)

• Wait function in master mode (I2C bus format)

 A wait can be inserted by driving the SCL pin low after data transfer, excluding

acknowledgement. The wait can be cleared by clearing the interrupt flag.

• Wait function in slave mode (I2C bus format)

 A wait request can be generated by driving the SCL pin low after data transfer, excluding

acknowledgement. The wait request is cleared when the next transfer becomes possible.

• Three interrupt sources

 Data transfer end (including transmission mode transition with I2C bus format and address

reception after loss of master arbitration)

 Address match: when any slave address matches or the general call address is received in

slave receive mode (I2C bus format)

 Stop con dition detection

• Selection of 16 internal clocks (in master mode)

• Direct bus drive (with SCL and SDA pins)

 Four pins P26/SCL0, P25/SDA0, P24/SCL1 and P23/SDA1 (normally CMOS pins)

function as NMOS-only outputs when the bus drive function is selected.

Rev. 1.0, 02/01, page 466 of 1184

23.1.2 Block Diagram

Figure 23.1 shows a block diagram of the I2C bus interface.

Figure 23.2 shows an example of I/O pin connections to external circuits. I/O pins are driven only

by NMOS and apparently function as NMOS open-drain outputs. However, applicable voltages to

input pins depend on the power (Vcc) voltage of this LSI.

SCL

Noise

canceller

Bus state

decision

circuit

Output data

control

circuit

ICCR

Clock

control ICMR

ICSR

ICDRS

Address

comparator

Arbitration

decision

circuit

SAR, SARX

SDA

Noise

canceler

Interrupt

generator Interrupt

request

Internal data bus

Legend:

ICCR

ICMR

ICSR

ICDR

SAR

SARX

: I

C control register

: I

C mode register

: I

C status register

: I

C data register

: Slave address register

: Slave address register X

: Prescaler

ICDRR

ICDRT

Figure 23.1 Block Diagram of I2C Bus Interface

Rev. 1.0, 02/01, page 467 of 1184

VCC

SCLin

SCLout

SCL

SDAin

SDAout

(Master)

This LSI

SDA

SCL

SDA

SCLin

SCLout

SCL

SDAin

SDAout

(Slave 1)

SDA

SCLin

SCLout

SCL

SDAin

SDAout

(Slave 2)

SDA

Figure 23.2 I2C Bus Interface Connections (Example: This Chip as Master)

23.1.3 Pin Configuration

Table 23.1 summarizes the input/output pins used by the I2C bus interface.

Table 23.1 I2C Bus Interface Pins

Channel Name Abbrev.* I/O Function

Serial clock pin SCL0 Input/output IIC0 serial clock input/output

Serial data pin SDA0 Input/outpu t IIC0 serial data input/output

Formatless serial clock pin SYNCI Input IIC0 formatless serial clock input

Serial clock pin SCL1 Input/output IIC1 serial clock input/output 1

Serial data pin SDA1 Input/outpu t IIC1 serial data input/output

Notes: * In this section, channel numbers in the abbreviated register names are omitted; SCL0

and SCL1 are collectively referred to as SCL, and SDA0 and SDA1 as SDA.

Channel 0 is not provided (incorporated in) for the H8S/2197S and H8S/2196S.

Rev. 1.0, 02/01, page 468 of 1184

23.1.4 Register Configuration

Table 23.2 summarizes the registers of the I2C bus interface.

Table 23.2 Register Co nf iguration

Channel Name Abbrev. R/W Initial Value Address*1

0*3 I

2C bus control register ICCR0 R/W H'01 H'D0E8

2C bus status register ICSR0 R/W H'00 H'D0E9

2C bus data register ICDR0 R/W  H'D0EE*2

2C bus mode register ICMR0 R/W H'00 H'D0EF*2

Slave address register SAR0 R/W H'00 H'D0EF*2

Second slave address register SARX0 R/W H'01 H'D0EE*2

1 I2C bus control regi ster ICCR1 R/W H'01 H'D158

2C bus status register ICSR1 R/W H'00 H'D159

2C bus data register ICDR1 R/W  H'D15E*2

2C bus mode register ICMR1 R/W H'00 H'D15F*2

Slave address register SAR1 R/W H'00 H'D15F*2

Second slave address register SARX1 R/W H'01 H'D15E*2

0 and 1 DDC switch register DDCSWR R/W H'0F H'D0E5

Module stop control register MSTPCRH

MSTPCRL R/W H'FF

H'FF H'FFEC

H'FFED

Notes: 1. Lower 16 bits of the address.

2. The registers that can be read from or written to depend on the ICE bit in the I2C bus

control register. The slave address registers can be accessed when ICE = 0, and the

I2C bus mode registers can be accessed when ICE = 1.

3. Channel 0 is not provided (incorporated in) for the H8S/2197S and H8S/2196S.

Rev. 1.0, 02/01, page 469 of 1184

23.2 Register Descriptions

23.2.1 I2C Bus Data Register (ICDR)

ICDR7

—

R/W

ICDR6

—

R/W

ICDR5

—

R/W

ICDR4

—

R/W

ICDR3

—

R/W

ICDR0

—

R/W

ICDR2

—

R/W

ICDR1

—

R/W

Bit :

Initial value :

R/W :

ICDRR

ICDRR7

—

ICDRR6

—

ICDRR5

—

ICDRR4

—

ICDRR3

—

ICDRR0

—

ICDRR2

—

ICDRR1

—

Bit :

Initial value :

R/W :

ICDRS

ICDRS7

—

ICDRS6

—

ICDRS5

—

ICDRS4

—

ICDRS3

—

ICDRS0

—

ICDRS2

—

ICDRS1

—

Bit :

Initial value :

R/W :

ICDRT

ICDRT7

—

ICDRT6

—

ICDRT5

—

ICDRT4

—

ICDRT3

—

ICDRT0

—

ICDRT2

—

ICDRT1

—

Bit :

Initial value :

R/W :

TDRE, RDRF (Internal flag)

—

RDRF

—

TDRE

—

Bit :

Initial value :

R/W :

Rev. 1.0, 02/01, page 470 of 1184

ICDR is an 8-bit readable/writable register that is used as a transmit data register when

transmitting and a receive data register when receiving. ICDR is divided internally into a shift

or written by the CPU, ICDRR is read-only, and ICDRT is write-only. Data transfers among the

three registers are performed automatically in coordination with changes in the bus state, and

affect the status of internal flags such as TDRE and RDRF.

After transmission/reception of one frame of data using ICDRS, if the I2C bus is in transmit mo de

and the next data is in I CDRT (th e TDRE flag is 0), data is transferre d automatically from ICDRT

to ICDRS. After transmission/reception of one frame of data using ICDRS, if the I2C bus is in

receive mode and no previous data remains in ICDRR (the RDRF flag is 0), data is transferred

automatically f rom ICDRS to ICDRR.

If the number of bits in a f r a me, exclu ding the acknowledge bit, is less than 8, transmit data and

receive data are stored differently. Transmit data should be written justified to ward the MSB side

when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB

side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1.

ICDR is assigned to the same address as SARX, an d can be written and read on ly when the ICE

bit is set to 1 in ICCR.

The value of ICDR is undefined after a reset.

The TDRE and RDRF flags are set and cleared under the conditions shown below. Setting the

TDRE and RDRF flags affects the status of the interrupt flags.

Rev. 1.0, 02/01, page 471 of 1184

TDRE Description

0 The next transmit data is in ICDR (ICDRT), or transmission cannot be started

[Clearing cond iti ons ] (Initial val ue)

1. When transmit data is written in ICDR (ICDRT) in transmit mode (TRS = 1)

2. When a stop condition is detected in the bus line state after a stop condition is

issued with the I2C bus format or serial form at sele cte d

3. When a stop condition is detected with the I2C bus format selected

4. In receive mode (TRS = 0)

(A 0 write to TRS during transfer is valid after reception of a frame containing an

acknowle dge bit)

1 The next transmit data can be written in ICDR (ICDRT)

[Setting conditions]

1. In transmit mode (TRS = 1), when a start condition is detected in the bus line state

after a start condition is issued in master mode with the I2C bus format or serial

format selected

2. In transmit mode (TRS = 1) when formatless transfer is selected

3. When data is transferred from ICDRT to ICDRS

(Data transfer from ICDRT to ICDRS when TRS = 1 and TDRE = 0, and ICDRS is

empty)

4. When a switch is made from receive mode (TRS = 0) to transmit mode (TRS = 1)

after detection of a start condition

RDRF Description

0 The data in ICDR (ICDRR) is invalid (Initial value)

[Clearing cond iti on]

When ICDR (ICDRR) receive data is read in receive mode

1 The ICDR (ICDRR) receive data can be read

[Setting condition]

When data is transferred from ICDRS to ICDRR

(Data transfer from ICDRS to ICDRR in case of normal termination with TRS = 0 and

RDRF = 0)

Rev. 1.0, 02/01, page 472 of 1184

23.2.2 Slave Address Register (SAR)

SVA6

R/W

SVA5

R/W

SVA4

R/W

SVA3

R/W

SVA2

R/W

SVA1

R/W

SVA0

R/W

Bit :

Initial value :

R/W :

SAR is an 8-bit readable/writable register that stores the slave address and selects the

communication format. When the chip is in slave mode (and the addressing format is selected), if

the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition,

the chip operates as the slave device specified by the master device. SAR is assigned to the same

address as ICMR, and can be written and read only when the ICE bit is cleared to 0 in ICCR.

SAR is initialized to H'00 by a reset.

Bits 7 to 1



Slave Address (SVA6 to SVA0 ): Set a unique address in bits SVA6 to SVA0,

differing from the addresses of other slave devices connected to the I2C bus.

Rev. 1.0, 02/01, page 473 of 1184

Bit 0



Format Select (FS): Used together with th e FSX bit in SARX and the SW bit in

DDCSWR to select the communication format.

• I

2C bus format: addressing format with acknowledge bit

• Synchronous serial format: non-addressing format without acknowledge bit, for master

mode only

• Formatless transfer (only for channel 0): non-addressing with or without an acknowledge

bit and without detection of start or stop condition, for slave mode only.

The FS bit also specifies whether or not SAR slave address recognition is performed in slave

mode.

DDCSWR

Bit 6

SAR

Bit 0

SARX

Bit 0

SW FS FSX Operating Mode

0 I2C bus format

• SAR and SARX slave addresses recognized

1 I2C bus format (Initial value)

• SAR slave address recognized

• SARX slave address ignored

0 I2C bus format

• SAR slave address ignored

• SARX slave address recognized

1 Synchronous serial format

• SAR and SARX slave addresses ignored

0 0

Formatless transfer (start and stop conditions are not

detected)

• With acknowledge bit

Formatless transfer* (start and stop conditions are not

detected)

• Without acknowledge bit

Note: * Do not use this setting when automatically switching the mode from formatless transfer to

I2C bus format by setting DDCSWR.

Rev. 1.0, 02/01, page 474 of 1184

23.2.3 Second Slave Address Reg ister (SARX)

SVAX6

R/W

SVAX5

R/W

SVAX4

R/W

SVAX3

R/W

SVAX2

R/W

FSX

R/W

SVAX1

R/W

SVAX0

R/W

Bit :

Initial value :

R/W :

SARX is an 8-bit readable/writable register that stores the second slave address and selects the

communication format. When the chip is in slave mode (and the addressing format is selected), if

the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition,

the chip operates as the slave device specified by the master device. SARX is assigned to the

same address as ICDR, and can be written and read on ly when the ICE bit is clear ed to 0 in ICCR.

SARX is initialized to H'01 by a reset and in hard war e standby mode .

Bits 7 to 1



Second Slave Address (SVAX6 to SVAX0): Set a unique address in bits SVAX6 to

SVAX0, differing from the addresses of other slave devices connected to the I2C bus.

Bit 0



Format Select X (FSX): Used together with the FSX bit in SARX an d the SW bit in

DDCSWR to select the communication format.

• I2C bus format: addressing format with acknowledge bit

• Synchronous serial format: non-addressing format withou t acknowledge bit, for master mode

only

• Formatless transfer: non-addressing with or without an acknowledge bit and without detection

of start or stop condition, for slave mode only.

The FSX bit also specifies whether or not SARX slave address recognition is performed in slave

mode. For details, see the description of the FS bit in section 23.2.2, Slave Address Register

(SAR).

Rev. 1.0, 02/01, page 475 of 1184

23.2.4 I2C Bus Mode Register (ICMR)

MLS

R/W

WAIT

R/W

CKS2

R/W

CKS1

R/W

CKS0

R/W

BC0

R/W

BC2

R/W

BC1

R/W

Bit :

Initial value :

R/W :

ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred

first, performs master mode wait control, and selects the master mode transfer clock frequ ency and

the transfer b it count. ICMR is assigned to the same address as SAR. ICMR can be written an d

read only when the ICE bit is set to 1 in ICCR.

ICMR is initialized to H'00 by a reset.

Bit 7



MSB-First/LSB-First Select (MLS): Selects whether data is tran sferred MSB-first or

LSB-first.

If the number of bits in a frame, excluding the acknowledg e bit, is less than 8, tr ansmit data and

receive data are stored differently. Transmit data shou ld be written justified toward the MSB side

when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB

side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1.

Do not set this b it to 1 when the I2C bus format is used.

Bit 7

MLS Description

0 MSB-first (Initial value)

1 LSB-first

Rev. 1.0, 02/01, page 476 of 1184

Bit 6



Wait Insertion Bit (WAIT): Selects whether to insert a wait between the transfer of data

and the acknowledge bit, in master mode with the I2C bus format. When WAIT is set to 1, after

the fall of th e clock for the final data bit, the IRIC flag is set to 1 in I CCR, an d a wait state begins

(with SCL a t the low lev el). When th e IRIC flag is c leared to 0 in ICCR, the w ait ends and the

acknowledge bit is transferred. If WAIT is cleared to 0, data and acknowledge bits are transferred

consecutively with no wait inserted.

The I RIC flag in ICCR is set t o 1 on c ompletion of the acknowledge b it transfe r, regardless of the

WAIT setting.

The setting of this bit is invalid in slave m ode.

Bit 6

WAIT Description

0 Data and acknowledge bits transferred consecutively (Initial value)

1 Wait inserted between data and acknowledge bits

Rev. 1.0, 02/01, page 477 of 1184

Bits 5 to 3



Transfer Clock Select (CKS2 to CKS0): These bits, together with the IICX1 bit

(for channel 1) or IICX0 bit (for channel 0) in STCR, select the serial clock frequency in master

mode. They should be set according to the required transfer rate.

STCR

Bits 5, 6 Bit 5 Bit 4 Bit 3 Transfer Rate

IICX CKS2 CKS1 CKS0 Clock φ

φφ

φ = 8 MHz φ

φφ

φ = 10 MHz

0 φ/28 286 kHz 357 kHz 0

1 φ/40 200 kHz 250 kHz

0 φ/48 167 kHz 208 kHz

1 φ/64 125 kHz 156 kHz

0 φ/80 100 kHz 125 kHz 0

1 φ/100 80.0 kHz 100 kHz

0 φ/112 71.4 kHz 89.3 kHz

1 φ/128 62.5 kHz 78.1 kHz

0 φ/56 143 kHz 179 kHz 0

1 φ/80 100 kHz 125 kHz

0 φ/96 83.3 kHz 104 kHz

1 φ/128 62.5 kHz 78.1 kHz

0 φ/160 50.0 kHz 62.5 kHz 0

1 φ/200 40.0 kHz 50.0 kHz

0 φ/224 35.7 kHz 44.6 kHz

1 φ/256 31.3 kHz 39.1 kHz

Rev. 1.0, 02/01, page 478 of 1184

Bits 2 to 0



Bit Counter (BC2 to BC0): Bits BC2 to BC0 specify the numb er of bits to be

transferred next. With the I2C bus for m at (wh en the FS bit in SAR or the FSX bit in SARX is 0),

the data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be

made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than

000, the setting should be made while the SCL line is low.

The bit counter is initialized to 000 by a reset and when a start condition is detected. The value

returns to 000 at the end of a data transfer, including the acknowledge bit.

Bit 2 Bit 1 Bit 0 Bits/Frame

BC2 BC1 BC0 Synchronous Serial Format I2C Bus Format

0 8 9 (Initial value) 0

1 1 2

0 2 3

1 3 4

0 4 5 0

1 5 6

0 6 7

1 7 8

Rev. 1.0, 02/01, page 479 of 1184

23.2.5 I2C Bus Control Register (ICCR)

ICE

R/W

IEIC

R/W

MST

R/W

TRS

R/W

ACKE

R/W

SCP

BBSY

R/W

IRIC

R/(W)*

Note: * Only 0 can be written to clear the flag.

Bit :

Initial value :

R/W :

ICCR is an 8-bit readable/writable register that enables or disables the I2C bus interface, enables or

disables interrupts, selects master or slave mode and transmission or reception, enables or disables

acknowledgement, confirms the I2C bus interface bus status, issues start/stop conditions, and

performs interrupt flag confirmation.

ICCR is initialized to H'01 by a reset.

Bit 7



I2C Bus Interface Enable (ICE): Selects whether or not the I2C bus interface is to be

used. When ICE is set to 1, port pins function as SCL and SDA input/output pins and transfer

operations are enabled. When ICE is cleared to 0, the IIC stops and its internal statu s is in itialized .

The SAR and SARX registers can be accessed when ICE is 0. The ICMR and ICDR registers can

be accessed when ICE is 1.

Bit 7

ICE Description

0 I2C bus interface module disabled, with SCL and SDA signal pins set to port function

The internal status of the IIC is initialized

SAR and SARX can be accessed (Initial value)

1 I2C bus interface module enabled for transfer operations (pins SCL and SCA are

driving the bus)

ICMR and ICDR can be accessed

Bit 6



I2C Bus Interface Interrupt Enable (IEIC): Enables or disables interrupts from the I2C

bus interface to the CPU.

Bit 6

IEIC Description

0 Interrupts disabled (Initial value)

1 Interrupts enabled

Rev. 1.0, 02/01, page 480 of 1184

Bits 5 and 4



Master/Slave Select (MST) and Transmit/Receive Select (TRS): MST selects

whether the I2C bus interface operates in master mode or slave mode.

TRS selects whether the I2C bus interface operates in transmit mode or receive mode.

In master mode with the I2C bus format, when arbitration is lost, MST and TRS are both reset by

hardware, causing a transition to slave receive mode. In slave receive mode with the addressing

format (FS = 0 or FSX = 0), hardware automatically selects transmit or receive mode according to

the R/W bit in the first frame after a start con dition.

Modification of th e TRS bit during transfer is de f e rred until tr ansfer of the frame containing the

acknowledge bit is completed, and the changeover is made after completion of the transfer.

MST and TRS select the operating mode as follows.

Bit 5 Bit 4

MST TRS Description

0 Slave receive mode (Initial value) 0

1 Slave transmit mode

0 Master receive mode 1

1 Master transmit mode

Bit 5

MST Description

0 Slave mode (Initial value)

[Clearing cond iti ons ]

1. When 0 is written by software

2. When bus arbitration is lost after transmission is started in I2C bus format master

mode

1 Master mode

[Setting conditions]

1. When 1 is written by software (in cases other than clearing condition 2)

2. When 1 is written in MST after reading MST = 0 (in case of clearing condition 2)

Rev. 1.0, 02/01, page 481 of 1184

Bit 4

TRS Description

0 Receive mode (Initial value)

[Clearing cond iti ons ]

1. When 0 is written by software (in cases other than setting condition 3)

2. When 0 is written in TRS afte r reading TRS = 1 (in case of setting condition 3)

3. When bus arbitration is lost after transmission is started in I2C bus format master

mode

4. When the SW bit in DDCSWR changes from 1 to 0

1 Transmit mode

[Setting conditions]

1. When 1 is written by software (in cases other than clearing conditions 3)

2. When 1 is written in TRS afte r reading TRS = 0 (in case of clearing conditions 3)

3. When a 1 is received as the R/W bit of the first frame in I2C bus format slave mode

Bit 3



Acknowledge Bit Judgement Selection (ACKE): Specifies whether the value of the

acknowledge bit returned from the receiving device when using the I2C bus format is to be ignored

and continuous transfer is performed, or transfer is to be aborted and error handling, etc.,

performed if the acknowledge bit is 1. When the ACKE bit is 0, the value of the received

acknowledge bit is not indicated by the ACKB bit, which is always 0.

When the ACKE bit is 0 , the TDRE, IRIC, and IRTR flags are set on completio n of data

transmission , r e gardless of th e valu e of the acknowledge bit. When the ACKE bit is 1, the TDRE,

IRIC, and IRTR flags are set o n completion of data tran smission when the acknowledge bit is 0,

and the IRIC flag alone is set on completion of data transmission when the acknowledge bit is 1.

Depending on the receiving device, the acknowledge bit may be significant, in indicating

completion of processing of the received data, for instance, or may be fixed at 1 and have no

significance.

Bit 3

ACKE Description

0 The value of the acknowledge bit is ignored, and continuous transfer is performed

(Initial value)

1 If the acknowledge bit is 1, continuous transfer is interrupted

Rev. 1.0, 02/01, page 482 of 1184

Bit 2



Bus Busy (BBSY) : The BBSY flag can be read to check whether the I2C bus (SCL, SDA)

is busy or free. In master mode, this bit is also used to issue start and stop co nditions.

A high-to-low transition of SDA while SCL is high is recognized as a start condition, setting

BBSY to 1. A low-to-high transition of SDA while SCL is high is recognized as a stop condition,

clearing BBSY to 0.

To issue a start con dition, use a MOV instructio n to write 1 in BBSY and 0 in SCP. A retransmit

start conditio n is issued in the same way. To issue a stop condition, use a MOV instru ction to

write 0 in BBSY and 0 in SCP.

It is not po ssible to write to BBSY in slav e m ode; the I2C bus interface must be set to master

transmit mode before issuing a start condition. MST and TRS should both be set to 1 before

writing 1 in BBSY and 0 in SCP.

Bit 2

BBSY Description

0 Bus is free (Initial value)

[Clearing cond iti on]

When a stop condition is detected

1 Bus is busy

[Setting condition]

When a start condition is detected

Bit 1



I2C Bus Interface Interrupt Reque st Flag (IRIC): Indicates that the I2C bus interface has

issued an interrupt request to the CPU. IRIC is set to 1 at the end of a data transfer, when a slave

address or general call addr ess is detected in slave receive mode, when bus arbitration is lost in

master transmit mode, and when a stop condition is detected. IRIC is set at different times

depending on the FS bit in SAR and the WAIT bit in ICMR. See section 23.3.6, IRIC Setting

Timing and SCL Control. The conditions under which IRIC is set also differ depending on the

setting of the ACKE bit in ICCR.

IRIC is cleared by reading I RIC after it has been set to 1, then writing 0 in IRIC.

When the DTC is used, IRIC is cleared automatically and transfer can be performed continuously

without CPU intervention.

Rev. 1.0, 02/01, page 483 of 1184

Bit 1

IRIC Description

0 Waiting for transfer, or transfer in progress (Initial value)

[Clearing cond iti on]

When 0 is written in IRIC after reading IRIC = 1

(1) Interrupt requested

[Setting conditions]

• I2C bus format master mode

1. When a start condition is detected in the bus line state after a start condition is

issued

(when the TDRE flag is set to 1 because of first frame transmission)

2. When a wait is inserted between the data and acknowledge bit when WAIT = 1

3. At the end of data transfer

(at the rise of the 9th transmit/receive clock pulse, or at the fall of the 8th

transmit/receive clock pulse when using wait insertion)

4. When a slave address is received after bus arbitration is lost

(when the AL flag is set to 1)

5. When 1 is received as the acknowledge bit when the ACKE bit is 1

(when the ACKB bit is set to 1)

• I2C bus format slave mode

1. When the slave address (SVA, SVAX) matches

(when the AAS and AASX flags are set to 1)

and at the end of data transfer up to the subsequent retransmission start condition

or stop condition detection

(when the TDRE or RDRF flag is set to 1)

2. When the general call address is detected

(when FS = 0 and the ADZ flag is set to 1)

and at the end of data transfer up to the subsequent retransmission start condition

or stop condition detection

(when the TDRE or RDRF flag is set to 1)

3. When 1 is received as the acknowledge bit when the ACKE bit is 1

(when the ACKB bit is set to 1)

4. When a stop condition is detected

(when the STOP or ESTP flag is set to 1)

• Synchronous serial format

1. At the end of data transfer

(when the TDRE or RDRF flag is set to 1)

2. When a start condition is detected with serial format selected

• When a condition, other than the above, that s e ts the TDRE or RDRF flag to 1 is

detected

Rev. 1.0, 02/01, page 484 of 1184

When, with the I 2C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags

must be checked in order to identify the source that set IRIC to 1. Although each source has a

corresponding flag, caution is needed at the end of a transfer.

When the TDRE or RDRF internal flag is set, the readable IRTR flag may or may not be set. The

IRTR flag (the DTC start request flag) is not set at the end of a data transfer up to detection of a

retransmission start condition or stop condition after a slave address (SVA) or general call address

match in I2C bus format slave mode.

Even when the IRIC flag and IRTR flag are set, the TDRE or RDRF internal flag may not be set.

The IRIC and IRTR flags are not cleared at the end of the specified number of transfers in

continuous transfer using the DTC. The TDRE or RDRF flag is cleared, however, since the

specified number of ICDR reads or writes have been completed.

Table 23.3 shows the relationship between the flags and the transfer states.

Note: * This LSI does not incorporate DTC.

Rev. 1.0, 02/01, page 485 of 1184

Table 23.3 Flags and Transfer States

MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB State

1/0 1/0 0 0 0 0 0 0 0 0 0 Idle state (flag clearing

required)

1 1 0 0 0 0 0 0 0 0 0 Start condition

issuance

1 1 1 0 0 1 0 0 0 0 0 Start condition

established

1 1/0 1 0 0 0 0 0 0 0 0/1 Master mode wait

1 1/0 1 0 0 1 0 0 0 0 0/1 Master mode

transmit/ receive end

0 0 1 0 0 0 1/0 1 1/0 1/0 0 Arbitration lost

0 0 1 0 0 0 0 0 1 0 0 SAR match by first

frame in slave mode

0 0 1 0 0 0 0 0 1 1 0 General call address

match

0 0 1 0 0 0 1 0 0 0 0 SARX match

0 1/0 1 0 0 0 0 0 0 0 0/1 Slave mode

transmit/ receive end

(except after SARX

match)

0 1/0

1 1

1 0

0 0

0 1

1 0

0 0

1 Slave mode

transmit/ receive end

(after SARX match)

0 1/0 0 1/0 1/0 0 0 0 0 0 0/1 Stop condition

detected

Bit 0



Start Condition/Stop Condition Prohibit (SCP): Controls the issuing of start and stop

conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A

retransmit star t condition is issued in the same way. To issue a stop condition, wr ite 0 in BBSY

and 0 in SCP. This bit is always read as 1. If 1 is written, the data is n ot stored.

Bit 0

SCP Description

0 Writing 0 issues a start or stop condition, in combination with the BBSY flag

1 Reading always returns a value of 1 (Initial value)

Writing is ignored

Rev. 1.0, 02/01, page 486 of 1184

23.2.6 I2C Bus Status Register (ICSR)

ESTP

R/(W)*

STOP

R/(W)*

IRTR

R/(W)*

AASX

R/(W)*

ACKB

R/W

AAS

R/(W)*

ADZ

R/(W)*

Note: * Only 0 can be written to clear the flag.

Bit :

Initial value :

R/W :

ICSR is an 8-bit readable/writable register that perf orms flag confirmation and acknowledge

confirmation and control.

ICSR is initialized to H'00 by a reset.

Bit 7



Error Stop Condition Detectio n F la g (ESTP): Indicates that a stop condition has been

detected during frame transfer in I2C bus format slave mode.

Bit 7

ESTP Description

0 No error stop condition (Initial value)

[Clearing cond iti ons ]

1. When 0 is written in ESTP after reading ESTP = 1

2. When the IRIC flag is cleared to 0

1 • In I2C bus format slave mode: Error stop condition detected

[Setting condition]

When a stop condition is detected during frame transfer

• In other modes: No meaning

Rev. 1.0, 02/01, page 487 of 1184

Bit 6



Normal Stop Condition Detection Flag (STOP): Indicates that a stop condition has been

detected after completion of frame transfer in I2C bus format slave mode.

Bit 6

STOP Description

0 No normal stop condition (Initial value)

[Clearing cond iti ons ]

1. When 0 is written in STOP after reading STOP = 1

2. When the IRIC flag is cleared to 0

1 • In I2C bus format slave mode: Error stop condition detected

[Setting condition]

When a stop condition is detected after completion of frame transfer

• In other modes:No meaning

Bit 5



I2C Bus Interface Continuous Transmission/Reception Interrupt Request Flag

(IRTR): Indicates that the I2C bus interface has issued an interrupt request to the CPU, and the

source is completion of reception/transmission of on e frame in continuous transmission/reception

for which DTC activation is possible. When the IRTR flag is set to 1, th e IRIC flag is also set to 1

at the same time.

IRTR flag setting is performed when the TDRE or RDRF flag is set to 1. IRTR is cleared by

reading IRTR after it has been set to 1, then writing 0 in IRTR. IRTR is al so cleared automatically

when the IRIC flag is cleared to 0.

Note: * This LSI does not incorporate DTC.

Bit 5

IRTR Description

0 Waiting for transfer, or transfer in progress (Initial value)

[Clearing cond iti ons ]

1. When 0 is written in IRTR after reading IRTR = 1

2. When the IRIC flag is cleared to 0

1 Continuous transfer state

[Setting conditions]

• In I2C bus interfac e slave mode: When the TDRE or RDRF flag is set to 1 when

AASX = 1

• In other modes: When the TDRE or RDRF flag is set to 1

Rev. 1.0, 02/01, page 488 of 1184

Bit 4



Second Slave Address Recognition Flag (AASX): In I2C bus format slave receive mode,

this flag is set to 1 if th e first frame fo llo wing a start condition matches bits SVAX6 to SVAX0 in

SARX.

AASX is cleared by readin g AASX after it has been set to 1, then writing 0 in AASX. AASX is

also cleared auto m atically when a start condition is detected.

Bit 4

AASX Description

0 Second slave address not recognized (Initial value)

[Clearing cond iti ons ]

1. When 0 is written in AASX after reading AASX = 1

2. When a start condition is detected

3. In master mode

1 Second slave address recognized

[Setting condition]

When the second slave address is detected in slave receive mode while FSX=0

Bit 3



Arbitration Lost (AL): This flag indicates that arbitration was lost in master mode. The

I2C bus interface monitors the bus. When two or more master devices attempt to seize the bus at

nearly the same time, if the I2C bus interface detects data differing from the data it sent, it sets AL

to 1 to indicate that the bus has been taken by another master.

AL is cleared by reading AL after it has been set to 1, then writing 0 in AL. In addition, AL is

reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive

mode.

Bit 3

AL Description

0 Bus arbitration won (Initial value)

[Clearing cond iti ons ]

1. When ICDR data is written (transmit mode) or read (receive mode)

2. When 0 is written in AL after reading AL = 1

1 Arbitration lost

[Setting conditions]

1. If the internal SDA and SDA pin disagree at the rise of SCL in master transmit

mode

2. If the internal SCL line is high at the fall of SCL in master transmit mode

Rev. 1.0, 02/01, page 489 of 1184

Bit 2



Slave Address Recognition Flag (AAS): In I2C bus format slave receive mode, this flag is

set to 1 if the f ir st fr ame following a start cond ition matches bits SVA6 to SVA0 in SAR, or if the

general call address (H'00) is detected.

AAS is cleared by reading AAS after it has been set to 1, then writing 0 in AAS. In addition, AAS

is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive

mode.

Bit 2

AAS Description

0 Slave address or general call addre ss not reco gni zed (Initial val ue)

[Clearing cond iti ons ]

1. When ICDR data is written (transmit mode) or read (receive mode)

2. When 0 is written in AAS after reading AAS = 1

3. In master mode

1 Slave address or general call addre ss reco gnized

[Setting condition]

When the slave address or general call address is detec ted when FS = 0 in slave

receive mode

Bit 1



General Call Address Recognition Flag (ADZ): In I2C bus format slave receive mode,

this flag is set to 1 if the first frame following a start condition is the g eneral call address (H'00).

ADZ is cleared by reading ADZ after it has been set to 1, then writing 0 in ADZ. In addition,

ADZ is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in

receive mode.

Bit 1

ADZ Description

0 General call address not recog nized (Initial value)

[Clearing cond iti ons ]

1. When ICDR data is written (transmit mode) or read (receive mode)

2. When 0 is written in ADZ after reading ADZ = 1

3. In master mode

1 General call address recognized

[Setting condition]

If the general call address is detected when FSX = 0 or FS = 0 is selected in the

slave receive mode.

Rev. 1.0, 02/01, page 490 of 1184

Bit 0



Acknowledge Bit (ACKB): Stores acknowledge data. In transmit mode, after the

receiving device receives data, it returns acknowledge data, and this data is loaded into ACKB. In

receive mode, after data has been received, the acknowledge data set in this bit is sent to the

transmitting device.

When this bit is r ead, in transmission (when TRS = 1), the value loaded from the bus line

(returned by the receiving device) is read. In reception (when TRS = 0), the value set by internal

software is read.

Bit 0

ACKB Description

0 Receive mode: 0 is output at acknowledge output timing (Initial value)

Transmit mode: Indicates that the receiving device has acknowledged the data

(signal is 0)

1 Receive mode: 1 is output at acknowledge output timing

Transmit mode: Indicates that the receiving device has not acknowledged the data

(signal is 1)

23.2.7 Serial/Timer Control Register (STCR)

—

IICX1

R/W

IICX0

R/W

—

FLSHE

R/W

—

OSROME

R/W

—

Bit :

Initial value :

R/W :

STCR is an 8-bit readable/writable register that controls the IIC operating mode.

STCR is initialized to H'00 by a reset.

Bit 7



Reserved: This bit cannot be modified and is always read as 0.

Bits 6 and 5



I2C Transfer Select 1, 0 (IICX1, IICX0): These bits, to gether with bits CKS2 to

CKS0 in ICMR of IIC, select the transfer rate in master mode. For details, see section 23.2.4, I2C

Bus Mode Register (ICMR).

Bit 3



Flash Memory Control Resister Enable (FLSHE): This bit selects the control resister of

the flash memory. For details, refer to section 7.3.5, Serial Timer Control Resister (STCR).

Bit 2



OSD ROM Enable (OSROME): This bit controls the OSD ROM. Fo r details, refer to

section 7, ROM.

Bits 4, 1, and 0



Reserved: These bits cannot be modified and are always read as 0.

Rev. 1.0, 02/01, page 491 of 1184

23.2.8 DDC Switch Register (DDCSWR)

SWE*

R/W

SW*

R/W

IE*

R/W

IF*

R/(W)*

CLR3

CLR0

CLR2

CLR1

Notes: 1.

Only 0 can be written to clear the flag.

Always read as 1.

These bits are not provided (incorporated in) for the H8S/2197S and H8S/2196S.

Bit :

Initial value :

R/W :

DDCSWR is an 8-bit read/write register that controls au tomatic for m at switching for IIC channel

0 and IIC internal latch clearing. DDCSWR is initialized to H'0F by a reset or in hardware standby

mode.

Bit 7



DDC Mode Switch Enable (SWE): Enables or disables automatic switching from

formatless tr ansfer to I2C bus format transfer for IIC channel 0.

Bit 7

SWE Description

0 Disables automatic switching from formatless transfer to I2C bus format transfer for

IIC channel 0. (Initial value)

1 Enables automati c switching from formatless transfer to I2C bus format transfer for IIC

channel 0.

Bit 6



DDC Mode Switch (SW): Selects formatless transfer or I2C bus format transfer for IIC

channel 0.

Bit 6

SW Description

0 I2C bus format is selected for IIC channel 0. (Initial value)

[Clearing cond iti ons ]

1. When 0 is written by software

2. When an SCL falling edge is detected when SWE = 1

1 Formatless transfer is selected for IIC channel 0.

[Setting condition]

When 1 is written after SW = 0 is read

Rev. 1.0, 02/01, page 492 of 1184

Bit 5



DDC Mode Switch Interrupt Enable Bit (IE): Enables or disables an interrupt request to

the CPU when the f ormat for IIC channel 0 is automatically switched.

Bit 5

IE Description

0 Disables an interrupt at automatic form at sw itching (Initial value)

1 Enables an interrupt at automatic format switching

Bit 4



DDC Mode Switch Interrupt Flag (IF): Indicates th e interrupt request to th e CPU when

the format for IIC chan nel 0 is automatically switched.

Bit 4

IF Description

0 Interrupt has not been requested (Initial value)

[Clearing cond iti on]

When 0 is written after IF = 1 is read

1 Interrupt has been requested

[Setting condition]

When an SCL falling edge is detected when SWE = 1

Bits 3 to 0



IIC Clear 3 to 0 (CLR3 to CLR0): Control the IIC0 and IIC1 initialization . These

are write-only bits and are always read as 1.

Writing to these bits gener ates a clearing signa l for the internal latch circuit which in itializes the

IIC status.

The data written to these bits are not held. When initializin g the IIC, be sure to use the MOV

instruction to write to all the CLR3 to CLR0 bits at the same time; do not use bit manipulatio n

instructions such as BCLR.

When reinitializing the module status, the CLR3 to CLR0 bits must be rewritten.

Rev. 1.0, 02/01, page 493 of 1184

Bit 3 Bit 2 Bit 1 Bit 0

CLR3 CLR2 CLR1 CLR0 Description

0   The setting is invalid

0 The setting is invalid 0

1 IIC0 internal latch cleared

0 IIC1 internal latch cleared

1 IIC 0 and IIC1 internal latches cleared

1    This setting is invalid

Rev. 1.0, 02/01, page 494 of 1184

23.2.9 Module Stop Control Register (MSTPCR)

MSTP15

R/W

MSTPCRH

MSTP14

R/W

MSTP13

R/W

MSTP12

R/W

MSTP11

R/W

MSTP10

R/W

MSTP9

R/W

MSTP8

R/W

MSTP7

R/W

MSTP6

R/W

MSTP5

R/W

MSTP4

R/W

MSTP3

R/W

MSTP2

R/W

MSTP1

R/W

MSTP0

R/W

MSTPCRL

Bit :

Initial value :

R/W :

MSTPCR comprises two 8-bit readable/writable registers, and is used to perform modu le stop

mode control.

When the corresponding bit in MSTPCR is set to 1, operation of the corresponding IIC channel is

halted at the end of the bus cycle, and a transition is made to module stop mode. For details, see

section 4.5, Module Stop Mode.

MSTPCR is initialized to H'FFFF by a reset. It is not initialized in standby mode.

MSTPCRL Bit 7



Module Sto p (MSTP7): Specifies the module stop mode for IIC channel 0.

MSTPCRL

Bit 7

MSTP7 Description

0 Module stop mode for IIC channel 0 is cleared

1 Module stop mode for IIC channel 0 is set (Initial value)

MSTPCRL Bit 6



Module Sto p (MSTP6): Specifies the module stop mode for IIC channel 1.

MSTPCRL

Bit 6

MSTP6 Description

0 Module stop mode for IIC channel 1 is cleared

1 Module stop mode for IIC channel 1 is set (Initial value)

Rev. 1.0, 02/01, page 495 of 1184

23.3 Operation

23.3.1 I2C Bus Data Format

The I2C bus interface has serial and I2C bus formats.

The I2C bus formats are addressing formats with an acknowledge bit. Th ese are shown in figures

23.3(1) and (2). The f ir st frame following a start con dition always consists of 8 bits. Formatless

transfer can be selected only for IIC channel 0. The formatless transfer data is shown in figure

23.3 (3).

The serial format is a non-ad dressing format with no acknowledge bit. This is shown in figure

23.4.

Figure 23.5 shows the I2C bus timin g.

The symbols used in figures 23.3 to 23.5 are explained in table 23.4.

SASLA

R/W DATA A

111A/A

1Transfer bit count

(n = 1 to 8)

Transfer frame count

(m = 1 or above)

S SLA

7n1 7

R/W A DATA

1m1

1A/A

1SLA R/W

1m2

1DATA

n2 A/A

Upper: Transfer bit count (n1 and N2 = 1 to 8)

Lower: Transfer frame count (m1 and m2 = 1 or above)

(1) FS = 0 or FSX = 0

DATADATA A

181 A/A

1Transfer bit count

(n = 1 to 8)

Transfer frame count

(m = 1 or above)

(3) Formatless (IIC channel 0 only, FS = 0 or FSX = 0)

(2) Start condition transmission, FS = 0 or FSX = 0

Figure 23.3 I2C Bus Data Formats (I2C Bus For mats)

Rev. 1.0, 02/01, page 496 of 1184

S DATA

DATA

1Transfer bit count

(n = 1 to 8)

Transfer frame count

(m = 1 or above)

FS = 1 and FSX = 1

Figure 23.4 I2C Bus Data Format (Serial Format)

SDA

SCL

S SLA R/WA

981-7 981-7 981-7

DATA A DATA A/AP

Figure 23.5 I2C Bus Timing

Table 23.4 I2C Bus Data Format Sy mbols

Symbol Description

S Start condition. The master device drives SDA from high to low while SCL is hig

SLA Slave address, by which the master device selects a slave device

R/W Indicates the direction of data transfer: from the slav e device to the master device

when R/W is 1, or from the master device to the slave device when R/W is 0

A Acknowledge. The receiving device (the slave in master transmit mode, or the

master in master receive mode) drives SDA low to acknowledge a transfer

DATA Transferred data. The bit length is set by bits BC2 to BC0 in ICMR. The MSB-first

or LSB-first format is selected by bit MLS in ICMR

P Stop condition. The master device drives SDA from low to high while SCL is high

23.3.2 Master Transmit Operation

In I2C bus format master tran smit mode, the master device ou tputs the transmit clock and transmit

data, and the slave device returns an acknowledge signal. The transmission procedure and

operations synchronize with the ICDR writing are described below.

[1] Set bit ICE in ICCR to 1. Set b its MLS, WAI T , and CKS2 to CKS0 in ICMR, and bit II CX in

STCR, according to the operating mode.

[2] Read the BBSY flag in ICCR to confirm that the bus is free.

[3] Set bits MST and TRS to 1 in ICCR to select ma ster transmit mode.

Rev. 1.0, 02/01, page 497 of 1184

[4] Write 1 to BBSY and 0 to SCP. This changes SDA from high to low when SCL is high, and

generates the start cond ition.

[5] Th en IRIC and IRTR flags are set to 1. If the IEIC bit in ICCR has been set to 1 , an interrupt

request is sen t to the CPU.

[6] Write the data (slave address + R/W) to ICD R. After the start cond ition instruction has been

issued and the start conditon has been generated, write data to ICDR. If this procedure is not

followed, d a ta may not b e output cor rectly. With the I2C bus form at (when the FS bit in SAR

or the FSX bit in SARX is 0), the first fram e data following the start con dition indicates the 7-

bit slave address and transmit/receive direction. As indicatin g the end of the transfer, and so

the IRIC flag is cleared to 0. After writing ICDR, clear IRIC immediately not to execute other

interrupt handling routine. If one frame of data has been transmitted before the IRIC clearing,

it can not be determine the end of transmission. The master device sequentially sends the

transmission clock and the data written to I CDR usin g the timing shown in figure 23.6. The

selected slave device (i.e. the slave device with the matching slave address) drives SDA low at

the 9th transmit clock pulse and returns an acknowledge signal.

[7] Wh en one frame of data h a s been tr an smitted, the IRIC flag is set to 1 at th e r ise o f the 9th

transmit clock pulse. After one frame has been transmitted SCL is automatically fixed low in

synchronization with the internal clock until the next transmit data is written.

[8] Read the ACKB bit in ICSR to confirm that ACKB is cleared to 0. When the slave device has

not acknowledged (ACKB bit is 1), operate the step [12] to end transmission, and retry the

transmit operation .

[9] Wr ite the transmit data to ICDR. As indicating th e end of the transfer, and so th e I RIC flag is

cleared to 0. After writing ICDR, clear IRIC immediately not to execute other interrupt

handling routine. The master device sequentially sends the transmission clock and the data

written to ICDR. Transmission of the next frame is performed in synchronizatio n with the

internal clock .

[10] When one frame of data has been tran smitted, the IRIC flag is set to 1 at th e rise of the 9th

transmit clock pulse. After one frame has been transmitted SCL is automatically fixed low in

synchronization with the internal clock until the next transmit data is written.

[11] Read the ACKB bit in ICSR and confirm ACKB is cleared to 0. When there is data to be

transmitted, go to the step [6] to continue next transmission . When the slave de vice has not

acknowledged (ACKB bit is set to 1), operate the step [12] to end transmission.

[12] Clear the IRIC flag to 0. And write 0 to BBSY and SCP in ICCR. This changes SDA from

low to high wh en SCL is high, and generates the stop condition.

Rev. 1.0, 02/01, page 498 of 1184

SDA

(master output)

SDA

(slave output)

R/W

43658712

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6

IRIC

IRTR

ICDR

SCL

(master output)

Start condition

Geberation

Slave address Data 1

[9] ICDR write [9] IRIC clear

[6] ICDR write [6] IRIC clear

address + R/W

[7]

[5]

Note: Data write

timing in ICDR

ICDR Writing

prohibited

[4] Write BBSY = 1

and SCP = 0

(start condition

issuance)

ICDR Writing

enable

Data 1

User processing

These processes are executed continuously. These processes are executed continuously.

Figure 23.6 Example of Master Transmit Mode Operation Timing (MLS = WAIT = 0)

Rev. 1.0, 02/01, page 499 of 1184

23.3.3 Master Receive Operation

In master receive mode, the master device outputs the receive clock, receives data, and returns an

acknowledge signal. The slave device transmits data. I2C bus interface module consists of the

data buffers of ICDRR and ICDRS, so data can be received continuously in master receive mode.

For this construction, when stop condition issuing timing delayed, it m ay occurs the internal

contention between stop condition issuance and SCL clock output for next data receiving, and then

the extra SCL clock would be outputted automatically or the SCL line would be held to low. And

for I2C bus interface system, the acknowledge bit must be set to 1 at the last data receiving, so the

change timing of ACKB bit in ICSR should be controlled by software. To take measures against

these problems, the wait function should be used in master receive mode. The reception procedure

and operations with the wait function in master receive mode are described below.

[1] Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode, and set the

WAIT bit in ICMR to 1. Also clear the ACKB bit in ICSR to 0 (acknowledge data setting).

[2] When ICDR is read (dummy data read), reception is started, and the receive clock is output,

and data received, in synchronization with the internal clock. In order to detect wait operation,

set the IRIC flag in ICCR must be cleared to 0. After reading ICDR, clear IRIC immediately

not to execute other interrupt handling routine. If one frame of data has been received before

the IRIC clearing, it can not be determine the end of reception.

[3] The IRIC flag is set to 1 at th e fall o f the 8th receive clock pulse. If the IEIC bit in ICCR has

been set to 1, an in ter rup t r equest is sent to th e CPU. SCL is automa tically fixed low in

synchro nization with the internal clock until the IRIC flag clearing. If the first frame is the last

receive data, execute step [10] to halt reception.

[4] Clear the IRIC flag to release from the Wait State. The master device outputs the 9th clock

and drives SDA at the 9th receive clock pulse to return an acknowledge signal.

[5] When one frame of data has been received, the IRIC flag in ICCR and the IRTR flag in ICSR

are set to 1 at the rise of the 9th receive clock pulse. The master device outputs SCL clock to

receive next data.

[6] Read ICDR.

[7] Clear the IRIC flag to detect next wait operation. From clearing of the IRIC flag to negation of

a wait as described in step [4] (and [9]) to clearing of the IRIC flag as described in steps [5],

[6], and [7], must be p e rfor med within the time taken to transfer one byte.

[8] The IRIC flags set to 1 at the fall of the 8th receive clock pulse. SCL is automatically fixed

low in synchronization with the intern al clock until the IRIC flag clearing. If th is frame is the

last receive data, execute step [10] to halt reception.

[9] Clear the IRIC flag in ICCR to cancel wait operation. The master device outputs the 9th clock

and drives SDA at the 9th receive clock pulse to return an acknowledge signal. Data can be

received continuously by repeating step [5] to [9].

[10] Set th e ACKB bit in ICSR to 1 so as to return “No acknowledge” data. Also set the TRS bit

to 1 to switch from receive mode to transmit mode.

Rev. 1.0, 02/01, page 500 of 1184

[11] Clear IRIC flag to 0 to release from the Wait State.

[12] When one frame of data has been received, the IRIC flag is set to 1 at the rise of the 9th

receive clock pulse.

[13] Clear the WAIT bit to 0 to switch from wait mode to no wait mode. Read ICDR and the

IRIC flag to 0. Clearing of the IRIC flag should be after the WAIT = 0.

[14] Clear the BBSY bit and SCP bit to 0. This changes SDA from low to high when SCL is high,

and generates the stop condition.

A Bit7

Master receive modeMaster transmit mode

SCL

(master output)

SDA

(slave output)

SDA

(master output)

IRIC

IRTR

ICDR

User processing [1] TRS cleared to 0

WAIT set to 1

ACKB cleared to 0

[2] ICDR read

(dummy read) [2] IRIC clearance [4] IRC clearance [6] ICDR read

(Data 1) [7] IRIC clearance

Bit6 Bit5 Bit4 Bit3 Bit7 Bit6 Bit5 Bit4 Bit3Bit2 Bit1 Bit0

1234 56 78

[3] [5]

912 345

Data 1 Data 2

Data 1

These processes are executed continuously. These processes are executed continuously.

Figure 23.7 Example of Master Receive Mode Operation Timing

(MLS = ACKB = 0, WAIT = 1)

Rev. 1.0, 02/01, page 501 of 1184

Bit0

Data 2

SCL

(master output)

SDA

(slave output)

SDA

(master output)

IRIC

IRTR

ICDR

User processing [9] IRIC clearance [6] ICDR read

(Data 2) [7] IRIC clearance [9] IRIC Clearance [6] ICDR read

(Data 3) [7] IRIC clearance

Bit7

[8] [5]

Bit6 Bit5 Bit4 Bit7 Bit6Bit3 Bit2 Bit1 Bit0

91 23 45 67

[8] [5]

8912

Data 3 Data 4

Data 3Data 2Data 1

These processes are executed continuously. These processes are executed continuously.

Figure 23.8 Example of Master Receive Mode Operation Timing

(MLS = ACKB = 0, WAIT = 1) continued

Rev. 1.0, 02/01, page 502 of 1184

23.3.4 Slave Receive Operation

In slave receive mode, the master device outputs the transmit clock and transmit data, and the

slave device returns an acknowledge signal. The receive procedure and operations in slave receive

mode are described below.

1. Set bit ICE in ICCR to 1. Set bits MLS in ICMR and bits MST and TRS in ICCR according to

the operating mode.

2. A start condition output by the master device sets the BBSY flag to 1 in ICCR.

3. After the slave device detects the start condition, if the first frame matches its slave address, it

functions as the slave device designated as the master device. If the 8th bit data (R/W) is 0,

TRS bit in ICCR remains 0 and executes slave receive operation.

4. At the ninth clock pulse of the receive frame, the slave device drives SDA low to acknowledge

the transfer. At the same time, the IRIC flag is set to 1 in ICCR. If IEIC is 1 in ICCR, a CPU

interrupt is requested. If the RDRF internal flag is 0, it is set to 1 and continuous reception is

performed. If the RDRF in ter nal flag is 1, the slav e device hold s SCL low f r om the fall of the

receive clock until it has read the data in ICDR.

5. Read ICDR and c l e a r IRIC to 0 in ICCR. At th is time, the RDFR flag is c l e a red to 0.

Steps 4 and 5 can be repeated to receive data continuously. When a stop co nditio n is detected (a

low-to-h igh transition of SDA while SCL is high), the BBSY f lag is cleared to 0 in ICCR.

Rev. 1.0, 02/01, page 503 of 1184

SDA

(Master output)

SDA

(Slave output)

21 214365879

Bit 7 Bit 6 Bit 7 Bit 6Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

IRIC

ICDRS

ICDRR

RDRF

SCL

(Master output)

Start condition

issurance

SCL

(Slave output)

Interrupt request

generated

Address + R/W

[5] Read ICDR [5] Clear IRIC

User processing

Slave address Data 1

[4]

R/W

Figure 23.9 Example of Timing in Slave Receive Mode (MLS = ACKB = 0)

Rev. 1.0, 02/01, page 504 of 1184

SDA

(Master output)

SDA

(Slave output)

214365879879

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bit 1 Bit 0

IRIC

ICDRS

ICDRR

RDRF

SCL

(Master output)

SCL

(Slave output)

Interrupt

request

generated

Interrupt

request

generated

Data 2

Data 1

[5] Read ICDR [5] Clear IRIC

User processing

Data 2

Data 1 [4] [4]

Figure 23.10 Example of Timing in Slave Receive Mode (MLS = ACKB = 0)

Rev. 1.0, 02/01, page 505 of 1184

23.3.5 Slave Transmit Operation

In slave transmit mode, the slave device ou tputs the transmit data, and the master device outputs

the transmit clock and returns an acknowledg e signal. The transmit procedure and operations in

slave transmit mode are described below.

1. Set bit ICE in I CCR to 1. Set bits MLS in I CMR and bits MST and TRS in ICCR according to

the operating mode.

2. After the slave device detects a start condition, if the first frame matches its slave address, at

the ninth clock pulse the slave device drives SDA low to acknowledge the transfer. At the

same time, the IRIC flag is set to 1 in ICCR, and if the IEIC bit in ICCR is set to 1 at this time,

an interrupt request is sen t to the CPU. If the eighth data bit (R/W) is 1, the TRS bit is set to 1

in ICCR, automatically causing a transition to slave tran smit mode. The slave device holds

SCL low from the fall of the transmit clock until data is written in ICDR.

3. Clear the IRIC flag to 0, then write data in ICDR. The written d ata is tr ansferred to ICDRS,

and the TDRE internal flag and the IRIC and IRTR flags are set to 1 again. Clear IRIC to 0,

then write the n ext data in I CDR. The slave de v ice outp uts the written data serially in step

with the clock output by the master device, with the timing shown in figure 23.11.

4. When o ne frame of data has been tran smitted, at the rise of the ninth tr ansmit clock pulse IRIC

is set to 1 in ICCR. If the TDRE in ternal fl a g is 1, the slave device holds SCL low from the

fall of the tr ansmit clock until data is written in ICDR. The master device drives SDA low at

the ninth clock pulse to acknowledge the data. The acknowledge signal is stored in the ACKB

bit in ICSR, and can be used to check whether the transfer was carried out normally. If TDRE

internal flag is set to 0, the data written in ICDR is tran sferred to I CDRS, then transmission

starts and TDRE internal flag and IRIC and IRTR flags are all set to 1 again.

5. To continue tr ansmitting, clear IRIC to 0, then write the next transmit data in ICDR. At this

time, the TDRE internal flag is cleared to 0.

Steps 4 and 5 can be repeated to transmit continuously. To end the transmission, write H'FF in

ICDR so that the SDA may be freed on the slave side. When a stop condition is detected (a low-

to-high transition of SDA while SCL is high), the BBSY flag will be clear ed to 0 in ICCR.

Rev. 1.0, 02/01, page 506 of 1184

SDA

(Slave output)

SDA

(Master output)

SCL

(Slave output)

21 21436587998

Bit 7 Bit 6 Bit 5 Bit 7 Bit 6Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

IRIC

ICDRS

ICDRT

TDRE

SCL

(Master output)

Interrupt

request

generated

Interrupt

request

generated

Interrupt

request

generated

Slave receive mode Slave transmit mode

Data 1 Data 2

[3] Clear IRIC [5] Clear IRIC[3] Write ICDR [3] Write ICDR [5] Write ICDR

User

processing

Data 1

Data 1 Data 2

Data 2

R/W

[3]

[2]

Figure 23.11 Example of Timing in Slave Transmit Mode (MLS = 0)

23.3 .6 IRIC Setting Timing a nd SCL Contro l

The interrupt request f lag (IRIC) is set at differen t times depend in g on the WAIT bit in ICMR, the

FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal f lag is set to 1, SCL is

automatically held low after one frame has been transferred; this timing is synchronized with the

internal clock. Figure 23.12 shows the IRIC set timing and SCL control.

Rev. 1.0, 02/01, page 507 of 1184

SCL

SDA

IRIC

User

processing Clear

IRIC Write to ICDR (transmit) or

read ICDR (receive)

1A8

198

SCL

SDA

IRIC

User

processing Clear IRIC Write to ICDR (transmit) or

read ICDR (receive)

Clear IRIC

SCL

SDA

IRIC

User

processing Clear IRIC Write to ICDR (transmit) or

read ICDR (receive)

187

(a) When WAIT = 0, and FS = 0 or FSX = 0 (I2C bus format, no wait)

(b) When WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait inserted)

Figure 23. 12 IRIC Setting Timi ng and SCL Contro l

Rev. 1.0, 02/01, page 508 of 1184

23.3.7 Automatic Switching from Formatless Transfer to I2C Bus Format Transfer

Setting the SW b it in DDCSWR to 1 selects the IIC0 formatless transfer operation . When an SCL

falling edge is detected, the operating mode automatically switches from formatless transfer to I2C

bus format tran sfer (slave mode). For automatic switching to be possible, the fo llowing four

conditions must be observed:

1. The same data pin (SDA) is used in common for formatless transfer and I2C bus format

transfer.

2. Separate clock pins are used for formatless transfer and I2C bus format transfer (SYNC1 for

formatless, and SCL for I2C bus format)

3. The SCL pin is kept high during formatless transfer.

4. Register bits other than th e TRS bit in I CC R are set to appropriate va lues so that I2C bus

format transfer can be performed.

The opera ting m ode is automatically switched from formatless transfer to I2C bus format transfer

when an SCL falling edge is detected and the SW bit in DDCSWR is automatically cleared to 0.

To switch the mode from I2C bus format transfer to formatless transfer, set th e SW bit to 1 by

software.

During formatless transfer, do not modify the bits that control the I2C bus interface operating

mode, such as the MSL or TRS bit. When switching from the I2C bus format transfer to formatless

transfer, specify the formatless transfer direction (transmit or receive) by setting or clearing the

TRS bit, then set the SW bit to 1. After the automatic switching f rom for matless transfer to I2C bus

format transfer (slave mode), the TRS bit is automatically cleared to 0 to enter the slave address

receive wait state.

If an SCL falling edge is detected during formatless transfer, the IIC does not wait f or the stop

condition but switches the operating mode immediately.

Note: The IIC0 is not provided (incorporated in) for the H8S/2197S and H8S/2196S.

Rev. 1.0, 02/01, page 509 of 1184

23.3.8 Noise Canceler

The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched

internally. Figure 23.13 shows a block diagram of the noise canceler circuit.

The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)

input signal is sampled on the system clock, but is not passed forward to the next circuit unless the

outputs of both latches agree. If they do not agree, the previous value is held.

SCL or SDA

input signal Internal SCL

or SDA signal

Sampling clock

Sampling

clock

System clock

period

Latch

QD Match

detector

Figure 23.13 Block Diagram of Noise Canceler

23.3.9 Sample Flowcharts

Figures 23.14 to 23.17 show sample flowcharts for using the I2C bus interface in each mode.

Rev. 1.0, 02/01, page 510 of 1184

Start

Initialize

Read BBSY in ICCR

No BBSY = 0?

Yes

Set MST = 1 and

TRS = 1 in ICCR

Write BBSY = 1

and SCP = 0 in ICCR

Clear IRIC in ICCR

Read IRIC in ICCR

Yes

IRIC = 1?

Write transmit data in ICDR

Read ACKB in ICSR

ACKB = 0? No

Yes No

Yes

Transmit mode?

Write transmit data in ICDR

Read IRIC in ICCR

IRIC = 1?

Yes

Clear IRIC in ICCR

Read ACKB in ICSR

End of transmission

or ACKB = 1?

Yes

Write BBSY = 0

and SCP = 0 in ICCR

End

Master receive mode

Read IRIC in ICCR

No IRIC = 1?

Clear IRIC in ICCR

[1] Initialize

[2] Test the status of the SCL and SDA lines.

[3] Select master transmit mode.

[4] Start condition issuance

[5] Wait for a start condition generation

[6] Set transmit data for the first byte (slave

address + R/W).

(After writing ICDR, clear IRIC

immediately)

[7] Wait for 1 byte to be transmitted.

[8] Test the acknowledge bit, transferred from

slave device.

[10] Wait for 1 byte to be transmitted.

[11] Test for end of transfer

[12] Stop condition issuance

[9] Set transmit data for the second and

subsequent bytes.

(After writing ICDR, clear IRIC

immediately)

Figure 23.14 Flowchart for Master Transmit Mode (Example)

Rev. 1.0, 02/01, page 511 of 1184

Master receive mode

Read ICDR

Clear IRIC in ICCR

IRIC = 1?

Clear IRIC in ICCR

Read IRIC in ICCR

IRIC = 1?

Last receive ?

Yes Yes

Yes

Read ICDR

Read IRIC in ICCR

IRIC = 1?

Last receive ?

Clear IRIC in ICCR

Read IRIC in ICCR

Clear IRIC in ICCR

Set ACKB = 1 in ICSR

Set TRS = 1 in ICCR

Clear IRIC in ICCR

Set WAIT = 0 in ICMR

Read ICDR

Write BBSY = 0

and SCP = 0 in ICCR

End

IRIC = 1?

Set TRS = 0 in ICCR

Set WAIT = 1 in ICMR

Set ACKB = 0 in ICSR

Read IRIC in ICCR

[1] Select receive mode

[2] Start receiving. The first read is a dummy

read. After reading ICDR, please clear

IRIC immediately.

[3] Wait for 1 byte to be received.

(8th clock falling edge)

[4] Clear IRIC to trigger the 9th clock.

(to end the wait insertion)

[5] Wait for 1 byte to be received.

(9th clock risig edge)

[6] Read the received data.

[7] Clear IRIC

[8] Wait for the next data to be received.

(8th clock falling edge)

[9] Clear IRIC to trigger the 9th clock.

(to end the wait insertion)

[10] Set ACKB = 1 so as to return No

acknowledge, or set TRS = 1 so as not

to issue Extra clock.

[12] Wait for 1 byte to be received.

[14] Stop condition issuance.

[13] Set WAIT = 0.

Read ICDR.

Clear IRIC.

(Note: After setting WAIT = 0, IRIC

should be cleared to 0)

[11] Clear IRIC to trigger the 9th clock.

(to end the wait insertion)

Figure 23.15 Flowchart for Master Receive Mode (Example)

Rev. 1.0, 02/01, page 512 of 1184

Start

End

Initialize

Read IRIC flag in ICCR

Read AAS and ADZ flags in ICSR

Read TRS bit in ICCR

Read IRIC flag in ICCR

Clear IRIC flag in ICCR

Read ICDR

Set ACKB=0 in ICSR

General call address processing

*Description omitted

Set MST=0 and

TRS=0 in ICCR

IRIC=1?

Yes

Read IRIC flag in ICCR

Set ACKB=0 in ICSR

IRIC=1?

Yes

TRS=0?

IRIC=1?

Yes

AAS=1 and

ADZ=0?

[2]

[1]

[3]

[8]

[5]

[6]

[4]

[7]

Slave transmit mode

Last receive?

Yes

Select slave receive mode.

Wait for 1 byte to be received (slave

address)

Start receiving. The first read is a dummy

read.

Wait for the transfer to end.

Set acknowledge data for the last receive.

Start the last receive.

Wait for the transfer to end.

Read the last receive data.

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

Figure 23.16 Flowchart for Slave Transmit Mode (Example)

Rev. 1.0, 02/01, page 513 of 1184

End

Write transmit data in ICDR

Clear IRIC flag in ICCR

Read ACKB bit in ICSR

Set TRS=0 in ICCR

Read ICDR

Read IRIC flag in ICCR

IRIC=1?

Yes

[1]

[4]

[5]

[2]

[3]

Slave transmit mode

End of transmission

(ACKB=1)?

Clear IRIC in ICCR

Set transmit data for the second and

subsequent bytes.

Wait for 1 byte to be transmitted.

Test for end of transfer.

Select slave receive mode.

Dummy read (to release the SCL line).

[1]

[2]

[3]

[4]

[5]

Figure 23.17 Flowchart for Slave Receive Mode (Example)

23.3.10 Initializing Internal Status

The I2C can forcibly initialize the I2C internal status when a dead lock occurs during

communication. Initialization is enabled by (1) setting the CLR3 to CLR0 bits in DDCSWR, or ( 2)

clearing the I CE bit. For details on CLR3 to CLR0 settings, refer to section 23.2.8, DDC Switch

(1) Initialized Status

This function initializes the followin g:

• TDRE and RDRF internal flags

• Transmit/receive sequencer and internal clock counter

• Internal latches (wait, clock, or data output) which holds the levels output from the SCL and

SDA pins

This function does not initialize the fo llowing:

• Register conte nts (ICDR, SAR, SA RX, ICM R, ICCR, ICS R, DDCSWR, and STCR)

Rev. 1.0, 02/01, page 514 of 1184

• Internal latches which holds the register read information to set or clear the flags in ICMR,

ICCR, ICSR, and DDCSWR

• Bit counter (BC2 to BC0) value in ICMR

• Sources of interrupts generated (interrupts that has been transferred to the interrupt

controller)

(2) Notes on Initialization

• Interrupt flags and interrupt sources are not cleared; clear them by software if necessary.

• Other register flags cannot be assumed to be cleared, either; clear them by software if

necessary.

• When initialization is specified by the DDCSWR settings, the da ta wr itten to the CLR3 to

CLR0 bits are not held. When initializing the I2C, be sure to use the MOV instru ction to

write to all the CLR3 to CLR0 bits at the same time; do not use bit manipulation

instructions such as BCLR. W hen reinitializin g the module status, all the CLR3 to CLR0

bits must be r e wr itten to at the same time.

• If a flag is cleared during transfer, the I2C module stops transfer immediately, and releases

the control of the SCL and SDA pins. Before starting again, set the registers to appropriate

values to make a correct communication if necessary.

This module initializing function does not modify the BBSY bit value, but in some cases,

depending on the SCL and SDA pin status and the release timing, the signal waveforms at the

SCL and SDA pins may indicate the stop condition, and accordingly the BBSY bit may be

cleared. Other bits or flags may be affected in the same way by modu le in itialization.

To avoid these problems, tak e the fo llowing procedure to initialize the I2C:

1. Initialize the I 2C by setting th e CLR3 to CLR0 bits or the ICE bit.

2. Execute a stop condition issuing instruction to clear the BBSY bit to 0 (writing 0 to BBSY and

SCP), and wait for two cycles of the transfer clock.

3. Initialize the I 2C again by setting the CLR3 to CLR0 bits o r the ICE bit.

4. Set the registers in I2C to appropriate values.

Rev. 1.0, 02/01, page 515 of 1184

23.4 Usage Notes

1. In master mode, if an instruction to generate a start condition is imme diately followed by an

instruction to generate a stop cond itio n, neither condition will be o utput correctly. To output

consecutive star t and stop condition s, af ter issuing the in str uction that generates the start

condition, read the relevant ports, check that SCL and SDA are both low, then issue the

instruction that generates the stop cond ition. Note that the SCL may briefly remain at a high

level immediately after BBSY is cleared to 0.

2. Either of the following two condition s will start the next transfer. Pay attention to these

conditions when reading or writing to ICDR.

a. Write access to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from

ICDRT to ICDRS)

b. Read access to ICDR when ICE = 1 and TRS = 0 (including automatic transfer fr om

ICDRS to ICDRR)

3. Table 23.5 shows the timing of SCL and SDA output in synchronization with the internal

clock. Timings on the bus are determined by the rise and fall times of signals affected by the

bus load capacitance, series resistance, and parallel resistance.

Table 23.5 I2C Bus Timing (SCL and SDA Output)

Item Symbol Output Timing Unit Notes

SCL output cycle time tSCLO 28tcyc to 256tcyc ns

SCL output high pulse width tSCLHO 0.5tSCLO ns

SCL output low pulse width tSCLLO 0.5tSCLO ns

SDA output bus free time tBUFO 0.5tSCLO-1tcyc ns

Start condition output hold time tSTAHO 0.5tSCLO-1tcyc ns

Retransmi ss ion start condi tion

output setup time tSTASO 1tSCLO ns

Stop condition output setup time tSTOSO 0.5tSCLO+2tcyc ns

Data output setup time (master) 1tSCLLO-3tcyc ns

Data output setup time (slave)

tSDASO

1tSCLL - (6tcyc or 12tcyc*) ns

Data output hold time tSDAHO 3tcyc ns

Figure 31.8

(reference)

Note: * 6tcyc when IICX is 0, 12tcyc when 1.

4. SCL and SDA input is sampled in synchronization with the in ternal clock. The AC timing

therefore depends on the system clock cycle tcyc, as shown in table 31.6 in section 31, Electrical

Characteristics. Note that the I2C bus interface AC timing specifications will not be met with a

system clock frequency of less than 5 MHz.

Rev. 1.0, 02/01, page 516 of 1184

5. The I2C bus interface specification for the SCL rise time tsr is under 1000 ns (300 ns for high-

speed mode). In master mode, the I 2C bus interface monitors the SCL line and synchronizes

one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) exceeds

the time determ in ed by the input clock of the I2C bus interface, the high period of SCL is

extended. The SCL rise time is determined by the pull-up resistance and load capacitance of

the SCL line. To insure proper opera tion at th e set transfer rate, adjust the pull- up r e sistance

and load capacitance so that the SCL rise time does not exceed the values given in table 23.6.

Table 23.6 Permissible SC L Ri se Time (t sr) Values

Time Indication [ns]

IICX tcyc Indication

I2C Bus

Specification

(Max.) φ

φφ

φ = 8 MHz φ

φφ

φ = 10 MHz

Normal mode 1000 937 750 0 7.5tcyc

High-speed mode 300 ← ←

Normal mode 1000 ← ← 1 17.5tcyc

High-speed mode 300 ← ←

6. The I2C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns

and 300 ns. The I2C bus interface SCL and SDA output timing is prescribed by tScyc, as shown

in table 23.5. However, because of the rise and fall times, the I2C bus interface specifications

may not be satisfied at the maximum transfer rate. Table 23.7 shows output timing

calculations for different operating frequencies, including the worst-case influence of rise and

fall times.

tBUFO fails to meet the I2C bus interface specifications at any frequency. The solution is either

(a) to provide coding to secure the necessary interval (approximately 1 µs) between issuance of

a stop condition and issuance of a start condition, or (b) to select devices whose input timing

permits this output timing for use as slave devices connected to the I2C bus.

tSCLLO in high-speed mode and tSTASO in standard mode fail to satisfy the I2C bus interface

specifications for worst-case calculations of tSr/tSf. Possible solutions that should be

investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and

capacitive load, (b) r educ ing the transf er rate to meet the specifications, or (c) selecting devices

whose input timing permits this output timing for use as slave devices connected to the I2C

bus.

Rev. 1.0, 02/01, page 517 of 1184

7. Precautions on reading ICDR at the end of master receive mode

When terminating the master receive mode, set TRS bit to 1, and select "write" for ICCR

BBSY = 0 and SCP = 0. This forces to move SDA from low to high level when SCL is at high

level, thereby gen e r ating the stop condition.

Now you can read received data from ICDR. If, however, any data is remaining on the buffer,

received data on ICDRS is not transferred to ICDR, thus you won't be able to read the second

byte data.

When it is required to read the second byte data, issue the stop condition from the master

receive state (TRS bit is 0).

Befor e reading data f rom ICDR register, make sure that BBSY bit on ICCR register is 0, sto p

condition is generated and bus is made free.

If you try to read received data after the stop condition issue instruction (setting ICCR's BBSY

= 0 and SCP = 0 to write) has been executed but before the actual sto p condition is ge nerated,

clock may not be appropriately signaled when the next master sending mode is turned on.

Thus, reasonable care is needed for determining when to read the received data.

After the master receive is complete, if you want to re-write IIC control bit (such as clearing MST

bit) for switching the sending/receiving mode or modifying settings, it must be done during period

(a) indicated in figure 23.18 (after making sure ICCR register BBSY bit is cleared to 0).

SDA

SCL

Internal clock

BBSY bit

Bit 0 A

(a)

Stop condition Start

condition

Start condition

is issued

Generation of the stop

condition is checked

(BBSY = 0 is set to read)

The stop condition

issue instruction

(BBSY = 0 and SCP = 0

set to write) is executed

Master receive mode

ICDR read

inhibit period

Figure 23.18 Precautions on Reading the Master Receive Data

Rev. 1.0, 02/01, page 518 of 1184

8. Notes on Start Condition Issuance for Retransmission

Figure 23.19 shows the timing of start cond ition issuance for retransmission, and the timing for

subsequently writing data to ICDR, together with the corresponding flowchart. After start

condition issuance is done and determin ed the start condition, write the tran sm it data to ICDR.

IRIC=1 ?

SCL=Low ?

IRIC=1 ?

Write transmit data to ICDR

Write BBSY=1,

SCP=0 (ICSR)

Clear IRIC in ICSR

Read SCL pin

Start condition

issuance? Other processing

No [1]

[2]

[3]

[4]

[5]

Yes

[1] Wait for end of 1-byte transfer

[2] Determine wheter SCL is low

[3] Issue restart condition instruction for transmission

[4] Determine whether start condition is generated or not

[5] Set transmit data (slave address + R/W)

Note: Program so that processing instruction [3] to [5] is

executed continuously.

[5] ICDR write (next transmit data)

[4] IRIC determination

[2] Determination of SCL=Low

[1] IRIC determination

SCL

SDA ACK bit 7

IRIC

Start condition

(retransmission)

[3] Issue restart condition instruction

for retransmission

Figure 23.19 Flowchart and Timing of Start Condition Instruction Issuance for

Retransmission

Rev. 1.0, 02/01, page 519 of 1184

9. Notes on I2C Bus Interface Stop Condition Instruction Issuance

If the rise time of the 9th SCL acknowledge exceeds the specification because the bu s load

capacitance is large, or if there is a slave device of the type that drives SCL low to effect a

wait, issue the stop condition instru ctio n after reading SCL and de ter mining it to be low, as

shown below.

Stop condition

SCL

IRIC

[1] Determination of SCL = low

9th clock

VIH High period secured

[2] Stop condition instruction issuance

SDA

As waveform rise is late,

SCL is detected as low

Figure 23.20 Timing of Stop Condition Issuance

Rev. 1.0, 02/01, page 520 of 1184

Table 23.7 I2C Bus Timing (w ith Maxi mum Influence of tSr/tSf)

Time Indication (at Maximum Transfer Rate) [ns]

Item tcyc Indication

tSr/tSf

Influence

(Max.)

I2C Bus

Specification

(Min.) φ

φφ

φ = 8 MHz φ

φφ

φ = 10 MHz

Normal mode −1000 4000 ← ← tSCLHO 0.5tSCLO

(-tSr) High-speed

mode −300 600 ← ←

Normal mode −250 4700 ← ← tSCLLO 0.5tSCLO

(-tSf) High-speed

mode −250 1300 ← ←

Normal mode −1000 4700 3875*1 3900*1 tBUFO 0.5tSCLO-1tcyc

(-tSr) High-speed

mode −300 1300 825*1 850*1

Normal mode −250 4000 4625 4650 tSTAHO 0.5tSCLO-1tcyc

(-tSf) High-speed

mode −250 600 875 900

Normal mode −1000 4700 9000 9000 tSTASO 1tSCLO

(-tSr) High-speed

mode −300 600 2200 2200

Normal mode −1000 4000 4250 4200 tSTOSO 0.5tSCLO+2tcyc

(-tSr) High-speed

mode −300 600 1200 1150

Normal mode −1000 250 3325 3400 tSDASO

(master) 1tSCLLO*3-3tcyc

(-tSr) High-speed

mode −300 100 625 700

Normal mode −1000 250 2200 2500 tSDASO

(slave) 1tSCLL*3-12tcyc*2

(-tSr) High-speed

mode −300 100 −500*1 −200*1

Normal mode 0 0 375 300 tSDAHO 3tcyc High-speed

mode 0 0 ↑ ↑

Notes: 1. Does not meet the I2C bus interface specification. Remedial action such as the

following is nec essary: (a) secure a start/sto p cond itio n issu a nce interval; (b) adjust the

rise and fall times by means of a pull-up resistor and capacitive load; (c) reduce the

transfer rate; (d) select slave de vices whose input timing permits this output timing.

The values in the above table will vary depending on the settings of the IICX bit and bits

CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the

maximum transfer rate; therefore, whether or not the I2C bus interface specifications are

met must be determined in ac corda nc e with the actual setting conditions.

2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is (tSCLL -

6tcyc).

3. Calculat ed using t he I2C bus specification values (standard mode: 4700 ns min.; high-

speed mode: 1300 ns min.).

Rev. 1.0, 02/01, page 521 of 1184

Section 24 A/D Converter

24.1 Overview

This LSI incorporates a 10-bit successive-approximations A/D converter that allows up to 12

analog input channels to be selected.

24.1.1 Features

A/D converter has the following features.

• 10-b it resolution

• 12 input channels

• Sample and hold function

• Choice of software, hardware (internal signal) triggering or external triggering for A/D

conversion start.

• A/D conversion end interrupt request generation

Rev. 1.0, 02/01, page 522 of 1184

24.1.2 Block Diagram

Figure 24.1 shows a block diagram of the A/D converter.

φ/2

φ/4

ADTRG

Interrupt request

AN0 Vref

Reference Voltage

Sample-and-

hold circuit

Chopper type

comparator

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AN8

AN9

ANA

ANB

DFG

ADTRG

(HSW timing generator)

Internal data bus

Legend:

ADR

AHR : Software trigger A/D result register

: Hardware trigger A/D result register ADTRG, DFG

ADTRG : Hardware trigger

: A/D external trigger input

ADCR

ADCSR: A/D control register

: A/D control/status register

ADTSR: A/D trigger selection register

10-bit

D/A

Hardware

control

circuit

Control circuit

Analog multiplexer

Successive

approximation register

Figure 24.1 Block Diagram of A/D Converter

Rev. 1.0, 02/01, page 523 of 1184

24.1.3 Pin Configuration

Table 24.1 summarizes the input pins used by the A/D converter.

Table 24.1 A/D Converter Pins

Name Abbrev. I/O Function

Analog power supply pin AVCC Input Analog block power supply and A/D

conversion reference voltage

Analog ground pin AVSS Input Analog block ground and A/D conversion

reference voltag e

Analog input pin 0 AN0 Input Analog input channel 0

Analog input pin 1 AN1 Input Analog input channel 1

Analog input pin 2 AN2 Input Analog input channel 2

Analog input pin 3 AN3 Input Analog input channel 3

Analog input pin 4 AN4 Input Analog input channel 4

Analog input pin 5 AN5 Input Analog input channel 5

Analog input pin 6 AN6 Input Analog input channel 6

Analog input pin 7 AN7 Input Analog input channel 7

Analog input pin 8 AN8 Input Analog input channel 8

Analog input pin 9 AN9 Input Analog input channel 9

Analog input pin A ANA Input Analog input channel A

Analog input pin B ANB Input Analog input channel B

A/D external trigger input pin ADTRG Input External trigger input for starting A/D

conversion

Rev. 1.0, 02/01, page 524 of 1184

24.1.4 Register Configuration

Table 24.2 summarizes the registers of the A/D converter.

Table 24.2 A/D Converter Registers

Name Abbrev. R/W Size Initial Value Address*2

Software trigger A/D

result register H ADRH R Byte H'00 H'D130

Software trigger A/D

result register L ADRL R Byte H'00 H'D131

Hardware trigger A/D

result register H AHRH R Byte H'00 H'D132

Hardware trigger A/D

result register L AHRL R Byte H'00 H'D133

A/D control register ADCR R/W By te H'40 H'D134

A/D control/status

A/D trigger selection

Port mode register 0 PMR0 R/W Byte H'00 H'FFCD

Notes: 1. Only 0 can be written in bits 7 and 6, to clear the flag. Bits 3 to 1 are read-only.

2. Lower 16 bits of the address.

Rev. 1.0, 02/01, page 525 of 1184

24.2 Register Descriptions

24.2.1 Software-Triggered A/D Result Register (ADR)

ADRH ADRL

103254 ——————

——————

ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0

12131415

000000

Bit :

Initial value :

R/W :

The software-triggered A/D result register (ADR) is a register that stores the result of an A/D

conversion started by software.

The A/D-converted data is 10-bit data. Upon completion of software-triggered A/D conversion,

the 10-bit result data is transferred to ADR and the data is retained u ntil the next software-

triggered A/D conversion completion. The upper 8 bits of the data are stored in the upper bytes

(bits 15 to 8) of ADR, and the lower 2 bits are stored in the lower bytes (bits 7 and 6). Bits 5 to 0

are always read as 0.

ADR can be read by the CPU at any time, but the ADR value during A/D conversion is not fixed.

The upper bytes can always be read directly, but the data in the lower bytes is transferred via a

temporary register (TEMP). For details, see section 24.3, Interface to Bus Master.

ADR is a 16-bit read-only register which is initialized to H'0000 at a reset, and in module stop

mode, standby mode, watch mode, subactive mode and subsleep mode.

24.2.2 Hardware-Triggered A/D Result Register (AHR)

AHRH AHRL

103254 ——————

——————

AHR9 AHR8 AHR7 AHR6 AHR5 AHR4 AHR3 AHR2 AHR1 AHR0

12131415

00000

Bit :

Initial value :

R/W :

The hardware-triggered A/D result register (AHR) is a register that stores the result of an A/D

conversion started by hardware (internal signal: ADTRG and DFG) or by external trigger input

(ADTRG).

The A/D-converted data is 10-bit data. Upon completion of hardware- or external-triggered A/D

conversion, the 10-bit result data is transferred to AHR and the data is retained until the next

hardware- or external- triggered A/D conversion completion. The upper 8 bits of the data are

stored in the upper bytes (bits 15 to 8) of AHR, and the lower 2 bits are stored in the lower bytes

(bits 7 and 6). Bits 5 to 0 are always read as 0.

Rev. 1.0, 02/01, page 526 of 1184

AHR can be read by the CPU at any time, but the AHR value during A/D conversion is not fixed.

The upper bytes can always be read directly, but the data in the lower bytes is transferred via a

temporary register (TEMP). For details, see section 24.3, Interface to Bus Master.

AHR is a 16-bit read-only register which is initialized to H'0000 at a reset, and in module stop

mode, standby mode, watch mode, subactive mode and subsleep mode.

24.2.3 A/D Control Register (ADCR)

R/W

—

R/WR/WR/W

HCH1

R/W

CK HCH0 SCH3 SCH2 SCH1 SCH0

Bit :

Initial value :

R/W :

ADCR is a register that sets A/D conversion speed and selects analog input channel. When

executing ADCR setting, make sure that the SST and HST flags in ADCSR is set to 0.

ADCR is an 8-b it readable/writable register that is initialized to H'40 by a reset, and in module

stop mode, standby mode, watch mode, subactive mode and subsleep mode.

Bit 7



Clock Select (CK): Sets A/D conversion speed.

Bit 7

CK Description

0 Conversion frequency is 266 states (Initial value)

1 Conversion frequency is 134 states

Note: A/D conversion starts when 1 is written in SST, or when HST is set to 1. The conversion

period is the time from when this start flag is set until the flag is cleared at the end of

conversion. Actual sample-and-hold takes place (repeatedly) during the conversion

frequency shown in figure 24.2.

Rev. 1.0, 02/01, page 527 of 1184

Conversion frequency

Note: IRQ sampling;

Conversion period (134 or 266 states)

Interrupt request flag

IRQ sampling

(CPU)

States

Instruction execution MOV.B

WRITE

Start flag

When conversion ends, the start flag is cleared and the interrupt request flag is

set. The CPU recognizes the interrupt in the last execution state of an instruction,

and executes interrupt exception handling after completing the instruction.

Figure 24.2 Internal Operation of A/D Converter

Bit 6



Reserved: This bit cannot be modified and is always read as 1.

Bits 5 and 4



Hardware Channel Select (HCH1, HCH0): These bits select the analog input

channel that is converted by hardware triggering or triggering by an external input. Only channels

AN8 to ANB are available for hardware- or external-triggered conversion.

Bit 5 Bit 4

HCH1 HCH0 Analog Input Channel

0 AN8 (Initial value) 0

1 AN9

0 ANA 1

1 ANB

Rev. 1.0, 02/01, page 528 of 1184

Bits 3 to 0



Software Channel Select (SCH3 to SCH0): These bits select the analog input

channel that is converted by software triggering.

When chann els AN0 to AN7 are used, appropriate pin settings must b e m a d e in port mo d e register

0 (PMR0). For pin settings, see section 24.2.6, Port Mode Register 0 (PMR0).

Bit 3 Bit 2 Bit 1 Bit 0

SCH3 SCH2 SCH1 SCH0 Analog Input Channel

0 AN0 (Initial value) 0

1 AN1

0 AN2

1 AN3

0 AN4 0

1 AN5

0 AN6

1 AN7

0 AN8 0

1 AN9

0 ANA

1 ANB

1 * * No channel selected for software-triggered conversion

Notes: 1. If conversion is started by software when SCH3 to SCH0 are set to 11**, the

conversion result is undetermined. Hardware- or external-triggered conversion,

however, will be performed on the channel selected by HCH1 and HCH0.

2. * Don't care.

Rev. 1.0, 02/01, page 529 of 1184

24.2.4 A/D Control/Status Register (ADCSR)

—

R/W

R/(W)*RR/W

ADIE

R/(W)*

SEND SST HST BUSY SCNLHEND

Bit :

Initial value :

R/W :

Note: * Only 0 can be written to bits 7 and 6, to clear the flag.

The A/D status register (ADCSR) is an 8-bit register that can be used to start or stop A/D

conversion, or check the status of the A/D converter.

A/D conversion starts when 1 is written in SST flag. A/D conversion can also start by setting HST

flag to 1 by hardware- or external-triggering.

For ADTRG start by HSW ti ming generator in hardware triggering, see section 26.4, HSW (Head-

switch) Timing Generator.

When conversion ends, the converted data is stored in the software-triggered A/D result register

(ADR) or hardware-triggered A/D result register (AHR), and the SST or HST bit is cleared to 0.

If software-triggering and hardware- or external-triggering are generated at the same time, priority

is given to hard ware- or external-triggering.

ADCSR is an 8-bit register which is initialized to H'01 by a reset, and in module stop mode,

standby mode, watch mode, subactive mode and subsleep mode.

Bit 7



Software A/D End Flag (SEND): Indicates the end of A/D conversion.

Bit 7

SEND Description

0 [Clearing Conditions] (Initial value)

0 is written after reading 1

1 [Setting Conditions]

Software-triggered A/D conversion has ended

Bit 6



Hardware A/D End Flag (HEND): Indicates that hardware- or external-triggered A/D

conversion has ended.

Bit 6

HEND Description

0 [Clearing Conditions] (Initial value)

0 is written after reading 1

1 [Setting Conditions]

Hardware- or external-triggered A/D conversion has ended

Rev. 1.0, 02/01, page 530 of 1184

Bit 5



A/D Interrupt Enable (ADIE): Selects enable or disable of interrupt (ADI) generation

upon A/D conversion end.

Bit 5

ADIE Description

0 Interrupt (ADI) upon A/D conversion end is disabled (Initial value)

1 Interrupt (ADI) upon A/D conversion end is enabled

Bit 4



Software A/D Start Flag (SST): Indicates or controls the start and end of software-

triggered A/D conversion. This bit remains 1 during software-triggered A/D conversion.

When 0 is written in this bit, softwar e-triggered A/D conversion operation can forcibly be aborted.

Bit 4

SST Description

Read: Indicates that software-triggered A/D conv ersion has ended or been stopped

(Initial value)

Write: Software-triggered A/D conversion is aborted

Read: Indicates that software-triggered A/D conv ersion is in progress 1

Write: Starts software-triggered A/D conversion

Bit 3



Hardware A/D Status Flag (HST): Indicates the status of hardware- or external-triggered

A/D conversion. When 0 is written in this bit, A/D conversion is aborted regardless of whether it

was hardware-triggered or external-triggered.

Bit 3

HST Description

Read: Hardware- or external-triggered A/D conv ersion is not in progress

(Initial value)

Write: Hardware- or external-triggered A/D conversion is aborted

1 Hardware- or external-triggered A/D conversion is in progress

Rev. 1.0, 02/01, page 531 of 1184

Bit 2



Busy Flag (BUSY): During hardware- or external-triggered A/D conversion, if software

attempts to start A/D conversion by writing to the SST bit, the SST bit is not modified and instead

the BUSY flag is set to 1 .

This flag is cleared when the hardware-triggered A/D result register (AHR) is read.

Bit 2

BUSY Description

0 No contention for A/D con ver si on (Initial value)

1 Indicates an attempt to execute software-triggered A/D conversion while hardware- or

external-triggered A/D conversion was in progress

Bit 1



Software-Triggered Conversion Cancel Flag (SCNL): Indicates that software-triggered

A/D conversion was canceled by the start of hardware-triggered A/D conversion.

This flag is cleared when A/D conversion is started by software.

Bit 1

SCNL Description

0 No contention for A/D con ver si on (Initial value)

1 Indicates that software-triggered A/D conversion was canceled by the start of

hardware-triggered A/D conversion

Bit 0



Reserved: This bit cannot be modified and is always read as 1.

Rev. 1.0, 02/01, page 532 of 1184

24.2.5 Trigger Select Register (ADTSR)

0123

R/W

567 ——————

——————

TRGS1

R/W

TRGS0

111111

Bit :

Initial value :

R/W :

The trigger select register (ADTSR) selects hardware- or external-triggered A/D conversion start

factor.

ADTSR is an 8-bit readable/writable register that is initialized to H'FC by a reset, and in module

stop mode, standby mode, watch mode, subactive mode and subsleep mode.

Bits 7 to 2



Reserved: These bits cannot be modified and are always read as 1.

Bits 1 and 0



Trigger Select (TRGS1, TRGS0): These bits select hardware- or external-

triggered A/D conversion start factor. Set these bits when A/D conversion is not in progress.

Bit 1 Bit 0

TRGS1 TRGS0 Description

0 Hardware- or external-triggered A/D conversion is disabled

(Initial value)

1 Hardware-triggered (ADTRG) A/D conversion is selected

0 Hardware-triggered (DFG) A/D conversion is selected 1

1 External-triggered (ADTRG) A/D conversion is selected

24.2.6 Port Mode Register 0 (PMR0)

R/W

7PMR04 PMR03 PMR02 PMR01 PMR00

R/W

PMR07

R/WR/WR/W

PMR06 PMR05

Bit :

Initial value :

R/W :

Port mode register 0 (PMR0) controls switching of each pin function of port 0. Switching is

specified for each bit.

PMR0 is an 8-b it r eadable/writable register and is initialized to H'00 by a re set.

Rev. 1.0, 02/01, page 533 of 1184

Bits 7 to 0



P07/AN7 to P00/AN0 Pin Switching (PMR07 to PMR00): These bits set the

P0n/ANn pin as the input pin for P0n or as the ANn pin for A/D conversion analog input channel.

Bit n

PMR0n Description

0 P0n/ANn functions as a general-purpose input port (Initial value)

1 P0n/ANn functions as an analog input channel

(n = 7 to 0)

24.2.7 Module Stop Control Register (MSTPCR)

MSTP15

R/W

MSTPCRH

MSTP14

R/W

MSTP13

R/W

MSTP12

R/W

MSTP11

R/W

MSTP10

R/W

MSTP9

R/W

MSTP8

R/W

MSTP7

R/W

MSTP6

R/W

MSTP5

R/W

MSTP4

R/W

MSTP3

R/W

MSTP2

R/W

MSTP1

R/W

MSTP0

R/W

MSTPCRL

Bit :

Initial value :

R/W :

MSTPCR consists of 8-bit readable/writable registers and performs module stop mode control.

When the MSTP2 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus

cycle and a transition is made to module stop mode. For details, see section 4.5, Module Stop

Mode.

MSTPCR is initialized to H'FFFF by a reset

Bit 2



Module Stop ( MSTP2 ): Specifies the A/D converter module stop mode.

MSTPCRL

Bit 2

MSTP2 Description

0 A/D converter module stop mode is cleared

1 A/D converter module stop mode is set (Initial value)

Rev. 1.0, 02/01, page 534 of 1184

24.3 Interface to Bus Master

ADR and AHR are 16-bit registers, but the data bus to the bus master is only 8 bits wide.

Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is

accessed via a temporary register (TEMP).

A data reading from ADR and AHR is performed as follows. When the upper byte is read, the

upper byte valu e is transferred to the CPU and the lower byte value is transferred to TEMP. Next,

when the lower byte is read, the TEMP contents are transferred to the CPU.

When reading ADR and AHR, always read the upper byte before the lower byte. It is possible to

read only the upper byte, but if only the lower byte is read, incorrect data may be obtained.

Figure 24.3 shows the data flow for ADR access. The data flow for AHR access is the same.

Bus master

(H'AA)

ADRH

(H'AA) ADRL

(H'40)

Lower byte read

Bus master

(H'40)

ADRH

(H'AA) ADRL

(H'40)

TEMP

(H'40)

TEMP

(H'40)

Module data bus

Bus

interface

Bus

interface

Upper byte read

Figure 24.3 ADR Access Operation (Reading H'AA40)

Rev. 1.0, 02/01, page 535 of 1184

24.4 Operation

The A/D converter operates by successive approximations with 10-bit resolution.

24.4.1 Software-Triggered A/D Conversion

A/D conversion starts when software sets the software A/D start flag (SST bit) to 1. The SST bit

remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends.

Conversion can be software-triggered on any of the 12 channels provided by analog input pins

AN0 to ANB. Bits SCH3 to SCH0 in ADCR select the analog input pin used for software-

triggered A/D conversion. Pins AN8 to ANB are also available for hardware- or external-

triggered conversion.

When conversion ends, SEND flag in ADCSR bit is set to 1. If ADIE bit in ADCSR is also set to

1, an A/D conversion end interrupt occurs.

If the conversion time or input channel selection in ADCR needs to be changed during A/D

conversion, to avoid malfunctions, first clear the SST bit to 0 to halt A/D conversion.

If software writes 1 in the SST bit to start software-triggered conversion while hardware- or

external-triggered conversion is in progress, the hardware- or external-triggered conversion has

priority and the software-triggered conversio n is not executed. At this time, BUSY flag in

ADCSR is set to 1 . The BUSY flag is cleared to 0 when the hardware-triggered A/D resu lt

conversion is in progress, the software-triggered conversion is immediately canceled and the SST

flag is cleared to 0, and SCNL flag in ADCSR is set to 1. The SCNL flag is cleared when

software writes 1 in the SST bit to start conversion after the hardware-triggered conversion ends.

Rev. 1.0, 02/01, page 536 of 1184

24.4.2 Hardware- or External-Triggered A/D Conversion

The system contains the hardware trigger function that allows to turn on A/D conversion at a

specified timing by use of the hardware trigger (internal signals: ADTRG and DFG) and the

incoming external trigger (ADTRG). This function can be used to measure an analog signal that

varies in synchronization with an external signal at a fixed timing.

To execute hardware- or external-triggered A/D conversion, select appropriate start factor in

TRGS1 and TRGS0 bits in ADTSR. When the selected triggering occurs, HST flag in ADCSR is

set to 1 and A/D conversion starts. The HST flag remains 1 during A/D conversion, and is

automatically cleared to 0 when conversion ends. For ADTRG start by HSW timing generator in

hardware triggering, see section 26.4, HSW Timing Generator. Setting of the analog input pins on

four channels from AN8 to ANB can be modified with the hardware trigger or the incoming

external trigger. Setting is done from HCH1 and HCH0 bits on ADCR. Pins AN8 to ANB are

also available for software-triggered conversion.

When conversion ends, HEND flag in ADCSR is set to 1. If ADIE bit in ADCSR is also set to 1,

an A/D conversion end interrupt occurs.

If the conversion time or input channel selection in ADCR needs to be changed during A/D

conversion, to avoid malfunctions, first clear the HST flag to 0 to halt A/D conversion.

If software writes 1 in the SST bit to start software-triggered conversion while hardware- or

external-triggered conversion is in progress, the hardware- or external-triggered conversion has

priority and the software-triggered conversio n is not executed. At this time, BUSY flag in

ADCSR is set to 1 . The BUSY flag is cleared to 0 when the hardware-triggered A/D resu lt

If conversion is triggered by hardware while software-trigg ered conversion is in progress, the

software-triggered conversion is immediately canceled and the SST flag is cleared to 0, and SCNL

flag in ADCSR is set to 1 (the SCNL flag is cleared when software writes 1 in the SST bit to start

conversion after the hardware-triggered conversion ends). The analog input channel changes

automatically from the channel that was undergoing software-triggered conversion (selected by

bits SCH3 to SC H0 in ADCR) to the channel selected by bits HCH1 and HCH0 in ADCR for

hardware- or external-triggered conversion. After the hardware- or ex ternal-triggered conversion

ends, the channel reverts to the channel selected by the software-triggered conversion channel

select bits in ADCR.

Hardware- or external-triggered conversion has priority over software-triggered conversion, so the

A/D interrupt-handling routine should check the SCNL and BUSY flags when it processes the

converted data.

Rev. 1.0, 02/01, page 537 of 1184

24.5 Interrupt Sources

When A/D conversion ends, SEND or HEND flag in ADCSR is set to 1. The A/D conversion end

interrupt (ADI) can be enabled or disabled by ADIE bit in ADCSR.

Figure 24.4 shows the block diagram of A/D conversion end interrupt.

A/D conversion end

interrupt (ADI)

To interrupt controller

A/D control/status register (ADCSR)

SEND HEND ADIE

Figure 24.4 Block Diagram of A/D Conversion End Interrupt

Rev. 1.0, 02/01, page 538 of 1184

Rev. 1.0, 02/01, page 539 of 1184

Section 25 Address Trap Controller (ATC)

25.1 Overview

The address trap controller (ATC) is capable of generating interrupt by setting an address to trap,

when the address set appears during bus cycle.

25.1.1 Features

Address to trap can be set independently at three points.

25.1.2 Block Diagram

Figure 25.1 shows a block diagram of the address trap controller.

ATCR

Legend:

TAR0 to 2

Interrupt request

Modules bus

Internal bus

ATCR TAR0 TAR1 TAR2

Trap condition comparator

Bus

interface

: Address trap control register

: Trap address register 0 to 2

Figure 25.1 Block Diagram of ATC

Rev. 1.0, 02/01, page 540 of 1184

25.1.3 Register Configuration

Table 25.1 Register List

Name Abbrev. R/W Initial Value Address*

Address trap control register ATCR R/W H'F8 H'FFB9

Trap address register 0 TAR0 R/W H'F00000 H'FFB0 to H'FFB2

Trap address register 1 TAR1 R/W H'F00000 H'FFB3 to H'FFB5

Trap address register 2 TAR2 R/W H'F00000 H'FFB6 to H'FFB8

Note: * Lower 16 bits of the address.

25.2 Register Descriptions

25.2.1 Address Trap Control Register (ATCR)

R/W

—————

————— R/W

TRC2 TRC1 TRC0

Bit :

Initial value :

R/W :

Bits 7 to 3



Reserved: These bits cannot be modified and are always read as 1.

Bit 2



Trap Control 2 (TRC2): Sets ON/OFF operation of the address trap function 2.

Bit 2

TRC2 Description

0 Address trap function 2 disabled (Initial value)

1 Address trap function 2 enabled

Rev. 1.0, 02/01, page 541 of 1184

Bit 1



Trap Control 1 (TRC1): Sets ON/OFF operation of the address trap function 1.

Bit 1

TRC1 Description

0 Address trap function 1 disabled (Initial value)

1 Address trap function 1 enabled

Bit 0



Trap Control 0 (TRC0): Sets ON/OFF operation of the address trap function 0.

Bit 0

TRC0 Description

0 Address trap function 0 disabled (Initial value)

1 Address trap function 0 enabled

Rev. 1.0, 02/01, page 542 of 1184

25.2.2 Trap Address Register 2 to 0 (TAR2 to TAR0)

R/W

34567

R/W

A18 A17 A16

R/W

R/W R/W

A23 A22 A21

R/W R/W

A20 A19

R/W

34567

R/W

A10 A9 A8

R/W

R/W R/W

A15 A14 A13

R/W R/W

A12 A11

—

R/W

34567

A2 A1

R/W

R/W R/W

A7 A6 A5

R/W R/W

A4 A3

Bit :

Initial value :

R/W :

Bit :

Initial value :

R/W :

Bit :

Initial value :

R/W :

The TAR is composed of three 8-bit readable/writable registers (TARnA, B, and C)(n = 2 to 0)

The TAR sets the addr ess to trap. The function of the TAR2 to TAR0 is the same.

The TAR is initialized to H'0 0 by a reset.

TARA bits 7 to 0: Addresses 23 to 16 (A23 to A16)

TARB bits 7 to 0: Addresses 15 to 8 (A15 to A8)

TARC bits 7 to 0: Addresses 7 to 1 (A7 to A1)

If the value installed in this register and internal address buses A23 to A1 match as a result of

comparison, an interruption occurs.

For the address to trap, set to the address where the first byte of an instruction exists. In the case

of other addresses, it may not be considered that the condition h a s been satisfied.

Bit 0 of this register is fixed at 0. The address to trap becomes an even address.

The range where comparison is made is H'000000 to H'FFFFFE.

Rev. 1.0, 02/01, page 543 of 1184

25.3 Precautions in Usage

Address trap interrupt arises 2 states after prefetching the trap address. Trap interrupt may occur

after the trap instruction has been executed, depending on a combination of instructions

immediately preceding the setting up of the address trap.

If the instruction to trap immediately follows the branch instruction or the conditional branch

instruction, operation may differ, depending on whether the condition was satisfied or not, or the

address to be stacked may be located at the branch. Figures 25.2 to 25.22 show specific

operations.

For information as to where the next instruction prefetch occurs during the ex ecution cycle of the

instruction, see appendix A.5 of this manual or section 2.7 Bus State during Execution of

Instruction of the H8S/2600 and H8S/2000 Series Programming Manual. (R:W NEXT is the next

instruction prefetch.)

25.3.1 Basic Operations

After terminating the execution of th e instru ction being executed in the second state f rom the trap

address prefetch, the address trap interrupt exception handling is started.

1. Figure 25.2 shows the operation when the instruction immediately preceding the trap address

is that of 3 states or more of the execution cycle and th e next instruction prefetch occurs in the

state before the last 2 states. The address to be stacked is 0260.

Address bus

Interrupt

request

signal

MOV

execution

MOV

instruc-

tion

pre-fetch

NOP

instruc-

tion

pre-fetch

Internal

opera-

tion

Data

read Start of exception

handling

Immediately

preceding

Instruction

Address

025E MOV.B @ER3+,R2L

0260 NOP

(ER3 = H'0000)

0262 NOP

0264 NOP

025E 0260 0000 0262

→

* Trap setting address

The underlines address is the

one to be actually stacked.

Note: In the figure above, the NOP instruction is used as the typical example of instruction with

execution cycle of 1 state. Other instructions with the execution cycle of 1 state also apply

(Ex. MOV.B, Rs, Rd).

Figure 25.2 Basic Operations (1)

Rev. 1.0, 02/01, page 544 of 1184

2. Figure 25.3 shows the operation when the instruction immediately preceding the trap address

is that of 2 states or more of the execution cycle and th e next instruction prefetch occurs in the

second state from the last. The address to be stacked is 02 68.

Address bus

Interrupt

request

signal

MOV

execution NOP

execution

Start of exception

handling Immediately

preceding

instruction

Address

0266 MOV.B

R2L, @0000

0268 NOP

026A NOP

026C NOP

0266 026A0268 0000 026C

Data

read

→

MOV

instruc-

tion

pre-fetch

NOP

instruc-

tion

pre-fetch

NOP

instruc-

tion

pre-fetch

Note: * Trap setting address

The underlines address is the one to be actually stacked.

Figure 25.3 Basic Operations (2)

3. Figure 25.4 shows the operation when the instruction immediately preceding the trap address

is that of 1 state or 2 states or more and the prefetch occurs in the last state. The address to be

stacked is 025C.

Address bus

Interrupt

request

signal

NOP

execu-

tion

NOP

execu-

tion

NOP

execu-

tion

Start of

exception

handling Immediately

preceding

instruction

Address

0256 NOP

0258 NOP

025A NOP

025C NOP

025E NOP

0256 025C0258 025A 025E

→

NOP

instruc-

tion

pre-fetch

NOP

instruc-

tion

pre-fetch

NOP

instruc-

tion

pre-fetch

NOP

instruc-

tion

pre-fetch

Note: * Trap setting address

The underlines address is the one to be actually stacked.

Figure 25.4 Basic Operations (3)