Wireless Components
ASK/FSK Transmitter 868/433 MHz
TDA 5100 Version 2.1
Specif ication June 2001
Edition 30.11.2000
Published by Infineon Technologies AG,
Balanstraße 73,
815 41 Mü nc he n
© Infineon Technologies AG 2001.
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Revision History
Current Version: 2 .1 as of 12.0 6..2 001
Previous Version: 2.0, November 2000
Page
(in previous
Version)
Page
(in current
Version)
Subjects (major changes since last revision)
3-3 ... 3-7 3-3 ... 3-7 Schematics corrected: ESD structures added
5-3 ... 5-8 5-3 ... 5-8 Limits tightened for:
Supply Current, Saturation Voltage of Clock Driver Output and Output Power
5-5, 5-8 5-5,5-8 Supply-voltage dependency of Output Power added as footnote
5-5, 5-8 5-5,5-8 Limits corrected for Input Current CSEL
5-3, 5-6 5-3,5-6 Limits corrected for Low Power Detect Current
Product Info
Product Info
Wireless Components
Specific atio n, June 2001
Package
TDA 5100
Product Info
General Description The TDA5100 is a single chip ASK/
FSK transmitter for the frequency
bands 868-870 MHz and 433-435
MHz. T he I C offers a hi gh l evel of inte-
gration and needs only a few external
components. The device contains a
fully integrated PLL synthesizer and a
high effic iency power amplif ier to drive
a loop ante nna. A sp ecial circ uit desi gn
and an unique power amplifier design
are used to save current consumption
and t her ef ore t o sa v e ba ttery liv e . Ad di-
tionally features like a power down
mode, a low power detect, a selectable
crystal oscillator frequency and a
divided clock output are implemented.
The IC can b e used for both ASK and
FSK modulation.
Features
fully integrated frequency synthe-
sizer
VCO without external components
high efficiency power amplifier
switchable frequency range
868-870/433-435 MHz
ASK/FSK modulation
low supply current (typically 7mA)
voltage supply range 2.1 - 4 V
power down mode
low voltage sensor
selectable crystal oscillator
6.78 MHz/13.56 MHz
programmable divided clock output
for µC
low ex te r nal compo nen t count
Applications
Keyless entry systems
Remote control systems
Alarm systems
Communication systems
Ordering Information Type Ordering Code Package
TDA 5100 Q67036-A1048 P-TSSOP-16
available on tape and reel
1Table of Contents
1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-i
2 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Pin Definitions and Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3 Functional Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.4 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
4.1 50 Ohm-Output Testboard Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2 50 Ohm-Output Testboard Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.3 Bill of material (50 Ohm-Output Testboard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.4 Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.5 Application Board Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.6 Application Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
4.7 Bill of material (Application Board) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
4.8 Application Board Photo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
5 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 -2
5.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3
2Product Description
2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Contents of this Chapter
Product Description
2 - 2
TDA 5100
Wireless Components
Specific atio n, June 2001
2.1 Overview
The TDA5100 is a single chip ASK/FSK transmitter for the frequency bands
868-870 MHz and 433-435 MHz. The IC offers a high level of integration and
needs only a few external components. The device contains a fully integrated
PLL synthesizer and a high efficiency power amplifier to drive a loop antenna.
A special circuit design and an unique power amplifier design are used to sav e
current consumption and therefore to save battery life. Additional features like
a power down mode, a low power detect, a selectable crystal oscillator fre-
quency and a divided clock output are implemented. The IC can be used for
both ASK and FSK modulation.
2.2 Applications
Keyless entry systems
Remote control systems
Alarm systems
Communication systems
2.3 Features
fully integrated frequency synthesizer
VCO without external components
high efficiency power amplifier
switchable frequency range 868-870/433-435 MHz
ASK/FSK modulation
low supply current (typically 7 mA)
voltage supply range 2.1 - 4 V
power down mode
low voltage sensor
selectable crystal oscillator 6.78 MHz/13.56 MHz
programmable divided clock output for µC
low external component count
Product Description
2 - 3
TDA 5100
Wireless Components
Specific atio n, June 2001
2.4 Package Outlines
Figure 2-1 P-TSSOP-16
3Functional Description
3.1 Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3 Functional Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.4 Functional Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.4.1 PLL Synthesizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.4.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.4.3 Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.4.4 Low Power Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.4.5 Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-10
3.4.5.1 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.4.5.2 PLL Enable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.4.5.3 Transmit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-10
3.4.6 Recommended timing diagrams for ASK- and FSK-Modulation . . 3-12
Contents of this Chapter
Functional Description
3 - 2
TDA 5100
Wireless Components
Specific atio n, June 2001
3.1 Pin Configuration
Pin_config.wmf
Figure 3-1 IC Pin Configur atio n
Table 3-1
Pin No. Symbol Function
1PDWN Power Down Mode Control
2LPD Low Power Detect Output
3VS Voltage Supply
4LF Loop Filter
5GND Ground
6ASKDTA Amplitude Shift Keying Data Input
7FSKDTA Frequency Shift Keying Data Input
8CLKOUT Clock Driver Output
9CLKDIV Clock Divider Control
10 COSC Crystal Oscillator Input
11 FSKOUT Frequency Shift Keying Switch Output
12 FSKGND Frequency Shift Keying Ground
13 PAGND Power Amplifier Ground
14 PAOUT Power Amplifier Output
15 FSEL Frequency Range Selection (433 or 868 MHz)
16 CSEL Crystal Frequency Selection (6.78 or 13.56 MHz)
CSEL
FSEL
PAOUT
PAGND
FSKGND
FSKOUT
COSC
CLKDIV
PDWN
LPD
VS
LF
GND
ASKDTA
FSKDTA
CLKOUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TDA 5100
Functional Description
3 - 3
TDA 5100
Wireless Components
Specific atio n, June 2001
3.2 Pin Definitions and Functions
Table 3-2
Pin
No. Symbol Interface Schematic Function
1PDWN Disable pin for the complete transmitter cir-
cuit.
A logic low (PDWN < 0.7 V) turns off all
transmitter functions.
A logic high (PDWN > 1.5 V) gives access to
all transmitter functions.
PDWN input will be pulled up by 40 µA inter-
nally by either setting FSKDTA or ASKDTA
to a logic high-state.
2LPD This pin provides an out put indicating the
low-voltage state of the supply voltage VS.
VS < 2.15 V will set LPD to the low-state.
An internal pull-up current of 40 µA gives the
output a high-state at supply voltages above
2.15 V.
3VS This pin is the positive supply of the trans-
mitter electronics.
An RF bypass capacitor should be con-
nected directly to this pin and returned to
GND (pin 5) as short as possible.
1
V
S
150 k
Ω
5 k
Ω
250 k
Ω
"ON"
40
µ
A
∗
(ASKDTA+FSKDT A)
V
S
300
Ω
2
40 µA
Functional Description
3 - 4
TDA 5100
Wireless Components
Specific atio n, June 2001
4LF Output of the charge pump and input of the
VCO control voltage.
The loop bandwidth of the PLL is 150 kHz
when only the internal loop filter is used.
The loop bandwidth may be reduced by
applying an external RC network referencing
to the positive supply VS (pin 3).
5GND General ground connection.
6ASKDTA Digital amplitude modulation can be
imparted to the Power Amplifier through this
pin.
A logic high (ASKDTA > 1.5 V or open)
enables the Power Amplifier.
A logic low (ASKDTA < 0.5 V)
disable s the Powe r Am pli fi er .
7FSKDTA Digital frequency modulation can be
imparted to the Xtal Oscillator by this pin.
The VCO-frequency varies in accordance to
the frequency of the reference oscillator.
A logic high (FSKDTA > 1.5V or open)
sets the FSK switch to a high impedance
state.
A logic low (FSKDTA < 0.5 V)
closes the FSK switch
from FSKOUT (pin 11) to FSKGND (pin 12).
A capacitor can be switched to the reference
crystal network this way. The Xtal Oscillator
frequency will be shifted giving the designed
FSK frequency deviation.
V
S
10 k
Ω
4
35 k
Ω
15 pF
140 pF
V
S
+ 1.2 V
90 k
Ω
6
50 pF 30
A
60 k
Ω
+ 1 .1 V
V
S
+1.2 V
90 k
Ω
7
30
A
60 k
Ω
+1.1 V
V
S
Functional Description
3 - 5
TDA 5100
Wireless Components
Specific atio n, June 2001
8CLKOUT Cl ock output to supply an external device.
An external pull-up resistor has to be added
in accordance to the driving requirements of
the external device.
A clock frequency of 3.39 MHz is selected
by a logic low at CLKDIV input (pin9).
A clock frequency of 847.5 kHz is selected
by a logic high at CLKDIV input (pin9).
9CLKDIV This pin is used to select the desired clock
division rate for the CLKOUT signal.
A logic low (CLKDIV < 0.2 V) applied to this
pin selects the 3.39 MHz output signal at
CLKOUT (pin 8).
A logic high (CLKDIV open) applied to this
pin selects the 847.5 kHz output signal at
CLKOUT (pin 8).
10 COSC This pin is connected to the reference oscil-
lator circuit.
The reference oscillator is working as a neg-
ative impedance converter. It presents a
negative resistance in series to an induc-
tance at the COSC pin.
11 FSKOUT This pin is connected to a switch to
FSKGND (pin 12).
The switch is closed when the signal at
FSKDTA (pin 7) is in a logic low state.
The switch is open when the signal at
FSKDTA (pin 7) is in a logic high state.
FSKOUT can switch an additional capacitor
to the reference crystal network to pull the
crystal fr eque nc y by an amou nt res ul tin g in
the desired FSK frequency shift of the trans-
mitter output frequency.
12 FSKGND Ground connection for FSK modulation out-
put FSKOUT.
8
300
Ω
V
S
+ 1 .2 V
60 k
Ω
9
5
µ
A
60 k
Ω
+ 0 .8 V
V
S
V
S
6 k
10
100
A
V
S
V
S
V
S
200 µA
1.5 k
11
12
V
S
Functional Description
3 - 6
TDA 5100
Wireless Components
Specific atio n, June 2001
13 PAGND Ground connection of the power amplifier.
The RF ground return path of the power
amplifier output PAOUT (pin 14) has to be
concentrated to this pin.
14 PAOUT RF output pin of the transmitter.
A DC path to the positive supply VS has to
be supplied by the antenna matching net-
work.
15 FSEL This pin is used to select the desired trans-
mitter frequency.
A logic low (FSEL < 0.5 V) applied to this pin
sets the transmitter to the 433 MHz fre-
quency ra nge .
A logic high (FSEL open) applied to this pin
sets the transmitter to the 868 MHz fre-
quency ra nge .
16 CSEL This pin is used to select the desired refer-
ence freque nc y.
A logic low (CSEL < 0.2 V) applied to this pin
sets the internal frequency divider to accept
a reference frequency of 6.78 MHz.
A logic high (CSEL open) applied to this pin
sets th e inte rnal fr equ ency divi der to ac cep t
a reference frequency of 13.56 MHz.
14
13
+1.2 V
90 k
Ω
15
30
A
30 k
Ω
+ 1 .1 V
V
S
+ 1 .2 V
60 k
Ω
16
5
µ
A
60 k
Ω
+ 0 .8 V
V
S
V
S
Functional Description
3 - 7
TDA 5100
Wireless Components
Specific atio n, June 2001
XTAL
Osc
:2/8
:4/16
PFD :128/64 VCO :1/2 Power
AMP
LF
Low V oltage
Sensor 2.2V
Power
Supply
713 2
14
13
154168
9
10
11
12
FSK
Ground
FSK
Data
Input
Power
Down
Control
Positive
Supply
V
S
Low Power
D e te c t Ou tp u t
Power
Amplifier
Output
Power
Amplifier
Ground
On
Frequency
Select
434/86 8 M Hz
Loop
Filter
Crystal
Select
6.78/13.5 6 M Hz
Clock
Output
Crystal
6.7 8/13.56 M H z
Clock O utput
Frequency
Select
0.85/3.39 M Hz
OR
6
ASK
Data
Input
5
Ground
FSK
Switch
3.3 Functional Block diagram
Block_diagram.wmf
Figure 3-2 Functional Block diagram
Functional Description
3 - 8
TDA 5100
Wireless Components
Specific atio n, June 2001
3.4 Functional Blocks
3.4.1 PLL Synthesizer
The Phase Locked Loop synthesizer consists of a Voltage Controlled Oscillator
(VCO), an asynchronous divider chain, a phase detector, a charge pump and a
loop filter. It is fully implemented on chip. The tuning circuit of the VCO consist-
ing of spiral inductors and varactor diodes is on chip, too. Therefore no addi-
tional external components are necessary. The nominal center frequency of the
VCO is 869 MHz. The oscillator signal is fed both, to the synthesizer divider
chain and to the power amplifier. The overall division ratio of the asynchronous
divider chain is 128 in case of a 6.78 MHz crystal or 64 in case of a 13.56 MHz
crystal and can be selected via CSEL (pin 16). The phase detector is a Type IV
PD with charge pump. The passive loop filter is realized on chip.
3.4.2 Crystal Oscillator
The crystal oscillator operates either at 6.78 MHz or at 13.56 MHz.
The reference frequency can be chosen by the signal at CSEL (pin 16).
For both quartz frequency options, 847.5 kHz or 3.39 MHz are available as out-
put frequencies of the clock output CLKOUT (pin 8) to drive the clock input of a
micro controller.
The frequency at CLKOUT (pin 8) is controlled by the signal at CLKDIV (pin 9)
Table 3-3 CSEL (pin 16) Crystal Frequency
Low1)
1) Low: Voltage at pin < 0.2 V
6.78 MHz
Open2)
2) Op en: Pin open
13.56 MHz
Table 3-4 CLKDIV (pin 9) CLKOUT Frequency
Low1)
1) Low: Voltage at pin < 0.2 V
3.39 MHz
Open2)
2) Op en: Pin open
847.5 kHz
Functional Description
3 - 9
TDA 5100
Wireless Components
Specific atio n, June 2001
To achieve FSK transmission, the oscillator frequency can be detuned by a
fixed amount by switching an external capacitor via FSKOUT (pin 11).
The condition of the switch is controlled by the signal at FSKDTA (pin 7).
3.4.3 Power Amplifier
In case of operation in the 868-870 MHz band, the power amplifier is fed directly
from the voltage controlled oscillator. In case of operation in the 433-435 MHz
band, the VCO frequency is divided by 2. This is controlled by FSEL (pin 15) as
described in the table below.
The Power Amplifier can be switched on and off
by the signal at ASKDTA (pin 6).
The Power Amplifier has an Open Collector output at PAOUT (pin 14) and
requires an external pull-up coil to provide bias. The coil is part of the tuning and
matching LC circuitry to get best performance with the external loop antenna.
To achieve the best power amplifier efficiency, the high frequency voltage swing
at PAOUT (pin 14) should be twice the supply voltage.
The power amplifier has its own ground pin PAGND (pin 13) in order to reduce
the amount of coupling to the other circuits.
Table 3-5 FSKDTA (pin7) FSK Switch
Low1)
1) Low: Voltage at pin < 0.5 V
CLOSED
Open2), High3)
2) Op en: Pin open
3) High: Voltage at pin > 1.5 V
OPEN
Table 3-6 FSEL (pin 15) Radiated Frequency Band
Low1)
1) Low: Voltage at pin < 0.5 V
433 MHz
Open2)
2) Op en: Pin open
868 MHz
Table 3-7 ASKDTA (pin 6) Power Amplifier
Low1)
1) Low: Voltage at pin < 0.5 V
OFF
Open2), High3)
2) Op en: Pin open
3) High: Voltage at pin > 1.5 V
ON
Functional Description
3 - 10
TDA 5100
Wireless Components
Specific atio n, June 2001
3.4.4 Low Power Detect
The supply voltage is sensed by a low power detector. When the supply voltage
drops below 2.15 V, the output LPD (pin 2) switches to the low-state. To mini-
mize the external component count, an internal pull-up current of 40 µA gives
the output a high-state at supply voltages above 2.15 V.
The output LPD (pin 2) can either be connected to ASKDTA (pin 6) to switch off
the PA as soon as the supply voltage drops below 2.15 V or it can be used to
inform a micro-controller to stop the transmission after the current data packet.
3.4.5 Power Modes
The IC provides three power modes, the POWER DOWN MODE, the PLL
ENABLE MODE and the TRANSMIT MODE.
3.4.5.1 Power Down Mode
In the POWER DOWN MODE the complete chip is switched off.
The current consumption is less than 100nA.
3.4.5.2 PLL Enable Mode
In the PLL ENABLE MODE the PLL is switched on but the power amplifier is
turned off to avoid undesired power radiation during the time the PLL needs to
settle. The turn on time of the PLL is determined mainly by the turn on time of
the crystal oscillator and is less than 1 msec when the specified crystal is used.
The current consumption is typically 3.5 mA.
3.4.5.3 Transmit Mode
In the TRANSMIT MODE the PLL is switched on and the power amplifier is
turned on too.
The current consumption of the IC is typically 7 mA when using a proper trans-
forming network at PAOUT, see Figure 4-1.
3.4.5.4 Power mode control
The bias circuitry is powered up via a voltage V > 1.5 V at the pin PDWN (pin 1).
When the bias circuitry is powered up, the pins ASKDTA and FSKDTA are
pulled up inte rn all y.
Forcing the voltage at the pins low overrides the internally set state.
Alternatively, if the voltage at ASKDTA or FSKDTA is forced high externally, the
PDWN pin is pulled up internally via a current source. In this case, it is not nec-
essary to connect the PDWN pin, it is recommended to leave it open.
Functional Description
3 - 11
TDA 5100
Wireless Components
Specific atio n, June 2001
The principle schematic of the power mode control circuitry is shown in
Figure 3-5.
Power_Mode.wmf
Figure 3-5 Power mode control circuitry
Table 3-8 provides a listing of how to get into the different power modes
Other combinations of the control pins PDWN, FSKDTA and ASKDTA are not
recommended.
Table 3-8
PDWN FSKDTA ASKDTA MODE
Low1)
1) Low: Voltage at pin < 0.7 V (PDWN)
Voltage at pin < 0.5 V (FSKDTA, ASKDTA)
Low, Open Low, Open POWER DO WN
Open2)
2) Op en: Pin open
Low Low
High3)
3) High: Voltage at pin > 1.5 V
Low, Open, High Low PLL ENABLE
Open High Low
High Low, Open, High Open, High
TRANSMITOpen High Open, High
Open Low, Open, Hig h Hi gh
OR
Bias
Source
FSKDTA
ASKDTA
PDWN
FSKOUT
PAOUT
TD A 5100
On
Bias Voltage
PA
On
120 k
PLL
FSK
120 k
868
MHz
Functional Description
3 - 12
TDA 5100
Wireless Components
Specific atio n, June 2001
3.4.6 Recommended timing diagrams for ASK- and FSK-Modulation
ASK Modulation using FSKDTA and ASKDTA, PDWN not connected
ASK_mod.wmf
Figure 3-6 ASK Modulation
FSK Modulation using FSKDTA and ASKDTA, PDWN not connected
FSK_mod.wmf
Figure 3-7 FSK Modulation
FSKDTA
High
Low
to
ASKDTA
to
m in. 1 m sec.
t
t
DATA
O pen, H igh
Low
Modes: TransmitPLL E nablePower Down
FSKDTA
High
Low
to
ASKDTA
to
m in. 1 m sec.
t
t
DATA
High
Low
Modes: TransmitPLL E nablePower Down
Functional Description
3 - 13
TDA 5100
Wireless Components
Specific atio n, June 2001
Alternative ASK Modulation, FSKDTA not connected.
Alt_ASK_mod.wmf
Figure 3-8 Alternative ASK Modulation
Alternative FSK Modulation
Alt_FSK_mod.wmf
Figure 3-9 Alternative FSK Modulation
PDWN
High
Low
to
ASKDTA
to
m in. 1 m sec.
t
t
DATA
O pen, H igh
Low
Modes: TransmitPLL E nablePower Down
FSKDTA
to
m in. 1 m sec.
t
DATA
O pen, H igh
Low
Modes: TransmitPLL E nablePower Down
PDWN
High
Low
to t
ASKDTA
O pen, H igh
Low
to t
4Applications
4.1 50 Ohm-Output Testboard Schematic . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2 50 Ohm-Output Testboard Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.3 Bill of material (50 Ohm-Output Testboard) . . . . . . . . . . . . . . . . . . . . 4-4
4.4 Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.5 Application Board Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.6 Application Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
4.7 Bill of material (Application Board) . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
4.8 Application Board Photo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Contents of this Chapter
Applications
4 - 2
TDA 5100
Wireless Components
Specification, June 2001
4.1 50 Ohm-Output Testboard Schematic
50ohm_test_v5.wmf
Figure 4-1 50Ω-outp ut tes tbo ard schem ati c
C6
L1
R1 C5
C3
C2
C8
C4
C1
X1SMA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TDA5100
VCC
L2
C7
Q1
VCC
VCC
R2
R4
R3F
R3A
X2SMA
T1
ASK FSK
0.85 (3.4)
MHz
6.78 (13.56)
MHz
433 (868)
MHz
Applications
4 - 3
TDA 5100
Wireless Components
Specification, June 2001
4.2 50 Ohm-Output Testboard Layout
Figure 4-2 Top Side of TDA 5100-Testboard with 50 Ω-Output
Figure 4-3 Bottom Side of TDA 5100-Testboard with 50 Ω-Output
Applications
4 - 4
TDA 5100
Wireless Components
Specification, June 2001
4.3 Bill of material (50 Ohm-Output Testboard)
Table 4-1 Bill of material
Part Value 434 MHz 869 MHz ASK FSK Specification
R1 4.7 kΩ0805, ± 5%
R2 12 kΩ0805, ± 5%
R3A 15 kΩ0805, ± 5%
R3F 15 kΩ0805, ± 5%
R4 open 0805, ± 5%
C1 47 nF 0805, X7R, ± 10%
C2 39 pF 47 pF 0805, COG, ± 5%
C3 3.9 pF 1.8 pF 0805, COG, ± 0.1 pF
C4 330 pF 100 pF 0805, COG, ± 5%
C5 1 nF 0805, X7R, ± 10%
C6 8.2 pF 0805, COG, ± 0.1 pF
C7 0Ω
Jumper 434MHz: 22 pF
868MHz: 47pF 0805, COG, ± 5%
0805, 0Ω Jumper
C8 15 pF 8.2 pF 0805, COG, ± 5%
L1 100 nH 33 nH TOKO LL2012 -J
L2 39 nH 15 nH 39 nH: TOKO LL2012-J
15 nH: TOKO LL1608-J
Q3 13.56875 MHz,
CL=20pF Tokyo Denpa TSS-3B
13568.75 kHz
Spec.No. 20-18906
IC1 TDA5100
T1 Taster replaced by a short
X1 SMA-S SMA standing
X2 SMA-S SMA standing
Applications
4 - 5
TDA 5100
Wireless Components
Specification, June 2001
4.4 Hints
1. Application Hints on the crystal oscillator
As mentioned before, the crystal oscillator achieves a turn on time less than
1 msec . To achi eve thi s, a NIC os cill ator ty pe is imp lemen ted in th e TDA 510 0.
The input impedance of this oscillator is a negative resistance in series to an
inductance. Therefore the load capacitance of the crystal CL (specified by the
crystal supplier) is transformed to the capacitance Cv.
CL: crystal load capacitance for nominal frequency
ω: angular frequency
L: inductivity of the crystal oscillator
Example for the ASK-Mode:
Referring to the application circuit, in ASK-Mode the capacitance C7 is replaced
by a short to ground. Assume a crystal frequency of 13.56 MHz and a crystal
load capacitance of CL = 20 pF. The inductance L is specified within the elec-
trical characteristics at 13.5 MHz to a value of 11 uH. Therefore C6 is calculated
to 7.7 pF.
TD A 5100
-R L f, CL Cv
L
CL
Cv 2
11
ω
+
=
6
11
2C
L
CL
Cv =
+
=
ω
Formula 1)
Applications
4 - 6
TDA 5100
Wireless Components
Specification, June 2001
Example for the FSK-Mode:
FSK modulation is achieved by switching the load capacitance of the crystal as
shown below.
The frequency deviation of the crystal oscillator is multiplied with the divider
factor N of the Phase Locked Loop to the output of the power amplifier. In case
of small frequency deviations (up to +/- 1000 ppm), the two desired load
capacitances can be calculated with the formula below.
CL: crystal load capacitance for nominal frequency
C0: shunt capacitance of the crystal
f: frequency
ω: ω = 2πf: angular frequency
N: divi si on ratio of the PLL
df: peak frequency deviation
Because of the inductive part of the TD A 5100, these values must be corrected
by Formula 1). The value of Cv± can be calculated.
TD A 5100
-R L f, CL Cv1 Cv2
COSC
FSKOUT
FSKDTA
Csw
)
1)0(2
1(
1*
1
)
1)0(2
1(
1*
0
CCLC
fN fCCLC
fN f
CCL
CL +
+
∆
±
+
+
∆
=±
m
L
CL
Cv 2
11
ω
+
±
=±
Applications
4 - 7
TDA 5100
Wireless Components
Specification, June 2001
If the FSK switch is closed, Cv_ is equal to Cv1 (C6 in the application diagram).
If the FSK switch is open, Cv2 (C7 in the application diagram) can be calculated.
Csw: parallel capacitance of the FSK switch (3 pF)
Remark: These calculations are only approximations. The necessary values
depend on the layout also and must be adapted for the specific
application board.
2. Design hints on the buffered clock output (CLKOUT)
The CLKOUT pin is an open collector output. An external pull up resistor (RL)
should be connected between this pin and the positive supply voltage. The
value of RL is depending on the clock frequency and the load capacitance CLD
(PCB board plus input capacitance of the microcontroller). RL can be calculated
to:
Remark: To achieve a low current consumption and a low
spurious radiation, the largest possible RL should be chosen.
Table 4-2 fCLKOUT=
847 kHz fCLKOUT=
3.39 MHz
CL[pF]RL[kOhm]CL[pF]RL[kOhm]
527 5 6.8
10 12 10 3.3
20 6.8 20 1.8
1)( )1()(1
72 CvCv CswCvCvCvCsw
CCv −+ +∗+−∗
==
CLDfCLKOUT
RL *8*
1
=
Applications
4 - 8
TDA 5100
Wireless Components
Specification, June 2001
4.5 Application Board Schematic
Application_circuit.wmf
Figure 4 -4 App lication board schemat ic
C6
C2
L1
C3
C1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TDA5100
VCC
L2 C7
Q3
VCC
VCC
R2
R4
R3F
R3A
T1
0.85 (3.4)
MHz
1
2
3
4
8
7
6
5
HCS360
VCC
C4
Antenna
6.78 (13.56)
MHz
433 (868)
MHz
R1 C5
ASK FSK
Applications
4 - 9
TDA 5100
Wireless Components
Specification, June 2001
4.6 Appli cation Board Layout
Figure 4-5 Top Side of TDA 5100-Application Board
Figure 4-6 Bottom Side of TDA 5100-Application Board
Applications
4 - 10
TDA 5100
Wireless Components
Specification, June 2001
4.7 Bill of material (Application Board)
Table 4-3 Bill of material
Part Value 434 MHz 869 MHz ASK FSK Specification
R1 4.7 kΩ0805, ± 5%
R2 12 kΩ0805, ± 5%
R3A 15 kΩ0805, ± 5%
R3F 15 kΩ0805, ± 5%
R4 15 kΩ0805, ± 5%
C1 47 nF 0805, X7R, ± 10%
C2 8.2 pF 1.5 pF 0805, COG, ± 5%
C3 4.7 pF 1.0 pF 0805, COG, ± 0.1 pF
C4 100 pF 0805, COG, ± 5%
C5 4.7 nF 0805, X7R, ± 10%
C6 8.2 pF 0805, COG, ± 0.1 pF
C7 0Ω 434MHz: 22 pF
868MH z: 47pF 0805, COG, ± 5%
0805, 0Ω Jumper
L1 100 nH 27 nH TOKO LL2012-J
L2 0Ω22 nH 0Ω resistor bridge
22 nH: TOKO LL1608 -J
Q3 13.56875 MHz
CL=20pF Tokyo Denpa TSS-3B
13568.75 kH z
Spec.No. 20-1 890 6
IC1 TDA5100
IC2 HCS360 Microchip
B1 Batteriehalter HU2031-1, RENATA
T1 Taster STTSKHMPW, ALPS
Applications
4 - 11
TDA 5100
Wireless Components
Specification, June 2001
4.8 Appli cation Board Photo
V6_photo.wmf
Figure 4-7 Photo of Application Board TDA 5100
The total radiated spectrum measured can be summarized as:
Table 4-4
Frequency ERP at
434 MHz ERP at
869 MHz regulations, limit
ETS 300 220
434/869 MHz
Carrier f C- 9 dBm -4 dBm +10 dBm
fC + 13.5 MHz -75 dBm -51dBm -36 dBm
fC – 13.5 MHz -73 dBm -59 dBm -36/-54 dBm
fC ± 847 kHz -62 dBm - 67 dBm -36 dBm
2nd harmonic -51dBm -56 dBm -36/-30 dBm
3rd harmonic -42 dBm -72 dBm -30 dBm
5Reference
5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Contents of this Chapter
Reference
5 - 2
TDA 5100
Wireless Components
Specific atio n, June 2001
5.1 Absolute Maximum Ratings
The AC / DC characteristic limits are not guaranteed. The maximum ratings
must not be exceeded under any circumstances, not even momentarily and
individually, as permanent damage to the IC may result.
Ambient Temperature under bias: TA=-25 to +85°C
5.2 Operating Range
Within the operational range the IC operates as described in the circuit
description.
Table 5-1
Parameter Symbol Limit Values Unit Remarks
Min Max
Junction Temperature TJ-40 150 °C
Storage Temper ature Ts-40 125 °C
Thermal Resistance RthJA 230 K/W
ESD integrity, all pins VESD -1 +1 kV 100 pF, 1500 Ω
Table 5-2
Parameter Symbol Limit Values Unit Test Conditions
Min Max
Supply voltage VS2.1 4.0 V
Ambient temperature TA-25 85 °C
Reference
5 - 3
TDA 5100
Wireless Components
Specific atio n, June 2001
5.3 AC/DC Characteristics
5.3. 1 AC/D C Cha rac te ristics at 3V, 25°C
Table 5-3 Supply Voltage VS = 3 V, Ambient temperature Tamb = 25°C
Parameter Symbol Limit Values Unit Test Conditions
Min Typ Max
Current consumption
Stand-by mode IS PDWN 100 nA V (Pins 1, 6 and 7)
< 0.2 V
PLL enable mode IS PLL_EN 3.3 4.2 mA
Transmit mo de 4 34 MHz IS TRANSM 78.5mA Load tank see
Figure 4-1 and 4-2
Transmit mo de 8 68 MHz 78.7mA
Power Down Mode Control (Pin 1)
Stand-by mode V PDWN 00.7 VV
ASKDTA < 0.2 V
VFSKDTA < 0.2 V
PLL enable mode V PDWN 1.5 VSVV
ASKDTA < 0.5 V
Transmit mo de V PDWN 1.5 VSVV
ASKDTA > 1.5 V
Input bias current PDWN IPDWN 30 µA VPDWN = VS
Low Power Detect Output (Pin 2)
Internal pull up current I LPD1 30 µA VS = 2.3 V ... VS
Input current low voltage I LPD2 1.2 mA VS = 1.9 V ... 2.1 V
Loop Filter (Pin 4)
VCO tuning voltag e VLF VS - 1.5 VS - 0.7 Vf
VCO = 869 MHz
Output frequency range
868 MHz-band fOUT, 868 854 869 884 MHz VS-VLF = 0.5V...1.8V
VFSEL = VS
Output frequency range
433 MHz-band fOUT, 433 427 434.5 442 MHz VS-VLF = 0.5V...1.8V
VFSEL = 0 V
ASK Modulation Data Input (Pin 6)
ASK Transmit disabled VASKDTA 00.5 V
ASK Transmit enabled VASKDTA 1.5 VSV
Input bias current ASKDTA IASKDTA 30 µA VASKDTA = VS
Input bias current ASKDTA IASKDTA -20 µA VASKDTA = 0 V
ASK data rate fASKDTA 20 kHz
Reference
5 - 4
TDA 5100
Wireless Components
Specific atio n, June 2001
Table 5-3 Supply Voltage VS = 3 V, Ambient temperature Tamb = 25°C
Parameter Symbol Limit Values Unit Test Conditi ons
Min Typ Max
FSK Modulation Data Input (Pin 7)
FSK Switch on VFSKDTA 00.5 V
FSK Switch off VFSKDTA 1.5 VSV
Input bi as current FSKDTA IFSKDTA 30 µA VFSKDTA = VS
Input bi as current FSKDTA IFSKDTA -20 µA VFSKDTA = 0 V
FSK data rate fFSKDTA 20 kHz
Clock Driver Output (Pin 8)
Output curre nt (Low) ICLKOUT 1.25 mA VCLKOUT = VS
Output current (High) ICLKOUT 5µA VCLKOUT = VS
Saturation Voltage (Low) VSATL 0.56 VI
CLKOUT = 1 mA
Clock Divider Control (Pin 9)
Setting Clock D riv er outpu t
frequency fCLKOUT=3.39 MHz VCLKDIV 00.2 V
Setting Clock D riv er outpu t
frequency fCLKOUT=847.5kHz VCLKDIV V pin open
Input bias current CLKDIV ICLKDIV 30 µA VCLKDIV = VS
Input bias current CLKDIV ICLKDIV -20 µA VCLKDIV = 0 V
Crystal Oscillator Input (Pin 10)
Load capacitance CCOSCmax 5pF
Serial Resistance of the crys-
tal 100 Ωf = 6.78 MHz
Input inductance of the
COSC pin 12 µH f = 6.78 MHz
Serial Resistance of the crys-
tal 100 Ωf = 13.56 MHz
Input inductance of the
COSC pin 11 µH f = 13.56 MHz
FSK Switch Output (Pin 11)
On resista nce RFSKOUT 220 ΩVFSKDTA = 0 V
On capacitance CFSKOUT 6pF VFSKDTA = 0 V
Off resistance RFSKOUT 10 kΩVFSKDTA = VS
Off capacitance CFSKOUT 1.5 pF VFSKDTA = V S
Reference
5 - 5
TDA 5100
Wireless Components
Specific atio n, June 2001
Table 5-3 Supply Voltage VS = 3 V, Ambient temperature Tamb = 25°C
Parameter Symbol Limit Values Unit Test Conditi ons
Min Typ Max
Power Amplifier Output (Pin 14)
Output Power1)
transformed to 50 Ohm POUT433 456dBm fOUT = 43 3 MHz
VFSEL = 0 V
POUT868 024dBm fOUT = 868 MHz
VFSEL = VS
Frequency Range Selection (Pin 15)
Transmit frequency 433 MHz VFSEL 00.5 V
Transmit frequency 868 MHz VFSEL V pin ope n
Input bias current FSEL IFSEL 30 µA VFSEL = VS
Input bias current FSEL IFSEL -20 µA VFSEL = 0 V
Crystal Frequency Selection (Pin 16)
Crystal frequency 6.78 MHz VCSEL 00.2 V
Crystal frequency 13.56 MHz VCSEL V pin ope n
Input bias current CSEL ICSEL 50 µA VCSEL = VS
Input bias current CSEL ICSEL -25 µA VCSEL = 0 V
1) Power amplifier in overcritical C-operation
Matching circuitry as used in the 50 Ohm-Output Testboard at the specified frequency.
Reference
5 - 6
TDA 5100
Wireless Components
Specific atio n, June 2001
5.3.2 AC/DC Characteristics at 2.1 V ... 4.0 V, -25°C ... +85°C
Table 5-4 Supply Voltage VS = 2.1 V ... 4.0 V, Ambient temperature Tamb = -25°C ... +85°C
Parameter Symbol Limit Values Unit Test Conditions
Min Typ Max
Current consumption
Stand-by mode IS PDWN 250 nA V (Pins 1, 6 and 7)
< 0.2 V
PLL enable mode IS PLL_EN 3.3 4.5 mA
Transmit mode Vs = 2.1 V IS TRANSM
8.2 mA Load tank see
Figure 4-1 and 4-2
Transmit mode Vs = 3.0 V 78.7mA
Transmit mode Vs = 4.0 V 9.2 mA
Power Down Mode Control (Pin 1)
Stand-by mode V PDWN 00.5 VV
ASKDTA < 0.2 V
VFSKDTA < 0.2 V
PLL enable mode V PDWN 1.5 VSVV
ASKDTA < 0.5 V
Transmit mo de V PDWN 1.5 VSVV
ASKDTA > 1.5 V
Input bias current PDWN IPDWN 30 µA VPDWN = VS
Low Power Detect Output (Pin 2)
Internal pull up current I LPD1 30 µA VS = 2.3 V ... VS
Input current low voltage I LPD2 0.9 mA VS = 1.9 V ... 2.1 V
Loop Filter (Pin 4)
VCO tuning voltag e VLF VS - 1.8 VS - 0.5 Vf
VCO = 869 MHz
Output frequency range
868 MHz-band fOUT, 868 865 869 874 MHz VS-VLF = 0.43 V...1 .9V
VFSEL = VS
Output frequency range
433 MHz-band fOUT, 433 432.5 434.5 437 MHz VS-VLF = 0.43V...1.9V
VFSEL = 0 V
ASK Modulation Data Input (Pin 6)
ASK Transmit disabled VASKDTA 00.5 V
ASK Transmit enabled VASKDTA 1.5 VSV
Input bias current ASKDTA IASKDTA 30 µA VASKDTA = VS
Input bias current ASKDTA IASKDTA -20 µA VASKDTA = 0 V
ASK data rate fASKDTA 20 kHz
Reference
5 - 7
TDA 5100
Wireless Components
Specific atio n, June 2001
Table 5-4 Supply Voltage VS = 2.1 V ... 4.0 V, Ambient temperature Tamb = -25°C ... +85°C
Parameter Symbol Limit Values Unit Test Conditions
Min Typ Max
FSK Modulation Data Input (Pin 7)
FSK Switch on VFSKDTA 00.5 V
FSK Switch off VFSKDTA 1.5 VSV
Input bi as current FSKDTA IFSKDTA 30 µA VFSKDTA = VS
Input bi as current FSKDTA IFSKDTA -20 µA VFSKDTA = 0 V
FSK data rate fFSKDTA 20 kHz
Clock Driver Output (Pin 8)
Output curre nt (Low) ICLKOUT 1mA VCLKOUT = VS
Output current (High) ICLKOUT 5µA VCLKOUT = VS
Saturation Voltage (Low)1) VSATL 0.5 VI
CLKOUT = 0.8 mA
Clock Divider Control (Pin 9)
Setting Clock D riv er outpu t
frequency fCLKOUT=3.39 MHz VCLKDIV 00.2 V
Setting Clock D riv er outpu t
frequency fCLKOUT=847.5kHz VCLKDIV V pin open
Input bias current CLKDIV ICLKDIV 30 µA VCLKDIV = VS
Input bias current CLKDIV ICLKDIV -20 µA VCLKDIV = 0 V
Crystal Oscillator Input (Pin 10)
Load capacitance CCOSCmax 5pF
Serial Resistance of the crys-
tal 100 Ωf = 6.78 MHz
Input inductance of the
COSC pin 12 µH f = 6.78 MHz
Serial Resistance of the crys-
tal 100 Ωf = 13.56 MHz
Input inductance of the
COSC pin 11 µH f = 13.56 MHz
FSK Switch Output (Pin 11)
On resista nce RFSKOUT 220 ΩVFSKDTA = 0 V
On capacitance CFSKOUT 6pF VFSKDTA = 0 V
Off resistance RFSKOUT 10 kΩVFSKDTA = VS
Off capacitance CFSKOUT 1.5 pF VFSKDTA = VS
Reference
5 - 8
TDA 5100
Wireless Components
Specific atio n, June 2001
Table 5-4 Supply Voltage VS = 2.1 V ... 4.0 V, Ambient temperature Tamb = -25°C ... +85°C
Parameter Symbol Limit Values Unit Test Conditions
Min Typ Max
Power Amplifier Output (Pin 14)
Output Power 2) at 434 MHz
transformed to 50 Ohm.
VFSEL = 0 V
POUT, 434 0.7 2.2 3.2 dBm VS = 2.1 V
POUT, 434 356.4dBm VS = 3.0 V
POUT, 434 3.3 6.8 9.4 dBm VS = 4.0 V
Output Power 3) at 868 MHz
transformed to 50 Ohm.
VFSEL = VS
POUT, 868 -2.3 0.2 1.8 dBm VS = 2.1 V
POUT, 868 -2.0 24.9dBm VS = 3.0 V
POUT, 868 -1.7 3.2 7.2 dBm VS = 4.0 V
Frequency Range Selection (Pin 15)
Transmit frequency 434 MHz VFSEL 00.5 V
Transmit frequency 868 MHz VFSEL V pin open
Input bias current FSEL IFSEL 30 µA VFSEL = VS
Input bias current FSEL IFSEL -20 µA VFSEL = 0 V
Crystal Frequency Selection (Pin 16)
Crystal frequency 6.78 MHz VCSEL 00.2 V
Crystal frequency 13.56 MHz VCSEL V pin open
Input bias current CSEL ICSEL 50 µA VCSEL = VS
Input bias current CSEL ICSEL -25 µA VCSEL = 0 V
1) Derating linearly to a saturation voltage of max. 140 mV at ICLKOUT = 0 mA
2) Matching circuitry as used in the 50 Ohm-Output Testboard for 434 MHz operation.
Range @ 2.1 V, +25°C: 2.2 dBm +/- 0.7 dBm
Temperature dependency at 2.1 V: +0.3 dBm@-25°C and -0.8 dBm@+85°C, reference +25°C.
Range @ 3.0 V, +25°C: 5.0 dBm +/- 1.0 dBm
Temperature dependency at 3.0 V: +0.4 dBm@-25°c and -1.0 dBm@+85°C, reference +25°C.
Range @ 4.0 V, +25°C: 6.8 dBm +/- 2.0 dBm
Temperature dependency at 4.0 V: +0.6 dBm@-25°c and -1.5 dBm@+85°C, reference +25°C.
3) Matching circuitry as used in the 50 Ohm-Output Testboard for 868 MHz operation.
Range @ 2.1 V, +25°C: 0.2 dBm +/- 1.0 dBm
Temperature dependency at 2.1 V: +0.6 dBm@-25°C and -1.5 dBm@+85°C, reference +25°C.
Range @ 3.0 V, +25°C: 2.0 dBm +/- 2.0 dBm
Temperature dependency at 3.0 V: +0.9 dBm@-25°c and -2.0 dBm@+85°C, reference +25°C.
Range @ 4.0 V, +25°C: 3.2 dBm +/- 2.7 dBm
Temperature dependency at 4.0 V: +1.3 dBm@-25°c and -2.2 dBm@+85°C, reference +25°C.
A smaller load impedance reduces the supply-voltage dependency.
A higher load impedance reduces the temperature dependency.
