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FEATURES DESCRIPTION
APPLICATIONS
VOUT2
SW1
FB1
SW2
ADJ2
DEF_1
OUT2
CIN
10 μF
VIN2.5V –6V VIN
EN_1
EN_2
MODE/
DATA
TPS62410
GND
Upto800mA
R21
360kΩ
R22
180kΩ
=1.8V
L2
2.2 μH
C =22 µF
Cff2
33pF
upto800mA
R11
270kΩ
R12
180kΩ
VOUT1 =1.5V
L1
2.2 μH
COUT1 =22 µF
V =5V
IN
V =3.6V
IN
PowerSaveMode
MODE/DATA =0
ForcedPWMMode
MODE/DATA =1
0
10
20
30
40
50
60
70
80
90
100
Efficiency-%
0.01 0.1 1 10 100 1000
I -mA
OUT
V =3.3V
OUT
V =3.6V
IN
V =5V
IN
TPS62410
SLVS737 – FEBRUARY 2007
2.25MHz 2x800mA Dual Step Down Converter In Small 3x3mm QFN Package
•High Efficiency—up to 95%
The TPS62410 device is a synchronous dualstep-down DC-DC converter optimized for battery•V
IN
Range From 2.5 V to 6 V
powered portable applications. It provides two•2.25 MHz Fixed Frequency Operation
independent output voltage rails powered by 1-cell•Output Current 2 x 800mA
Li-Ion or 3-cell NiMH/NiCD batteries. The device is•Adjustable Output Voltage From 0.6 V to V
IN
also suitable to operate from a standard 3.3V or 5Vvoltage rail.•EasyScale™ Optional One Pin Serial Interfacefor Dynamic Output Voltage Adjustment
With an input voltage range of 2.5V to 6V, theTPS62410 is ideal to power portable applications like•Power Save Mode at Light Load Currents
smart phones, PDAs, and other portable equipment.•180 °Out of Phase Operation
With the EasyScale™ serial interface the output•Output Voltage Accuracy in PWM Mode ±1%
voltages can be modified during operation. It•Typical 32 µA Quiescent Current for both
therefore supports Dynamic Voltage Scaling for lowConverters
power DSP and processors.•100% Duty Cycle for Lowest Dropout
The TPS62410 operates at 2.25MHz fixed switching•Available in a 10-Pin QFN (3 ×3mm)
frequency and enter the Power Save Mode operationat light load currents to maintain high efficiency overthe entire load current range. For low noiseapplications the devices can be forced into fixed•Cell Phones, Smart-phones
frequency PWM mode by pulling the MODE/DATA•PDAs, Pocket PCs
pin high. In the shutdown mode, the current•OMAP™ and Low Power DSP Supply
consumption is reduced to 1.2 µA. The device allows•Portable Media Players
the use of small inductors and capacitors to achieve•Digital Radio
a small solution size.•Digital Cameras
The TPS62410 is available in a 10-pin leadlesspackage (3 ×3mm QFN)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.EasyScale, OMAP, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATINGS
RECOMMENDED OPERATING CONDITIONS
TPS62410
SLVS737 – FEBRUARY 2007
ORDERING INFORMATION
(1)
T
A
PART DEFAULT OUTPUT OUTPUT QFN (1) ORDERING PACKAGENUMBER VOLTAGE (2) CURRENT PACKAGE MARKING(1)
OUT1 800mA–40 °C to 85 °C TPS62410 Adjustable DRC TPS62410DRC CATOUT2 800mA
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIWeb site at www.ti.com .
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE UNIT
Input voltage range on V
IN
(2)
–0.3 to 7 VVoltage range on EN, MODE/DATA, DEF_1 –0.3 to V
IN
+0.3, ≤7 VMaximum Current into MODE/DATA 500 µAVoltage on SW1, SW2 –0.3 to 7 VVoltage on ADJ2, FB1 –0.3 to V
IN
+0.3, ≤7 VESD rating
(3)
HBM Human body nodel 2 kVCharge device model 1 kVMachine model 200 VT
J(max)
Maximum junction temperature 150 °CT
A
Operating ambient temperature range –40 to 85 °CT
stg
Storage temperature range –65 to 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.(2) All voltage values are with respect to network ground terminal.(3) The human body model is a 100pF capacitor discharged through a 1.5k Ωresistor into each pin. The machine model is a 200pFcapacitor discharged directly into each pin.
PACKAGE R
θJA
POWER RATING FOR T
A
≤25 °C DERATING FACTOR ABOVE T
A
= 25 °C
DRC 49 °C/W 2050mW 21mW/ °C
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Supply voltage 2.5 6 VOutput voltage range for adjustable voltage 0.6 VIN VT
A
Operating ambient temperature -40 85 °CT
J
Operating junction temperature -40 125 °C
2
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ELECTRICAL CHARACTERISTICS
TPS62410
SLVS737 – FEBRUARY 2007
V
IN
= 3.6V, V
OUT
= 1.8V, EN = V
IN
, MODE = GND, L = 2.2 µH, C
OUT
= 20 µF, T
A
= –40 °C to 85 °C typical values are at T
A
=25 °C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
V
IN
Input voltage range 2.5 6.0 VOne converter, I
OUT
= 0mA. PFM mode enabled 19 29 µA(Mode = 0) device not switching,EN1 = 1 OR EN2 = 1Two converter, I
OUT
= 0mA. PFM mode enabled 32 48 µA(Mode = 0) device not switching,I
Q
Operating quiescent current
EN1 = 1 AND EN2 = 1I
OUT
= 0mA, MODE/DATA = GND, for one 23 µAconverter, V
OUT
1.575V
(1)
I
OUT
= 0mA, MODE/DATA = V
IN
, for one 3.6 mAconverter, V
OUT
1.575V
(1)
EN1, EN2 = GND, V
IN
= 3.6V
(2)
1.2 3I
SD
Shutdown current µAEN1, EN2 = GND, V
IN
ramped from 0V to 3.6V
(3)
0.1 1Falling 1.5 2.35V
UVLO
Undervoltage lockout threshold VRising 2.4
ENABLE EN1, EN2
V
IH
High-level input voltage, EN1, EN2 1.2 V
IN
VV
IL
Low-level input voltage, EN1, EN2 0 0.4 VI
IN
Input bias current, EN1, EN2 EN1, EN2 = GND or VIN 0.05 1.0 µA
DEF_1 INPUT
I
IN
Input biasd current DEF_1 DEF_1 = GND or VIN 0.01 1.0 µA
MODE/DATA
V
IH
High-level input voltage, 1.2 V
IN
VMODE/DATAV
IL
Low-level input voltage, 0 0.4 VMODE/DATAI
IN
Input bias current, MODE/DATA MODE/DATA = GND or VIN 0.01 1.0 µAV
OH
Acknowledge output voltage high Open drain, via external pullup resistor V
IN
VV
OL
Acknowledge output voltage low Open drain, sink current 500 µA 0 0.4 V
INTERFACE TIMING
t
Start
Start time 2 µst
H_LB
High time low bit, logic 0 detection Signal level on MODE/DATA pin is > 1.2V 2 200 µst
L_LB
Low time low bit, logic 0 detection Signal level on MODE/DATA pin < 0.4V 2x 400 µst
H_LB
t
L_HB
Low time high bit, logic 1 detection Signal level on MODE/DATA pin < 0.4V 2 200 µst
H_LB
High time high bit, logic 1 detection Signal level on MODE/DATA pin is > 1.2V 2x 400 µst
L_HS
T
EOS
End of Stream T
EOS
2µst
ACKN
Duration of acknowledge condition V
IN
2.5V to 6V 400 520 µs(MODE/DATE line pulled low by thedevice)t
valACK
Acknowledge valid time 2 µst
timeout
Timeout for entering power save MODE/DATA Pin changes from high to low 520 µsmode
(1) Device is switching with no load on the output, L = 3.3 µH, value includes losses of the coil(2) These values are valid after the device has been already enabled one time (EN1 or EN2 = high) and supply voltage V
IN
has notpowered down.(3) These values are valid when the device is disabled (EN1 and EN2 low) and supply voltage V
IN
is powered up. The values remain validuntil the device has been enabled first time (EN1 or EN2 = high). After first enable, Note 3 becomes valid.
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TPS62410
SLVS737 – FEBRUARY 2007
ELECTRICAL CHARACTERISTICS (continued)V
IN
= 3.6V, V
OUT
= 1.8V, EN = V
IN
, MODE = GND, L = 2.2 µH, C
OUT
= 20 µF, T
A
= –40 °C to 85 °C typical values are at T
A
=25 °C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SWITCH
R
DS(ON)
P-Channel MOSFET On-resistance, V
IN
= V
GS
= 3.6V 280 620 m ΩConverter 1,2I
LK_PMOS
P-Channel leakage current V
DS
= 6.0V 1 µAR
DS(ON)
N-Channel MOSFET On-resistance V
IN
= V
GS
= 3.6V 200 450 m ΩConverter 1,2I
LK_SW1/SW2
Leakage Current into SW1/SW2 Pin Includes N-Chanel leakage currnet, 6 7.5 µAV
IN
= open, V
SW
= 6.0V, EN = GND
(4)
I
LIMF
Forward Current OUT 1/2 800mA 2.5V ≤V
IN
≤6.0V 1.0 1.2 1.38 ALimit PMOS andNMOST
SD
Thermal shutdown Increasing junction temperature 150 °CThermal shudown hysteresis Decreasing junction temperature 20 °C
OSCILLATOR
fSW Oscillator frequency 2.5V ≤VIN ≤6.0V 2.0 2.25 2.5 MHz
OUTPUT
V
OUT
Adjustable output votage range 0.6 V
IN
VV
ref
Reference voltage 600 mVVoltage positioning active, MODE/DATA = GND,
1.01xV
OUT (PFM)
device operating in PFM mode, VIN = 2.5V to –1.5% 2.5%V
OUT5.0V
(6) (7)DC output voltage accuracy PFMmode, adjustable and fixed output MODE/DATA = GND; device operating in PWM
–1% 0% 1%voltage
(5)
Mode VIN = 2.5V to 6.0V
(7)
V
OUT
V
IN
= 2.5V to 6.0V, Mode/Data = V
IN
, Fixed PWM
–1% 0% 1%operation, 0mA < I
OUT
< I
OUTMAX
(8)
DC output voltage load regulation PWM operation mode 0.5 %/At
Start up
Start-up time Activation time to start switching
(9)
170 µst
Ramp
V
OUT
Ramp UP time Time to ramp from 5% to 95% of V
OUT
750 µs
(4) At pins SW1 and SW2 an internal resistor of 1M Ωis connected to GND(5) Output voltage specification does not include tolerance of external voltage programming resistors(6) Configuration L typ 2.2 µH, C
OUT
typ 20 µF, see parameter measurement information, the output voltage ripple depends on the effectivecapacitance of the output capacitor, larger output capacitors lead to tighter output voltage tolerance(7) In Power Save Mode, PWM operation is typically entered at I
PSM
= V
IN
/32 Ω.(8) For V
OUT
> 2.2V, V
IN
min = V
OUT
+0.3V(9) This time is valid if one converter turns from shutdown mode (EN2 = 0) to active mode (EN2 =1) AND the other converter is alreadyenabled (e.g., EN1 = 1). In case both converters are turned from shutdown mode (EN1 and EN2 = low) to active mode (EN1 and/orEN2=1) a value of typ 80 µs for ramp up of internal circuits needs to be added. After t
Start
the converter starts switching and rampsV
OUT
.
4
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DEVICE INFORMATION
PIN ASSIGNMENTS
DEF_1
FB1
MODE/DATA
VIN
EN1
SW2
ADJ2
GND
EN2
PowerPAD
SW1
1
2
3
4
5
10
9
8
7
6
TopviewDRCpackage
TPS62410
SLVS737 – FEBRUARY 2007
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNO.NAME
(QFN)
ADJ2 1 I Input to adjust output voltage of converter 2. In adjustable version (TPS62410) connect a externalresistor divider between VOUT2, this pin and GND to set output voltage between 0.6V and VIN. IfEasyScale™ Interface is used for converter 2, this pin must be directly connected to the output.MODE/DATA 2 I This Pin has 2 functions:1. Operation Mode selection: With low level, Power Save Mode is enabled where the deviceoperates in PFM mode at light loads and enters automatically PWM mode at heavy loads.Pulling this PIN to high forces the device to operate in PWM mode over the whole load range.2. EasyScale™ Interface function: One wire serial interface to change the output voltage of bothconverters. The pin has an open drain output to provide an acknowledge condition if requested.The current into the open drain output stage may not exceed 500 µA. The interface is active ifeither EN1 or EN2 is high.VIN 3 I Supply voltage, connect to VBAT, 2.5V to 6VFB1 4 I Direct feedback voltage sense input of converter 1, connect directly to Vout 1. An internal feed forwardcapacitor is connected between this pin and the error amplifier. In case of fixed output voltage versionsor when the Interface is used, this pin is connected to an internal resistor divider network.DEF_1 5 I/O This pin defines the output voltage of converter 1. The pin acts in TPS62410 as an analog input foroutput voltage setting via external resistors. In fixed default output voltage versions this pin is a digitalinput to select between two fixed default output voltages.In TPS62410 an external resistor network needs to be connected to this pin to adjust the default outputvoltage.SW1 6 Switch Pin of Converter1. Connected to Inductor 1EN1 7 I Enable Input for Converter1, active highGND 8 I GND for both converters, this pin should be connected with the PowerPADEN2 9 I/O Enable Input for Converter 2, active highSW2 10 Switch Pin of Converter 2. Connected to Inductor 2PowerPAD™ Connect to GND
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FUNCTIONAL BLOCK DIAGRAM
Internal
compensated
Error Amp.
Sawtooth
Generator
Skip Comp.Low
PWM
Comp.
Average
CurrentDetector
Skip ModeEntry
VREF Control
Stage
GateDriver
PMOSCurrent
LimitComparator
NMOSCurrent
LimitComparator
LoadComparator
VREF-1%
FB
VOUT1
FB_VOUT
Undervoltage
Lockout
Thermal
Shutdown Softstart
VIN
GND
MODE
Error Amp.
Sawtooth
Generator
PWM
Comp.
VREF Control
Stage
GateDriver
PMOSCurrent
LimitComparator
NMOSCurrent
LimitComparator
LoadComparator
FB_VOUT2
Thermal
Shutdown
Softstart
VIN
GND
MODE
CLK180°
Easy Scale
Interface
CLK0°
CLK180°
2.25MHz
Oscillator
Converter1
Converter2
SW1
SW2
ADJ2
FB1
DEF1
Mode/
DATA
EN1
EN2
VIN
GND
Ext. res. network
Reference
Average
CurrentDetector
Skip ModeEntry
ACK
MOSFET
Opendrain
Internal
compensated
Skip Comp.
VREF+1%
FB_VOUT
Skip Comp.Low
VREF-1%
FB_VOUT
Skip Comp.
VREF+1%
FB_VOUT
Note A
RI3
RI1
RI..N
Int.Resistor
Network
Cff 25pF
Register
DEF1_High
DEF1_Low
RI1
RI..N
Int.Resistor
Network
Cff 25pF
Register
DEF2
NoteB
TPS62410
SLVS737 – FEBRUARY 2007
A. In fixed output voltage version, the PIN DEF_1 is connected to an internal digital input and disconnected from theerror amplifierB. To set the output voltage of Converter 2 via EasyScale Interface, ADJ2 pin must be directly connected to VOUT2
6
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PARAMETER MEASUREMENT INFORMATION
SW1
FB1
SW2
ADJ2
DEF_1
VIN
EN_1
EN_2
MODE/
DATA
TPS62410
GND
R11
R12
L1
VIN2.5V-6V
C
10 F
IN
m
2.2 H
LPS4018
m
VOUT1
C 2x10 F
GRM21BR61A106K
OUT1 m
R21
R22
L2
VOUT2
C 2x10 F
GRM21BR61A106K
OUT2 m
C
33pF
ff2
2.2 H
LPS4018
m
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
TPS62410
SLVS737 – FEBRUARY 2007
FIGURE NO.
Efficiency V
OUT1
= 1.2V 1Efficiency V
OUT1
= 1.5V 2Efficiency V
OUT2
= 1.8V 3Efficiency V
OUT2
= 3.3V 4Efficiency vs V
IN
5, 6DC Output Accuracy V
OUT1
= 1.5V 7DC Output Accuracy V
OUT2
= 3.3V 8F
OSC
vs V
IN
9I
q
for one converter 10I
q
for both converters, not switching 11R
DSON
PMOS vs V
IN
12R
DSON
NMOS vs V
IN
13Light Load Output Voltage Ripple in Power Save Mode 14Output Voltage Ripple in Forced PWM Mode 15Output Voltage Ripple in PWM Mode 16Forced PWM/ PFM ModeTransition 17Load Transient Response PFM/PWM 18Load Transient Response PWM Operation 19Line Rransient Response 20Startup Timing One Converter 21Typical Operation V
IN
= 3.6V, V
OUT1
= 1.575V, VOUT2 = 1.8V 22Typical Operation V
IN
= 3.6V, V
OUT1
= 1.8V, V
OUT2
= 3.0V 23Typical Operation V
IN
= 3.6V, V
OUT1
= 1.2V, V
OUT2
= 1.2V 24Dynamic Voltage Positioning 25
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0
10
20
30
40
50
60
70
80
90
100
0.01 0.1 1 10 100 1000
I -mA
OUT
Efficiency-%
V =1.2V
OUT
MODE/DATA =Low
V =5V
V =3.7V
V =3.3V
V =2.7V
IN
IN
IN
IN
MODE/DATA =High
V =5V
V =3.7V
V =3.3V
V =2.7V
IN
IN
IN
IN
0
10
20
30
40
50
60
70
80
90
100
Efficiency-%
0.01 0.1 1 10 100 1000
I -mA
OUT
V =1.8V
OUT
V =2.7V
IN
V =5V
IN
V =3.6V
IN
V =2.7V
IN
V =5V
IN
V =3.6V
IN
PowerSaveMode
MODE/DATA =0
ForcedPWMMode
MODE/DATA =1
V =5V
IN
V =3.6V
IN
PowerSaveMode
MODE/DATA =0
ForcedPWMMode
MODE/DATA =1
0
10
20
30
40
50
60
70
80
90
100
Efficiency-%
0.01 0.1 1 10 100 1000
I -mA
OUT
V =3.3V
OUT
V =3.6V
IN
V =5V
IN
TPS62410
SLVS737 – FEBRUARY 2007
TYPICAL CHARACTERISTICS (continued)
FIGURE NO.
Soft Start 26EasyScale Protocol Overview 27EasyScale Protocol Without Acknowledge 28EasyScale Protocol Including Acknowledge 29EasyScale – Bit Coding 30MODE/DATA PIN: Mode Selection 31MODE/DATA Pin: Power Save Mode / Interface Communication 32Typical Application Circuit 1.5V / 2.85V Adjustable Outputs 33,34Layout Diagram 35PCB Layout 36
EFFICIENCY V
OUT
= 1.2V EFFICIENCY V
OUT
= 1.5V
Figure 1. Figure 2.
EFFICIENCY V
OUT2
= 1.8V EFFICIENCY V
OUT2
= 3.3V
Figure 3. Figure 4.
8
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50
55
60
65
70
75
80
85
90
95
100
23 4 5 6
Efficiency
MODE/DATA =0
V =1.575V
OUT I =10mA
OUT
I =1mA
OUT
I =200mA
OUT
V -V
IN
50
60
70
80
90
100
3 4 5 6
V -V
IN
Efficiency
MODE/DATA =0
V =3.3V
OUT
I =100mA
OUT
I =10mA
OUT
I =1mA
OUT
1.425
1.450
1.475
1.500
1.525
1.550
1.575
VDC-V
OUT
MODE/DATA =low,PFMMode,VoltagePositioning Active
MODE/DATA = high, forced PWM Mode
V =1.5V
OUT
0.01 0.1 1 10 100 1000
I -mA
OUT
V =2.7V
IN
V =5V
IN
V =3.7V
IN
V =5V
IN
V =3.7V
IN
V =3.3V
IN
V =2.7V
IN
V =3.3V
IN
3.200
3.250
3.300
3.350
3.400
V DC-V
OUT
0.01 0.1 1 10 100 1000
I -mA
OUT
MODE/DATA =low,PFMMode,VoltagePositioning Active
MODE/DATA = high, forced PWM Mode
V =5V
IN
V =5V
IN
V =3.3V
OUT
V 3.7V
IN =
V 4.2V
IN =
PWMMode
Operation
V =3.7V
IN V =4.2V
IN
TPS62410
SLVS737 – FEBRUARY 2007
EFFICIENCY vs V
IN
, V
OUT
= 1.575V EFFICIENCY vs V
IN
, V
OUT
= 3.3V
Figure 5. Figure 6.
DC OUTPUT ACCURACY V
OUT1
= 1.5V DC OUTPUT ACCURACY V
OUT2
= 3.3V
Figure 7. Figure 8.
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2
2.05
2.1
2.15
2.2
2.25
2.3
2.35
2.4
2.45
2.5
2.5 3 3.5 4 4.5 5 5.5 6
V -V
IN
Fosc-MHz
-40 C°
85 C°
25 C°
17
18
19
20
21
22
23
24
2.5 3 3.5 4 4.5 5 5.5 6
V -V
IN
Iddq- Am
-40°C
85°C
25°C
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
2.5 3 3.5 4 4.5 5 5.5 6
V -V
IN
RDSon- W
85°C
25°C
-40°C
28
30
32
34
36
38
40
42
2.5 3 3.5 4 4.5 5 5.5 6
V -V
IN
Iddq- Am
85°C
25°C
-40°C
TPS62410
SLVS737 – FEBRUARY 2007
F
OSC
vs V
IN
I
q
FOR ONE CONVERTER, NOT SWITCHING
Figure 9. Figure 10.
I
q
FOR BOTH CONVERTERS, NOT SWITCHING R
DSON
PMOS vs V
IN
Figure 11. Figure 12.
10
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0.05
0.1
0.15
0.2
0.25
0.3
2.5 3 3.5 4 4.5 5 5.5 6
V -V
IN
RDSon- W
85°C
25°C
-40°C
IOUT =10mA
VOUT =1.8V20mV/Div
Inductorcurrent100mA/Div
PowerSaveMode
Mode/Data=low
Timebase-10 s/Divm
IOUT =10mA
VOUT =1.8V20mV/Div
Inductorcurrent100mA/Div
Mode/Data=high,
forcedPWMMODEoperation
Timebase-400ns/Div
TPS62410
SLVS737 – FEBRUARY 2007
LIGHT LOAD OUTPUT VOLTAGE RIPPLER
DSON
NMOS vs V
IN
IN POWER SAVE MODE
Figure 13. Figure 14.
OUTPUT VOLTAGE RIPPLE OUTPUT VOLTAGE RIPPLEIN FORCED PWM MODE IN PWM MODE
Figure 15. Figure 16.
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IOUT=60mA
IOUT1=540mA
VOUT =1.575V
50mV/Div
Voltagepositioning inPFM
Modereduces voltage drop
duringloadstep
IOUT 200mA/Div
MODE/DATA =low
PWMModeoperation
Timebase-100 s/Divm
IOUT=60mA
IOUT1=540mA
VOUT =1.575V
50mV/Div
IOUT 200mA/Div
MODE/DATA =high
PWMModeoperation
Timebase-100 s/Divm
VIN1V/Div
VOUT 1.575
IOUT 200mA
VIN3.6Vto4.6V
VOUT 50mV/Div
MODE/DATA =high
Timebase-400 s/Divm
TPS62410
SLVS737 – FEBRUARY 2007
FORCED PWM/PFM MODE TRANSITION LOAD TRANSIENT RESPONSE PFM/PWM
Figure 17. Figure 18.
LOAD TRANSIENT RESPONSE PWM OPERATION LINE TRANSIENT RESPONSE
Figure 19. Figure 20.
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SW15V/Div
SW25V/Div
Icoil1 200mA/Div
Icoil2 200mA/Div
VIN 3.6V,
VOUT1:1.575V
VOUT2:1.8V
IOUT1 =IOUT2 =200mA
Timebase-100ns/Div
VIN=3.8V
IOUT1max=400mA
SW11V/Div
EN1/EN25V/Div
VOUT1
500mV/Div
Icoil500mA/Div
Timebase-200 s/Divm
SW15V/Div
SW25V/Div
Icoil1 200mA/Div
Icoil2 200mA/Div
VIN 3.6V,
VOUT1:1.8V
VOUT2:3.0V
IOUT1 =IOUT2 =200mA
Timebase-100ns/Div
SW15V/Div
SW25V/Div
Icoil1 200mA/Div
Icoil2 200mA/Div VIN 3.6V,
VOUT1:1.2V
VOUT2:1.2V
IOUT1 =IOUT2 =200mA
Timebase-100ns/Div
DETAILED DESCRIPTION
OPERATION
TPS62410
SLVS737 – FEBRUARY 2007
TYPICAL OPERATION V
IN
= 3.6V,STARTUP TIMING ONE CONVERTER V
OUT1
= 1.575V, V
OUT2
= 1.8V
Figure 21. Figure 22.
TYPICAL OPERATION V
IN
= 3.6V, TYPICAL OPERATION V
IN
= 3.6V,V
OUT1
= 1.8V, V
OUT2
= 3.0V V
OUT1
= 1.2V, V
OUT2
= 1.2V
Figure 23. Figure 24.
V
OUT1
CHANGE WITH EASYSCALE
The TPS62410 includes two synchronous step-down converters. The converters operate with typically 2.25MHzfixed frequency pulse width modulation (PWM) at moderate to heavy load currents. If Power Save Mode isenabled, the converters automatically enter Power Save Mode at light load currents and operate in PFM (Pulse
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Converter 1
Converter 2
POWER SAVE MODE
IOUT_PFM_enter +VINDCDC
32 W
(1)
IOUT_PFM_leave +VINDCDC
24 W
(2)
TPS62410
SLVS737 – FEBRUARY 2007
DETAILED DESCRIPTION (continued)Frequency Modulation). During PWM operation the converters use a unique fast response voltage modecontroller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use ofsmall ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, theP-channel MOSFET switch is turned on and the inductor current ramps up until the comparator trips and thecontrol logic turns off the switch.
Each converter integrates two current limits, one in the P-channel MOSFET and another one in the N-channelMOSFET. When the current in the P-channel MOSFET reaches its current limit, the P-channel MOSFET isturned off and the N-channel MOSFET is turned on. If the current in the N-channel MOSFET is above theN-MOS current limit threshold, the N-channel MOSFET remains on until the current drops below its current limit.The two DC-DC converters operate synchronized to each other. A 180 °phase shift between converter 1 andconverter 2 decreases the input RMS current.
In the adjustable output voltage version TPS62410 the converter 1 output voltage can be set via an externalresistor network on PIN DEF_1, which operates as an analog input. In this case, the output voltage can be set inthe range of 0.6V to VIN V. The FB1 Pin must be directly connected to the converter 1 output voltage VOUT1. Itfeeds back the output voltage directly to the regulation loop.
The output voltage of converter 1 can also be changed by the EasyScale serial Interface. This makes the devicevery flexible for output voltage adjustment. In this case, the device uses an internal resistor network.
In the adjustable output voltage version TPS62410, the converter 2 output voltage is set by an external resistordivider connected to ADJ2 Pin and uses an external feed forward capacitor of 33pF.
It is also possible to change the output voltage of converter 2 via the EasyScale Interface. In this case, the ADJ2Pin must be directly connected to converter 2 output voltage VOUT2. At TPS62410 no external resistor networkmay be connected.
The Power Save Mode is enabled with Mode/Data Pin set to 0 for both converters. If the load current of aconverter decreases, this converter will enter Power Save Mode operation automatically. The transition to PowerSave Mode of a converter is independent from the operating condition of the other converter. During PowerSave Mode the converter operates with reduced switching frequency in PFM mode and with a minimumquiescent current to maintain high efficiency. The converter will position the output voltage in PFM mode totypically 1.01xVOUT. This voltage positioning feature minimizes voltage drops caused by a sudden load step.
In order to optimize the converter efficiency at light load the average inductor current is monitored. The devicechanges from PWM Mode to Power Save Mode, if in PWM mode the inductor current falls below a certainthreshold. The typical output current threshold depends on VIN and can be calculated according to Equation 1for each converter.
Equation 1 : Average output current threshold to enter PFM Mode
Equation 2 : Average output current threshold to leave PFM Mode
In order to keep the output voltage ripple in Power Save Mode low, the output voltage is monitored with a singlethreshold comparator (skip comparator). As the output voltage falls below the skip comparator threshold (skipcomp) of 1.01 x VOUTnominal, the corresponding converter starts switching for a minimum time period oftypically 1 µs and provides current to the load and the output capacitor. Therefore the output voltage increasesand the device maintains switching until the output voltage trips the skip comparator threshold (skip comp)again. At this moment all switching activity is stopped and the quiescent current is reduced to minimum. Theload is supplied by the output capacitor until the output voltage has dropped below the threshold again.
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Dynamic Voltage Positioning
VOUT_NOM
+1%
PWMMode
medium/heavyload
PFMMode
lightload
Smooth
increasedload
PWMMode
medium/heavyload
PFMMode
lightload
Fastloadtransient
PWMMode
medium/heavyload
COMP_LOWthreshold –1%
Soft Start
95%
5%
tRAMP
tStartup
EN
VOUT
TPS62410
SLVS737 – FEBRUARY 2007
DETAILED DESCRIPTION (continued)Hereupon the device starts switching again. The Power Save Mode is exited and PWM Mode entered in casethe output current exceeds the current IOUT_PFM_leave, or if the output voltage falls below a secondcomparator threshold, called skip comparator low (Skip Comp Low) threshold. This skip comparator lowthreshold is set to –2% below nominal Vout, and enables a fast transition from Power Save Mode to PWM Modeduring a load step. In Power Save Mode the quiescent current is reduced typically to 19 µA for one converter and32 µA for both converters active. This single skip comparator threshold method in Power Save Mode results in avery low output voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor.Increasing output capacitor values minimizes the output ripple. The Power Save Mode can be disabled throughthe MODE/DATA pin set to high. Both converters then operate in fixed PWM mode. Power Save ModeEnable/Disable applies to both converters.
This feature reduces the voltage under/overshoots at load steps from light to heavy load and vice versa. It isactivated in Power Save Mode operation. It provides more headroom for both the voltage drop at a load step,and the voltage increase at a load throw-off. This improves load transient behavior.
At light loads, in which the converter operate in PFM Mode, the output voltage is regulated typically 1% higherthan the nominal value. In case of a load transient from light load to heavy load, the output voltage drops until itreaches the skip comparator low threshold set to –2% below the nominal value and enters PWM mode. During aload throw off from heavy load to light load, the voltage overshoot is also minimized due to active regulationturning on the N-channel switch.
Figure 25. Dynamic Voltage Positioning
The two converters have an internal soft start circuit that limits the inrush current during start-up. During softstart, the output voltage ramp up is controlled as shown in Figure 26 .
Figure 26. Soft Start
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100% Duty Cycle Low Dropout Operation
Vinmin +Voutmax )Ioutmax ǒRDSonmax )RLǓ
(3)
Under-Voltage Lockout
MODE SELECTION
ENABLE
TPS62410
SLVS737 – FEBRUARY 2007
DETAILED DESCRIPTION (continued)
The converters offer a low input to output voltage difference while still maintaining operation with the use of the100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly useful inbattery-powered applications to achieve longest operation time by taking full advantage of the whole batteryvoltage range; i.e., the minimum input voltage to maintain regulation depends on the load current and outputvoltage, and can be calculated as:
With:
Iout
max
= maximum output current plus inductor ripple currentRDSon
max
= maximum P-channel switch RDSonR
L
= DC resistance of the inductorVout
max
= nominal output voltage plus maximum output voltage tolerance
With decreasing load current, the device automatically switches into pulse skipping operation in which the powerstage operates intermittently based on load demand. By running cycles periodically the switching losses areminimized and the device runs with a minimum quiescent current maintaining high efficiency.
The under voltage lockout circuit prevents the device from malfunctioning at low input voltages and fromexcessive discharge of the battery and disables the converters. The under-voltage lockout threshold is typically1.5V, max 2.35V. In case the default register values are overwritten by the Interface, the new values in theregisters REG_DEF_1_Low and REG_DEF_2 remain valid as long the supply voltage does not fall under theunder-voltage lockout threshold, independent of whether the converters are disabled.
The MODE/DATA pin allows mode selection between forced PWM Mode and Power Save Mode for bothconverters. Furthermore, this pin is a multipurpose pin and provides (besides Mode selection) a one-pininterface to receive serial data from a host to set the output voltage. This is described in the section EasyScaleInterface.
Connecting this pin to GND enables the automatic PWM and power save mode operation. The convertersoperate in fixed-frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads,maintaining high efficiency over a wide load current range.
Pulling the MODE/DATA pin high forces both converters to operate constantly in the PWM mode even at lightload currents. The advantage is the converters operate with a fixed frequency that allows simple filtering of theswitching frequency for noise sensitive applications. In this mode, the efficiency is lower compared to the powersave mode during light loads. For additional flexibility it is possible to switch from Power Save Mode to forcedPWM mode during operation. This allows efficient power management by adjusting the operation of theconverter to the specific system requirements.
In case the operation mode will be changed from forced PWM mode (MODE/DATA = high) to Power Save ModeEnable (MODE/DATA = 0) the Power Save Mode will be enabled after a delay time of typically t
timeout
, which is amaximum of 520 µs.
The forced PWM Mode operation is enabled immediately with Pin MODE/DATA set to 1.
The device has for each converter a separate EN pin to start up each converter independently. If EN1, EN2 areset to high, the corresponding converter starts up with soft start as previously described.
Pulling EN1 and EN2 pin low forces the device into shutdown, with a shutdown quiescent current of typically1.2 µA. In this mode, the P and N-Channel MOSFETs are turned-off and the entire internal control circuitry isswitched-off. For proper operation the EN1 and EN2 pins must be terminated and must not be left floating.
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DEF_1 PIN FUNCTION
180 °OUT OF PHASE OPERATION
SHORT-CIRCUIT PROTECTION
THERMAL SHUTDOWN
EasyScale™: One Pin Serial Interface for Dynamic Output Voltage Adjustment
General
Protocol
Addressable Registers
TPS62410
SLVS737 – FEBRUARY 2007
DETAILED DESCRIPTION (continued)
The DEF_1 pin is dedicated to converter 1 and works as an analog input for adjustable output voltage setting.Connecting an external resistor network to this pin adjusts the default output voltage to any value starting from0.6V to V
IN
.
In PWM Mode the converters operate with a 180 °turn-on phase shift of the PMOS (high side) transistors. Itprevents the high side switches of both converters to be turned on simultaneously, and therefore smooths theinput current. This feature reduces the surge current drawn from the supply.
Both outputs are short-circuit protected with maximum output current = I
LIMF
(P-MOS and N-MOS). Once thePMOS switch reaches its current limit, it will be turned off and the NMOS turned on. The PMOS only turns onagain, once the current in the NMOS decreases below the NMOS current limit.
As soon as the junction temperature, T
J
, exceeds typically 150 °C the device goes into thermal shutdown. In thismode, the P and N-Channel MOSFETs are turned-off. The device continues its operation when the junctiontemperature falls below the thermal shutdown hysteresis again.
EasyScale is a simple but very flexible one pin interface to configure the output voltage of both DC/DCconverters. The interface is based on a master – slave structure, where the master is typically a µController orApplication processor. Figure 27 and Table 2 give an overview of the protocol. The protocol consists of a devicespecific address byte and a data byte. The device specific address byte is fixed to 4E hex. The data byteconsists of five bit for information, two address bits and the RFA bit. RFA bit set to high indicates the RequestFor Acknowledge condition. The Acknowledge condition is only applied if the protocol was received correctly.
The advantage of EasyScale compared to other one-pin interfaces is that its bit detection is, to a large extent,independent from the bit transmission rate. It can automatically detect bit rates between 1.7kBit/sec and up to160kBit/sec. Furthermore, the interface is shared with the Mode/Data Pin and requires therefore no additionalpin.
All bits are transmitted MSB first and LSB last. Figure 28 shows the protocol without acknowledge request (bitRFA = 0), Figure 29 with acknowledge (bit RFA = 1) request.
Prior to both bytes, device address byte and data byte, a start condition needs to be applied. For this, theMode/Data pin needs to be pulled high for at least t
Start
before the bit transmission starts with the falling edge. Incase the Mode/Data line was already at high level (forced PWM Mode selection) no start condition need beapplied prior the device address byte.
The transmission of each byte needs to be closed with an End Of Stream condition for at least T
EOS
.
In TPS62410 two registers with a data content of 5 bits can be addressed to change the output voltage of bothconverters. With 5 bit data content, 32 different values for each register are available. Table 1 shows theaddressable registers if DEF_1 pin acts as analog input with external resistors connected.
The available output voltages for converter 1 are shown in Table 3 , for converter 2 in Table 4 . To generate theseoutput voltages, a precise internal resistor divider network is used, which makes external resistors unnecessaryand results therefore in an higher output voltage accuracy and less board space.
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Bit Decoding
Acknowledge
MODE Selection
TPS62410
SLVS737 – FEBRUARY 2007
DETAILED DESCRIPTION (continued)The Interface is activated if at least one of the converters is enabled (EN1 or EN2 is high). After the Startup-timet
Start
(170 µs) the interface is ready for data reception.
Table 1. Addressable Registers for Adjustable Output Voltage Devices
REGISTER DESCRIPTION A1 A0 D4 D3 D2 D1 D0
REG_DEF_1_High Not available in TPS62410 adjustable version 0 1REG_DEF_1_Low Converter 1 output voltage setting 0 0 TPS62410 see Table 3REG_DEF_2 Converter 2 output voltage 1 0 TPS62410 see Table 4 , connect ADJ2pin directly to VOUT
2
Don’t use 1 1
The bit detection is based on a PWM scheme, where the criterion is the relation between t
LOW
and t
HIGH
. It canbe simplified to:High Bit: t
High
> t
Low
, but with t
High
at least 2x t
Low
, see Figure 30Low Bit: tLow> tHigh, but with tLow at least 2x tHigh, see Figure 30
The bit detection starts with a falling edge on the MODED/DATA pin and ends with the next falling edge.Depending on the relation between t
Low
and t
High
a 0 or 1 is detected.
The Acknowledge condition is only applied if:•Acknowledge is requested by a set RFA bit•The transmitted device address matches with the device address of the device•16 bits were received correctly
In this case, the device turns on the internal ACKN-MOSFET and pulls the MODE/DATA pin low for the timetACKN, which is max. 520 µs. The Acknowledge condition is valid after an internal delay time t
valACK
. This meansthe internal ACKN-MOSFET is turned on after t
valACK
, when the last falling edge of the protocol was detected.The master controller keeps the line low during this time.
The master device can detect the acknowledge condition with it’s input by releasing the MODE/DATA pin aftertvalACK and read back a 0.
In case of an invalid device address or not correctly received protocol, no acknowledge condition will be applied,thus the internal MOSFET will not be turned on and the external pullup resistor pulls MODE/DATA pin high aftert
valACK
. The MODE/DATA pin can be used again after the acknowledge condition ends.
NOTE:
The acknowledge condition may only be requested in case the master device has anopen drain output.
In case of a push pull output stage it is recommended to use a series resistor in the MODE/DATA line to limit thecurrent to 500 µA in case of an accidentally requested acknowledge to protect the internal ACKN-MOSFET.
Because of the MODE/DATA pin is used for two functions, interface and a MODE selection, the device needs todetermine when it has to decode the bit stream or to change the operation mode.
The device enters forced PWM mode operation immediately whenever the MODE/DATA pin turns to high level.The device stays also in forced PWM mode during the whole time of a protocol reception.
With a falling edge on the MODE/DATA pin the device starts bit decoding. If the MODE/DATA pin stays low forat least t
timeout
, the device get’s an internal timeout and Power Save Mode operation is enabled.
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DATA IN
Start
DATA OUT ACK
RFA A1 A0 D4 D3 D2 D1 D0DA7
0
DA6
1
DA5
0
DA4
0
DA3
1
DA2
1
DA1
1
DA0
0
Device Address DATABYTE
EOS Start EOS
Start
DA7
0
tStart
Mode,Static
HighorLow
Mode,Static
HighorLow
DATA IN
tStart
TEOS TEOS
DA0
0
RFA
0
D0
1
AddressByte DATA Byte
TPS62410
SLVS737 – FEBRUARY 2007
A protocol which is sent within this time will be ignored, because the falling edge for the Mode change will befirst interpreted as start of the first bit. In this case it is recommended to send first the protocol and change at theend of the protocol to Power Save Mode.
Figure 27. Easy Scale Protocol Overview
Table 2. Easy Scale Bit Description
BYTE BIT NAME TRANSMISSION DESCRIPTIONNUMBER DIRECTION
Device 7 DA7 IN 0 MSB device addressAddress
6 DA6 IN 1Byte
5 DA5 IN 04 DA4 IN 04Ehex 3 DA3 IN 12 DA2 IN 11 DA1 IN 10 DA0 IN 0 LSB device addressDatabyte 7(MSB) RFA IN Request For Acknowledge, if high, Acknowledge condition will applied by the device6 A1 Address Bit 15 A0 Address Bit 04 D4 Data Bit 43 D3 Data Bit 32 D2 Data Bit 21 D1 Data Bit 10(LSB) D0 Data Bit 0ACK OUT Acknowledge condition active 0, this condition will only be applied in case RFA bit isset. Open drain output, Line needs to be pulled high by the host with a pullupresistor.
This feature can only be used if the master has an open drain output stage. In caseof a push pull output stage Acknowledge condition may not be requested!
Figure 28. Easy Scale Protocol Without Acknowledge
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Mode,Static
HighorLow
tACKN
Acknowledge
true,DataLine
pulleddownby
device
DATA IN
DATA OUT Acknowledge
false,nopull
down
Controllerneedsto
PullupDataLineviaa
resistortodetect ACKN
ACKN
DA7
0
Mode,Static
HighorLow
TEOS tvalACK
DA0
0
RFA
1
D0
1
tStart tStart
AddressByte DATA Byte
LowBit
(Logic0)
HighBit
(Logic1)
tLow tHigh tLOW tHigh
PowerSaveMode ForcedPWMMODE PowerSaveMode
ttimeout
MODE/DATA
tStart tStart
TEOS
TEOS
AddressByte DATA Byte
ForcedPWMMODE PowerSaveMode
ttimeout
MODE/DATA
PowerSaveMode
TPS62410
SLVS737 – FEBRUARY 2007
Figure 29. Easy Scale Protocol Including Acknowledge
Figure 30. EasyScale – Bit Coding
Figure 31. MODE/DATA PIN: Mode Selection
Figure 32. MODE/DATA Pin: Power Save Mode/Interface Communication
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TPS62410
SLVS737 – FEBRUARY 2007
Table 3. Selectable Output Voltages for Converter 1,With DEF1 Pin as Analog Input (TPS62410)
TPS62410 OUTPUT VOLTAGE [V] D4 D3 D2 D1 D0REGISTER REG_DEF_1_LOW
0 V
OUT1
Adjustable Output With Resistor Network on DEF_1 Pin 0 0 0 0 0
0.6V with DEF_1 Pin connected to V
OUT1
1 0.825 0 0 0 0 12 0.85 0 0 0 1 03 0.875 0 0 0 1 14 0.9 0 0 1 0 05 0.925 0 0 1 0 16 0.95 0 0 1 1 07 0.975 0 0 1 1 18 1.0 0 1 0 0 09 1.025 0 1 0 0 110 1.050 0 1 0 1 011 1.075 0 1 0 1 112 1.1 0 1 1 0 013 1.125 0 1 1 0 114 1.150 0 1 1 1 015 1.175 0 1 1 1 116 1.2 1 0 0 0 017 1.225 1 0 0 0 118 1.25 1 0 0 1 019 1.275 1 0 0 1 120 1.3 1 0 1 0 021 1.325 1 0 1 0 122 1.350 1 0 1 1 023 1.375 1 0 1 1 124 1.4 1 1 0 0 025 1.425 1 1 0 0 126 1.450 1 1 0 1 027 1.475 1 1 0 1 128 1.5 1 1 1 0 029 1.525 1 1 1 0 130 1.55 1 1 1 1 031 1.575 1 1 1 1 1
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TPS62410
SLVS737 – FEBRUARY 2007
Table 4. Selectable Output Voltages for Converter 2,(ADJ2 Connected to V
OUT
)
OUTPUT VOLTAGE [V] D4 D3 D2 D1 D0FOR REGISTER REG_DEF_2
0 V
OUT2
Adjustable Output With Resistor Network on ADJ2 0 0 0 0 0
0.6V with ADJ2 Pin connected to V
OUT2
1 0.85 0 0 0 0 12 0.9 0 0 0 1 03 0.95 0 0 0 1 14 1.0 0 0 1 0 05 1.05 0 0 1 0 16 1.1 0 0 1 1 07 1.15 0 0 1 1 18 1.2 0 1 0 0 09 1.25 0 1 0 0 110 1.3 0 1 0 1 011 1.35 0 1 0 1 112 1.4 0 1 1 0 013 1.45 0 1 1 0 114 1.5 0 1 1 1 015 1.55 0 1 1 1 116 1.6 1 0 0 0 017 1.7 1 0 0 0 118 1.8 1 0 0 1 019 1.85 1 0 0 1 120 2.0 1 0 1 0 021 2.1 1 0 1 0 122 2.2 1 0 1 1 023 2.3 1 0 1 1 124 2.4 1 1 0 0 025 2.5 1 1 0 0 126 2.6 1 1 0 1 027 2.7 1 1 0 1 128 2.8 1 1 1 0 029 2.85 1 1 1 0 130 3.0 1 1 1 1 031 3.3 1 1 1 1 1
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APPLICATION INFORMATION
OUTPUT VOLTAGE SETTING
Converter1 Adjustable Default Output Voltage Setting
VOUT +VREF ǒ1)R11
R12Ǔwith an internal reference voltage VREF typical 0.6V
(4)
Converter 2
VOUT +VREF ǒ1)R21
R22Ǔwith an internal reference voltage VREF typical 0.6V
(5)
SW1
FB1
SW2
ADJ2
DEF_1
VIN3.3V – 6V
VIN
EN_1
EN_2
MODE/
DATA
TPS62410
GND
L1
C
10 F
IN
m2.2 HmR11
270kW
R12
180kW
V =1.5V
upto800mA
OUT1
C =22 F
OUT1 m
V =2.85V
upto800mA
OUT2
L2
Cff2
33pF
3.3 HmR21
825kW
R22
220kW
C =22 F
OUT2 m
TPS62410
SLVS737 – FEBRUARY 2007
The output voltage can be calculated to:
To keep the operating current to a minimum, it is recommended to select R
12
within a range of 180k Ωto 360k Ω.The sum of R
12
and R
11
should not exceed ~1M Ω. For higher output voltages than 3.3V, it is recommended tochoose lower values than 180k Ωfor R12. Route the DEF_1 line away from noise sources, such as the inductoror the SW1 line. The FB1 line needs to be directly connected to the output capacitor. An internal feed forwardcapacitor is connected to this pin, therefore there is no need for an external feed forward capacitor for converter1.
The default output voltage of converter 2 can be set by an external resistor network. For converter 2 the samerecommendations apply as for converter 1. In addition to that, a 33pF external feed forward capacitor C
ff2
forgood load transient response must be used.
The output voltage can be calculated to:
Route the ADJ2 line away from noise sources, such as the inductor or the SW2 line. In case the interface isused for converter 2, connect ADJ2 pin directly to V
OUT2
Figure 33. Typical Application Circuit 1.5V/2.85V Adjustable Outputs, low PFM Voltage ripple Optimized
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SW1
FB1
SW2
ADJ2
DEF_1
VIN3.3V – 6V
VIN
EN_1
EN_2
MODE/
DATA
TPS62410
GND
L1
C
10 F
IN
m2.2 HmR11
270kW
R12
180kW
V =1.5V
upto800mA
OUT1
C =10 F
OUT1 m
V =2.85V
upto800mA
OUT2
L2
Cff2
33pF
3.3 HmR21
825kW
R22
220kW
C =10 F
OUT2 m
OUTPUT FILTER DESIGN (INDUCTOR AND OUTPUT CAPACITOR)
Inductor Selection
DIL+Vout 1*Vout
Vin
L ƒ
(6)
ILmax +Ioutmax )
DIL
2
(7)
TPS62410
SLVS737 – FEBRUARY 2007
APPLICATION INFORMATION (continued)
Figure 34. Typical Application Circuit 1.5V/2.85V Adjustable Outputs
The device is optimized to operate with inductors of 2.2 µH to 4.7 µH and output capacitors of 10 µF to 22 µF.
For operation with a 2.2 µH inductor, a 22 µF capacitor is suggested.
The selected inductor has to be rated for its DC resistance and saturation current. The DC resistance of theinductance will influence directly the efficiency of the converter. Therefore an inductor with lowest DC resistanceshould be selected for highest efficiency.
Equation 6 calculates the maximum inductor current under static load conditions. The saturation current of theinductor should be rated higher than the maximum inductor current as calculated with Equation 7 . This isrecommended because during heavy load transient the inductor current will rise above the calculated value.
With:
f = Switching Frequency (2.25MHz typical)L = Inductor Value∆I
L
= Peak to Peak inductor ripple currentI
Lmax
= Maximum Inductor current
The highest inductor current will occur at maximum Vin.
Open core inductors have a soft saturation characteristic and they can usually handle higher inductor currentsversus a comparable shielded inductor.
A more conservative approach is to select the inductor current rating just for the maximum switch current of thecorresponding converter. It must be considered, that the core material from inductor to inductor differs and willhave an impact on the efficiency especially at high switching frequencies.
24
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Output Capacitor Selection
IRMSCout +Vout 1*Vout
Vin
L ƒ 1
2 3
Ǹ
(8)
DVout +Vout 1*Vout
Vin
L ƒ ǒ1
8 Cout ƒ)ESRǓ
(9)
Input Capacitor Selection
LAYOUT CONSIDERATIONS
TPS62410
SLVS737 – FEBRUARY 2007
APPLICATION INFORMATION (continued)Refer to Table 5 and the typical applications for possible inductors.
Table 5. List of Inductors
DIMENSIONS [mm
3
] INDUCTOR TYPE SUPPLIER
2.8x2.6 ×1.4 VLF3014 TDK3×3×1.4 LPS3015 Coilcraft3.9 ×3.9 ×1.7 LPS4018 Coilcraft
The advanced fast response voltage mode control scheme of the two converters allows the use of small ceramiccapacitors with a typical value of 10 µF, without having large output voltage under and overshoots during heavyload transients. Ceramic X7R/X5R capacitors having low ESR values result in lowest output voltage ripple andare therefore recommended.
If ceramic output capacitors are used, the capacitor RMS ripple current rating will always meet the applicationrequirements. The RMS ripple current is calculated as:
At nominal load current the inductive converters operate in PWM mode and the overall output voltage ripple isthe sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging anddischarging the output capacitor:
Where the highest output voltage ripple occurs at the highest input voltage Vin.
At light load currents the converters operate in Power Save Mode and the output voltage ripple is dependent onthe output capacitor value. The output voltage ripple is set by the internal comparator delay and the externalcapacitor. Higher output capacitors like 22 µF values minimize the voltage ripple in PFM Mode and tighten DCoutput accuracy in PFM Mode.
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor isrequired for best input voltage filtering and minimizing the interference with other circuits caused by high inputvoltage spikes. The converters need a ceramic input capacitor of 10 µF. The input capacitor can be increasedwithout any limit for better input voltage filtering.
As for all switching power supplies, the layout is an important step in the design. Proper function of the devicedemands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. Ifthe layout is not carefully done, the regulator could show poor line and/or load regulation, stability issues as wellas EMI problems. It is critical to provide a low inductance, impedance ground path. Therefore, use wide andshort traces for the main current paths as indicated in bold in Figure 35 .
The input capacitor should be placed as close as possible to the IC pins as well as the inductor and outputcapacitor.
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SW1
FB1
DEF_1
VIN2.5V – 6V
VIN
EN_1
EN_2
MODE/
DATA
TPS62410
GND
R11
R12
PowerPAD
R21
R22
SW2
ADJ2
C
10 F
IN
m
COUT2
C
33pF
ff2
L1
3.3 Hm3.3 Hm
COUT2
L2
TPS62410
SLVS737 – FEBRUARY 2007
Connect the GND Pin of the device to the PowerPAD of the PCB and use this Pad as a star point. For eachconverter use a common Power GND node and a different node for the Signal GND to minimize the effects ofground noise. Connect these ground nodes together to the PowerPAD (star point) underneath the IC. Keep thecommon path to the GND PIN, which returns the small signal components and the high current of the outputcapacitors as short as possible to avoid ground noise. The output voltage sense lines (FB 1, ADJ2, DEF_1)should be connected right to the output capacitor and routed away from noisy components and traces (e.g., SWline). If the EasyScale interface is operated with high transmission rates, the MODE/DATA trace must be routedaway from the ADJ2 line to avoid capacitive coupling into the ADJ2 pin. A GND guard ring between theMODE/DATA pin and ADJ2 pin avoids potential noise coupling.
Figure 35. Layout Diagram
26
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CIN
COUT1
COUT2
GNDPin
connected
withPower
Pad
TPS62410
SLVS737 – FEBRUARY 2007
Figure 36. PCB Layout
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TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS62410DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62410DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62410DRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62410DRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS62410DRCR SON DRC 10 3000 367.0 367.0 35.0
TPS62410DRCR SON DRC 10 3000 367.0 367.0 35.0
TPS62410DRCT SON DRC 10 250 210.0 185.0 35.0
TPS62410DRCT SON DRC 10 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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