MB881822BPVA1-G-EFE1 - Fujitsu Semiconductor

FUJITSU MICROELECTRONICS

DATA SHEET

2009.4

ASSP

Spread Spectrum Clock Generator

MB88182

■DESCRIPTION

MB88182 is the multi-output clock generator for EMI (Electro Magnetic Interference) reduction. The peak of

unnecessary radiation noise (EMI) can be attenuated by making the oscillation frequency slightly modulate

periodically with the internal modulator.

It is possible to set the frequency in the built-in register using the I2C bus that can vary depending on the application.

■FEATURES

• Built-in PLL : 3

Without spread-spectrum function : 1 (PLL)

With spread-spectrum function : 2 (SSCG1, SSCG2)

• Clock output pins : 5 pins

CLK1 : Clock output when setting to CLK1 (PLL).

CLK2 : Clock output when setting to CLK2 (SSCG1) .

CLK3 : Clock output when setting to CLK3 (SSCG2) .

CLK4 : Clock output when setting to CLK4 (SSCG2) .

Note: It is not possible to output CLK3 and CLK4 at the same time.

CKREF : Buffered output for CKIN clock.

• Power down pins : 5 pins

XPD1 : Control the stop state of PLL and the CLK1 output.

XPD2 : Control the stop state of SSCG1 and the CLK2 output.

XPD3 : Control the stop state of the CLK3 output.

XPD4 : Control the stop state of the CLK4 output.

Note: Halting both CLK3 and CLK4 stops operating the SSCG2.

Control the stop state of the CKREF output. (Continued)

DS04-29138-1E

MB88182

2DS04-29138-1E

(Continued)

• Modulation enable pins : ENS

Switch on and off for the modulation (For SSCG1, SSCG2)

• Function to set the output clock frequency

This has the slave transfer function for the I2C bus, and can set the output frequency of CLK1 (when setting

to CLK1), CLK2 (when setting to CLK2), CLK3 (when setting to CLK3) and CLK4 (when setting to CLK4) from

the outside.

Also, it is possible to set the output drive ability of CLK1, CLK2, CLK3 and CLK4.

Output frequency* : 8 MHz to 100 MHz, internal oscillation frequency : 16 MHz to 168 MHz

*: When VDP is 1.8 V ± 0.15 V, the frequency range to output is 8 MHz to 50 MHz.

Programmable of the parameter of N divider, M divider, K divider

Setting to CLK1 : N divider : 5-bit, M divider : 6-bit, K divider : 5-bit

Setting to CLK2, 3, 4 : N divider : 11-bit, M divider : 12-bit, K divider : 5-bit

Modulation rate : Selectable from no modulation, ± 0.25%, ± 0.5%, ± 0.75%, ± 1.0%, ± 1.25%, ± 1.5% and ± 1.75%.

• Input clock 10 MHz to 30 MHz

• Power supply voltage: 1.8 V ± 0.15 V (VDD), 2.6 V ± 0.1 V (VDDE), 1.65 V to 2.7 V (VDP)

• Operating temperature: − 40 °C to + 85 °C

• Power consumption: At operation 18 mW (Power supply voltage:1.8 V (VDD),

2.6 V (VDDE, VDP) normal temperature, no load,

CKREF(19.2 MHz), CLK1 (48 MHz, 1.8 V), CLK2 (27 MHz),

CLK3 (37 MHz) during the clock output)

During the power down state for all outputs

0.01 mW (Power supply voltage: 1.8 V (VDD) ,

2.6 V (VDDE, VDP), normal temperature)

• Cycle-Cycle Jitter : Less than 100 ps-rms

• Package : BCC20 (3.50 mm × 3.50 mm, Lead pitch 0.50 mm, Mounting height 0.60 mm)

■PRODUCT LINEUP

MB88182 has 4 lineups corresponding to the different voltages of CLK1 pin and I2C addresses.

Part number CLK1 CLK2 CLK3/CLK4/CKREF I2C address

MB881821APVA1 1.8 V

2.6 V VDP level

(1.8 V/2.6 V)

1001111

MB881822APVA1 2.6 V

MB881821BPVA1 1.8 V 1011111

MB881822BPVA1 2.6 V

MB88182

DS04-29138-1E 3

■PIN ASSIGNMENT

(TOP VIEW)

(LCC-20P-M06)

810

1920 18

VDP

CKREF

CKIN

VSS

VDD

CLK1

XPDREF

XPD1

SDA

SCL

ENS

VDDE

VSS

CLK2

XPD4

XPD3

XPD2

CLK3

CLK4

VSS

MB88182

4DS04-29138-1E

■PIN DESCRIPTION

Pin name I/O Pin no. Description

VDP ⎯1 Power supply pin (2.6 V / 1.8 V)

CKREF O 2 Reference clock output pin

CKIN I 3 Clock input pin (19.2 MHz)

VSS ⎯4GND pin

VDD ⎯5 Power supply pin (1.8 V)

CLK1 O 6 Clock output pin 1

XPDREF I 7 CKREF Power down pin

SCL I 8 I2C bus clock input pin

SDA I/O 9 I2C bus data I/O pin

XPD1 I 10 CLK1 Power down pin

XPD2 I 11 CLK2 Power down pin

XPD3 I 12 CLK3 Power down pin

XPD4 I 13 CLK4 Power down pin

CLK2 O 14 Clock output pin 2

VSS ⎯15 GND pin

VDDE ⎯16 Power supply pin (2.6 V)

ENS I 17 Modulation enable pin

CLK3 O 18 Clock output pin 3

CLK4 O 19 Clock output pin 4

VSS ⎯20 GND pin

MB88182

DS04-29138-1E 5

■I/O CIRCUIT TYPE

(Continued)

Pin Circuit type Remarks

XPDREF

XPD1

XPD2

XPD3

XPD4

• CMOS hysteresis input

• With pull-up resistor (20 kΩ)

The pull-up resistor is cut off during

the “L” input.

ENS CMOS hysteresis input

SCL CMOS hysteresis input

SDA • CMOS hysteresis input

• CMOS output

•I

OL = 4 mA

2.6 V

MB88182

6DS04-29138-1E

(Continued)

Pin Circuit type Remarks

CKIN • Feedback resistors 1 MΩ

• Possible to input clock via the cou-

pling capacity

CLK1 • CMOS output

•I

OH = − 2 mA or − 4 mA

•I

OL = 2 mA or 4 mA

(Switchable by the output drive

ability setting bit)

• Operates at 1.8 v or 2.6 v depending

on the part number.

CLK2 • CMOS output

•I

OH = − 2 mA or − 4 mA

•I

OL = 2 mA or 4 mA

(Switchable by the output drive

ability setting bit)

CLK3

CLK4 • CMOS output

• At VDP = 2.6 V ± 0.1 V

IOH = − 2 mA or − 4 mA

IOL = 2 mA or 4 mA

(Switchable by the output drive

ability setting bit)

• At VDP = 1.8 V ± 0.15 V

IOH = − 1 mA or − 2 mA

IOL = 1 mA or 2 mA

1.8 V 1 MΩ

1.8 V

2.6 V

VDP

MB88182

DS04-29138-1E 7

(Continued)

Pin Circuit type Remarks

CKREF • CMOS output

• At VDP = 2.6 V ± 0.1 V

IOH = − 2 mA

IOL = 2 mA

• At VDP = 1.8 V ± 0.15 V

IOH = − 1 mA

IOL = 1 mA

VDP

MB88182

8DS04-29138-1E

■HANDLING DEVICES

(1) Preventing Latch-up

A latch-up can occur if, on this device, (a) a voltage higher than power supply voltage or a voltage lower than

GND is applied to an input or output pin or (b) a v oltage higher than the rating is applied between po w er supply

and GND pins. The latch-up may cause components to burn out because the power supply current increases

significantly. Make sure that the maximum ratings are not exceeded while the device is being used.

(2) Handling unused pins

Leaving un used input pins unconnected ma y cause a malfunction. Handle un used pins b y connecting to a pull-

up or pull-down resistor.

(3) Power supply pins

Ensure that the impedance of the connection from the power supply source to the power supply pins on the

device is as low as possible.

We recommend connecting electrolytic capacitor (about 10 μF) and the ceramic capacitor (about 0.01 μF) in

parallel between power supply and GND near the device, as a bypass capacitor.

MB88182

DS04-29138-1E 9

■BLOCK DIAGRAM

SSCG2

XPD4

XPD3

SSCG1

XPD2

SCL

SDA

CLK4

CLK3

CLK2

PLL

XPD1 CLK1

CKIN

XPDREF

CKREF

ENS

Power down control

Setting to CLK4

Setting to CLK3

Setting to CLK2

Setting to CLK1

Oscillates when setting to the

enable side

I2C circuit

MB88182

10 DS04-29138-1E

■PIN SETTING

ENS Modulation enable setting

When setting 0 to the ENS pin, the spectrum will not spread.

The setting is for CLK2 (SSCG1) and CLK3, and CLK4 (SSCG2).

XPD Power down setting

The pin in XPDREF, XPD1, XPD2, XPD3 and XPD4 is connected to the pull-up resistor.

However, the pull-up resistor is cut off during “0” input.

When both XPD3 and XPD4 are “0”, SSCG2 is in the power down state.

ENS Modulation

0 No modulation

1 (2.6 V) Modulation

XPDREF 0 CKREF is fixed to the output “L”.

1 (2.6 V) CKREF is the clock output.

XPD1 0PLL1 is in the power down state.

CLK1 is fixed to the output “L”.

1 (2.6 V) PLL1 and CLK1 are in operation.

XPD2 0SSCG1 is in the power down state.

CLK2 is fixed to the output “L”.

1 (2.6 V) SSCG1 and CLK2 are in operation.

XPD3 0 CLK3 is fixed to the output “L”.

1 (2.6 V) SSCG2 and CLK3 are in operation.

XPD4 0 CLK4 is fixed to the output “L”.

1 (2.6 V) SSCG2 and CLK4 are in operation.

MB88182

DS04-29138-1E 11

■SETTING REGISTER

Setting register for CLK2, CLK3, CLK4 (All registers have the same configurations.)

CLK1 setting register

Note: The bit's initial value in a register is undefined. Therefore, if the power down of clock output is released before

the register setting, the clock is output with settings unintended. The power down of the clock output for

CLK1, CLK2, CLK3 and CLK4 should be released after setting to registers.

Address Function Remarks

bit0 to 11 M divider setting (12-bit) Selectable in the range of 100 to 3600

bit12 to 22 N divider setting (11-bit) Selectable in the range of 3 to 2047

bit23 to 27 K divider setting (5-bit) Selectable in the range of 1 to 32

bit28 to 30 L divider setting (3-bit) Modulation frequency setting (selectable in the range of 1 to 8)

bit31 to 34 Charge Pump setting (4-bit) Charge pump current setting due to internal oscillation frequency

and M divider setting

bit35 to 40 VCO Gain setting (6-bit) Gain setting due to internal oscillation frequency

bit41 to 43 Modulation rate setting

(3-bit) modulation, off, ± 0.25%, ± 0.50%, ± 0.75%, ± 1.00%,

± 1.25%, ± 1.50%, ± 1.75% are selectable

bit44 Output drive setting 0 : Ability small, 1 : Ability large

bit45 Slewing rate setting 0 : Slewing rate low, 1 : Slewing rate high

bit46, 47 Invalid bit When in writing : The written data is ignored.

When in reading : Undefined

Address Function Remarks

bit0 to 5 M divider setting (6-bit) Selectable in the range of 3 to 52

bit6 to 10 N divider setting (5-bit) Selectable in the range of 3 to 31

bit11 to 15 K divider setting (5-bit) Selectable in the range of 1 to 32

bit16 to 19 Charge Pump setting (4-bit) Charge pump current setting due to internal oscillation frequency

and M divider setting

bit20 to 25 VCO Gain setting (6-bit) Gain setting due to internal oscillation frequency

bit26 Output drive setting 0 : Ability small, 1 : Ability large

bit27 Slewing rate setting 0 : Slewing rate low, 1 : Slewing rate high

bit28 to 31 Invalid bit When in writing : The written data is ignored.

When in reading : Undefined

MB88182

12 DS04-29138-1E

When setting each divider parameter of the oscillator to a register, the output frequency can be set.

Internal oscillation frequency and output frequency can be calculated with following formula:

Internal oscillation frequency (fvco*) = Input frequency (fin) × M/N

* : Please set the fvco range from 16 MHz to 168 MHz.

Output frequency (fout*) = fvco/K

* : Please set the fout range from 8 MHz to 100 MHz.

Set the output frequency to 8 MHz to 50 MHz for CLK3 and CLK4 setting registers when VDP is 1.8 V ± 0.15 V .

(Setting example)

fin : 19.2 MHz, fout : 29.6 MHz

M divider parameter : 222 ( = 0DEH) , N divider parameter : 144 ( = 090H) , K divider par ameter : 1 ( = 01H)

(19.2 × 222 / 144) / 1 = 29.6 (MHz) (fvco : 19.2 × 222 / 144 = 29.6 (MHz) )

Note: The recommended setting value of the VCO gain and the M divider depends on the internal oscillation

frequency.

Also, the recommended setting value of the Charge Pump depends on the setting values of the VCO gain

and the M divider. Please confirm the recommended value with the Fujitsu Microelectronics support tool.

Contact the sales representatives for details on the support tools.

Modulation frequency can be set by writing L divider parameter to the register.

The average of modulation frequency can be calculated with following formula:

(Setting example) fin : 19.2 MHz 19.2 / (266 × 6) × 1000 = Approximately 12.0 (kHz)

Input frequency

266 × L (L = 1, 2, 3, 4, 5, 6, 7, 8)

bit30 bit29 bit28 L divider parameter

000 8

001 1

010 2

011 3

100 4

101 5

110 6

(Recommended value)

111 7

MB88182

DS04-29138-1E 13

Modulation rate can be selectab le from no modulation, ± 0.25%, ± 0.50%, ± 0.75%, ± 1.00%, ± 1.25%, ± 1.50%,

± 1.75%.

Please refer and confirm the recommended value by our support tool. Contact the sales representatives for

details on the support tools.

Output drive ability of clock output pin can be selected.

Slew rate of clock output pin can be selected.

bit43 bit42 bit41 Modulation rate setting

000 No modulation

001 ± 0.25%

010 ± 0.50%

011 ± 0.75%

100 ± 1.00%

101 ± 1.25%

110 ± 1.50%

111 ± 1.75%

bit44 Output drive ability

0Small

1 Large

bit45 Slew rate

0Low

1High

MB88182

14 DS04-29138-1E

■I2C

This de vice contains the I2C macro and enables the sla ve tr ansfer operation. The I2C is set to the corresponding

registers via the I2C bus.

• The transf er rate should be in either standard mode or the fast mode (The high speed mode is not supported) .

• 7-bit address specified (The general call and the 10-bit address specifications are not supported).

: Transmit from master device : Transmit from this device (slave)

S : START condition A : Acknowledge P : STOP condition

When receiving the slave address, the address is compared with the address in the following table. If the sla ve

address matches the address in the table only, I2C judges to access to this device.

“0” : Write to slave device

“1” : Read from slave device

first S6 S0 R/W C7 C0 D7 D0 Last

SSlave address

(7 bit) 0ACommand

(8 bit) ARegister setting

(8 bit) AA

Slave address (7-bit)

S6 S5 S4 S3 S2 S1 S0 Part number

1001111 MB881821APVA1/MB881822APVA1

1011111 MB881821BPVA1/MB881822BPVA1

MB88182

DS04-29138-1E 15

Set for the CLK2, CLK3 and CLK4 setting registers with either individual or successive settings. Settings other

than those in the following table are prohibited.

Transfer data from the upper address. When writing successively to the setting registers of multiple clocks, the

data will be written from the setting registers CLK1, CLK2, CLK3 and to CLK4 in order.

: Transmit from master device : Transmit from this device (slave)

S : START condition A : Acknowledge P : STOP condition

When reading data, the data will be output from the upper address of the CLK1 setting register, then CLK2

setting register, CLK3 setting register, CLK4 setting register, in order. The data will be output 22 bytes in total.

Note: When all outputs in this device are powered do wn, the I2C function also stops. Theref ore , setting b y the I2C

should be performed when the CKREF clock is being output.

Command (8-bit)

C7 C6 C5 C4 C3 C2 C1 C0 Transfer

bytes

00000001 4 Set to CLK1 setting register

00000010 6 Set to CLK2 setting register

00000100 6 Set to CLK3 setting register

00001000 6 Set to CLK4 setting register

00001111 22 Successive set to all registers

0000Other than “0000” or

those above 10 to 18 Successive set to the register

corresponding to the bit which is set “1”.

first S6 S0 R/W D7 D0 D7 D0 Last

SSlave address

(7 bit) 1A

CLK1 setting register

bit31-24 output ACLK1 setting register

bit23-16 output Aoutput register

values A P

MB88182

16 DS04-29138-1E

■ABSOLUTE MAXIMUM RATINGS

* : The parameter is based on VSS = 0.0 V.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Parameter Symbol Pin Rating Unit

Min Max

Power supply voltage*

VDD VDD − 0.5 + 2.5 V

VDDE VDDE − 0.5 + 4.0 V

VDP VDP − 0.5 + 4.0 V

Input voltage* VI

CKIN VSS − 0.5 VDD + 0.5 V

XPDREF,

XPD1, XPD2,

XPD3, XPD4,

SCL, SDA

VSS − 0.5 VDDE + 0.5 V

Output voltage* VO

CLK1 VSS − 0.5 VDD + 0.5 V

CKREF,

CLK2, CLK3,

CLK4, SDA VSS − 0.5 VDDE + 0.5 V

Storage temperature TST ⎯− 55 + 125 °C

Operation junction

temperature TJ⎯− 40 + 125 °C

Output current IO⎯− 13 + 13 mA

Overshoot VIOVER XPDREF,

XPD1, XPD2,

XPD3, XPD4,

SCL, SDA

⎯VDDE + 1.0

(tOVER ≤ 50 ns) V

Undershoot VIUNDER VSS − 1.0

(tUNDER ≤ 50 ns) ⎯V

DDE

Overshoot / Undershoot

Input pin

tunder ≤ 50 ns

VIOVER ≤ VDDE + 1.0 V

tOVER ≤ 50 ns VIUNDER ≤ VSS + 1.0 V

MB88182

DS04-29138-1E 17

■RECOMMENDED OPERATING CONDITIONS

* : Capacity value when clock signal is input to the CKIN pin via coupling capacity.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of

the semiconductor device. All of the device's electrical characteristics are warranted when the

device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented

on the data sheet. Users considering application outside the listed conditions are advised to contact

their representatives beforehand.

Parameter Symbol Pin Condition Value Unit

Min Typ Max

Power supply voltage

VDD VDD ⎯1.65 1.8 1.95

VDDE VDDE ⎯2.5 2.6 2.7

VDP VDP ⎯1.65 1.8 1.95

2.5 2.6 2.7

“H” level input voltage VIH1

CKIN, ENS,

XPDREF,

XPD1, XPD2,

XPD3, XPD4

⎯VDD × 0.8 ⎯VDD + 0.3 V

VIH2 SDA, SCL ⎯VDD × 0.7 ⎯VDD + 0.3

“L” level input voltage VIL1

CKIN, ENS,

XPDREF,

XPD1, XPD2,

XPD3, XPD4

⎯Vss − 0.3 ⎯VDD × 0.2 V

VIL2 SDA, SCL ⎯Vss − 0.3 ⎯VDD × 0.3

Input clock amplitude

level VIC CKIN During clock

input of

capacitive

coupling

0.45 ⎯VDD V p-p

Input coupling capacity CC⎯ *20 ⎯⎯pF

Input clock duty cycle tDCI CKIN 19.2

[MHz] 40 50 60 %

Operating temperature Ta⎯⎯ − 40 ⎯ + 85 °C

VDD/2

CKIN

Input clock duty cycle (tDCI = th/tp)

MB88182

18 DS04-29138-1E

■ELECTRICAL CHARACTERISTICS

• DC Characteristics

(Ta = − 40 °C to + 85 °C, VDD = 1.8 V ± 0.15 V, VDDE = 2.6 V ± 0.1 V, VDP = 2.6 V ± 0.1 V)

(Continued)

Parameter Symbol Pin Conditions Value Unit

Min Typ Max

Power

supply

current

ICC VDD*1CKREF = 19.2 MHz,

CLK1 = 48 MHz*2,

CLK2 = 27 MHz,

CLK3 = 37 MHz,

CLK4 output stop,

output no load,

CKIN direct input

⎯711

ICCE VDDE ⎯0.5 ⎯

ICCP VDP ⎯0.9 ⎯

ICCH VDD When all clock output

disable

⎯250

μAICCEH VDDE ⎯15

ICCPH VDP ⎯15

Output

voltage

VOH1

CLK1*3,

CLK2,

CLK3,

CLK4

Driving ability small setting

“H” level output

IOH = − 2 mA

VDDE − 0.2

VDP − 0.2 ⎯VDDE

VDP

VOL1 Driving ability small setting

“L” level output

IOL = 2 mA VSS ⎯0.2

VOH2 Driving ability large setting

“H” level output

IOH = − 4 mA

VDDE − 0.2

VDP − 0.2 ⎯VDDE

VDP

VOL2 Driving ability large setting

“L” level output

IOL = 4 mA VSS ⎯0.2

VOH1 CKREF

“H” level output

IOL = − 2 mA VDP − 0.2 ⎯VDP V

VOL1 “L” level output

IOL = 2 mA VSS ⎯0.2

VOH3

CLK1*2

Driving ability small setting

“H” level output

IOH = − 2 mA VDD − 0.2 ⎯VDD

VOL3 Driving ability small setting

“L” level output

IOL = 2 mA VSS ⎯0.2

VOH4 Driving ability large setting

“H” level output

IOH = − 4 mA VDD − 0.2 ⎯VDD

VOL4 Driving ability large setting

“L” level output

IOL = 4 mA VSS ⎯0.2

MB88182

DS04-29138-1E 19

(Continued) (Ta = − 40 °C to + 85 °C, VDD = 1.8 V ± 0.15 V, VDDE = 2.6 V ± 0.1 V, VDP = 2.6 V ± 0.1 V)

*1 : Excluding power supply current in the CLK1 output

*2 : Part number: MB881821APVA1/MB881821BPVA1

*3 : Part number: MB881822APVA1/MB881822BPVA1

*4 : The pull up resistor for each pin is cut off when the pin input is in “L” level.

(Ta = − 40 °C to + 85 °C, VDP = 1.8 V ± 0.15 V)

Parameter Symbol Pin Conditions Value Unit

Min Typ Max

Output voltage VOL2 SDA “L” level output

IOL = 4 mA VSS ⎯0.2 V

Pull-up resistance

value*4RPU XPDREF,

XPD1, XPD2,

XPD3, XPD4 VIH = VDDE × 0.8102030kΩ

Input capacitance CIN

CKIN, ENS,

XPDREF,

XPD1, XPD2,

XPD3, XPD4,

SDA, SCL

Ta = + 25 °C

VDD = VDDE = VI = 0 V

f = 1 MHz ⎯⎯10 pF

Parameter Symbol Pin Conditions Value Unit

Min Typ Max

Output voltage

VOH5

CLK3,

CLK4

Driving ability small

setting

“H” level output

IOH = − 1 mA

VDP − 0.2 ⎯VDP

VOL5

Driving ability small

setting

“L” level output

IOL = 1 mA

VSS ⎯0.2

VOH6

Driving ability large

setting

“H” level output

IOH = − 2 mA

VDP − 0.2 ⎯VDP

VOL6

Driving ability large

setting

“L” level output

IOL = 2 mA

VSS ⎯0.2

VOH5 CKREF

“H” level output

IOL = − 1 mA VDP − 0.2 ⎯VDP V

VOL5 “L” level output

IOL = 1 mA VSS ⎯0.2

MB88182

20 DS04-29138-1E

• AC characteristics 1

(Ta = − 40 °C to + 85 °C, VDD = 1.8 V ± 0.15 V, VDDE = 2.6 V ± 0.1 V, VDP = 2.6 V ± 0.1 V)

(Continued)

Parameter Symbol Pin Conditions Value Unit

Min Typ Max

Input frequency fIN CKIN ⎯10 19.2 30 MHz

Output

frequency fOUT

CKREF Load capacitance

15 pF or less 10 19.2 30

MHz

CLK1*1Load capacitance

15 pF or less 8⎯100

CLK1*2,

CLK2,

CLK3,

CLK4

Load capacitance

15 pF or less 8⎯90

Load capacitance

10 pF or less 8⎯100

Output slewing

rate SR CLK1*1

Slewing rate low,

Driving ability small setting

15 pF load capacitance

8 MHz to 70 MHz

0.32 ⎯⎯

V/ns

Slewing rate high,

Driving ability small setting

15 pF load capacitance

8 MHz to 70 MHz

0.33 ⎯⎯

Slewing rate low,

Driving ability large setting

15 pF load capacitance

8 MHz to 80 MHz

0.37 ⎯⎯

Slewing rate high,

Driving ability large setting

15 pF load capacitance

8 MHz to 100 MHz

0.43 ⎯⎯

MB88182

DS04-29138-1E 21

(Ta = − 40 °C to + 85 °C, VDD = 1.8 V ± 0.15 V, VDDE = 2.6 V ± 0.1 V, VDP = 2.6 V ± 0.1 V)

(Continued)

Parameter Symbol Pin Conditions Value Unit

Min Typ Max

Output

slewing rate SR

CLK1*2,

CLK2,

CLK3,

CLK4

Slewing rate low,

Driving ability small setting

15 pF load capacitance

8 MHz to 50 MHz

0.31 ⎯⎯

V/ns

Slewing rate high,

Driving ability small setting

15 pF load capacitance

8 MHz to 60 MHz

0.33 ⎯⎯

Slewing rate low,

Driving ability large setting

15 pF load capacitance

8 MHz to 60 MHz

0.46 ⎯⎯

Slewing rate high,

Driving ability large setting

15 pF load capacitance

8 MHz to 90 MHz

0.50 ⎯⎯

Slewing rate high,

Driving ability large setting

10 pF load capacitance

90 MHz to 100 MHz

0.63 ⎯⎯

CKREF 15 pF load capacitance 0.33 ⎯⎯

Output

impedance ZO

CLK1*1Driving ability small setting ⎯40 ⎯

Driving ability large setting ⎯28 ⎯

CLK1*2Driving ability small setting ⎯60 ⎯

Driving ability large setting ⎯30 ⎯

CLK2,

CLK3,

CLK4

Driving ability small setting ⎯60 ⎯

Driving ability large setting ⎯30 ⎯

CKREF ⎯⎯60 ⎯

MB88182

22 DS04-29138-1E

(Continued) (Ta = − 40 °C to + 85 °C, VDD = 1.8 V ± 0.15 V, VDDE = 2.6 V ± 0.1 V, VDP = 2.6 V ± 0.1 V)

*1 : Part number: MB881821APVA1/MB881821BPVA1

*2 : Part number: MB881822APVA1/MB881822BPVA1

*3 : When K divider parameter = 1 and output frequency is above 50 MHz.

*4 : When K divider parameter ≠ 1, or K divider parameter = 1 and output frequency is 50 MHz or less.

*5 : Duty cycle of the CKREF output depends on the tDCI, input clock duty cycle.

*6 : The wait time for clock stabilization is needed after turning the power on or when changing the setting of ENS/

power down pins. The lock-up time varies depending on the setting value to the respective register. Please

confirm the recommended value with the Fujitsu Microelectronics support tool. Contact the sales representa-

tives for details on the support tools.

Parameter Symbol Pin Conditions Value Unit

Min Typ Max

Output clock

duty cycle tDCC

CLK1*1VDD / 2*340 ⎯60

VDD / 2*445 ⎯55

CLK1*2VDDE / 2*340 ⎯60

VDDE / 2*445 ⎯55

CLK2,

CLK3,

CLK4

VDDE / 2, VDP / 2*340 ⎯60

VDDE / 2, VDP / 2*445 ⎯55

CKREF VDP / 2tDCI − 5*5 ⎯tDCI + 5*5

Modulation

frequency FMOD CLK2,

CLK3,

CLK4 ⎯fin/ (224 × L)

( 224 × L ) fin/ (266 × L)

( 266 × L ) fin/ (308 × L)

( 308 × L ) kHz

(clks)

Lock-up time*6tLK

CLK1 ⎯⎯⎯0.3 ms

CLK2,

CLK3,

CLK4 ⎯⎯⎯16 ms

Cycle-cycle

jitter tJC

CKREF,

CLK1,

CLK2,

CLK3,

CLK4

No load

capacitance ⎯⎯100 ps-rms

CKREF

Power down tRPD CKREF ⎯⎯⎯tP × 2 + 2ns

CKREF

Power down

release tROE CKREF ⎯⎯⎯tP × 2 + 2ns

MB88182

DS04-29138-1E 23

(Ta = − 40 °C to + 85 °C, VDP = 1.8 V ± 0.15 V)

* : Duty cycle of the CKREF output depends on the tDCI, input clock duty cycle.

Parameter Symbol Pin Conditions Value Unit

Min Typ Max

Output

frequency fOUT CLK3,

CLK4

Load capacitance

10 pF or less 8⎯50 MHz

Load capacitance

15 pF or less 8⎯40

Output slewing

rate SR CLK3,

CLK4

Slewing rate low,

Driving ability small setting

15 pF load capacitance

8 MHz to 25 MHz

0.13 ⎯⎯

V/ns

Slewing rate high,

Driving ability small setting

15 pF load capacitance

8 MHz to 30 MHz

0.14 ⎯⎯

Slewing rate low,

Driving ability large setting

15 pF load capacitance

8 MHz to 30 MHz

0.19 ⎯⎯

Slewing rate high,

Driving ability large setting

15 pF load capacitance

8 MHz to 40 MHz

0.22 ⎯⎯

Slewing rate high,

Driving ability large setting

10 pF load capacitance

8 MHz to 50 MHz

0.29 ⎯⎯

CKREF 15 pF load capacitance 0.14 ⎯⎯

Output

impedance ZO

CLK3,

CLK4 Driving ability small setting ⎯80 ⎯

ΩDriving ability large setting ⎯40 ⎯

CKREF ⎯⎯80 ⎯

Output clock

duty cycle tDCC

CLK3,

CLK4 VDP / 245⎯55 %

CKREF VDP / 2tDCI − 5* ⎯tDCI + 5*

CKREF

Power down tRPD CKREF ⎯⎯⎯tP × 2 + 2ns

CKREF

Power down

release tROE CKREF ⎯⎯⎯tP × 2 + 2ns

MB88182

24 DS04-29138-1E

This product contains the modulation period to realize the efficient EMI reduction.

The modulation period FMOD depends on the input frequency and changes between FMOD (Min) and FMOD (Max).

Furthermore, the typical value of the electrical characteristics is equivalent to the average value of the modulation

period FMOD.

<Cycle-cycle jitter (tJC = |tn − tn + 1|)>

MOD

(Min) F

MOD

(Max)

Modulation waveform

Input clock

Clock count

NMOD (Max) Clock count

NMOD (Min)

f (Output frequency)

(VDD − 0.2) V,(VDP − 0.2) V,

(VDDE − 0.2) V

0.2 V

CLK1

CLK2

CLK3

CLK4 t

Note: SR = (power supply voltage − 0.4) / tr, SR = (power supply voltage − 0.4) / tf

n+1

CLK1

CLK2

CLK3

CLK4

MB88182

DS04-29138-1E 25

<Lock-up time>

If the pow er down control is perf ormed on pins XPD1, XPD2, XPD3 and XPD4, the desired clock frequency will

be obtained once the power down pin becomes at the “H” level and after the lock-up time tLK has passed at

maximum.

If the ENS pin setting changes during the normal operation, setting clocks CLK2, CLK3 and CLK4 will be output

once the ENS pin level is decided and after lock-up time tLK has passed at maximum.

Note: When the ENS pin setting is changed, the stabilization wait time is needed f or the output cloc k from CLK2,

CLK3 and CLK4 pins. During the stabilization wait time, the output frequency, output clock duty cycle,

modulation frequency, and cycle-cycle jitter cannot be guaranteed. It is therefore advisable to perform pro-

cessing such as cancelling a reset of the device at the succeeding stage after the lock-up time.

XPDREF

CKREF

XPDREF

CKREF

VIL

VIH

tPtRPD

tROE

CLK1, CLK2,

CLK3, CLK4

CKIN

XPD1, XPD2,

XPD3, XPD4

tLK (lock-up time)

CLK2,

CLK3,CLK4

CKIN

ENSV

tLK

(lock-up time)

tLK

(lock-up time)

MB88182

26 DS04-29138-1E

• AC characteristics 2 (Serial timing) (Ta = − 40 °C to + 85 °C, VDD = 1.8 V ± 0.15 V, VDDE = 2.6 V ± 0.1 V)

Parameter Symbol Pin Conditions Value Unit

Min Max

SCL clock frequency fSCL SCL ⎯0 400 kHz

During data input

set up time tISU SDA ⎯100 ⎯ns

During data input

hold time tIH SDA ⎯0⎯ns

Noise removal width tNC SDA

SCL ⎯100 160 ns

Input hysteresis VHYS SDA

SCL ⎯0.3 ⎯V

(Repeat) START condition

hold time tSTAH SDA

SCL ⎯0.5 ⎯μs

Repeat START condition

setup time tSTASU SDA

SCL ⎯0.5 ⎯μs

SCL clock “L” width tCL SCL ⎯1⎯μs

SCL clock “H” width tCH SCL ⎯0.5 ⎯μs

STOP condition setup time tSTOSU SDA

SCL ⎯0.5 ⎯μs

Bus free time between stop

condition and start condition tBUF SDA

SCL ⎯1⎯μs

During bus drive

set up time tOSU SDA

Bus load: under 400 pF,

Resistor value for bus

pull-up: at least 75 Ω

1⎯μs

During bus drive

hold time tOH SDA 0 0.6 μs

During bus drive

fall time tOF SDA ⎯300 ns

MB88182

DS04-29138-1E 27

ISU

OSU

VDD*0.3

SCL VDD*0.7

SDA

SCL

SDA

tSTASU

tSTAH

tSTOSU

tBUF

• During data input/bus drive

• Noise cancel operation

External SCL

signal

Internal SCL signal

after noise removal

The pulse in the tNC range is

removed.

• (Repeat) Start operation • Stop operation

MB88182

28 DS04-29138-1E

■RECOMMENDED CIRCUIT

2.6 V to 1.8 V

CKIN

CKREF R

1.8 V

CLK1

XPDREF +

SDA

SCL

XPD1

XPD4

XPD3

XPD2

CLK2

2.6 V

ENS

CLK4

CLK3

MB88182

C1, C2, C3 : Capacitor of 10 μF or higher

C4, C5, C6 : Capacitor of about 0.01 μF (connect a capacitor of good high frequency

property (ex. laminated ceramic capacitor) to close to this device)

R1, R2, R3, R4, R5 : Impedance matching resistor for board pattern

R6, R7 : I2C bus Pull-up resistor

MB88182

DS04-29138-1E 29

■CLOCK INPUT VIA COUPLING CAPACITY

It is possible to input cloc ks to the CKIN pin via the coupling capacity as shown in the f ollowing figure. The de vice

input part contains the CMOS inverter and the feedback resistor (1 MΩ). The clock input via the coupling capacity

operates near the threshold level of the CMOS inverter, therefore the current for the capacity connection clock

input increases compared to the normal input.

■ORDERING INFORMATION

Part number Package

MB881821APVA1-GE1

MB881821APVA1-G-ERE1

MB881821APVA1-G-EFE1

MB881821BPVA1-GE1

MB881821BPVA1-G-ERE1

MB881821BPVA1-G-EFE1

MB881822APVA1-GE1

MB881822APVA1-G-ERE1

MB881822APVA1-G-EFE1

MB881822BPVA1-GE1

MB881822BPVA1-G-ERE1

MB881822BPVA1-G-EFE1

20-pin plastic BCC

(LCC-20P-M06)

(1 MΩ)

Input clock

LSI external LSI internal

CKIN pin

Input via

coupling capacity

Clock after the coupling

capacity passes by

MB88182

30 DS04-29138-1E

■PACKAGE DIMENSION

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/package/en-search/

20-pin plastic BCC Lead pitch 0.50 mm

Package width ×

package length 3.50 mm × 3.50 mm

Sealing method Plastic mold

Mounting height 0.60 mm MAX

Weight 0.01 g

20-pin plastic BCC

(LCC-20P-M06)

2004 FUJITSU LIMITED C20057S-c-1-1

0.50±0.10

(.020±.004)

0.50(.020)

TYP.

3.50±0.10

(.138±.004) 0.55±0.050

(.022±.0020)

0.075±0.025

(.003±.001)

(Stand off)

0.05(.002)

1.00(.004)

REF.

"B"

Details of "B" part

(.012±.002)

0.30±0.06

0.20(.008)

INDEX AREA

(.138±.004)

3.50±0.10

(.012±.002)

0.30±0.06

(.016±.002)

0.40±0.06

Details of "A" part

3.00(.118)REF.

0.50(.020)

TYP

0.14(.006)

MIN

17 11

Mount height

"A"

1PIN INDEX

1.55(.061)

0.95

(.037)

2.90(.114)

TYP.

2.90(.114)

0.20(.008)

0.40±0.06

(.016±.002)

1PIN INDEX

Note: The values in parentheses are reference values.

MB88182

DS04-29138-1E 31

MEMO

MB88182

FUJITSU MICROELECTRONICS LIMITED

Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,

Shinjuku-ku, Tokyo 163-0722, Japan

Tel: +81-3-5322-3347 Fax: +81-3-5322-3387

http://jp.fujitsu.com/fml/en/

For further information please contact:

North and South America

FUJITSU MICROELECTRONICS AMERICA, INC.

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94085-5401, U.S.A.

Tel: +1-408-737-5600 Fax: +1-408-737-5999

http://www.fma.fujitsu.com/

Europe

FUJITSU MICROELECTRONICS EUROPE GmbH

Pittlerstrasse 47, 63225 Langen, Germany

Tel: +49-6103-690-0 Fax: +49-6103-690-122

http://emea.fujitsu.com/microelectronics/

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

206 Kosmo Tower Building, 1002 Daechi-Dong,

Gangnam-Gu, Seoul 135-280, Republic of Korea

Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

http://kr.fujitsu.com/fmk/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE. LTD.

151 Lorong Chuan,

#05-08 New Tech Park 556741 Singapore

Tel : +65-6281-0770 Fax : +65-6281-0220

http://www.fmal.fujitsu.com/

FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.

Rm. 3102, Bund Center, No.222 Yan An Road (E),

Shanghai 200002, China

Tel : +86-21-6146-3688 Fax : +86-21-6335-1605

http://cn.fujitsu.com/fmc/

FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.

10/F., World Commerce Centre, 11 Canton Road,

Tsimshatsui, Kowloon, Hong Kong

Tel : +852-2377-0226 Fax : +852-2376-3269

http://cn.fujitsu.com/fmc/en/

Specifications are subject to change without notice. For further information please contact each office.

The contents of this document are subject to change without notice.

Customers are advised to consult with sales representatives before ordering.

The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose

of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS

does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating

the device based on such information, you must assume any responsibility arising out of such use of the information.

FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.

Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use

or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS

or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or

other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result from the use of information contained herein.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured

as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to

the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear

facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon

system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).

Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising

in connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current

levels and other abnormal operating conditions.

Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of

the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.

The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

Edited: Sales Promotion Department