LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash and 8 kB SRAM Rev. 3 -- 10 November 2010 Product data sheet 1. General description The LPC1111/12/13/14 are a ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures. The LPC1111/12/13/14 operate at CPU frequencies of up to 50 MHz. The peripheral complement of the LPC1111/12/13/14 includes up to 32 kB of flash memory, up to 8 kB of data memory, one Fast-mode Plus I2C-bus interface, one RS-485/EIA-485 UART, up to two SPI interfaces with SSP features, four general purpose counter/timers, a 10-bit ADC, and up to 42 general purpose I/O pins. Remark: The LPC1111/12/13/14 series consists of the LPC1100 series (parts LPC111x/101/201/301) and the LPC1100L series (parts LPC111x/102/202/302). The LPC1100L include the power profiles. 2. Features and benefits System: ARM Cortex-M0 processor, running at frequencies of up to 50 MHz. ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC). Serial Wire Debug. System tick timer. Memory: 32 kB (LPC1114), 24 kB (LPC1113), 16 kB (LPC1112), or 8 kB (LPC1111) on-chip flash programming memory. 8 kB, 4 kB, or 2 kB SRAM. In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software. Digital peripherals: Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors. GPIO pins can be used as edge and level sensitive interrupt sources. High-current output driver (20 mA) on one pin. High-current sink drivers (20 mA) on two I2C-bus pins in Fast-mode Plus. Four general purpose counter/timers with a total of four capture inputs and 13 match outputs. Programmable WatchDog Timer (WDT). LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Analog peripherals: 10-bit ADC with input multiplexing among 8 pins. Serial interfaces: UART with fractional baud rate generation, internal FIFO, and RS-485 support. Two SPI controllers with SSP features and with FIFO and multi-protocol capabilities (second SPI on LQFP48 and PLCC44 packages only). I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a data rate of 1 Mbit/s with multiple address recognition and monitor mode. Clock generation: 12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a system clock. Crystal oscillator with an operating range of 1 MHz to 25 MHz. Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz. PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator or the internal RC oscillator. Clock output function with divider that can reflect the system oscillator clock, IRC clock, CPU clock, and the Watchdog clock. Power control: Integrated PMU (Power Management Unit) to minimize power consumption during Sleep, Deep-sleep, and Deep power-down modes. Power profiles residing in boot ROM allowing to optimize performance and minimize power consumption for any given application through one simple function call. (LPC1100L series, on LPC111x/102/202/302 only.) Three reduced power modes: Sleep, Deep-sleep, and Deep power-down. Processor wake-up from Deep-sleep mode via a dedicated start logic using up to 13 of the functional pins. Power-On Reset (POR). Brownout detect with four separate thresholds for interrupt and forced reset. Unique device serial number for identification. Single power supply (1.8 V to 3.6 V). Available as 48-pin LQFP package, 33-pin HVQFN package, and 44-pin PLCC package. 3. Applications eMetering Alarm systems LPC1111_12_13_14 Product data sheet Lighting White goods All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 2 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 4. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC1111FHN33/101 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm n/a LPC1111FHN33/102 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm n/a LPC1111FHN33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm n/a LPC1111FHN33/202 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm n/a LPC1112FHN33/101 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm n/a LPC1112FHN33/102 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm n/a LPC1112FHN33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm n/a LPC1112FHN33/202 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm n/a LPC1113FHN33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm n/a LPC1113FHN33/202 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm n/a LPC1113FHN33/301 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm n/a LPC1113FHN33/302 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm n/a LPC1114FHN33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm n/a LPC1114FHN33/202 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm n/a LPC1114FHN33/301 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm n/a LPC1114FHN33/302 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm n/a LPC1113FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x sot313-2 1.4 mm LPC1113FBD48/302 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x sot313-2 1.4 mm LPC1114FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x sot313-2 1.4 mm LPC1114FBD48/302 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x sot313-2 1.4 mm LPC1114FA44/301[1] PLCC44 PLCC44; plastic leaded chip carrier; 44 leads sot187-2 LPC1114FA44/302[1] PLCC44 PLCC44; plastic leaded chip carrier; 44 leads sot187-2 [1] Sampling in Q2 2011. LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 3 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 4.1 Ordering options Table 2. Ordering options Series Flash Total SRAM Power profiles UART I2C/ SPI ADC Package RS-485 Fast+ channels LPC1111FHN33/101 LPC1100 8 kB 2 kB no 1 1 1 8 HVQFN33 LPC1111FHN33/102 LPC1100L 8 kB 2 kB yes 1 1 1 8 HVQFN33 LPC1111FHN33/201 LPC1100 8 kB 4 kB no 1 1 1 8 HVQFN33 LPC1111FHN33/202 LPC1100L 8 kB 4 kB yes 1 1 1 8 HVQFN33 LPC1112FHN33/101 LPC1100 16 kB 2 kB no 1 1 1 8 HVQFN33 LPC1112FHN33/102 LPC1100L 16 kB 2 kB yes 1 1 1 8 HVQFN33 Type number LPC1111 LPC1112 LPC1112FHN33/201 LPC1100 16 kB 4 kB no 1 1 1 8 HVQFN33 LPC1112FHN33/202 LPC1100L 16 kB 4 kB yes 1 1 1 8 HVQFN33 LPC1113FHN33/201 LPC1100 24 kB 4 kB no 1 1 1 8 HVQFN33 LPC1113FHN33/202 LPC1100L 24 kB 4 kB yes 1 1 1 8 HVQFN33 LPC1113FHN33/301 LPC1100 24 kB 8 kB no 1 1 1 8 HVQFN33 LPC1113FHN33/302 LPC1100L 24 kB 8 kB yes 1 1 1 8 HVQFN33 LPC1113FBD48/301 LPC1100 24 kB 8 kB no 1 1 2 8 LQFP48 LPC1113FBD48/302 LPC1100L 24 kB 8 kB yes 1 1 2 8 LQFP48 LPC1114FHN33/201 LPC1100 32 kB 4 kB no 1 1 1 8 HVQFN33 LPC1114FHN33/202 LPC1100L 32 kB 4 kB yes 1 1 1 8 HVQFN33 LPC1113 LPC1114 LPC1114FHN33/301 LPC1100 32 kB 8 kB no 1 1 1 8 HVQFN33 LPC1114FHN33/302 LPC1100L 32 kB 8 kB yes 1 1 1 8 HVQFN33 LPC1114FBD48/301 LPC1100 32 kB 8 kB no 1 1 2 8 LQFP48 LPC1114FBD48/302 LPC1100L 32 kB 8 kB yes 1 1 2 8 LQFP48 LPC1114FA44/301[1] LPC1100 32 kB 8 kB no 1 1 2 8 PLCC44 LPC1114FA44/302[1] LPC1100L 32 kB 8 kB yes 1 1 2 8 PLCC44 [1] Sampling in Q2 2011. LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 4 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 5. Block diagram XTALIN XTALOUT RESET SWD LPC1111/12/13/14 IRC TEST/DEBUG INTERFACE CLOCK GENERATION, POWER CONTROL, SYSTEM FUNCTIONS POR ARM CORTEX-M0 system bus clocks and controls FLASH 8/16/24/32 kB slave GPIO ports PIO0/1/2/3 HIGH-SPEED GPIO CLKOUT SRAM 2/4/8 kB slave ROM slave slave AHB-LITE BUS slave AHB TO APB BRIDGE RXD TXD DTR, DSR(1), CTS, DCD(1), RI(1), RTS CT32B0_MAT[3:0] CT32B0_CAP0 CT32B1_MAT[3:0] CT32B1_CAP0 CT16B0_MAT[2:0] CT16B0_CAP0 CT16B1_MAT[1:0] CT16B1_CAP0 UART AD[7:0] 10-bit ADC SPI0 SCK0, SSEL0 MISO0, MOSI0 SPI1(1) SCK1, SSEL1 MISO1, MOSI1 32-bit COUNTER/TIMER 0 32-bit COUNTER/TIMER 1 SCL SDA I2C-BUS 16-bit COUNTER/TIMER 0 WDT 16-bit COUNTER/TIMER 1 IOCONFIG SYSTEM CONTROL PMU 002aae696 (1) LQFP48 and PLCC44 packages only. Fig 1. LPC1111/12/13/14 block diagram LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 5 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 6. Pinning information 37 PIO3_1/DSR 38 PIO2_3/RI/MOSI1 39 SWDIO/PIO1_3/AD4/CT32B1_MAT2 40 PIO1_4/AD5/CT32B1_MAT3/WAKEUP 41 VSS 42 PIO1_11/AD7 43 PIO3_2/DCD 44 VDD 45 PIO1_5/RTS/CT32B0_CAP0 46 PIO1_6/RXD/CT32B0_MAT0 PIO2_6 1 36 PIO3_0/DTR PIO2_0/DTR/SSEL1 2 35 R/PIO1_2/AD3/CT32B1_MAT1 RESET/PIO0_0 3 34 R/PIO1_1/AD2/CT32B1_MAT0 PIO0_1/CLKOUT/CT32B0_MAT2 4 33 R/PIO1_0/AD1/CT32B1_CAP0 VSS 5 XTALIN 6 XTALOUT 7 VDD 8 PIO1_8/CT16B1_CAP0 9 28 PIO0_9/MOSI0/CT16B0_MAT1 PIO0_2/SSEL0/CT16B0_CAP0 10 27 PIO0_8/MISO0/CT16B0_MAT0 32 R/PIO0_11/AD0/CT32B0_MAT3 LPC1113FBD48/301 LPC1113FBD48/302 LPC1114FBD48/301 LPC1114FBD48/302 31 PIO2_11/SCK0 30 PIO1_10/AD6/CT16B1_MAT1 29 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO2_9 24 PIO0_7/CTS 23 PIO0_6/SCK0 22 PIO3_5 21 PIO2_5 20 PIO2_4 19 PIO3_4 18 PIO1_9/CT16B1_MAT0 17 PIO0_5/SDA 16 25 PIO2_10 PIO0_4/SCL 15 26 PIO2_2/DCD/MISO1 PIO2_8 12 PIO0_3 14 PIO2_7 11 PIO2_1/DSR/SCK1 13 Fig 2. 47 PIO1_7/TXD/CT32B0_MAT1 48 PIO3_3/RI 6.1 Pinning 002aae697 Pin configuration LQFP48 package LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 6 of 65 LPC1111/12/13/14 NXP Semiconductors 40 PIO2_3/RI/MOSI1 41 SWDIO/PIO1_3/AD4/CT32B1_MAT2 42 PIO1_4/AD5/CT32B1_MAT3/WAKEUP 43 VSS VDD 1 44 PIO1_11/AD7 PIO1_6/RXD/CT32B0_MAT0 PIO1_5/RTS/CT32B0_CAP0 PIO1_7/TXD/CT32B0_MAT1 4 2 PIO2_6 5 3 PIO2_0/DTR/SSEL1 6 32-bit ARM Cortex-M0 microcontroller RESET/PIO0_0 7 39 R/PIO1_2/AD3/CT32B1_MAT1 PIO0_1/CLKOUT/CT32B0_MAT2 8 38 R/PIO1_1/AD2/CT32B1_MAT0 VSS 9 37 R/PIO1_0/AD1/CT32B1_CAP0 XTALIN 10 36 R/PIO0_11/AD0/CT32B0_MAT3 XTALOUT 11 35 PIO2_11/SCK0 LPC1114FA44/301 LPC1114FA44/302 VDD 12 34 PIO1_10/AD6/CT16B1_MAT1 PIO1_8/CT16B1_CAP0 13 33 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO0_2/SSEL0/CT16B0_CAP0 14 32 PIO0_9/MOSI0/CT16B0_MAT1 PIO2_7 15 31 PIO0_8/MISO0/CT16B0_MAT0 PIO2_8 16 30 PIO2_2/DCD/MISO1 PIO2_1/DSR/SCK1 17 PIO2_9 28 PIO0_7/CTS 27 PIO3_5 25 PIO0_6/SCK0 26 PIO2_5 24 PIO2_4 23 PIO3_4 22 PIO1_9/CT16B1_MAT0 21 PIO0_5/SDA 20 PIO0_3 18 Fig 3. PIO0_4/SCL 19 29 PIO2_10 002aaf020 Pin configuration PLCC44 package LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 7 of 65 LPC1111/12/13/14 NXP Semiconductors VDD PIO3_2 PIO1_11/AD7 PIO1_4/AD5/CT32B1_MAT3/WAKEUP SWDIO/PIO1_3/AD4/CT32B1_MAT2 27 26 25 PIO1_5/RTS/CT32B0_CAP0 28 PIO1_6/RXD/CT32B0_MAT0 30 29 PIO1_7/TXD/CT32B0_MAT1 31 terminal 1 index area 32 32-bit ARM Cortex-M0 microcontroller PIO2_0/DTR 1 24 R/PIO1_2/AD3/CT32B1_MAT1 RESET/PIO0_0 2 23 R/PIO1_1/AD2/CT32B1_MAT0 PIO0_1/CLKOUT/CT32B0_MAT2 3 22 R/PIO1_0/AD1/CT32B1_CAP0 XTALIN 4 21 R/PIO0_11/AD0/CT32B0_MAT3 XTALOUT 5 20 PIO1_10/AD6/CT16B1_MAT1 VDD 6 19 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO1_8/CT16B1_CAP0 7 18 PIO0_9/MOSI0/CT16B0_MAT1 PIO0_2/SSEL0/CT16B0_CAP0 8 17 PIO0_8/MISO0/CT16B0_MAT0 9 10 11 12 13 14 15 16 PIO0_3 PIO0_4/SCL PIO0_5/SDA PIO1_9/CT16B1_MAT0 PIO3_4 PIO3_5 PIO0_6/SCK0 PIO0_7/CTS 33 VSS 002aae698 Transparent top view Fig 4. Pin configuration HVQFN 33 package LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 8 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 6.2 Pin description Table 3. LPC1113/14 pin description table (LQFP48 package) Symbol Pin Start logic input PIO0_0 to PIO0_11 RESET/PIO0_0 PIO0_1/CLKOUT/ CT32B0_MAT2 Type Reset Description state [1] I/O 3[2] 4[3] yes yes Port 0 -- Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block. I I; PU RESET -- External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. I/O - PIO0_0 -- General purpose digital input/output pin with 10 ns glitch filter. I/O I; PU PIO0_1 -- General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler. O - CLKOUT -- Clockout pin. O - CT32B0_MAT2 -- Match output 2 for 32-bit timer 0. I/O I; PU PIO0_2 -- General purpose digital input/output pin. I/O - SSEL0 -- Slave Select for SPI0. PIO0_2/SSEL0/ CT16B0_CAP0 10[3] I - CT16B0_CAP0 -- Capture input 0 for 16-bit timer 0. PIO0_3 14[3] yes I/O I; PU PIO0_3 -- General purpose digital input/output pin. PIO0_4/SCL 15[4] yes I/O I; IA PIO0_4 -- General purpose digital input/output pin (open-drain). I/O - SCL -- I2C-bus, open-drain clock input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. I/O I; IA PIO0_5 -- General purpose digital input/output pin (open-drain). I/O - SDA -- I2C-bus, open-drain data input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. PIO0_5/SDA PIO0_6/SCK0 16[4] 22[3] yes yes yes PIO0_7/CTS 23[3] yes PIO0_8/MISO0/ CT16B0_MAT0 27[3] yes PIO0_9/MOSI0/ CT16B0_MAT1 28[3] LPC1111_12_13_14 Product data sheet yes I/O I; PU PIO0_6 -- General purpose digital input/output pin. I/O - SCK0 -- Serial clock for SPI0. I/O I; PU PIO0_7 -- General purpose digital input/output pin (high-current output driver). I - CTS -- Clear To Send input for UART. I/O I; PU PIO0_8 -- General purpose digital input/output pin. I/O - MISO0 -- Master In Slave Out for SPI0. O - CT16B0_MAT0 -- Match output 0 for 16-bit timer 0. I/O I; PU PIO0_9 -- General purpose digital input/output pin. I/O - MOSI0 -- Master Out Slave In for SPI0. O - CT16B0_MAT1 -- Match output 1 for 16-bit timer 0. All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 9 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 3. LPC1113/14 pin description table (LQFP48 package) ...continued Symbol Pin SWCLK/PIO0_10/ SCK0/ CT16B0_MAT2 29[3] R/PIO0_11/ AD0/CT32B0_MAT3 32[5] Start logic input Type yes I I; PU SWCLK -- Serial wire clock. I/O - PIO0_10 -- General purpose digital input/output pin. I/O - SCK0 -- Serial clock for SPI0. O - CT16B0_MAT2 -- Match output 2 for 16-bit timer 0. I I; PU R -- Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO0_11 -- General purpose digital input/output pin. I - AD0 -- A/D converter, input 0. O - CT32B0_MAT3 -- Match output 3 for 32-bit timer 0. yes PIO1_0 to PIO1_11 R/PIO1_0/ AD1/CT32B1_CAP0 R/PIO1_1/ AD2/CT32B1_MAT0 R/PIO1_2/ AD3/CT32B1_MAT1 SWDIO/PIO1_3/ AD4/CT32B1_MAT2 PIO1_4/AD5/ CT32B1_MAT3/ WAKEUP LPC1111_12_13_14 Product data sheet Reset Description state [1] I/O 33[5] 34[5] 35[5] 39[5] 40[5] yes no no no no Port 1 -- Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block. I I; PU R -- Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_0 -- General purpose digital input/output pin. I - AD1 -- A/D converter, input 1. I - CT32B1_CAP0 -- Capture input 0 for 32-bit timer 1. O I; PU R -- Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_1 -- General purpose digital input/output pin. I - AD2 -- A/D converter, input 2. O - CT32B1_MAT0 -- Match output 0 for 32-bit timer 1. I I; PU R -- Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_2 -- General purpose digital input/output pin. I - AD3 -- A/D converter, input 3. O - CT32B1_MAT1 -- Match output 1 for 32-bit timer 1. I/O I; PU SWDIO -- Serial wire debug input/output. I/O - PIO1_3 -- General purpose digital input/output pin. I - AD4 -- A/D converter, input 4. O - CT32B1_MAT2 -- Match output 2 for 32-bit timer 1. I/O I; PU PIO1_4 -- General purpose digital input/output pin with 10 ns glitch filter. I - AD5 -- A/D converter, input 5. O - CT32B1_MAT3 -- Match output 3 for 32-bit timer 1. I - WAKEUP -- Deep power-down mode wake-up pin with 20 ns glitch filter. This pin must be pulled HIGH externally to enter Deep power-down mode and pulled LOW to exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part. All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 10 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 3. LPC1113/14 pin description table (LQFP48 package) ...continued Symbol PIO1_5/RTS/ CT32B0_CAP0 Pin 45[3] PIO1_6/RXD/ CT32B0_MAT0 46[3] PIO1_7/TXD/ CT32B0_MAT1 47[3] PIO1_8/ CT16B1_CAP0 9[3] PIO1_9/ CT16B1_MAT0 17[3] PIO1_10/AD6/ CT16B1_MAT1 30[5] PIO1_11/AD7 42[5] Start logic input Type no I/O no no no no no no PIO2_0 to PIO2_11 PIO2_0/DTR/SSEL1 PIO2_1/DSR/SCK1 PIO2_2/DCD/MISO1 PIO2_3/RI/MOSI1 Reset Description state [1] I; PU O - RTS -- Request To Send output for UART. I - CT32B0_CAP0 -- Capture input 0 for 32-bit timer 0. I/O I; PU PIO1_6 -- General purpose digital input/output pin. I - RXD -- Receiver input for UART. O - CT32B0_MAT0 -- Match output 0 for 32-bit timer 0. I/O I; PU PIO1_7 -- General purpose digital input/output pin. O - TXD -- Transmitter output for UART. O - CT32B0_MAT1 -- Match output 1 for 32-bit timer 0. I/O I; PU PIO1_8 -- General purpose digital input/output pin. I - CT16B1_CAP0 -- Capture input 0 for 16-bit timer 1. I/O I; PU PIO1_9 -- General purpose digital input/output pin. O - CT16B1_MAT0 -- Match output 0 for 16-bit timer 1. I/O I; PU PIO1_10 -- General purpose digital input/output pin. I - AD6 -- A/D converter, input 6. O - CT16B1_MAT1 -- Match output 1 for 16-bit timer 1. I/O I; PU PIO1_11 -- General purpose digital input/output pin. I - AD7 -- A/D converter, input 7. I/O 2[3] 13[3] 26[3] 38[3] no no no no PIO1_5 -- General purpose digital input/output pin. Port 2 -- Port 2 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 2 pins depends on the function selected through the IOCONFIG register block. I/O I; PU PIO2_0 -- General purpose digital input/output pin. O - DTR -- Data Terminal Ready output for UART. I/O - SSEL1 -- Slave Select for SPI1. I/O I; PU PIO2_1 -- General purpose digital input/output pin. I - DSR -- Data Set Ready input for UART. I/O - SCK1 -- Serial clock for SPI1. I/O I; PU PIO2_2 -- General purpose digital input/output pin. I - DCD -- Data Carrier Detect input for UART. I/O - MISO1 -- Master In Slave Out for SPI1. I/O I; PU PIO2_3 -- General purpose digital input/output pin. I - RI -- Ring Indicator input for UART. I/O - MOSI1 -- Master Out Slave In for SPI1. PIO2_4 19[3] no I/O I; PU PIO2_4 -- General purpose digital input/output pin. PIO2_5 20[3] no I/O I; PU PIO2_5 -- General purpose digital input/output pin. PIO2_6 1[3] no I/O I; PU PIO2_6 -- General purpose digital input/output pin. PIO2_7 11[3] no I/O I; PU PIO2_7 -- General purpose digital input/output pin. PIO2_8 12[3] no I/O I; PU PIO2_8 -- General purpose digital input/output pin. PIO2_9 24[3] no I/O I; PU PIO2_9 -- General purpose digital input/output pin. LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 11 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 3. LPC1113/14 pin description table (LQFP48 package) ...continued Symbol Pin Start logic input Type I/O PIO2_10 25[3] no PIO2_11/SCK0 31[3] no PIO3_0 to PIO3_5 Reset Description state [1] I; PU PIO2_10 -- General purpose digital input/output pin. I/O I; PU PIO2_11 -- General purpose digital input/output pin. I/O - SCK0 -- Serial clock for SPI0. I/O PIO3_0/DTR 36[3] PIO3_1/DSR 37[3] PIO3_2/DCD 43[3] PIO3_3/RI 48[3] no no no no Port 3 -- Port 3 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 3 pins depends on the function selected through the IOCONFIG register block. Pins PIO3_6 to PIO3_11 are not available. I/O I; PU PIO3_0 -- General purpose digital input/output pin. O - DTR -- Data Terminal Ready output for UART. I/O I; PU PIO3_1 -- General purpose digital input/output pin. I - DSR -- Data Set Ready input for UART. I/O I; PU PIO3_2 -- General purpose digital input/output pin. I - DCD -- Data Carrier Detect input for UART. I/O I; PU PIO3_3 -- General purpose digital input/output pin. I - RI -- Ring Indicator input for UART. PIO3_4 18[3] no I/O I; PU PIO3_4 -- General purpose digital input/output pin. PIO3_5 21[3] no I/O I; PU PIO3_5 -- General purpose digital input/output pin. VDD 8; 44 - I - 3.3 V supply voltage to the internal regulator, the external rail, and the ADC. Also used as the ADC reference voltage. XTALIN 6[6] - I - Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. XTALOUT 7[6] - O - Output from the oscillator amplifier. VSS 5; 41 - I - Ground. [1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled. [2] See Figure 32 for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. [3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 31). [4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. [5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 31). [6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 12 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 4. LPC1114 pin description table (PLCC44 package) Symbol Pin Start Type Reset Description logic state [1] input PIO0_0 to PIO0_11 RESET/PIO0_0 PIO0_1/CLKOUT/ CT32B0_MAT2 I/O 7[2] 8[3] yes yes Port 0 -- Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block. I I; PU RESET -- External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states and processor execution to begin at address 0. I/O - PIO0_0 -- General purpose digital input/output pin with 10 ns glitch filter. I/O I; PU PIO0_1 -- General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler. O - CLKOUT -- Clockout pin. O - CT32B0_MAT2 -- Match output 2 for 32-bit timer 0. I/O I; PU PIO0_2 -- General purpose digital input/output pin. I/O - SSEL0 -- Slave Select for SPI0. PIO0_2/SSEL0/ CT16B0_CAP0 14[3] I - CT16B0_CAP0 -- Capture input 0 for 16-bit timer 0. PIO0_3 18[3] yes I/O I; PU PIO0_3 -- General purpose digital input/output pin. PIO0_4/SCL 19[4] I/O I; PU PIO0_4 -- General purpose digital input/output pin (open-drain). I/O - SCL -- I2C-bus, open-drain clock input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. I/O I; PU PIO0_5 -- General purpose digital input/output pin (open-drain). I/O - SDA -- I2C-bus, open-drain data input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. I/O I; PU PIO0_6 -- General purpose digital input/output pin. I/O - SCK0 -- Serial clock for SPI0. I/O I; PU PIO0_7 -- General purpose digital input/output pin (high-current output driver). I - CTS -- Clear To Send input for UART. I/O I; PU PIO0_8 -- General purpose digital input/output pin. I/O - MISO0 -- Master In Slave Out for SPI0. O - CT16B0_MAT0 -- Match output 0 for 16-bit timer 0. I/O I; PU PIO0_9 -- General purpose digital input/output pin. I/O - MOSI0 -- Master Out Slave In for SPI0. O - CT16B0_MAT1 -- Match output 1 for 16-bit timer 0. PIO0_5/SDA yes yes 20[4] yes PIO0_6/SCK0 26[3] yes PIO0_7/CTS 27[3] PIO0_8/MISO0/ CT16B0_MAT0 31[3] PIO0_9/MOSI0/ CT16B0_MAT1 32[3] yes SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 33[3] LPC1111_12_13_14 Product data sheet yes yes yes I I; PU SWCLK -- Serial wire clock. I/O - PIO0_10 -- General purpose digital input/output pin. I/O - SCK0 -- Serial clock for SPI0. O - CT16B0_MAT2 -- Match output 2 for 16-bit timer 0. All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 13 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 4. LPC1114 pin description table (PLCC44 package) ...continued Symbol Pin Start Type Reset Description logic state [1] input R/PIO0_11/ AD0/CT32B0_MAT3 36[5] yes - I; PU R -- Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO0_11 -- General purpose digital input/output pin. I - AD0 -- A/D converter, input 0. O - CT32B0_MAT3 -- Match output 3 for 32-bit timer 0. PIO1_0 to PIO1_11 R/PIO1_0/ AD1/CT32B1_CAP0 R/PIO1_1/ AD2/CT32B1_MAT0 R/PIO1_2/ AD3/CT32B1_MAT1 SWDIO/PIO1_3/AD4/ CT32B1_MAT2 PIO1_4/AD5/ CT32B1_MAT3/ WAKEUP Port 1 -- Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block. 37[5] yes 38[5] 39[5] no 41[5] 42[5] PIO1_5/RTS/ CT32B0_CAP0 2[3] PIO1_6/RXD/ CT32B0_MAT0 3[3] LPC1111_12_13_14 Product data sheet no no no no no - I; PU R -- Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_0 -- General purpose digital input/output pin. I - AD1 -- A/D converter, input 1. I - CT32B1_CAP0 -- Capture input 0 for 32-bit timer 1. - I; PU R -- Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_1 -- General purpose digital input/output pin. I - AD2 -- A/D converter, input 2. O - CT32B1_MAT0 -- Match output 0 for 32-bit timer 1. - I; PU R -- Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_2 -- General purpose digital input/output pin. I - AD3 -- A/D converter, input 3. O - CT32B1_MAT1 -- Match output 1 for 32-bit timer 1. I/O I; PU SWDIO -- Serial wire debug input/output. I/O - PIO1_3 -- General purpose digital input/output pin. I - AD4 -- A/D converter, input 4. O - CT32B1_MAT2 -- Match output 2 for 32-bit timer 1. I/O I; PU PIO1_4 -- General purpose digital input/output pin with 10 ns glitch filter. I - AD5 -- A/D converter, input 5. O - CT32B1_MAT3 -- Match output 3 for 32-bit timer 1. I - WAKEUP -- Deep power-down mode wake-up pin with 20 ns glitch filter. This pin must be pulled HIGH externally to enter Deep power-down mode and pulled LOW to exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part. I/O I; PU PIO1_5 -- General purpose digital input/output pin. O - RTS -- Request To Send output for UART. I - CT32B0_CAP0 -- Capture input 0 for 32-bit timer 0. I/O I; PU PIO1_6 -- General purpose digital input/output pin. I - RXD -- Receiver input for UART. O - CT32B0_MAT0 -- Match output 0 for 32-bit timer 0. All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 14 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 4. LPC1114 pin description table (PLCC44 package) ...continued Symbol Pin Start Type Reset Description logic state [1] input PIO1_7/TXD/ CT32B0_MAT1 4[3] no PIO1_8/CT16B1_CAP0 13[3] PIO1_9/CT16B1_MAT0 21[3] no no PIO1_10/AD6/ CT16B1_MAT1 34[5] no PIO1_11/AD7 44[5] no PIO2_0 to PIO2_11 PIO2_0/DTR/SSEL1 PIO2_1/DSR/SCK1 PIO2_2/DCD/MISO1 PIO2_3/RI/MOSI1 I/O I; PU PIO1_7 -- General purpose digital input/output pin. O - TXD -- Transmitter output for UART. O - CT32B0_MAT1 -- Match output 1 for 32-bit timer 0. I/O I; PU PIO1_8 -- General purpose digital input/output pin. I - CT16B1_CAP0 -- Capture input 0 for 16-bit timer 1. I/O I; PU PIO1_9 -- General purpose digital input/output pin. O - CT16B1_MAT0 -- Match output 0 for 16-bit timer 1. I/O I; PU PIO1_10 -- General purpose digital input/output pin. I - AD6 -- A/D converter, input 6. O - CT16B1_MAT1 -- Match output 1 for 16-bit timer 1. I/O I; PU PIO1_11 -- General purpose digital input/output pin. I - AD7 -- A/D converter, input 7. I/O 6[3] no 17[3] no 30[3] 40[3] no no Port 2 -- Port 2 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 2 pins depends on the function selected through the IOCONFIG register block. I/O I; PU PIO2_0 -- General purpose digital input/output pin. O - DTR -- Data Terminal Ready output for UART. I/O - SSEL1 -- Slave Select for SPI1. I/O I; PU PIO2_1 -- General purpose digital input/output pin. I - DSR -- Data Set Ready input for UART. I/O - SCK1 -- Serial clock for SPI1. I/O I; PU PIO2_2 -- General purpose digital input/output pin. I - DCD -- Data Carrier Detect input for UART. I/O - MISO1 -- Master In Slave Out for SPI1. I/O I; PU PIO2_3 -- General purpose digital input/output pin. I - RI -- Ring Indicator input for UART. I/O - MOSI1 -- Master Out Slave In for SPI1. PIO2_4 23[3] no I/O I; PU PIO2_4 -- General purpose digital input/output pin. PIO2_5 24[3] no I/O I; PU PIO2_5 -- General purpose digital input/output pin. PIO2_6 5[3] no I/O I; PU PIO2_6 -- General purpose digital input/output pin. PIO2_7 15[3] no I/O I; PU PIO2_7 -- General purpose digital input/output pin. PIO2_8 16[3] no I/O I; PU PIO2_8 -- General purpose digital input/output pin. PIO2_9 28[3] no I/O I; PU PIO2_9 -- General purpose digital input/output pin. PIO2_10 29[3] no I/O I; PU PIO2_10 -- General purpose digital input/output pin. PIO2_11/SCK0 35[3] no I/O I; PU PIO2_11 -- General purpose digital input/output pin. PIO3_0 to PIO3_5 PIO3_4 LPC1111_12_13_14 Product data sheet 22[3] no I/O SCK0 -- Serial clock for SPI0. I/O Port 3 -- Port 3 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 3 pins depends on the function selected through the IOCONFIG register block. Pins PIO3_0 to PIO3_3 and PIO3_6 to PIO3_11 are not available. I/O I; PU PIO3_4 -- General purpose digital input/output pin. All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 15 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 4. LPC1114 pin description table (PLCC44 package) ...continued Symbol Pin Start Type Reset Description logic state [1] input PIO3_5 25[3] no I/O I; PU PIO3_5 -- General purpose digital input/output pin. VDD 1; 12 - I - 3.3 V supply voltage to the internal regulator, the external rail, and the ADC. Also used as the ADC reference voltage. XTALIN 10[6] - I - Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. XTALOUT 11[6] VSS 9; 43 - - O - Output from the oscillator amplifier. I - Ground. [1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled. [2] See Figure 32 for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. [3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 31). [4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. [5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 31). [6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. Table 5. LPC1111/12/13/14 pin description table (HVQFN33 package) Symbol Pin Start Type logic input Reset Description state [1] PIO0_0 to PIO0_11 RESET/PIO0_0 PIO0_1/CLKOUT/ CT32B0_MAT2 PIO0_2/SSEL0/ CT16B0_CAP0 Port 0 -- Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block. 2[2] 3[3] 8[3] yes yes yes I I;PU RESET -- External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states and processor execution to begin at address 0. I/O - PIO0_0 -- General purpose digital input/output pin with 10 ns glitch filter. I/O I;PU PIO0_1 -- General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler. O - CLKOUT -- Clock out pin. O - CT32B0_MAT2 -- Match output 2 for 32-bit timer 0. I/O I;PU PIO0_2 -- General purpose digital input/output pin. I/O - SSEL0 -- Slave select for SPI0. I - CT16B0_CAP0 -- Capture input 0 for 16-bit timer 0. PIO0_3 9[3] yes I/O I;PU PIO0_3 -- General purpose digital input/output pin. PIO0_4/SCL 10[4] yes I/O I;PU PIO0_4 -- General purpose digital input/output pin (open-drain). I/O - SCL -- I2C-bus, open-drain clock input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 16 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 5. LPC1111/12/13/14 pin description table (HVQFN33 package) ...continued Symbol PIO0_5/SDA Pin 11[4] PIO0_6/SCK0 15[3] PIO0_7/CTS 16[3] PIO0_8/MISO0/ CT16B0_MAT0 17[3] PIO0_9/MOSI0/ CT16B0_MAT1 18[3] SWCLK/PIO0_10/ SCK0/ CT16B0_MAT2 19[3] R/PIO0_11/AD0/ CT32B0_MAT3 21[5] Start Type logic input Reset Description state yes I/O I;PU PIO0_5 -- General purpose digital input/output pin (open-drain). I/O - SDA -- I2C-bus, open-drain data input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. I/O I;PU PIO0_6 -- General purpose digital input/output pin. I/O - SCK0 -- Serial clock for SPI0. I/O I;PU PIO0_7 -- General purpose digital input/output pin (high-current output driver). I - CTS -- Clear To Send input for UART. I/O I;PU PIO0_8 -- General purpose digital input/output pin. I/O - MISO0 -- Master In Slave Out for SPI0. O - CT16B0_MAT0 -- Match output 0 for 16-bit timer 0. I/O I;PU PIO0_9 -- General purpose digital input/output pin. I/O - MOSI0 -- Master Out Slave In for SPI0. yes yes yes yes yes yes [1] O - CT16B0_MAT1 -- Match output 1 for 16-bit timer 0. I I;PU SWCLK -- Serial wire clock. I/O - PIO0_10 -- General purpose digital input/output pin. I/O - SCK0 -- Serial clock for SPI0. O - CT16B0_MAT2 -- Match output 2 for 16-bit timer 0. - I;PU R -- Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO0_11 -- General purpose digital input/output pin. I - AD0 -- A/D converter, input 0. O - CT32B0_MAT3 -- Match output 3 for 32-bit timer 0. PIO1_0 to PIO1_11 R/PIO1_0/AD1/ CT32B1_CAP0 R/PIO1_1/AD2/ CT32B1_MAT0 R/PIO1_2/AD3/ CT32B1_MAT1 LPC1111_12_13_14 Product data sheet Port 1 -- Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block. 22[5] 23[5] 24[5] yes no no - I;PU R -- Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_0 -- General purpose digital input/output pin. I - AD1 -- A/D converter, input 1. I - CT32B1_CAP0 -- Capture input 0 for 32-bit timer 1. - I;PU R -- Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_1 -- General purpose digital input/output pin. I - AD2 -- A/D converter, input 2. O - CT32B1_MAT0 -- Match output 0 for 32-bit timer 1. - I;PU R -- Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_2 -- General purpose digital input/output pin. I - AD3 -- A/D converter, input 3. O - CT32B1_MAT1 -- Match output 1 for 32-bit timer 1. All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 17 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 5. LPC1111/12/13/14 pin description table (HVQFN33 package) ...continued Symbol SWDIO/PIO1_3/ AD4/CT32B1_MAT2 PIO1_4/AD5/ CT32B1_MAT3/ WAKEUP PIO1_5/RTS/ CT32B0_CAP0 Pin 25[5] 26[5] 30[3] PIO1_6/RXD/ CT32B0_MAT0 31[3] PIO1_7/TXD/ CT32B0_MAT1 32[3] PIO1_8/ CT16B1_CAP0 7[3] PIO1_9/ CT16B1_MAT0 12[3] PIO1_10/AD6/ CT16B1_MAT1 20[5] PIO1_11/AD7 27[5] Start Type logic input Reset Description state no I;PU SWDIO -- Serial wire debug input/output. I/O - PIO1_3 -- General purpose digital input/output pin. I - AD4 -- A/D converter, input 4. O - CT32B1_MAT2 -- Match output 2 for 32-bit timer 1. I/O I;PU PIO1_4 -- General purpose digital input/output pin with 10 ns glitch filter. I - AD5 -- A/D converter, input 5. O - CT32B1_MAT3 -- Match output 3 for 32-bit timer 1. I - WAKEUP -- Deep power-down mode wake-up pin with 20 ns glitch filter. This pin must be pulled HIGH externally to enter Deep power-down mode and pulled LOW to exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part. I/O I;PU PIO1_5 -- General purpose digital input/output pin. O - RTS -- Request To Send output for UART. I - CT32B0_CAP0 -- Capture input 0 for 32-bit timer 0. I/O I;PU PIO1_6 -- General purpose digital input/output pin. I - RXD -- Receiver input for UART. no no no no no no no no I/O [1] O - CT32B0_MAT0 -- Match output 0 for 32-bit timer 0. I/O I;PU PIO1_7 -- General purpose digital input/output pin. O - TXD -- Transmitter output for UART. O - CT32B0_MAT1 -- Match output 1 for 32-bit timer 0. I/O I;PU PIO1_8 -- General purpose digital input/output pin. I - CT16B1_CAP0 -- Capture input 0 for 16-bit timer 1. I/O I;PU PIO1_9 -- General purpose digital input/output pin. O - CT16B1_MAT0 -- Match output 0 for 16-bit timer 1. I/O I;PU PIO1_10 -- General purpose digital input/output pin. I - AD6 -- A/D converter, input 6. O - CT16B1_MAT1 -- Match output 1 for 16-bit timer 1. I/O I;PU PIO1_11 -- General purpose digital input/output pin. I - AD7 -- A/D converter, input 7. PIO2_0 PIO2_0/DTR Port 2 -- Port 2 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 2 pins depends on the function selected through the IOCONFIG register block. Pins PIO2_1 to PIO2_11 are not available. 1[3] no I/O I;PU PIO2_0 -- General purpose digital input/output pin. O - DTR -- Data Terminal Ready output for UART. PIO3_0 to PIO3_5 Port 3 -- Port 3 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 3 pins depends on the function selected through the IOCONFIG register block. Pins PIO3_0, PIO3_1, PIO3_3 and PIO3_6 to PIO3_11 are not available. PIO3_2 28[3] no I/O I;PU PIO3_2 -- General purpose digital input/output pin. PIO3_4 13[3] no I/O I;PU PIO3_4 -- General purpose digital input/output pin. LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 18 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 5. LPC1111/12/13/14 pin description table (HVQFN33 package) ...continued Symbol Pin Start Type logic input Reset Description state no I/O I;PU PIO3_5 -- General purpose digital input/output pin. [1] PIO3_5 14[3] VDD 6; 29 - I - 3.3 V supply voltage to the internal regulator, the external rail, and the ADC. Also used as the ADC reference voltage. XTALIN 4[6] - I - Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. XTALOUT 5[6] - O - Output from the oscillator amplifier. VSS 33 - - - Thermal pad. Connect to ground. [1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled. [2] See Figure 32 for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. [3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 31). [4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. [5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled, and the pin is not 5 V tolerant (see Figure 31). [6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 19 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7. Functional description 7.1 ARM Cortex-M0 processor The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. 7.2 On-chip flash program memory The LPC1111/12/13/14 contain 32 kB (LPC1114), 24 kB (LPC1113), 16 kB (LPC1112), or 8 kB (LPC1111) of on-chip flash memory. 7.3 On-chip SRAM The LPC1111/12/13/14 contain a total of 8 kB, 4 kB, or 2 kB on-chip static RAM memory. 7.4 Memory map The LPC1111/12/13/14 incorporates several distinct memory regions, shown in the following figures. Figure 5 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping. The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128 peripherals. The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows simplifying the address decoding for each peripheral. LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 20 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller AHB peripherals LPC1111/12/13/14 4 GB 0x5020 0000 0xFFFF FFFF reserved 0xE010 0000 private peripheral bus 127-16 reserved 0xE000 0000 0x5004 0000 12-15 GPIO PIO3 0x5020 0000 8-11 GPIO PIO2 0x5000 0000 4-7 GPIO PIO1 0-3 GPIO PIO0 reserved AHB peripherals reserved APB peripherals 0x5003 0000 0x5002 0000 0x5001 0000 0x5000 0000 0x4008 0000 31-23 reserved 0x4005 C000 0x4008 0000 APB peripherals 1 GB SPI1(1) 22 0x4000 0000 0x4005 8000 21-19 reserved 0x4004 C000 reserved 0x2000 0000 0.5 GB 18 system control 17 IOCONFIG 16 15 SPI0 flash controller 14 PMU reserved 0x4004 4000 0x4004 0000 0x4003 C000 0x4003 8000 13-10 reserved 0x1FFF 4000 16 kB boot ROM 0x4002 8000 9 reserved 8 reserved 0x4002 0000 0x1000 2000 7 ADC 0x4001 C000 0x1000 1000 6 32-bit counter/timer 1 0x4001 8000 0x1000 0800 5 32-bit counter/timer 0 0x4001 4000 4 16-bit counter/timer 1 0x4001 0000 3 16-bit counter/timer 0 0x4000 C000 2 UART 0x4000 8000 1 0 WDT 0x4000 4000 I2C-bus 0x4000 0000 0x1FFF 0000 reserved 8 kB SRAM (LPC1113/14/301/302) 4 kB SRAM (LPC1111/12/13/14/201/202) 2 kB SRAM (LPC1111/12/101/102) 0x1000 0000 reserved 0x0000 8000 32 kB on-chip flash (LPC1114) 24 kB on-chip flash (LPC1113) 16 kB on-chip flash (LPC1112) 8 kB on-chip flash (LPC1111) 0 GB 0x4004 8000 0x0000 6000 0x4002 4000 0x0000 4000 0x0000 2000 0x0000 00C0 active interrupt vectors 0x0000 0000 0x0000 0000 002aae699 (1) LQFP48/PLCC44 packages only. Fig 5. LPC1111/12/13/14 memory map 7.5 Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.5.1 Features * Controls system exceptions and peripheral interrupts. LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 21 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller * In the LPC1111/12/13/14, the NVIC supports 32 vectored interrupts including up to 13 inputs to the start logic from individual GPIO pins. * Four programmable interrupt priority levels with hardware priority level masking. * Software interrupt generation. 7.5.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. Any GPIO pin (total of up to 42 pins) regardless of the selected function, can be programmed to generate an interrupt on a level, or rising edge or falling edge, or both. 7.6 IOCONFIG block The IOCONFIG block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. 7.7 Fast general purpose parallel I/O Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs can be set or cleared in one write operation. LPC1111/12/13/14 use accelerated GPIO functions: * GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing can be achieved. * Entire port value can be written in one instruction. Additionally, any GPIO pin (total of up to 42 pins) providing a digital function can be programmed to generate an interrupt on a level, a rising or falling edge, or both. 7.7.1 Features * Bit level port registers allow a single instruction to set or clear any number of bits in one write operation. * Direction control of individual bits. * All I/O default to inputs with pull-ups enabled after reset with the exception of the I2C-bus pins PIO0_4 and PIO0_5. * Pull-up/pull-down resistor configuration can be programmed through the IOCONFIG block for each GPIO pin (except for pins PIO0_4 and PIO0_5). 7.8 UART The LPC1111/12/13/14 contain one UART. LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 22 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Support for RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode. The UART includes a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 7.8.1 Features * * * * * Maximum UART data bit rate of 3.125 MBit/s. 16 Byte Receive and Transmit FIFOs. Register locations conform to 16C550 industry standard. Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. * FIFO control mechanism that enables software flow control implementation. * Support for RS-485/9-bit mode. * Support for modem control. 7.9 SPI serial I/O controller The LPC1111/12/13/14 contain two SPI controllers on the LQFP48/PLCC44 packages and one SPI controller on the HVQFN33 packages (SPI0). Both SPI controllers support SSP features. The SPI controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SPI supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 7.9.1 Features * Maximum SPI speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode) * Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National Semiconductor Microwire buses * * * * Synchronous serial communication Master or slave operation 8-frame FIFOs for both transmit and receive 4-bit to 16-bit frame 7.10 I2C-bus serial I/O controller The LPC1111/12/13/14 contain one I2C-bus controller. The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line (SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 23 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it. 7.10.1 Features * The I2C-interface is a standard I2C-bus compliant interface with open-drain pins. The I2C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s. * * * * * Easy to configure as master, slave, or master/slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters and slaves. Multi-master bus (no central master). Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. * Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. * Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. * The I2C-bus can be used for test and diagnostic purposes. * The I2C-bus controller supports multiple address recognition and a bus monitor mode. 7.11 10-bit ADC The LPC1111/12/13/14 contains one ADC. It is a single 10-bit successive approximation ADC with eight channels. 7.11.1 Features * * * * * * * * 10-bit successive approximation ADC. Input multiplexing among 8 pins. Power-down mode. Measurement range 0 V to VDD. 10-bit conversion time 2.44 s. Burst conversion mode for single or multiple inputs. Optional conversion on transition of input pin or timer match signal. Individual result registers for each ADC channel to reduce interrupt overhead. 7.12 General purpose external event counter/timers The LPC1111/12/13/14 includes two 32-bit counter/timers and two 16-bit counter/timers. The counter/timer is designed to count cycles of the system derived clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. Each counter/timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.12.1 Features * A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler. LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 24 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller * Counter or timer operation. * One capture channel per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also generate an interrupt. * Four match registers per timer that allow: - Continuous operation with optional interrupt generation on match. - Stop timer on match with optional interrupt generation. - Reset timer on match with optional interrupt generation. * Up to four external outputs corresponding to match registers, with the following capabilities: - Set LOW on match. - Set HIGH on match. - Toggle on match. - Do nothing on match. 7.13 System tick timer The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a fixed time interval (typically 10 ms). 7.14 Watchdog timer The purpose of the watchdog is to reset the microcontroller within a selectable time period. 7.14.1 Features * Internally resets chip if not periodically reloaded. * Debug mode. * Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. * * * * Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. Flag to indicate watchdog reset. Programmable 24-bit timer with internal prescaler. Selectable time period from (Tcy(WDCLK) x 256 x 4) to (Tcy(WDCLK) x 224 x 4) in multiples of Tcy(WDCLK) x 4. * The Watchdog Clock (WDCLK) source can be selected from the Internal RC oscillator (IRC), the Watchdog oscillator, or the main clock. This gives a wide range of potential timing choices of Watchdog operation under different power reduction conditions. It also provides the ability to run the WDT from an entirely internal source that is not dependent on an external crystal and its associated components and wiring for increased reliability. LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 25 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7.15 Clocking and power control 7.15.1 Crystal oscillators The LPC1111/12/13/14 include three independent oscillators. These are the system oscillator, the Internal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Following reset, the LPC1111/12/13/14 will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. See Figure 6 for an overview of the LPC1111/12/13/14 clock generation. SYSTEM CLOCK DIVIDER AHB clock 0 (system) system clock 18 AHB clocks 1 to 18 (memories and peripherals) AHBCLKCTRL[1:18] (AHB clock enable) IRC oscillator SPI0 PERIPHERAL CLOCK DIVIDER SPI0 UART PERIPHERAL CLOCK DIVIDER UART SPI1 PERIPHERAL CLOCK DIVIDER SPI1 WDT CLOCK DIVIDER WDT main clock watchdog oscillator MAINCLKSEL (main clock select) IRC oscillator SYSTEM PLL system oscillator IRC oscillator SYSPLLCLKSEL (system PLL clock select) watchdog oscillator WDTUEN (WDT clock update enable) IRC oscillator system oscillator watchdog oscillator CLKOUTUEN (CLKOUT update enable) Fig 6. CLKOUT PIN CLOCK DIVIDER CLKOUT pin 002aae514 LPC1111/12/13/14 clock generation block diagram 7.15.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to 1 % accuracy over the entire voltage and temperature range. LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 26 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Upon power-up or any chip reset, the LPC1111/12/13/14 use the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.15.1.2 System oscillator The system oscillator can be used as the clock source for the CPU, with or without using the PLL. The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the system PLL. 7.15.1.3 Watchdog oscillator The watchdog oscillator can be used as a clock source that directly drives the CPU, the watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is programmable between 7.8 kHz and 1.7 MHz. The frequency spread over processing and temperature is 40 %. 7.15.2 System PLL The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The PLL output frequency must be lower than 100 MHz. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source. The PLL settling time is 100 s. 7.15.3 Clock output The LPC1111/12/13/14 features a clock output function that routes the IRC oscillator, the system oscillator, the watchdog oscillator, or the main clock to an output pin. 7.15.4 Wake-up process The LPC1111/12/13/14 begin operation at power-up and when awakened from Deep power-down mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the system oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. 7.15.5 Power control The LPC1111/12/13/14 support a variety of power control features. There are three special modes of processor power reduction: Sleep mode, Deep-sleep mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, a register is provided for shutting down the clocks to individual on-chip LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 27 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected peripherals have their own clock divider which provides even better power control. 7.15.5.1 Power profiles (LPC1100L series, LPC111x/102/202/302 only) The power consumption in Active and Sleep modes can be optimized for the application through simple calls to the power profile. The power configuration routine configures the LPC1111/12/13/14 for one of the following power modes: * Default mode corresponding to power configuration after reset. * CPU performance mode corresponding to optimized processing capability. * Efficiency mode corresponding to optimized balance of current consumption and CPU performance. * Low-current mode corresponding to lowest power consumption. In addition, the power profile includes routines to select the optimal PLL settings for a given system clock and PLL input clock. 7.15.5.2 Sleep mode When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence but re-enabling the clock to the ARM core. In Sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 7.15.5.3 Deep-sleep mode In Deep-sleep mode, the chip is in Sleep mode, and in addition all analog blocks are shut down. As an exception, the user has the option to keep the watchdog oscillator and the BOD circuit running for self-timed wake-up and BOD protection. Deep-sleep mode allows for additional power savings. Up to 13 pins total serve as external wake-up pins to the start logic to wake up the chip from Deep-sleep mode. Unless the watchdog oscillator is selected to run in Deep-sleep mode, the clock source should be switched to IRC before entering Deep-sleep mode, because the IRC can be switched on and off glitch-free. 7.15.5.4 Deep power-down mode In Deep power-down mode, power is shut off to the entire chip with the exception of the WAKEUP pin. The LPC1111/12/13/14 can wake up from Deep power-down mode via the WAKEUP pin. A LOW-going pulse as short as 50 ns wakes up the part from Deep power-down mode. When entering Deep power-down mode, an external pull-up resistor is required on the WAKEUP pin to hold it HIGH. The RESET pin must also be held HIGH to prevent it from floating while in Deep power-down mode. LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 28 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7.16 System control 7.16.1 Start logic The start logic connects external pins to corresponding interrupts in the NVIC. Each pin shown in Table 3 to Table 5 as input to the start logic has an individual interrupt in the NVIC interrupt vector table. The start logic pins can serve as external interrupt pins when the chip is running. In addition, an input signal on the start logic pins can wake up the chip from Deep-sleep mode when all clocks are shut down. The start logic must be configured in the system configuration block and in the NVIC before being used. 7.16.2 Reset Reset has four sources on the LPC1111/12/13/14: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage attains a usable level, starts the IRC and initializes the flash controller. A LOW-going pulse as short as 50 ns resets the part. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. An external pull-up resistor is required on the RESET pin if Deep power-down mode is used. 7.16.3 Brownout detection The LPC1111/12/13/14 includes four levels for monitoring the voltage on the VDD pin. If this voltage falls below one of the four selected levels, the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. Four additional threshold levels can be selected to cause a forced reset of the chip. 7.16.4 Code security (Code Read Protection - CRP) This feature of the LPC1111/12/13/14 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP. In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For details see the LPC111x user manual. There are three levels of Code Read Protection: 1. CRP1 disables access to the chip via the SWD and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 29 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 2. CRP2 disables access to the chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands. 3. Running an application with level CRP3 selected fully disables any access to the chip via the SWD pins and the ISP. This mode effectively disables ISP override using PIO0_1 pin, too. It is up to the user's application to provide (if needed) flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via the UART. CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be disabled. For details see the LPC111x user manual. 7.16.5 APB interface The APB peripherals are located on one APB bus. 7.16.6 AHBLite The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main static RAM, and the Boot ROM. 7.16.7 External interrupt inputs All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs serve as external interrupts (see Section 7.16.1). 7.17 Emulation and debugging Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four breakpoints and two watchpoints is supported. LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 30 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions VDD supply voltage (core and external rail) Min Max Unit 1.8 3.6 V -0.5 +5.5 V VI input voltage 5 V tolerant I/O pins; only valid when the VDD supply voltage is present [2] IDD supply current per supply pin [3] - 100 mA [3] - 100 mA - 100 mA -65 +150 C - 150 C - 1.5 W -6500 +6500 V ISS ground current per ground pin Ilatch I/O latch-up current -(0.5VDD) < VI < (1.5VDD); Tj < 125 C Tstg storage temperature [4] Tj(max) maximum junction temperature Ptot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption VESD electrostatic discharge voltage human body model; all pins [1] [5] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. [2] Including voltage on outputs in 3-state mode. [3] The peak current is limited to 25 times the corresponding maximum current. [4] Dependent on package type. [5] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 31 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9. Static characteristics Table 7. Static characteristics Tamb = -40 C to +85 C, unless otherwise specified. Symbol Parameter VDD supply voltage (core and external rail) Min Typ[1] Max Unit 1.8 3.3 3.6 V - 3 - mA - 9 - mA - 2 - mA [2][3][8] - 6 - A [2][9] - 220 - nA - 2 - mA - 7 - mA - 1 - mA [2][3][8] - 2 - A [2][9] - 220 - nA Conditions LPC1100 series (LPC111x/101/201/301) power consumption IDD supply current Active mode; code while(1){} executed from flash system clock = 12 MHz VDD = 3.3 V system clock = 50 MHz VDD = 3.3 V Sleep mode; system clock = 12 MHz [2][3][4] [5][6] [2][3][5] [6][7] [2][3][4] [5][6] VDD = 3.3 V Deep-sleep mode; VDD = 3.3 V Deep power-down mode; VDD = 3.3 V LPC1100L series (LPC111x/102/202/302) power consumption in low-current mode[10] IDD supply current Active mode; code while(1){} executed from flash system clock = 12 MHz VDD = 3.3 V system clock = 50 MHz VDD = 3.3 V Sleep mode; system clock = 12 MHz [2][3][4] [5][6] [2][3][5] [6][7] [2][3][4] [5][6] VDD = 3.3 V Deep-sleep mode; VDD = 3.3 V Deep power-down mode; VDD = 3.3 V Standard port pins, RESET IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10 nA IIH HIGH-level input current VI = VDD; on-chip pull-down resistor disabled - 0.5 10 nA IOZ OFF-state output current VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled - 0.5 10 nA LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 32 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 7. Static characteristics ...continued Tamb = -40 C to +85 C, unless otherwise specified. Symbol VI Parameter input voltage Conditions pin configured to provide a digital function [11][12] Min Typ[1] Max Unit 0 - 5.0 V [13] VO output voltage 0 - VDD V VIH HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage VOH HIGH-level output voltage VOL IOH output active - 0.4 - V 2.0 V VDD 3.6 V; IOH = -4 mA VDD - 0.4 - - V 1.8 V VDD < 2.0 V; IOH = -3 mA VDD - 0.4 - - V 2.0 V VDD 3.6 V; IOL = 4 mA - - 0.4 V 1.8 V VDD < 2.0 V; IOL = 3 mA - - 0.4 V HIGH-level output current VOH = VDD - 0.4 V; -4 - - mA LOW-level output current VOL = 0.4 V LOW-level output voltage 2.0 V VDD 3.6 V 1.8 V VDD < 2.0 V IOL -3 - - mA 4 - - mA 2.0 V VDD 3.6 V 1.8 V VDD < 2.0 V 3 - - mA IOHS HIGH-level short-circuit VOH = 0 V output current [14] - - -45 mA IOLS LOW-level short-circuit output current VOL = VDD [14] - - 50 mA Ipd pull-down current VI = 5 V 10 50 150 A Ipu pull-up current VI = 0 V; -15 -50 -85 A -10 -50 -85 A 0 0 0 A 2.0 V VDD 3.6 V 1.8 V VDD < 2.0 V VDD < VI < 5 V High-drive output pin (PIO0_7) IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10 nA IIH HIGH-level input current VI = VDD; on-chip pull-down resistor disabled - 0.5 10 nA IOZ OFF-state output current VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled - 0.5 10 nA VI input voltage pin configured to provide a digital function 0 - 5.0 V 0 - VDD V 0.7VDD - - V VO output voltage VIH HIGH-level input voltage LPC1111_12_13_14 Product data sheet [11][12] [13] output active All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 33 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 7. Static characteristics ...continued Tamb = -40 C to +85 C, unless otherwise specified. Min Typ[1] Max Unit LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage 0.4 - - V VOH HIGH-level output voltage 2.5 V VDD 3.6 V; IOH = -20 mA VDD - 0.4 - - V 1.8 V VDD < 2.5 V; IOH = -12 mA VDD - 0.4 - - V 2.0 V VDD 3.6 V; IOL = 4 mA - - 0.4 V 1.8 V VDD < 2.0 V; IOL = 3 mA - - 0.4 V VOH = VDD - 0.4 V; 2.5 V VDD 3.6 V 20 - - mA 1.8 V VDD < 2.5 V 12 - - mA VOL = 0.4 V 4 - - mA 3 - - mA - - 50 mA Symbol Parameter VIL LOW-level output voltage VOL HIGH-level output current IOH LOW-level output current IOL Conditions 2.0 V VDD 3.6 V 1.8 V VDD < 2.0 V [14] IOLS LOW-level short-circuit output current VOL = VDD Ipd pull-down current VI = 5 V 10 50 150 A Ipu pull-up current VI = 0 V -15 -50 -85 A -10 -50 -85 A 0 0 0 A 2.0 V VDD 3.6 V 1.8 V VDD < 2.0 V VDD < VI < 5 V I2C-bus pins (PIO0_4 and PIO0_5) VIH HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage - 0.5VDD - V 4 - - mA 3 - - 20 - - 16 - - IOL LOW-level output current I2C-bus VOL = 0.4 V; pins configured as standard mode pins 2.0 V VDD 3.6 V 1.8 V VDD < 2.0 V IOL LOW-level output current I2C-bus VOL = 0.4 V; pins configured as Fast-mode Plus pins mA 2.0 V VDD 3.6 V 1.8 V VDD < 2.0 V ILI input leakage current VI = VDD [15] VI = 5 V - 2 4 A - 10 22 A Oscillator pins Vi(xtal) crystal input voltage -0.5 1.8 1.95 V Vo(xtal) crystal output voltage -0.5 1.8 1.95 V LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 34 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] Tamb = 25 C. [3] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled. [4] IRC enabled; system oscillator disabled; system PLL disabled. [5] BOD disabled. [6] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to UART and SPI0/1 disabled in system configuration block. [7] IRC disabled; system oscillator enabled; system PLL enabled. [8] All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 18FF. [9] WAKEUP pin pulled HIGH externally. [10] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles. [11] Including voltage on outputs in 3-state mode. [12] VDD supply voltage must be present. [13] 3-state outputs go into 3-state mode in Deep power-down mode. [14] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [15] To VSS. Table 8. ADC static characteristics Tamb = -40 C to +85 C unless otherwise specified; ADC frequency 4.5 MHz, VDD = 2.5 V to 3.6 V. Symbol Parameter VIA analog input voltage 0 - VDD V Cia analog input capacitance - - 1 pF ED differential linearity error [1][2] - - 1 LSB integral non-linearity [3] - - 1.5 LSB EO offset error [4] - - 3.5 LSB EG gain error [5] - - 0.6 % ET absolute error [6] - - 4 LSB Rvsi voltage source interface resistance - - 40 k Ri input resistance - - 2.5 M EL(adj) Conditions Min [7][8] [1] The ADC is monotonic, there are no missing codes. Typ Max Unit [2] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 7. [3] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 7. [4] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 7. [5] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 7. [6] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See Figure 7. [7] Tamb = 25 C; maximum sampling frequency fs = 4.5 MHz and analog input capacitance Cia = 1 pF. [8] Input resistance Ri depends on the sampling frequency fs: Ri = 1 / (fs x Cia). LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 35 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller offset error EO gain error EG 1023 1022 1021 1020 1019 1018 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 VIA (LSBideal) offset error EO 1 LSB = VDD - VSS 1024 002aaf426 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve. Fig 7. ADC characteristics LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 36 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9.1 BOD static characteristics Table 9. BOD static characteristics[1] Tamb = 25 C. Symbol Parameter Conditions Vth threshold voltage interrupt level 0 Min Typ Max Unit assertion - 1.65 - V de-assertion - 1.80 - V assertion - 2.22 - V de-assertion - 2.35 - V assertion - 2.52 - V de-assertion - 2.66 - V assertion - 2.80 - V de-assertion - 2.90 - V interrupt level 1 interrupt level 2 interrupt level 3 reset level 0 assertion - 1.46 - V de-assertion - 1.63 - V assertion - 2.06 - V de-assertion - 2.15 - V assertion - 2.35 - V de-assertion - 2.43 - V assertion - 2.63 - V de-assertion - 2.71 - V reset level 1 reset level 2 reset level 3 [1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC111x user manual. 9.2 Power consumption LPC111x/101/201/301 Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC111x user manual): * Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block. * Configure GPIO pins as outputs using the GPIOnDIR registers. * Write 0 to all GPIOnDATA registers to drive the outputs LOW. LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 37 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aaf390 12 IDD (mA) 48 MHz(2) 8 36 MHz(2) 24 MHz(2) 4 12 MHz(1) 0 1.8 2.4 3.0 3.6 VDD (V) Conditions: Tamb = 25 C; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 8. Active mode: Typical supply current IDD versus supply voltage VDD for different system clock frequencies (for LPC111x/101/201/301) 002aaf391 12 IDD (mA) 48 MHz(2) 8 36 MHz(2) 24 MHz(2) 4 0 -40 12 MHz(1) -15 10 35 60 85 temperature (C) Conditions: VDD = 3.3 V; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 9. LPC1111_12_13_14 Product data sheet Active mode: Typical supply current IDD versus temperature for different system clock frequencies (for LPC111x/101/201/301) All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 38 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aaf392 8 IDD (mA) 48 MHz(2) 6 36 MHz(2) 4 24 MHz(2) 12 MHz(1) 2 0 -40 -15 10 35 60 85 temperature (C) Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 10. Sleep mode: Typical supply current IDDversus temperature for different system clock frequencies (for LPC111x/101/201/301) 002aaf394 40 IDD (A) 30 3.6 V 3.3 V 2.0 V 1.8 V 20 10 0 -40 -15 10 35 60 85 temperature (C) Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG = 0x0000 18FF). Fig 11. Deep-sleep mode: Typical supply current IDD versus temperature for different supply voltages VDD (for LPC111x/101/201/301) LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 39 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aaf457 0.8 IDD (A) 0.6 VDD = 3.6 V 3.3 V 2.0 V 1.8 V 0.4 0.2 0 -40 -15 10 35 60 85 temperature (C) Fig 12. Deep power-down mode: Typical supply current IDD versus temperature for different supply voltages VDD (for LPC111x/101/201/301) 9.3 Power consumption LPC111x/102/202/302 Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC111x user manual): * Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block. * Configure GPIO pins as outputs using the GPIOnDIR registers. * Write 0 to all GPIOnDATA registers to drive the outputs LOW. LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 40 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 001aab173 X X (X) X X <tbd> X X X X X X X X X X (X) Conditions: Tamb = 25 C; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 13. Active mode: Typical supply current IDD versus supply voltage VDD for different system clock frequencies (for LPC111x/102/202/302) 001aab173 X X (X) X X <tbd> X X X X X X X X X X (X) Conditions: VDD = 3.3 V; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 14. Active mode: Typical supply current IDD versus temperature for different system clock frequencies (for LPC111x/102/202/302) LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 41 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 001aab173 X X (X) X X <tbd> X X X X X X X X X X (X) Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 15. Sleep mode: Typical supply current IDDversus temperature for different system clock frequencies (for LPC111x/102/202/302) 001aab173 X X (X) X X <tbd> X X X X X X X X X X (X) Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG = 0x0000 18FF). Fig 16. Deep-sleep mode: Typical supply current IDD versus temperature for different supply voltages VDD (for LPC111x/102/202/302) LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 42 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 001aab173 X X (X) X X <tbd> X X X X X X X X X X (X) Fig 17. Deep power-down mode: Typical supply current IDD versus temperature for different supply voltages VDD (for LPC111x/102/202/302) LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 43 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9.4 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed. Measured on a typical sample at Tamb = 25 C. Unless noted otherwise, the system oscillator and PLL are running in both measurements. The supply currents are shown for system clock frequencies of 12 MHz and 48 MHz. Table 10. Power consumption for individual analog and digital blocks Peripheral LPC1111_12_13_14 Product data sheet Typical supply current in mA Notes n/a 12 MHz 48 MHz IRC 0.27 - - System oscillator running; PLL off; independent of main clock frequency. System oscillator at 12 MHz 0.22 - - IRC running; PLL off; independent of main clock frequency. Watchdog oscillator at 500 kHz/2 0.004 - - System oscillator running; PLL off; independent of main clock frequency. BOD 0.051 - - Independent of main clock frequency. Main PLL - 0.21 - ADC - 0.08 0.29 CLKOUT - 0.12 0.47 CT16B0 - 0.02 0.06 CT16B1 - 0.02 0.06 CT32B0 - 0.02 0.07 CT32B1 - 0.02 0.06 GPIO - 0.23 0.88 IOCONFIG - 0.03 0.10 I2C - 0.04 0.13 ROM - 0.04 0.15 SPI0 - 0.12 0.45 SPI1 - 0.12 0.45 UART - 0.22 0.82 WDT - 0.02 0.06 Main clock divided by 4 in the CLKOUTDIV register. GPIO pins configured as outputs and set to LOW. Direction and pin state are maintained if the GPIO is disabled in the SYSAHBCLKCFG register. Main clock selected as clock source for the WDT. All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 44 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9.5 Electrical pin characteristics 002aae990 3.6 VOH (V) T = 85 C 25 C -40 C 3.2 2.8 2.4 2 0 10 20 30 40 50 60 IOH (mA) Conditions: VDD = 3.3 V; on pin PIO0_7. Fig 18. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level output current IOH. 002aaf019 60 T = 85 C 25 C -40 C IOL (mA) 40 20 0 0 0.2 0.4 0.6 VOL (V) Conditions: VDD = 3.3 V; on pins PIO0_4 and PIO0_5. Fig 19. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus LOW-level output voltage VOL LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 45 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aae991 15 IOL (mA) T = 85 C 25 C -40 C 10 5 0 0 0.2 0.4 0.6 VOL (V) Conditions: VDD = 3.3 V; standard port pins and PIO0_7. Fig 20. Typical LOW-level output current IOL versus LOW-level output voltage VOL 002aae992 3.6 VOH (V) T = 85 C 25 C -40 C 3.2 2.8 2.4 2 0 8 16 24 IOH (mA) Conditions: VDD = 3.3 V; standard port pins. Fig 21. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 46 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aae988 10 Ipu (A) -10 -30 T = 85 C 25 C -40 C -50 -70 0 1 2 3 4 5 VI (V) Conditions: VDD = 3.3 V; standard port pins. Fig 22. Typical pull-up current Ipu versus input voltage VI 002aae989 80 T = 85 C 25 C -40 C Ipd (A) 60 40 20 0 0 1 2 3 4 5 VI (V) Conditions: VDD = 3.3 V; standard port pins. Fig 23. Typical pull-down current Ipd versus input voltage VI LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 47 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10. Dynamic characteristics 10.1 Flash memory Table 11. Flash characteristics Tamb = -40 C to +85 C, unless otherwise specified. Symbol Parameter Nendu endurance tret retention time ter erase time tprog programming time Conditions Min [1] Typ Max Unit 10000 - - cycles powered 10 - - years unpowered 20 - - years sector or multiple consecutive sectors 95 100 105 ms 0.95 1 1.05 ms [2] [1] Number of program/erase cycles. [2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes. 10.2 External clock Table 12. Dynamic characteristic: external clock Tamb = -40 C to +85 C; VDD over specified ranges.[1] Min Typ[2] Max Unit oscillator frequency 1 - 25 MHz Tcy(clk) clock cycle time 40 - 1000 ns tCHCX clock HIGH time Tcy(clk) x 0.4 - - ns tCLCX clock LOW time Tcy(clk) x 0.4 - - ns tCLCH clock rise time - - 5 ns tCHCL clock fall time - - 5 ns Symbol Parameter fosc Conditions [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. tCHCL tCHCX tCLCH tCLCX Tcy(clk) 002aaa907 Fig 24. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 48 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.3 Internal oscillators Table 13. Dynamic characteristic: internal oscillators Tamb = -40 C to +85 C; 2.7 V VDD 3.6 V.[1] Symbol Parameter Conditions fosc(RC) internal RC oscillator frequency - Min Typ[2] Max Unit 11.88 12 12.12 MHz [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. 002aaf403 12.15 f (MHz) VDD = 3.6 V 3.3 V 3.0 V 2.7 V 2.4 V 2.0 V 12.05 11.95 11.85 -40 -15 10 35 60 85 temperature (C) Conditions: Frequency values are typical values. 12 MHz 1 % accuracy is guaranteed for 2.7 V VDD 3.6 V and Tamb = -40 C to +85 C. Variations between parts may cause the IRC to fall outside the 12 MHz 1 % accuracy specification for voltages below 2.7 V. Fig 25. Internal RC oscillator frequency vs. temperature Table 14. Dynamic characteristics: Watchdog oscillator Min Typ[1] Max Unit internal oscillator DIVSEL = 0x1F, FREQSEL = 0x1 frequency in the WDTOSCCTRL register; [2][3] - 7.8 - kHz DIVSEL = 0x00, FREQSEL = 0xF in the WDTOSCCTRL register [2][3] - 1700 - kHz Symbol Parameter fosc(int) LPC1111_12_13_14 Product data sheet Conditions [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] The typical frequency spread over processing and temperature (Tamb = -40 C to +85 C) is 40 %. [3] See the LPC111x user manual. All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 49 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.4 I/O pins Table 15. Dynamic characteristic: I/O pins[1] Tamb = -40 C to +85 C; 3.0 V VDD 3.6 V. Symbol Parameter Conditions Min Typ Max Unit tr rise time pin configured as output 3.0 - 5.0 ns tf fall time pin configured as output 2.5 - 5.0 ns [1] Applies to standard port pins and RESET pin. 10.5 I2C-bus Table 16. Dynamic characteristic: I2C-bus pins[1] Tamb = -40 C to +85 C.[2] Symbol Parameter Conditions Min Max Unit fSCL SCL clock frequency Standard-mode 0 100 kHz Fast-mode 0 400 kHz Fast-mode Plus 0 1 MHz of both SDA and SCL signals - 300 ns 20 + 0.1 x Cb 300 ns [4][5][6][7] fall time tf Standard-mode Fast-mode Fast-mode Plus tLOW tHIGH tHD;DAT tSU;DAT [1] LPC1111_12_13_14 Product data sheet LOW period of the SCL clock HIGH period of the SCL clock data hold time data set-up time [3][4][8] [9][10] - 120 ns Standard-mode 4.7 - s Fast-mode 1.3 - s Fast-mode Plus 0.5 - s Standard-mode 4.0 - s Fast-mode 0.6 - s Fast-mode Plus 0.26 - s Standard-mode 0 - s Fast-mode 0 - s Fast-mode Plus 0 - s Standard-mode 250 - ns Fast-mode 100 - ns Fast-mode Plus 50 - ns See the I2C-bus specification UM10204 for details. [2] Parameters are valid over operating temperature range unless otherwise specified. [3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. [4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. [5] Cb = total capacitance of one bus line in pF. All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 50 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller [6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. [7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. [8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. [9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge. [10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time. tf SDA tSU;DAT 70 % 30 % 70 % 30 % tHD;DAT tf 70 % 30 % SCL tVD;DAT tHIGH 70 % 30 % 70 % 30 % 70 % 30 % tLOW S 1 / fSCL 002aaf425 Fig 26. I2C-bus pins clock timing 10.6 SPI interfaces Table 17. Dynamic characteristics of SPI pins in SPI mode Symbol Parameter Conditions Min Typ Max Unit - - ns SPI master (in SPI mode) Tcy(clk) tDS clock cycle time data set-up time when only receiving [1] 40 when only transmitting [1] 27.8 in SPI mode [2] 15 2.0 V VDD < 2.4 V [2] 20 1.8 V VDD < 2.0 V [2] 24 - - ns - - ns 2.4 V VDD 3.6 V ns ns tDH data hold time in SPI mode [2] 0 - - ns tv(Q) data output valid time in SPI mode [2] - - 10 ns th(Q) data output hold time in SPI mode [2] 0 - - ns SPI slave (in SPI mode) LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 51 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 17. Dynamic characteristics of SPI pins in SPI mode Symbol Parameter Tcy(PCLK) PCLK cycle time Conditions Min Typ Max Unit 20 - - ns in SPI mode [3][4] 0 - - ns in SPI mode [3][4] 3 x Tcy(PCLK) + 4 - - ns tv(Q) data output valid time in SPI mode [3][4] - - 3 x Tcy(PCLK) + 11 ns th(Q) data output hold time in SPI mode [3][4] - - 2 x Tcy(PCLK) + 5 ns data set-up time tDS data hold time tDH [1] Tcy(clk) = (SSPCLKDIV x (1 + SCR) x CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the main clock frequency fmain, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register), and the SPI CPSDVSR parameter (specified in the SPI clock prescale register). [2] Tamb = -40 C to 85 C. [3] Tcy(clk) = 12 x Tcy(PCLK). [4] Tamb = 25 C; for normal voltage supply range: VDD = 3.3 V. Tcy(clk) tclk(H) tclk(L) SCK (CPOL = 0) SCK (CPOL = 1) tv(Q) th(Q) DATA VALID MOSI DATA VALID tDS DATA VALID MISO tDH DATA VALID th(Q) tv(Q) MOSI DATA VALID DATA VALID tDH tDS MISO DATA VALID CPHA = 1 CPHA = 0 DATA VALID 002aae829 Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1. Fig 27. SPI master timing in SPI mode LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 52 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Tcy(clk) tclk(H) tclk(L) tDS tDH SCK (CPOL = 0) SCK (CPOL = 1) MOSI DATA VALID DATA VALID tv(Q) MISO th(Q) DATA VALID tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO DATA VALID CPHA = 1 DATA VALID th(Q) CPHA = 0 DATA VALID 002aae830 Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1. Fig 28. SPI slave timing in SPI mode LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 53 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 11. Application information 11.1 ADC usage notes The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in Table 8: * The ADC input trace must be short and as close as possible to the LPC1111/12/13/14 chip. * The ADC input traces must be shielded from fast switching digital signals and noisy power supply lines. * Because the ADC and the digital core share the same power supply, the power supply line must be adequately filtered. * To improve the ADC performance in a very noisy environment, put the device in Sleep mode during the ADC conversion. 11.2 XTAL input The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with Ci = 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave mode, a minimum of 200 mV(RMS) is needed. LPC1xxx XTALIN Ci 100 pF Cg 002aae788 Fig 29. Slave mode operation of the on-chip oscillator In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure 29), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected. External components and models used in oscillation mode are shown in Figure 30 and in Table 18 and Table 19. Since the feedback resistance is integrated on chip, only a crystal and the capacitances CX1 and CX2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequency is represented by L, CL and RS). Capacitance CP in Figure 30 represents the parallel package capacitance and should not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal manufacturer (see Table 18). LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 54 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller LPC1xxx L XTALIN XTALOUT = CL CP XTAL RS CX2 CX1 002aaf424 Fig 30. Oscillator modes and models: oscillation mode of operation and external crystal model used for CX1/CX2 evaluation Table 18. Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters) low frequency mode Fundamental oscillation frequency FOSC Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1, CX2 1 MHz - 5 MHz 10 pF < 300 18 pF, 18 pF 20 pF < 300 39 pF, 39 pF 5 MHz - 10 MHz 10 MHz - 15 MHz 15 MHz - 20 MHz Table 19. 30 pF < 300 57 pF, 57 pF 10 pF < 300 18 pF, 18 pF 20 pF < 200 39 pF, 39 pF 30 pF < 100 57 pF, 57 pF 10 pF < 160 18 pF, 18 pF 20 pF < 60 39 pF, 39 pF 10 pF < 80 18 pF, 18 pF Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters) high frequency mode Fundamental oscillation frequency FOSC Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1, CX2 15 MHz - 20 MHz 10 pF < 180 18 pF, 18 pF 20 pF < 100 39 pF, 39 pF 20 MHz - 25 MHz 10 pF < 160 18 pF, 18 pF 20 pF < 80 39 pF, 39 pF 11.3 XTAL Printed Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors Cx1, Cx2, and Cx3 in case of third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plain. Loops must be made as small as possible in LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 55 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller accordingly to the increase in parasitics of the PCB layout. 11.4 Standard I/O pad configuration Figure 31 shows the possible pin modes for standard I/O pins with analog input function: * * * * * Digital output driver Digital input: Pull-up enabled/disabled Digital input: Pull-down enabled/disabled Digital input: Repeater mode enabled/disabled Analog input VDD ESD output enable pin configured as digital output driver output PIN ESD VDD VSS weak pull-up pull-up enable pin configured as digital input weak pull-down repeater mode enable pull-down enable data input select analog input pin configured as analog input analog input 002aaf304 Fig 31. Standard I/O pad configuration LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 56 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 11.5 Reset pad configuration VDD VDD VDD Rpu reset ESD 20 ns RC GLITCH FILTER PIN ESD VSS 002aaf274 Fig 32. Reset pad configuration LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 57 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 12. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE e E HE A A2 (A 3) A1 w M bp pin 1 index Lp L 13 48 1 detail X 12 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 7.1 6.9 0.5 9.15 8.85 9.15 8.85 1 0.75 0.45 0.2 0.12 0.1 Z D (1) Z E (1) 0.95 0.55 7 o 0 0.95 0.55 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT313-2 136E05 MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-25 Fig 33. Package outline SOT313-2 (LQFP48) LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 58 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller PLCC44: plastic leaded chip carrier; 44 leads SOT187-2 eD eE y X 39 A 29 28 40 bp ZE b1 w M 44 1 E HE pin 1 index A A4 A1 e (A 3) 6 18 Lp k 7 detail X 17 e v M A ZD D B HD v M B 0 5 10 mm scale DIMENSIONS (mm dimensions are derived from the original inch dimensions) A4 A1 e UNIT A A3 D(1) E(1) eD eE HD bp b1 max. min. 4.57 4.19 mm inches 0.81 0.66 HE k 16.66 16.66 16.00 16.00 17.65 17.65 1.22 1.27 16.51 16.51 14.99 14.99 17.40 17.40 1.07 0.51 0.25 3.05 0.53 0.33 0.180 0.02 0.165 0.01 0.12 0.021 0.032 0.656 0.656 0.05 0.013 0.026 0.650 0.650 0.63 0.59 0.63 0.59 Lp v w y 1.44 1.02 0.18 0.18 0.1 ZD(1) ZE(1) max. max. 2.16 2.16 45 o 0.695 0.695 0.048 0.057 0.007 0.007 0.004 0.085 0.085 0.685 0.685 0.042 0.040 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT187-2 112E10 MS-018 EDR-7319 EUROPEAN PROJECTION ISSUE DATE 99-12-27 01-11-14 Fig 34. Package outline PLCC44 LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 59 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm A B D terminal 1 index area A E A1 c detail X e1 e 9 16 C C A B C v w b y y1 C L 8 17 e e2 Eh 33 1 terminal 1 index area 24 32 X 25 Dh 0 2.5 scale Dimensions Unit mm 5 mm A(1) A1 b max 1.00 0.05 0.35 nom 0.85 0.02 0.28 min 0.80 0.00 0.23 c D(1) Dh E(1) 0.2 7.1 7.0 6.9 4.85 4.70 4.55 7.1 7.0 6.9 Eh e e1 e2 L 0.75 4.85 4.70 0.65 4.55 4.55 0.60 0.45 4.55 v 0.1 w y 0.05 0.08 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version References IEC JEDEC JEITA --- hvqfn33_po European projection Issue date 09-03-17 09-03-23 Fig 35. Package outline (HVQFN33) LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 60 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 13. Abbreviations Table 20. LPC1111_12_13_14 Product data sheet Abbreviations Acronym Description ADC Analog-to-Digital Converter AHB Advanced High-performance Bus APB Advanced Peripheral Bus BOD BrownOut Detection GPIO General Purpose Input/Output PLL Phase-Locked Loop RC Resistor-Capacitor SPI Serial Peripheral Interface SSI Serial Synchronous Interface SSP Synchronous Serial Port UART Universal Asynchronous Receiver/Transmitter All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 61 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 14. Revision history Table 21. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC1111_12_13_14 v.3 20101110 Product data sheet - LPC1111_12_13_14 v.2 Modifications: LPC1111_12_13_14 v.2 Modifications: LPC1111_12_13_14 v.1 LPC1111_12_13_14 Product data sheet * * * * * * Parts LPC111x/102/202/302 added (LPC1100L series). Power consumption data for parts LPC111x/102/202/302 added in Table 7. PLL output frequency limited to 100 MHz in Section 7.15.2. Description of RESET and WAKEUP functions updated in Section 6. WDT description updated in Section 7.14. The WDT is a 24-bit timer. Power profiles added to Section 2 and Section 7 for parts LPC111x/102/202/302. 20100818 Product data sheet - LPC1111_12_13_14 v.1 * * * VESD limit changed to -6500 V (min) /+6500 V (max) in Table 6. * * * * * * VDD range changed to 3.0 V VDD 3.6 V in Table 15. tDS updated for SPI in master mode (Table 17). Deep-sleep mode functionality changed to allow BOD and watchdog oscillator as the only analog blocks allowed to remain running in Deep-sleep mode (Section 7.15.5.3). Reset state of pins and start logic functionality added in Table 3 to Table 5. Section 7.16.1 added. Section "Memory mapping control" removed. VOH and IOH specifications updated for high-drive pins in Table 7. Section 9.4 added. 20100416 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 - (c) NXP B.V. 2010. All rights reserved. 62 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 15. 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Export might require a prior authorization from national authorities. LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 63 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC1111_12_13_14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 10 November 2010 (c) NXP B.V. 2010. All rights reserved. 64 of 65 LPC1111/12/13/14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 17. Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.5.1 7.5.2 7.6 7.7 7.7.1 7.8 7.8.1 7.9 7.9.1 7.10 7.10.1 7.11 7.11.1 7.12 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional description . . . . . . . . . . . . . . . . . . 20 ARM Cortex-M0 processor . . . . . . . . . . . . . . . 20 On-chip flash program memory . . . . . . . . . . . 20 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 20 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 20 Nested Vectored Interrupt Controller (NVIC) . 21 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 22 IOCONFIG block . . . . . . . . . . . . . . . . . . . . . . 22 Fast general purpose parallel I/O . . . . . . . . . . 22 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 23 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 I2C-bus serial I/O controller . . . . . . . . . . . . . . 23 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 General purpose external event counter/timers . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.13 System tick timer . . . . . . . . . . . . . . . . . . . . . . 25 7.14 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 25 7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.15 Clocking and power control . . . . . . . . . . . . . . 26 7.15.1 Crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 26 7.15.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 26 7.15.1.2 System oscillator . . . . . . . . . . . . . . . . . . . . . . 27 7.15.1.3 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 27 7.15.2 System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.15.3 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.15.4 Wake-up process . . . . . . . . . . . . . . . . . . . . . . 27 7.15.5 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.15.5.1 Power profiles (LPC1100L series, LPC111x/102/202/302 only) . . . . . . . . . . . . . . 28 7.15.5.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.15.5.3 Deep-sleep mode . . . . . . . . . . . . . . . . . . . . . . 28 7.15.5.4 Deep power-down mode . . . . . . . . . . . . . . . . 7.16 System control . . . . . . . . . . . . . . . . . . . . . . . . 7.16.1 Start logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.16.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.16.3 Brownout detection . . . . . . . . . . . . . . . . . . . . 7.16.4 Code security (Code Read Protection - CRP) 7.16.5 APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 7.16.6 AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.16.7 External interrupt inputs . . . . . . . . . . . . . . . . . 7.17 Emulation and debugging . . . . . . . . . . . . . . . 8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 9 Static characteristics . . . . . . . . . . . . . . . . . . . 9.1 BOD static characteristics . . . . . . . . . . . . . . . 9.2 Power consumption LPC111x/101/201/301 . . 9.3 Power consumption LPC111x/102/202/302 . . 9.4 Peripheral power consumption . . . . . . . . . . . 9.5 Electrical pin characteristics. . . . . . . . . . . . . . 10 Dynamic characteristics. . . . . . . . . . . . . . . . . 10.1 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 10.2 External clock. . . . . . . . . . . . . . . . . . . . . . . . . 10.3 Internal oscillators . . . . . . . . . . . . . . . . . . . . . 10.4 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6 SPI interfaces. . . . . . . . . . . . . . . . . . . . . . . . . 11 Application information . . . . . . . . . . . . . . . . . 11.1 ADC usage notes. . . . . . . . . . . . . . . . . . . . . . 11.2 XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 XTAL Printed Circuit Board (PCB) layout guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 Standard I/O pad configuration . . . . . . . . . . . 11.5 Reset pad configuration . . . . . . . . . . . . . . . . . 12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information . . . . . . . . . . . . . . . . . . . . . . 15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 15.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information . . . . . . . . . . . . . . . . . . . . 17 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 29 29 29 29 29 30 30 30 30 31 32 37 37 40 44 45 48 48 48 49 50 50 51 54 54 54 55 56 57 58 61 62 63 63 63 63 64 64 65 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 10 November 2010 Document identifier: LPC1111_12_13_14