EEEFP0J152AP - EBM PAPST - Datasheet.Live

1. General description

The LPC1111/12/13/14 are a ARM Cortex-M0 based, low-cost 32-bit MCU family,

designed for 8/16-bit micr ocontroller applications, of fering performance, low power, simple

instruction set and memory addressing together with reduced code size compared to

existing 8/16-bit architectures.

The LPC1111/12/13/14 operate at CPU frequencies of up to 50 MHz.

The peripheral complement of the LPC1111/12/13/14 includes up to 32 kB of flash

memory, up to 8 kB of data memory, one Fast-mode Plus I2C-bus in te r face, one

RS-485/EIA-485 UART, up to two SPI interfaces with SSP features, four general purpose

counter/timers, a 10-bit ADC, and up to 42 general purpose I/O pins.

Remark: The LPC1111/12/13/14 series consists of the LPC1100 series (parts

LPC111x/101/201/301) and the LPC1100L series (parts LPC111x/102/202/302). The

LPC1100L include the power profiles.

2. Features and benefits

System:

ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.

ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).

Serial Wire Debug.

System tick timer.

Memory:

32 kB (LPC1114), 24 kB (LPC1113), 16 kB (LPC1112), or 8 kB (LPC1111) on-chip

flash programming memory.

8 kB, 4 kB, or 2 kB SRAM.

In-System Programming (ISP) and In- A pplication Programming (IAP) via on-chip

bootloader software.

Digital peripherals:

Up to 42 General Purpose I/O (GPIO) pi ns with configurable pull-up/pull-down

resistors.

GPIO pins can be used as edge and level sensitive interrupt sources.

High-current output driver (20 mA) on one pin.

High-current sink drivers (20 mA) on two I2C-bus pins in Fast-mode Plus.

Four general pu rp os e co un te r/ tim er s w ith a to tal of four captu re inpu ts and 13

match outpu ts.

Programmable WatchDog Timer (WDT).

LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash and

8 kB SRAM

Rev. 3 — 10 November 2010 Product data sheet

Product data sheet Rev. 3 — 10 November 2010 2 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

Analog peripherals:

10-bit ADC with input multiplexing among 8 pins.

Serial interfaces:

UART with fractional baud rate generation, internal FIFO, and RS-485 support.

Two SPI controllers with SSP features and with FIFO and multi-protocol

capabilities (second SPI on LQFP48 and PLCC44 packages only).

I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a

data rate of 1 Mbit/s with multiple address recognition and monitor mode.

Clock generation :

12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used

as a system clock.

Crystal oscillator with an operating range of 1 MHz to 25 MHz.

Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz.

PLL allows CPU operation up to the maximum CPU rate without the need for a

high-frequency crystal. May be run from the system oscillator or the internal RC

oscillator.

Clock output function with divider that can reflect the system oscillator clock, IRC

clock, CPU clock, and the Watchdog clock.

Power control:

Integrated PMU (Power Management Unit) to minimize power consumption during

Sleep, Deep-sleep, and Deep power-down modes.

Power profiles residing in boot ROM allowing to optimize performance and

minimize power consumption for any given application through one simp le function

call. (LPC1100L series, on LPC111x/102/202/302 only.)

Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.

Processor wake-up from Deep-sleep mode via a dedicated start logic using up to

13 of the functional pins.

Power-On Reset (POR).

Brownout detect with four separate thresholds for interrupt and forced reset.

Unique device serial number for identification.

Single power supply (1.8 V to 3.6 V).

Availa ble as 48-pin LQFP package, 33-pin HVQFN package, and 44-pin PLCC

package.

3. Applications

eMetering Lighting

Alarm systems White goods

Product data sheet Rev. 3 — 10 November 2010 3 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

4. Ordering information

[1] Sampling in Q2 2011.

Table 1. Ordering information

Type number Package

Name Description Version

LPC1111FHN33/101 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7 × 7 × 0.85 mm n/a

LPC1111FHN33/102 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7 × 7 × 0.85 mm n/a

LPC1111FHN33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7 × 7 × 0.85 mm n/a

LPC1111FHN33/202 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7 × 7 × 0.85 mm n/a

LPC1112 FHN 33/101 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7 × 7 × 0.85 mm n/a

LPC1112 FHN 33/102 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7 × 7 × 0.85 mm n/a

LPC1112 FHN 33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7 × 7 × 0.85 mm n/a

LPC1112 FHN 33/202 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7 × 7 × 0.85 mm n/a

LPC1113 FHN 33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7 × 7 × 0.85 mm n/a

LPC1113 FHN 33/202 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7 × 7 × 0.85 mm n/a

LPC1113 FHN 33/301 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7 × 7 × 0.85 mm n/a

LPC1113 FHN 33/302 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7 × 7 × 0.85 mm n/a

LPC1114 FHN 33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7 × 7 × 0.85 mm n/a

LPC1114 FHN 33/202 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7 × 7 × 0.85 mm n/a

LPC1114 FHN 33/301 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7 × 7 × 0.85 mm n/a

LPC1114 FHN 33/302 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7 × 7 × 0.85 mm n/a

LPC1113FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 ×

1.4 mm sot313-2

LPC1113FBD48/302 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 ×

1.4 mm sot313-2

LPC1114FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 ×

1.4 mm sot313-2

LPC1114FBD48/302 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 ×

1.4 mm sot313-2

LPC1114FA44/301[1] PLCC44 PLCC44; plastic leaded chip carrier; 44 leads sot187-2

LPC1114FA44/302[1] PLCC44 PLCC44; plastic leaded chip carrier; 44 leads sot187-2

Product data sheet Rev. 3 — 10 November 2010 4 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

4.1 Ordering options

[1] Sampling in Q2 2011.

Table 2. Ordering options

Type number Series Flash Total

SRAM Power

profiles UART

RS-485 I2C/

Fast+ SPI ADC

channels Package

LPC1111

LPC1111FHN33/101 LPC1100 8 kB 2 kB no 1 1 1 8 HVQFN33

LPC1111FHN33/102 LPC1100L 8 kB 2 kB yes 1 1 1 8 HVQFN33

LPC1111FHN33/201 LPC1100 8 kB 4 kB no 1 1 1 8 HVQFN33

LPC1111FHN33/202 LPC1100L 8 kB 4 kB yes 1 1 1 8 HVQFN33

LPC1112

LPC1112FHN33/101 LPC1100 16 kB 2 kB no 1 1 1 8 HVQFN33

LPC1112FHN33/102 LPC1100L 16 kB 2 kB yes 1 1 1 8 HVQFN33

LPC1112FHN33/201 LPC1100 16 kB 4 kB no 1 1 1 8 HVQFN33

LPC1112FHN33/202 LPC1100L 16 kB 4 kB yes 1 1 1 8 HVQFN33

LPC1113

LPC1113FHN33/201 LPC1100 24 kB 4 kB no 1 1 1 8 HVQFN33

LPC1113FHN33/202 LPC1100L 24 kB 4 kB yes 1 1 1 8 HVQFN33

LPC1113FHN33/301 LPC1100 24 kB 8 kB no 1 1 1 8 HVQFN33

LPC1113FHN33/302 LPC1100L 24 kB 8 kB yes 1 1 1 8 HVQFN33

LPC1113FBD48/301 LPC1100 24 kB 8 kB no 1 1 2 8 LQFP48

LPC1113FBD48/302 LPC1100L 24 kB 8 kB yes 1 1 2 8 LQFP48

LPC1114

LPC1114FHN33/201 LPC1100 32 kB 4 kB no 1 1 1 8 HVQFN33

LPC1114FHN33/202 LPC1100L 32 kB 4 kB yes 1 1 1 8 HVQFN33

LPC1114FHN33/301 LPC1100 32 kB 8 kB no 1 1 1 8 HVQFN33

LPC1114FHN33/302 LPC1100L 32 kB 8 kB yes 1 1 1 8 HVQFN33

LPC1114FBD48/301 LPC1100 32 kB 8 kB no 1 1 2 8 LQFP48

LPC1114FBD48/302 LPC1100L 32 kB 8 kB yes 1 1 2 8 LQFP48

LPC1114FA44/301[1] LPC1100 32 kB 8 kB no 1 1 2 8 PLCC44

LPC1114FA44/302[1] LPC1100L 32 kB 8 kB yes 1 1 2 8 PLCC44

Product data sheet Rev. 3 — 10 November 2010 5 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

5. Block diagram

(1) LQFP48 and PLCC44 packages only.

Fig 1. LPC1111/12/13/14 block diagram

SRAM

2/4/8 kB

ARM

CORTEX-M0

TEST/DEBUG

INTERFACE

FLASH

8/16/24/32 kB

HIGH-SPEED

GPIO

AHB TO APB

BRIDGE

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

FUNCTIONS

XTALIN

XTALOUT

RESET

clocks and

controls

SWD

LPC1111/12/13/14

002aae696

slave

slave slave

ROM

slave

AHB-LITE BUS

GPIO ports

PIO0/1/2/3

CLKOUT

IRC

POR

SPI0

10-bit ADC

UART

32-bit COUNTER/TIMER 0

I2C-BUS

WDT

IOCONFIG

CT32B0_MAT[3:0]

AD[7:0]

CT32B0_CAP0

SDA

SCL

RXD

TXD

DTR, DSR(1), CTS,

DCD(1), RI(1), RTS

SYSTEM CONTROL

PMU

32-bit COUNTER/TIMER 1

CT32B1_MAT[3:0]

CT32B1_CAP0

16-bit COUNTER/TIMER 1

CT16B1_MAT[1:0]

CT16B1_CAP0

16-bit COUNTER/TIMER 0

CT16B0_MAT[2:0]

CT16B0_CAP0

SCK0, SSEL0

MISO0, MOSI0

SCK1, SSEL1

MISO1, MOSI1

SPI1(1)

system bus

Product data sheet Rev. 3 — 10 November 2010 6 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

6. Pinning information

6.1 Pinning

Fig 2. Pin configuration LQFP48 package

LPC1113FBD48/301

LPC1113FBD48/302

LPC1114FBD48/301

LPC1114FBD48/302

PIO2_6 PIO3_0/DTR

PIO2_0/DTR/SSEL1 R/PIO1_2/AD3/CT32B1_MAT1

RESET/PIO0_0 R/PIO1_1/AD2/CT32B1_MAT0

PIO0_1/CLKOUT/CT32B0_MAT2 R/PIO1_0/AD1/CT32B1_CAP0

VSS R/PIO0_11/AD0/CT32B0_MAT3

XTALIN PIO2_11/SCK0

XTALOUT PIO1_10/AD6/CT16B1_MAT1

VDD SWCLK/PIO0_10/SCK0/CT16B0_MAT2

PIO1_8/CT16B1_CAP0 PIO0_9/MOSI0/CT16B0_MAT1

PIO0_2/SSEL0/CT16B0_CAP0 PIO0_8/MISO0/CT16B0_MAT0

PIO2_7 PIO2_2/DCD/MISO1

PIO2_8 PIO2_10

PIO2_1/DSR/SCK1 PIO3_3/RI

PIO0_3 PIO1_7/TXD/CT32B0_MAT1

PIO0_4/SCL PIO1_6/RXD/CT32B0_MAT0

PIO0_5/SDA PIO1_5/RTS/CT32B0_CAP0

PIO1_9/CT16B1_MAT0 VDD

PIO3_4 PIO3_2/DCD

PIO2_4 PIO1_11/AD7

PIO2_5 VSS

PIO3_5 PIO1_4/AD5/CT32B1_MAT3/WAKEUP

PIO0_6/SCK0 SWDIO/PIO1_3/AD4/CT32B1_MAT2

PIO0_7/CTS

PIO2_9

PIO2_3/RI/MOSI1

PIO3_1/DSR

002aae697

Product data sheet Rev. 3 — 10 November 2010 7 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

Fig 3. Pin configuration PLCC44 package

LPC1114FA44/301

LPC1114FA44/302

RESET/PIO0_0 R/PIO1_2/AD3/CT32B1_MAT1

PIO0_1/CLKOUT/CT32B0_MAT2 R/PIO1_1/AD2/CT32B1_MAT0

VSS R/PIO1_0/AD1/CT32B1_CAP0

XTALIN R/PIO0_11/AD0/CT32B0_MAT3

XTALOUT PIO2_11/SCK0

VDD PIO1_10/AD6/CT16B1_MAT1

PIO1_8/CT16B1_CAP0 SWCLK/PIO0_10/SCK0/CT16B0_MAT2

PIO0_2/SSEL0/CT16B0_CAP0 PIO0_9/MOSI0/CT16B0_MAT1

PIO2_7 PIO0_8/MISO0/CT16B0_MAT0

PIO2_8 PIO2_2/DCD/MISO1

PIO2_1/DSR/SCK1 PIO2_10

PIO0_3 PIO2_0/DTR/SSEL1

PIO0_4/SCL PIO2_6

PIO0_5/SDA PIO1_7/TXD/CT32B0_MAT1

PIO1_9/CT16B1_MAT0 PIO1_6/RXD/CT32B0_MAT0

PIO3_4 PIO1_5/RTS/CT32B0_CAP0

PIO2_4 VDD

PIO2_5 PIO1_11/AD7

PIO3_5 VSS

PIO0_6/SCK0 PIO1_4/AD5/CT32B1_MAT3/WAKEUP

PIO0_7/CTS SWDIO/PIO1_3/AD4/CT32B1_MAT2

PIO2_9 PIO2_3/RI/MOSI1

002aaf020

Product data sheet Rev. 3 — 10 November 2010 8 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

Fig 4. Pin configuration HVQFN 33 package

002aae698

Transparent top view

PIO0_8/MISO0/CT16B0_MAT0

PIO1_8/CT16B1_CAP0

PIO0_2/SSEL0/CT16B0_CAP0

PIO0_9/MOSI0/CT16B0_MAT1

VDD SWCLK/PIO0_10/SCK0/CT16B0_MAT2

XTALOUT PIO1_10/AD6/CT16B1_MAT1

XTALIN R/PIO0_11/AD0/CT32B0_MAT3

PIO0_1/CLKOUT/CT32B0_MAT2 R/PIO1_0/AD1/CT32B1_CAP0

RESET/PIO0_0 R/PIO1_1/AD2/CT32B1_MAT0

PIO2_0/DTR R/PIO1_2/AD3/CT32B1_MAT1

PIO0_3

PIO0_4/SCL

PIO0_5/SDA

PIO1_9/CT16B1_MAT0

PIO3_4

PIO3_5

PIO0_6/SCK0

PIO0_7/CTS

PIO1_7/TXD/CT32B0_MAT1

PIO1_6/RXD/CT32B0_MAT0

PIO1_5/RTS/CT32B0_CAP0

VDD

PIO3_2

PIO1_11/AD7

PIO1_4/AD5/CT32B1_MAT3/WAKEUP

SWDIO/PIO1_3/AD4/CT32B1_MAT2

8 17

7 18

6 19

5 20

4 21

3 22

2 23

1 24

terminal 1

index area

33 VSS

Product data sheet Rev. 3 — 10 November 2010 9 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

6.2 Pin description

Table 3. LPC1113/14 pin description table (LQFP48 package)

Symbol Pin Start

logic

input

Type Reset

state

[1]

Description

PIO0_0 to PIO0_11 I/O Port 0 — Port 0 is a 12-bit I/O port with individual direction and

function controls for each bit. The operation of port 0 pins

depends on the function selected through the IOCONFIG

RESET/PIO0_0 3[2] yes I I; PU RESET — External reset input with 20 ns glitch filter. A

LOW-going pulse as short as 50 ns on this pin resets the

device, causing I/O ports and peripherals to take on their default

states, and processor execution to begin at address 0.

I/O - PIO0_0 — General purpose digital input/output pin with 10 ns

glitch filter.

PIO0_1/CLKOUT/

CT32B0_MAT2 4[3] yes I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW

level on this pin during reset starts the ISP command handler.

O-CLKOUT — Clockout pin.

O-CT32B0_MAT2 — Match output 2 for 32-bit timer 0.

PIO0_2/SSEL0/

CT16B0_CAP0 10[3] yes I/O I; PU PIO0_2 — Gen eral purpose digital input/output pin.

I/O - SSEL0 — Slave Select for SPI0.

I-CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.

PIO0_3 14[3] yes I/O I; PU PIO0_3 — General purpose digital input/output pin.

PIO0_4/SCL 15[4] yes I/O I; IA PIO0_4 — General purpose digital input/output pin

(open-drain).

I/O - SCL — I2C-bus, open-drain clock input/output. High-current

sink only if I2C Fast-mode Plus is selected in the I/O

configuration regi ster.

PIO0_5/SDA 16[4] yes I/O I; IA PIO0_5 — General purpose digital input/output pin

(open-drain).

I/O - SDA — I2C-bus, open-drain data input/output. High-current sink

only if I2C Fast-mode Plus is selected in the I/O configuration

PIO0_6/SCK0 22[3] yes I/O I; PU PIO0_6 — General purpose digital input/output pin.

I/O - SCK0 — Serial clock for SPI0.

PIO0_7/CTS 23[3] yes I/O I; PU PIO0_7 — General purpose digital input/output pin

(high-current output driv e r).

I-CTS — Clear To Send input for UART.

PIO0_8/MISO0/

CT16B0_MAT0 27[3] yes I/O I; PU PIO0_8 — General purpose digital input/output pin.

I/O - MISO0 — Master In Slave Out for SPI0.

O-CT16B0_MAT0 — Match output 0 for 16-bit timer 0.

PIO0_9/MOSI0/

CT16B0_MAT1 28[3] yes I/O I; PU PIO0_9 — General purpose digital input/output pin.

I/O - MOSI0 — Master Out Slave In for SPI0.

O-CT16B0_MAT1 — Match output 1 for 16-bit timer 0.

Product data sheet Rev. 3 — 10 November 2010 10 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

SWCLK/PIO0_10/

SCK0/

CT16B0_MAT2

29[3] yes I I; PU SWCLK — Serial wire clock.

I/O - PIO0_10 — General purpose digital input/output pin.

I/O - SCK0 — Serial clock for SPI0.

O-CT16B0_MAT2 — Match output 2 for 16-bit timer 0.

R/PIO0_11/

AD0/CT32B0_MAT3 32[5] yes I I; PU R — Reserved. Configure for an alternate function in the

IOCONFIG block.

I/O - PIO0_11 — General purpose digital input/output pin.

I-AD0 — A/D converter, input 0.

O-CT32B0_MAT3 — Match output 3 for 32-bit timer 0.

PIO1_0 to PIO1_11 I/O Port 1 — Port 1 is a 12-bit I/O port with individual direction and

function controls for each bit. The operation of port 1 pins

depends on the function selected through the IOCONFIG

R/PIO1_0/

AD1/CT32B1_CAP0 33[5] yes I I; PU R — Reserved. Configure for an alternate function in the

IOCONFIG block.

I/O - PIO1_0 — General purpose digital input/output pin.

I-AD1 — A/D converter, input 1.

I-CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.

R/PIO1_1/

AD2/CT32B1_MAT0 34[5] no O I; PU R — Reserved. Configure for an alterna te function in the

IOCONFIG block.

I/O - PIO1_1 — General purpose digital input/output pin.

I-AD2 — A/D converter, input 2.

O-CT32B1_MAT0 — Match output 0 for 32-bit timer 1.

R/PIO1_2/

AD3/CT32B1_MAT1 35[5] no I I; PU R — Reserved. Configure for an alternate function in the

IOCONFIG block.

I/O - PIO1_2 — General purpose digital input/output pin.

I-AD3 — A/D converter, input 3.

O-CT32B1_MAT1 — Match output 1 for 32-bit timer 1.

SWDIO/PIO1_3/

AD4/CT32B1_MAT2 39[5] no I/O I; PU SWDIO — Serial wire debug input/output.

I/O - PIO1_3 — General purpose digital input/output pin.

I-AD4 — A/D converter, input 4.

O-CT32B1_MAT2 — Match output 2 for 32-bit timer 1.

PIO1_4/AD5/

CT32B1_MAT3/

WAKEUP

40[5] no I/O I; PU PIO1_4 — General purpose digital input/output pin with 10 ns

glitch filter.

I-AD5 — A/D converter, input 5.

O-CT32B1_MAT3 — Match output 3 for 32-bit timer 1.

I-WAKEUP — Deep power-down mode wake-up pin with 20 ns

glitch filter. This pin must be pull ed HIGH externally to enter

Deep power-down mode and pulled LOW to exit Deep

power-down mode. A LOW-going pulse as short as 50 ns

wakes up the part.

Table 3. LPC1113/14 pin description table (LQFP48 package) …continued

Symbol Pin Start

logic

input

Type Reset

state

[1]

Description

Product data sheet Rev. 3 — 10 November 2010 11 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

PIO1_5/RTS/

CT32B0_CAP0 45[3] no I/O I; PU PIO1_5 — General purpose digital input/ou tput pin.

O-RTS — Request To Send output for UART.

I-CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.

PIO1_6/RXD/

CT32B0_MAT0 46[3] no I/O I; PU PIO1_6 — General purpose digital input/output pin.

I-RXD — Receiver input for UART.

O-CT32B0_MAT0 — Match output 0 for 32-bit timer 0.

PIO1_7/TXD/

CT32B0_MAT1 47[3] no I/O I; PU PIO1_7 — General purpose digital input/output pin.

O-TXD — Transmitter output for UART.

O-CT32B0_MAT1 — Match output 1 for 32-bit timer 0.

PIO1_8/

CT16B1_CAP0 9[3] no I/O I; PU PIO1_8 — General purpose digital input/output pin.

I-CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.

PIO1_9/

CT16B1_MAT0 17[3] no I/O I; PU PIO1_9 — General purpose digital input/output pin.

O-CT16B1_MAT0 — Match output 0 for 16-bit timer 1.

PIO1_10/AD6/

CT16B1_MAT1 30[5] no I/O I; PU PIO1_10 — General purpose digital input/output pin.

I-AD6 — A/D converter, input 6.

O-CT16B1_MAT1 — Match output 1 for 16-bit timer 1.

PIO1_11/AD7 42[5] no I/O I; PU PIO1_11 — General purpose digital input/outp ut pin.

I-AD7 — A/D converter, input 7.

PIO2_0 to PIO2_11 I/O Port 2 — Port 2 is a 12-bit I/O port with individual direction and

function controls for each bit. The operation of port 2 pins

depends on the function selected through the IOCONFIG

PIO2_0/DTR/SSEL1 2[3] no I/O I; PU PIO2_0 — General purpose digital input/ou tput pin.

O-DTR — Data Terminal Ready output for UART.

I/O - SSEL1 — Slave Select for SPI1.

PIO2_1/DSR/SCK1 13[3] no I/O I; PU PIO2_1 — General purpose digital input/output pin.

I-DSR — Data Set Ready input for UART.

I/O - SCK1 — Serial clock for SPI1.

PIO2_2/DCD/MISO1 26[3] no I/O I; PU PIO2_2 — General purpose di gital input/output pin.

I-DCD — Data Carrier Detect input for UART.

I/O - MISO1 — Master In Slave Out for SPI1.

PIO2_3/RI/MOSI1 38[3] no I/O I; PU PIO2_3 — General purpose digital input/output pin.

I-RI — Ring Indicator input for UART.

I/O - MOSI1 — Master Out Slave In for SPI1.

PIO2_4 19[3] no I/O I; PU PIO2_4 — General purpose digital input/output pin.

PIO2_5 20[3] no I/O I; PU PIO2_5 — General purpose digital input/output pin.

PIO2_6 1[3] no I/O I; PU PIO2_6 — General purpose digital input/output pin.

PIO2_7 11[3] no I/O I; PU PIO2_7 — General purpose digital input/output pin.

PIO2_8 12[3] no I/O I; PU PIO2_8 — General purpose digital input/output pin.

PIO2_9 24[3] no I/O I; PU PIO2_9 — General purpose digital input/output pin.

Table 3. LPC1113/14 pin description table (LQFP48 package) …continued

Symbol Pin Start

logic

input

Type Reset

state

[1]

Description

Product data sheet Rev. 3 — 10 November 2010 12 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled.

[2] See Figure 32 for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to

reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down

mode.

[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 31).

[4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus.

[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 31).

[6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

PIO2_10 25[3] no I/O I; PU PIO2_10 — General purpose digital input/output pin.

PIO2_11/SCK0 31[3] no I/O I; PU PIO2_11 — General purpose digital input/output pin.

I/O - SCK0 — Serial clock for SPI0.

PIO3_0 to PIO3_5 I/O Port 3 — Port 3 is a 12-bit I/O port with individual direction and

function controls for each bit. The operation of port 3 pins

depends on the function selected through the IOCONFIG

PIO3_0/DTR 36[3] no I/O I; PU PIO3_0 — General purpose digital input/output pin.

O-DTR — Data Terminal Ready output for UART.

PIO3_1/DSR 37[3] no I/O I; PU PIO3_1 — General purpose digital input/output pin.

I-DSR — Data Set Ready input for UART.

PIO3_2/DCD 43[3] no I/O I; PU PIO3_2 — General purpose digital input/output pin.

I-DCD — Data Carrier Detect input for UART.

PIO3_3/RI 48[3] no I/O I; PU PIO3_3 — General purpose digital input/output pin.

I-RI — Ring Indicator input for UART.

PIO3_4 18[3] no I/O I; PU PIO3_4 — General purpose digital input/output pin.

PIO3_5 21[3] no I/O I; PU PIO3_5 — General purpose digital input/output pin.

VDD 8; 44 - I - 3.3 V supply voltage to the internal regulator, the external rail,

and the ADC. Also used as the ADC reference voltage.

XTALIN 6[6] - I - Input to the oscillator circuit and internal clock generator circuits.

Input voltage must not exceed 1.8 V.

XTALOUT 7[6] - O - Output from the oscillator amplifier.

VSS 5; 41 - I - Ground.

Table 3. LPC1113/14 pin description table (LQFP48 package) …continued

Symbol Pin Start

logic

input

Type Reset

state

[1]

Description

Product data sheet Rev. 3 — 10 November 2010 13 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

Table 4. LPC1114 p in description table (PLCC44 package)

Symbol Pin Start

logic

input

Type Reset

state

[1]

Description

PIO0_0 to PIO0_11 I/O Port 0 — Port 0 is a 12-bit I/O port with individual direction and

function controls for each bit. The operation of port 0 pins depends

on the function selected through the IOCONFIG register block.

RESET/PIO0_0 7[2] yes I I; PU RESET — External reset input with 20 ns glitch filter. A LOW-going

pulse as short as 50 ns on this pin resets the device, causing I/O

ports and peripherals to take on their default states and processor

execution to begin at address 0.

I/O - PIO0_0 — General purpose digital input/output pin with 10 ns glitch

filter.

PIO0_1/CLKOUT/

CT32B0_MAT2 8[3] yes I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW level on

this pin during reset starts the ISP command handler.

O- CLKOUT — Clockout pin.

O- CT32B0_MAT2 — Match output 2 for 32-bit timer 0.

PIO0_2/SSEL0/

CT16B0_CAP0 14[3] yes I/O I; PU PIO0_2 — General purpose digital input/ou tput pin.

I/O - SSEL0 — Slave Select for SPI0.

I- CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.

PIO0_3 18[3] yes I/O I; PU PIO0_3 — General purpose digital input/output pin.

PIO0_4/SCL 19[4] yes I/O I; PU PIO0_4 — General purpose digital input/output pin (open-drain).

I/O - SCL — I2C-bus, open-drain clock input/output. High-current sink

only if I2C Fast-mode Plus is selected in the I/O configuration

PIO0_5/SDA 20[4] yes I/O I; PU PIO0_5 — General purpose digital input/output pin (open-drain).

I/O - SDA — I2C-bus, open-drain data input/output. High-current sink only

if I2C Fast-mode Plus is selected in the I/O configuration register.

PIO0_6/SCK0 26[3] yes I/O I; PU PIO0_6 — General purpose digital input/output pin.

I/O - SCK0 — Serial clock for SPI0.

PIO0_7/CTS 27[3] yes I/O I; PU PIO0_7 — General purpose digital input/outp ut pin (high-current

output driver).

I- CTS — Clear To Send input for UART.

PIO0_8/MISO0/

CT16B0_MAT0 31[3] yes I/O I; PU PIO0_8 — General purpose digital input/outp ut pin.

I/O - MISO0 — Master In Slave Out for SPI0.

O- CT16B0_MAT0 — Match output 0 for 16-bit timer 0.

PIO0_9/MOSI0/

CT16B0_MAT1 32[3] yes I/O I; PU PIO0_9 — General purpose digital input/outp ut pin.

I/O - MOSI0 — Master Out Slave In for SPI0.

O- CT16B0_MAT1 — Match output 1 for 16-bit timer 0.

SWCLK/PIO0_10/

SCK0/CT16B0_MAT2 33[3] yes I I; PU SWCLK — Serial wire clock.

I/O - PIO0_10 — General purpose digital input/output pin.

I/O - SCK0 — Serial clock for SPI0.

O- CT16B0_MAT2 — Match output 2 for 16-bit timer 0.

Product data sheet Rev. 3 — 10 November 2010 14 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

R/PIO0_11/

AD0/CT32B0_MAT3 36[5] yes - I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block.

I/O - PIO0_11 — General purpose digital input/output pin.

I- AD0 — A/D converter, input 0.

O- CT32B0_MAT3 — Match output 3 for 32-bit timer 0.

PIO1_0 to PIO1_11 Port 1 — Port 1 is a 12-bit I/O port with individual direction and

function controls for each bit. The operation of port 1 pins depends

on the function selected through the IOCONFIG register block.

R/PIO1_0/

AD1/CT32B1_CAP0 37[5] yes - I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block.

I/O - PIO1_0 — General purpose dig ital input/output pin.

I- AD1 — A/D converter, input 1.

I- CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.

R/PIO1_1/

AD2/CT32B1_MAT0 38[5] no - I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block.

I/O - PIO1_1 — General purpose dig ital input/output pin.

I- AD2 — A/D converter, input 2.

O- CT32B1_MAT0 — Match output 0 for 32-bit timer 1.

R/PIO1_2/

AD3/CT32B1_MAT1 39[5] no - I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block.

I/O - PIO1_2 — General purpose dig ital input/output pin.

I- AD3 — A/D converter, input 3.

O- CT32B1_MAT1 — Match output 1 for 32-bit timer 1.

SWDIO/PIO1_3/AD4/

CT32B1_MAT2 41[5] no I/O I; PU SWDI O — Serial wire debug input/output.

I/O - PIO1_3 — General purpose dig ital input/output pin.

I- AD4 — A/D converter, input 4.

O- CT32B1_MAT2 — Match output 2 for 32-bit timer 1.

PIO1_4/AD5/

CT32B1_MAT3/

WAKEUP

42[5] no I/O I; PU PIO1_4 — General purpose digital input/outp ut pin with 10 ns glitch

filter.

I- AD5 — A/D converter, input 5.

O- CT32B1_MAT3 — Match output 3 for 32-bit timer 1.

I- WAKEUP — Deep powe r -down mode wake-up pin with 20 ns glitch

filter. This pin must be pulled HIGH externall y to enter Deep

power-down mode and pulled LOW to exit Deep power-down mode.

A LOW-going pulse as short as 50 ns wakes up the part.

PIO1_5/RTS/

CT32B0_CAP0 2[3] no I/O I; PU PIO1_5 — General purpose digital input/output pin.

O- RTS — Request To Send output for UART.

I- CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.

PIO1_6/RXD/

CT32B0_MAT0 3[3] no I/O I; PU PIO1_6 — General purpose digital input/output pin.

I- RXD — Receiver input for UART.

O- CT32B0_MAT0 — Match output 0 for 32-bit timer 0.

Table 4. LPC1114 p in description table (PLCC44 package) …continued

Symbol Pin Start

logic

input

Type Reset

state

[1]

Description

Product data sheet Rev. 3 — 10 November 2010 15 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

PIO1_7/TXD/

CT32B0_MAT1 4[3] no I/O I; PU PIO1_7 — General purpose digital input/output pin.

O- TXD — Transmitter output for UART.

O- CT32B0_MAT1 — Match output 1 for 32-bit timer 0.

PIO1_8/CT16B1_CAP0 13[3] no I/O I; PU PIO1_8 — General purp ose digital input/output pin.

I- CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.

PIO1_9/CT16B1_MAT0 21[3] no I/O I; PU PIO1_9 — General purp ose digital input/output pin.

O- CT16B1_MAT0 — Match output 0 for 16-bit timer 1.

PIO1_10/AD6/

CT16B1_MAT1 34[5] no I/O I; PU PIO1_10 — General purpose digital input/output pin.

I- AD6 — A/D converter, input 6.

O- CT16B1_MAT1 — Match output 1 for 16-bit timer 1.

PIO1_11/AD7 44[5] no I/O I; PU PIO1_11 — Gen eral purpose digital input/output pin.

I- AD7 — A/D converter, input 7.

PIO2_0 to PIO2_11 I/O Port 2 — Port 2 is a 12-bit I/O port with individual direction and

function controls for each bit. The operation of port 2 pins depends

on the function selected through the IOCONFIG register block.

PIO2_0/DTR/SSEL1 6[3] no I/O I; PU PIO2_0 — General purpose digital input/output pin.

O- DTR — Data Terminal Ready output for UART.

I/O - SSEL1 — Slave Select for SPI1.

PIO2_1/DSR/SCK1 17[3] no I/O I; PU PIO2_1 — General purpose digital input/output pin.

I- DSR — Data Set Ready input for UART.

I/O - SCK1 — Serial clock for SPI1.

PIO2_2/DCD/MISO1 30[3] no I/O I; PU PIO2_2 — General purpose digital input/output pin.

I- DCD — Data Carrier Detect input for UART.

I/O - MISO1 — Master In Slave Out for SPI1.

PIO2_3/RI/MOSI1 40[3] no I/O I; PU PIO2_3 — General purpose digital input/output pin.

I- RI — Ring Indicator input for UART.

I/O - MOSI1 — Master Out Slave In for SPI1.

PIO2_4 23[3] no I/O I; PU PIO2_4 — General purpose digital input/output pin.

PIO2_5 24[3] no I/O I; PU PIO2_5 — General purpose digital input/output pin.

PIO2_6 5[3] no I/O I; PU PIO2_6 — General purpose digital input/output pin.

PIO2_7 15[3] no I/O I; PU PIO2_7 — General purpose digital input/output pin.

PIO2_8 16[3] no I/O I; PU PIO2_8 — General purpose digital input/output pin.

PIO2_9 28[3] no I/O I; PU PIO2_9 — General purpose digital input/output pin.

PIO2_10 29[3] no I/O I; PU PIO2_10 — General purpose digital input/output pin.

PIO2_11/SCK0 35[3] no I/O I; PU PIO2_11 — General purpose digital input/output pin.

I/O SCK0 — Serial clock for SPI0.

PIO3_0 to PIO3_5 I/O Port 3 — Port 3 is a 12-bit I/O port with individual direction and

function controls for each bit. The operation of port 3 pins depends

on the function selected through the IOCONFIG register block. Pins

PIO3_0 to PIO3_3 and PIO3_6 to PIO3_11 are not available.

PIO3_4 22[3] no I/O I; PU PIO3_4 — General purpose digital input/output pin.

Table 4. LPC1114 p in description table (PLCC44 package) …continued

Symbol Pin Start

logic

input

Type Reset

state

[1]

Description

Product data sheet Rev. 3 — 10 November 2010 16 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled.

[2] See Figure 32 for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to

reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down

mode.

[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 31).

[4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus.

[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 31).

[6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

PIO3_5 25[3] no I/O I; PU PIO3_5 — General purpose digital input/output pin.

VDD 1; 12 - I - 3.3 V supply voltage to the internal regulator, the external rail, and

the ADC. Also used as the ADC reference voltage.

XTALIN 10[6] - I - Input to the oscillator circuit and internal clock generator circuits.

Input voltage must not exceed 1.8 V.

XTALOUT 11[6] - O - Output from the oscillator amplifier.

VSS 9; 43 - I - Ground.

Table 4. LPC1114 p in description table (PLCC44 package) …continued

Symbol Pin Start

logic

input

Type Reset

state

[1]

Description

Table 5. LPC1111/12/13/14 pin description table (HVQFN33 package)

Symbol Pin Start

logic

input

Type Reset

state

[1]

Description

PIO0_0 to PIO0_11 Port 0 — Port 0 is a 12-bit I/O port with individual direction and

function controls for each bit. The operation of port 0 pins depends on

the function selected through the IOCONFIG register block.

RESET/PIO0_0 2[2] yes I I;PU RESET — External reset input with 20 ns glitch filter. A LOW-going

pulse as short as 50 ns on this pin resets the device, causing I/O ports

and peripherals to take on their default states and processor execution

to begin at ad dre ss 0.

I/O - PIO0_0 — General purpose digital input/output pin with 10 ns glitch

filter.

PIO0_1/CLKOUT/

CT32B0_MAT2 3[3] yes I/O I;PU PIO0_1 — General purpose digital input/output pin. A LOW level on

this pin during reset starts the ISP command handler.

O- CLKOUT — Clock out pin.

O- CT32B0_MAT2 — Match output 2 for 32-bit timer 0.

PIO0_2/SSEL0/

CT16B0_CAP0 8[3] yes I/O I;PU PIO0_2 — General purpose digital input/o utput pin.

I/O - SSEL0 — Slave select for SPI0.

I-CT16B0_CAP0 — Capture input 0 for 16-bi t timer 0.

PIO0_3 9[3] yes I/O I;PU PIO0_3 — General purpose digital input/output pin.

PIO0_4/SCL 10[4] yes I/O I;PU PIO0_4 — General purpose digital input/output pin (open-drain).

I/O - SCL — I2C-bus, open-drain clock input/output. High-current sink only

if I2C Fast-mode Plus is selected in the I/O configuration register.

Product data sheet Rev. 3 — 10 November 2010 17 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

PIO0_5/SDA 11[4] yes I/O I;PU PIO0_5 — General purpose digital input/output pin (open-drain).

I/O - SDA — I2C-bus, open-drain data input/output. High-current sink only if

I2C Fast-mode Plus is selected in the I/O configuration register.

PIO0_6/SCK0 15[3] yes I/O I;PU PIO0_6 — General purpose digital input/output pin.

I/O - SCK0 — Serial clock for SPI0.

PIO0_7/CTS 16[3] yes I/O I;PU PIO0_7 — General purpose digital inpu t/output pin (high-current

output driver).

I-CTS — Clear To Send input for UART.

PIO0_8/MISO0/

CT16B0_MAT0 17[3] yes I/O I;PU PIO0_8 — General purpose digital input/o utput pin.

I/O - MISO0 — Master In Slave Out for SPI0.

O- CT16B0_MAT0 — Match output 0 for 16-bit timer 0.

PIO0_9/MOSI0/

CT16B0_MAT1 18[3] yes I/O I;PU PIO0_9 — General purpose digital input/o utput pin.

I/O - MOSI0 — Master Out Slave In for SPI0.

O- CT16B0_MAT1 — Match output 1 for 16-bit timer 0.

SWCLK/PIO0_10/

SCK0/

CT16B0_MAT2

19[3] yes I I;PU SWCLK — Serial wire clock.

I/O - PIO0_10 — General purpose digital input/output pin.

I/O - SCK0 — Serial clock for SPI0.

O- CT16B0_MAT2 — Match output 2 for 16-bit timer 0.

R/PIO0_11/AD0/

CT32B0_MAT3 21[5] yes - I;PU R — Reserved. Configure for an alternate function in th e IOCONFIG

block.

I/O - PIO0_11 — General purpose digital input/output pin.

I-AD0 — A/D converter, input 0.

O- CT32B0_MAT3 — Match output 3 for 32-bit timer 0.

PIO1_0 to PIO1_11 Port 1 — Port 1 is a 12-bit I/O port with individual direction and

function controls for each bit. The operation of port 1 pins depends on

the function selected through the IOCONFIG register block.

R/PIO1_0/AD1/

CT32B1_CAP0 22[5] yes - I;PU R — Reserved. Configure for an alternate function in the IOCONFIG

block.

I/O - PIO1_0 — General purpose digital input/output pin.

I-AD1 — A/D converter, input 1.

I-CT32B1_CAP0 — Capture input 0 for 32-bi t timer 1.

R/PIO1_1/AD2/

CT32B1_MAT0 23[5] no - I;PU R — Reserved. Configure for an alternate function in the IOCONFIG

block.

I/O - PIO1_1 — General purpose digital input/output pin.

I-AD2 — A/D converter, input 2.

O- CT32B1_MAT0 — Match output 0 for 32-bit timer 1.

R/PIO1_2/AD3/

CT32B1_MAT1 24[5] no - I;PU R — Reserved. Configure for an alternate function in the IOCONFIG

block.

I/O - PIO1_2 — General purpose digital input/output pin.

I-AD3 — A/D converter, input 3.

O- CT32B1_MAT1 — Match output 1 for 32-bit timer 1.

Table 5. LPC1111/12/13/14 pin description table (HVQFN33 package) …continued

Symbol Pin Start

logic

input

Type Reset

state

[1]

Description

Product data sheet Rev. 3 — 10 November 2010 18 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

SWDIO/PIO1_3/

AD4/CT32B1_MAT2 25[5] no I/O I;PU SWDIO — Serial wire debug input/output.

I/O - PIO1_3 — General purpose digital input/output pin.

I-AD4 — A/D converter, input 4.

O- CT32B1_MAT2 — Match output 2 for 32-bit timer 1.

PIO1_4/AD5/

CT32B1_MAT3/

WAKEUP

26[5] no I/O I;PU PIO1_4 — General purpose digital input/output pin with 10 ns glitch

filter.

I-AD5 — A/D converter, input 5.

O- CT32B1_MAT3 — Match output 3 for 32-bit timer 1.

I-WAKEUP — Deep power-down mode wake-up pin with 20 ns glitch

filter. This pin must be pulled HIGH externally to enter Deep

power-down mode and pulled LOW to exit Deep power-down mode. A

LOW-going pulse as short as 50 ns wakes up the part.

PIO1_5/RTS/

CT32B0_CAP0 30[3] no I/O I;PU PIO1_5 — General purpose digital input/output pin.

O- RTS — Request To Send output for UART.

I-CT32B0_CAP0 — Capture input 0 for 32-bi t timer 0.

PIO1_6/RXD/

CT32B0_MAT0 31[3] no I/O I;PU PIO1_6 — General purpose digital input/output pin.

I-RXD — Receiver input for UART.

O- CT32B0_MAT0 — Match output 0 for 32-bit timer 0.

PIO1_7/TXD/

CT32B0_MAT1 32[3] no I/O I;PU PIO1_7 — General purpose digital input/output pin.

O- TXD — Transmitter output for UART.

O- CT32B0_MAT1 — Match output 1 for 32-bit timer 0.

PIO1_8/

CT16B1_CAP0 7[3] no I/O I;PU PIO1_8 — General purpose digital input/output pin.

I-CT16B1_CAP0 — Capture input 0 for 16-bi t timer 1.

PIO1_9/

CT16B1_MAT0 12[3] no I/O I;PU PIO1_9 — General purpose digital input/output pin.

O- CT16B1_MAT0 — Match output 0 for 16-bit timer 1.

PIO1_10/AD6/

CT16B1_MAT1 20[5] no I/O I;PU PIO1_10 — General purpose digital input/output pin.

I-AD6 — A/D converter, input 6.

O- CT16B1_MAT1 — Match output 1 for 16-bit timer 1.

PIO1_11/AD7 27[5] no I/O I;PU PIO1_11 — General purpose digital input/output pin.

I-AD7 — A/D converter, input 7.

PIO2_0 Port 2 — Port 2 is a 12-bit I/O port with individual direction and

function controls for each bit. The operation of port 2 pins depends on

the function selected through the IOCONFIG register block. Pins

PIO2_1 to PIO2_11 are not available.

PIO2_0/DTR 1[3] no I/O I;PU PIO2_0 — General purpose digital input/output pin.

O- DTR — Data Terminal Ready output for UART.

PIO3_0 to PIO3_5 Port 3 — Port 3 is a 12-bit I/O port with individual direction and

function controls for each bit. The operation of port 3 pins depends on

the function selected through the IOCONFIG register block. Pins

PIO3_0, PIO3_1, PIO3_3 and PIO3_6 to PIO3_11 are not available.

PIO3_2 28[3] no I/O I;PU PIO3_2 — General purpose digital input/output pin.

PIO3_4 13[3] no I/O I;PU PIO3_4 — General purpose digital input/output pin.

Table 5. LPC1111/12/13/14 pin description table (HVQFN33 package) …continued

Symbol Pin Start

logic

input

Type Reset

state

[1]

Description

Product data sheet Rev. 3 — 10 November 2010 19 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled.

[2] See Figure 32 for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to

reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down

mode.

[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 31).

[4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus.

[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled, and the pin is not 5 V tolerant (see Figure 31).

[6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

PIO3_5 14[3] no I/O I;PU PIO3_5 — General purpose digital input/output pin.

VDD 6; 29 - I - 3.3 V supply voltage to the internal regulator, the external rail, and the

ADC. Also used as the ADC reference voltage.

XTALIN 4[6] - I - Input to the oscillator circuit and internal clock generator circuits. Input

voltage must not exceed 1.8 V.

XTALOUT 5[6] - O - Output from the oscillator amplifier.

VSS 33 - - - Thermal pad. Connect to ground.

Table 5. LPC1111/12/13/14 pin description table (HVQFN33 package) …continued

Symbol Pin Start

logic

input

Type Reset

state

[1]

Description

Product data sheet Rev. 3 — 10 November 2010 20 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

7. Functional description

7.1 ARM Cortex-M0 processor

The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption.

7.2 On-chip flash program memory

The LPC1111/12/13/14 contain 32 kB (LPC1114), 24 kB (LPC1113), 16 kB (LPC1112), or

8 kB (LPC1111) of on-chip flash memory.

7.3 On-chip SRAM

The LPC1111/12/13/14 contain a total of 8 kB, 4 kB, or 2 kB on-chip static RAM memory.

7.4 Memory map

The LPC1111/12/13/14 incorporates several distinct memory regions, shown in the

following figures. Figure 5 shows the overall map of the entire address space from the

user program viewpoint following reset. The interrupt vector area supports address

remapping.

The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128

peripherals. The APB peripheral area is 512 kB in size and is divided to allow for up to 32

peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows

simplifying the address decoding for each peripheral.

Product data sheet Rev. 3 — 10 November 2010 21 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

7.5 Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The

tight coupling to the CPU allows for low interrupt latency and efficient processing of late

arriving interrupts.

7.5.1 Features

•Controls system exceptions and peripheral interrupts.

(1) LQFP48/PLCC44 packages only.

Fig 5. LPC1111/12/13/14 memory map

0x5000 0000

0x5001 0000

0x5002 0000

0x5020 0000

AHB peripherals

127-16 reserved

GPIO PIO1

4-7

0x5003 0000

0x5004 0000

GPIO PIO2

GPIO PIO3

8-11

12-15

GPIO PIO0

0-3

APB peripherals

0x4000 4000

0x4000 8000

0x4000 C000

0x4001 0000

0x4001 8000

0x4002 0000

0x4002 8000

0x4003 8000

0x4003 C000

0x4004 0000

0x4004 4000

0x4004 8000

0x4004 C000

0x4005 8000

0x4005 C000

0x4008 0000

0x4002 4000

0x4001 C000

0x4001 4000

0x4000 0000

WDT

32-bit counter/timer 0

32-bit counter/timer 1

ADC

UART

PMU

I2C-bus

13-10 reserved

reserved

21-19 reserved

31-23 reserved

reserved

0x0000 0000

0 GB

0.5 GB

4 GB

1 GB

0x0000 2000

0x1000 2000

0x1000 1000

0x1000 0800

0x1FFF 0000

0x1FFF 4000

0x2000 0000

0x4000 0000

0x4008 0000

0x5000 0000

0x5020 0000

0xFFFF FFFF

reserved

APB peripherals

AHB peripherals

8 kB SRAM (LPC1113/14/301/302)

0x1000 0000

4 kB SRAM (LPC1111/12/13/14/201/202)

2 kB SRAM (LPC1111/12/101/102)

LPC1111/12/13/14

8 kB on-chip flash (LPC1111)

0x0000 4000

0x0000 6000

16 kB on-chip flash (LPC1112)

0x0000 8000

32 kB on-chip flash (LPC1114)

24 kB on-chip flash (LPC1113)

16 kB boot ROM

0x0000 0000

0x0000 00C0

active interrupt vectors

002aae69

reserved

SPI0

16-bit counter/timer 1

16-bit counter/timer 0

IOCONFIG

system control

22 SPI1(1)

flash controller

0xE000 0000

0xE010 0000

private peripheral bus

Product data sheet Rev. 3 — 10 November 2010 22 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

•In the LPC1111/12/13/14, the NVIC supports 32 vectored interru pts including up to 13

inputs to the start logic from individual GPIO pins.

•Four programmable interrupt priority levels with hardware priority level masking.

•Software interrupt generation .

7.5.2 Interrupt sources

Each peripheral devi ce has one interrupt line conne cted to the NVIC but may have several

interrupt flags. Individual interrup t flags may also represent more than one interrupt

source.

Any GPIO pin (total of up to 42 pins) regardless of the selected function, can be

programmed to generate an interrupt on a level, or rising edge or falling edge, or both.

7.6 IOCONFIG block

The IOCONFIG block allows selected pins of the microcontroller to have more than one

function. Configuration registers control the multiplexers to allow connection between the

pin and the on-chip peripherals.

Peripherals should be conn ected to th e appro priate pins prior to being activated and prior

to any related interrup t(s) being enabled. Activity of any enabled peripheral function that is

not mapped to a related pin should be considered undefined.

7.7 Fast general purpose parallel I/O

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamica lly configured as input s or outputs. Multip le outputs

can be set or cleared in on e wr ite op e ra tio n.

LPC1111/12/13/14 use accelerated GPIO functions:

•GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing

can be achiev ed .

•Entire port value can be written in one instruction.

Additionally, any GPIO pin (total of up to 42 pins) providing a digital function can be

programmed to generate an interrupt on a level, a rising or falling edge, or both.

7.7.1 Features

•Bit level port registers allow a single instruction to set or clear any number of bits in

one write operation.

•Direction control of individual bits.

•All I/O default to inputs with pull-ups enabled after reset with the exception of the

I2C-bus pins PIO0_4 and PIO0_5.

•Pull-up/pull-down resistor configuration can be programmed through the IOCONFIG

block for each GPIO pin (except for pins PIO0_4 and PIO0_ 5).

7.8 UART

The LPC1111/12/13/14 contain one UART.

Product data sheet Rev. 3 — 10 November 2010 23 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

Support for RS-4 85 /9 -b it mo d e allo ws bo th software addr ess detection and auto m at ic

address detection using 9-bit mode.

The UART includes a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

7.8.1 Features

•Maximum UART data bit rate of 3.125 MBit/s.

•16 Byte Receive and Transmit FIFOs.

•Register locations conform to 16C550 industry standard.

•Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

•Built-in fractional baud ra te generator covering wide range of baud rates without a

need for external crystals of particular values.

•FIFO control mechanism that enables software flow control implementation.

•Support for RS -485 /9 -b it mo d e.

•Support for modem control.

7.9 SPI serial I/O controller

The LPC1111/12/13/14 contain two SPI controllers on the LQFP48/PLCC44 packages

and one SPI controller on the HVQFN33 packages (SPI0). Both SPI controllers support

SSP features.

The SPI controller is capable of operation on a SSP, 4-wire SSI, or Mi crowire bus. It can

interact with multiple masters and slaves on the bus. Only a sing le mas te r and a sing le

slave can communicate on the bus during a given data transfer. The SPI supports full

duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the

slave and from the slave to the master. In practice, often only one of these data flows

carries meaningful data.

7.9.1 Features

•Maximum SPI speed of 25 Mbit/s (maste r) or 4.17 Mbit/s (slave) (in SSP mode)

•Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

•Synchronous serial communication

•Master or slave operation

•8-frame FIFOs for both transmit and receive

•4-bit to 16-bit frame

7.10 I2C-bus serial I/O controller

The LPC1111/12/13/14 contain one I2C-bus controller.

The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line

(SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and

can operate as either a r eceiver-only de vice ( e.g., an LCD driver) or a tra nsmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

Product data sheet Rev. 3 — 10 November 2010 24 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

receivers can oper ate in eithe r master or sl ave mo de, dependin g on whe ther th e chip ha s

to initiate a data transfer or is only addressed. The I2C is a multi-master bus and ca n be

controlled by more than one bus master connected to it.

7.10.1 Features

•The I2C-interface is a standard I2C-bus compliant interface with open-drain pins. The

I2C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s.

•Easy to configure as master, slave, or master/slave.

•Programmable clocks allow versatile rate control.

•Bidirectional data transfer between masters and slaves.

•Multi-master bus (no central master).

•Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

•Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

•Serial clock synchronization can be used as a handshake me chanism to suspend and

resume serial transfer.

•The I2C-bus can be used for test an d diagnostic purposes.

•The I2C-bus controller supports multiple address recognition and a bu s monitor mode.

7.11 10-bit ADC

The LPC1111/12/13/14 contains one ADC. It is a single 10-bit successive approximation

ADC with eight channels.

7.11.1 Features

•10-bit successive approximation ADC.

•Input multiplexing among 8 pins.

•Power-down mode.

•Measurement range 0 V to VDD.

•10-bit conver sio n time ≥ 2.44 μs.

•Burst conversion mode for single or multiple inputs.

•Optional conversion on transition of input pin or timer match signal.

•Individual result registers for each ADC channel to reduce interrupt overhead.

7.12 General purpose external event counter/timers

The LPC1111/12/13/14 includes two 32-bit counter/timers and two 16-bit counter/timers.

The counter/timer is designed to count cycles of the system derived clock. It can optionally

generate interrupts or perform other actions at specified timer values, based on four

match registers. Each counter/timer also includes one capture input to trap the timer value

when an input signal transitions, optionally generating an interrupt.

7.12.1 Features

•A 32-bit/16-bit timer/counter with a prog rammable 32-bit/16-bit prescaler.

Product data sheet Rev. 3 — 10 November 2010 25 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

•Counter or time r op er a tion .

•One capture channel per timer, that can take a snapshot of the timer value when an

input signal transitions. A capture event may also generate an interrupt.

•Four match re gis ter s pe r tim er that allow :

–Continuous operation with optional interrupt generation on match.

–Stop timer on match with optional interrupt generation.

–Reset timer on match with optional inter rupt generation.

•Up to four external outputs corresponding to match registers, with the following

capabilities:

–Set LOW on match.

–Set HIGH on match.

–Toggle on match.

–Do nothing on match.

7.13 System tick timer

The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate

a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).

7.14 Watchdog timer

The purpose of the watchdog is to reset the microcontroller within a selectable time

period.

7.14.1 Features

•Internally resets chip if not periodically reloaded.

•Debug mode.

•Enabled by soft ware but requires a hardwar e reset or a watchdog reset/interrupt to be

disabled.

•Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

•Flag to indicate watchdog reset.

•Programmable 24-bit tim er with internal prescaler.

•Selectable time period from (Tcy(WDCLK) ×256 ×4) to (Tcy(WDCLK) ×224 ×4) in

multiples of Tcy(WDCLK) ×4.

•The W atchdog Clock (WDCLK) source can be selected from the Internal RC oscillator

(IRC), the Watchdog oscillator, or the main clock. This gives a wide range of potential

timing choices of Watchdog operation under different po wer reduction conditions. It

also provides the ability to run the WDT from an entirely internal source that is not

dependent on an external crystal and its associated components and wiring for

increased reliability.

Product data sheet Rev. 3 — 10 November 2010 26 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

7.15 Clocking and power control

7.15.1 Crystal oscillators

The LPC1111/12/13/14 include three independent oscillators. These are the system

oscillator , the Internal RC oscillator (IRC), and the W atchdog oscillator . Each oscillator can

be used for more than one purpose as required in a pa rticular application.

Following reset, the LPC1111/12/13/14 will operate from the Internal RC oscillator until

switched by software. This allows systems to oper ate without any exte rnal cryst al and the

bootloader code to operate at a known frequency.

See Figure 6 for an overview of the LPC1111/12/13/14 clock generation.

7.15.1.1 Internal RC oscillator

The IRC may be used as th e clock source for th e WDT, and/or as the clock that drives the

PLL and subsequently the CPU. The nominal IRC frequ ency is 12 MHz. The IRC is

trimmed to 1 % accuracy over the entire voltage and temperature range.

Fig 6. LPC1111/12/13/14 clock generation block diagram

SYSTEM PLL

IRC oscillator

system oscillator

watchdog oscillator

IRC oscillator

watchdog oscillator

MAINCLKSEL

(main clock select)

SYSPLLCLKSEL

(system PLL clock select)

SYSTEM CLOCK

DIVIDER

AHB clock 0

(system)

AHBCLKCTRL[1:18]

(AHB clock enable)

AHB clocks 1 to 18

(memories

and peripherals)

SPI0 PERIPHERAL

CLOCK DIVIDER SPI0

SPI1 PERIPHERAL

CLOCK DIVIDER SPI1

UART PERIPHERAL

CLOCK DIVIDER UART

WDT CLOCK

DIVIDER WDT

WDTUEN

(WDT clock update enable)

watchdog oscillator

IRC oscillator

system oscillator CLKOUT PIN CLOCK

DIVIDER CLKOUT pin

CLKOUTUEN

(CLKOUT update enable) 002aae514

main clock

system clock

IRC oscillator

Product data sheet Rev. 3 — 10 November 2010 27 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

Upon power-up or an y chip reset, the LPC1111/12/13/14 use the IRC as the clock source.

Software may later switch to one of the other available clock sources.

7.15.1.2 System oscillator

The system oscillator can be used as the clock source for the CPU, with or without using

the PLL.

The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be

boosted to a higher frequency, up to the maximum CPU operating frequency, by the

system PLL.

7.15.1.3 Watchdog oscillator

The watchdog oscillator can be used as a clock source that directly drives the CPU, the

watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is

programmable between 7.8 kHz and 1.7 MHz. The frequency spread over p rocessing and

temperature is ±40 %.

7.15.2 System PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).

The multiplier can be an integer value from 1 to 32. The CCO operates in the range of

156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within

its freq uency range while the PLL is providing the desired output frequen cy. The PLL

output frequency must be lower tha n 100 MHz. The o utput divider may be set to divide by

2, 4, 8, or 16 to pr oduce the output clock. Si nce the minimum outp ut divider value is 2 , it is

insured that the PL L output has a 50 % duty cycle. The PLL is turned off and bypassed

following a chip reset and may be enabled by software. The program must configure and

activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source.

The PLL settling time is 100 μs.

7.15.3 Clock output

The LPC1111/12/13/14 features a clock output function that routes the IRC oscillator, the

system oscillator, the watchdog oscillator, or the main clock to an output pin.

7.15.4 Wake-up process

The LPC1111/12/13/14 begin operation at power-up and when awakened from Deep

power-down mode by using the 12 MHz IRC oscillator as the clock source. This allows

chip operation to resume quickly. If the system oscillator or the PLL is needed by the

application, software will need to enable these features and wait for them to stabilize

before they are used as a clock source.

7.15.5 Power control

The LPC1111/12/13/14 support a variety of power control features. There are three

special modes of processor power reduction: Sleep mode, Deep-sleep mode, and Deep

power-down mode. The CPU clock rate may also be controlled as needed by changing

clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This

allows a trade-off of power versus processing speed based on application requirements.

In addition, a register is provided for shutting down the clocks to individual on -chip

Product data sheet Rev. 3 — 10 November 2010 28 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

peripherals, allowing fine tuning of power consumption by eliminating all dynamic power

use in any periph era ls th at ar e no t req uir ed for the a pplica tion. Selected periph erals have

their own clock divide r wh ich pr ovides even better power control.

7.15.5.1 Power profiles (LPC1100L series, LPC111x/102/202/302 only)

The power consumption in Active and Sleep modes can be optimized for the application

through simple calls to the power profile. The power configuration routine configu res the

LPC1111/12/13/14 for one of the following power modes:

•Default mode corresponding to power configuration after reset.

•CPU performance mode corresponding to optimized processing capability.

•Efficie ncy mode corresponding to optimize d balance of current consumption and CPU

performance.

•Low-current mode corresponding to lowest power consumption.

In addition, the power profile include s routines to select the optimal PLL settings for a

given system clock and PLL input clo ck.

7.15.5.2 Sleep mode

When Sleep mode is entered, the clock to the core is stoppe d. Resumption from the Sleep

mode does not need an y special sequence but re-enabling the clock to the ARM core.

In Sleep mode, execution of instructions is suspended until either a reset or interrupt

occurs. Peripheral functions continue operation during Sleep mode and may generate

interrupts to cause the processor to resume execution. Slee p mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

7.15.5.3 Deep-sleep mode

In Deep-sleep mode, the chip is in Sleep mode, and in add ition all analo g blocks are sh ut

down. As an exception, the user has the option to keep the watchdog oscillator and the

BOD circuit running for se lf-timed wake- up and BOD protection. Dee p-sleep mod e allows

for additiona l powe r sa vin gs.

Up to 13 pins total serve as external wake-up pins to the start logic to wake up the chip

from Deep-sleep mode.

Unless the watchdog oscillator is selected to run in Deep-sleep mode, the clock source

should be switched to IRC before entering Deep-sleep mode, because the IRC can be

switched on and off glitch-free.

7.15.5.4 Deep power-down mode

In Deep power-down mode, power is shut off to the entire chip with the exception of the

WAKEUP pin. The LPC1111/12/13/14 can wake up from Deep power-down mode via the

WAKEUP pin.

A LOW-going pulse as short as 50 ns wakes up the part from Deep power-down mode.

When entering Deep power-do wn mode, an external pull-up resistor is required on the

WAKEUP pin to hold it HIGH. The RESET pin must also be held HIGH to prevent it from

floating while in Deep power-down mode.

Product data sheet Rev. 3 — 10 November 2010 29 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

7.16 System control

7.16.1 Start logic

The start logic connects externa l pins to corresponding interrupts in the NVIC. Each pin

shown in Table 3 to Table 5 as input to the start logic has an individu al interrupt in the

NVIC interrupt vector table. The start logic pins can serve as external interrupt pins when

the chip is running. In addition, an input signal on the start logic pins can wake up the chip

from Deep-sleep mode when all clocks are shut down.

The start logic must be configured in the system configuration block and in the NVIC

before being used.

7.16.2 Reset

Reset has four sources on the LPC1111/12/13/14: the RESET pin, the Watchdog reset,

power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a

Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage

attains a usable level, starts the IRC and initializes the fla sh co nt ro ller.

A LOW-going pulse as short as 50 ns resets the part.

When the internal Reset is removed, th e processor begins executing at address 0, which

is initially the Reset vector mapped from the boot block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

An external pull-up resistor is required on the RESET pin if Deep power-down mode is

used.

7.16.3 Brownout detection

The LPC1111/12/13/14 includes four levels for monitoring the voltage on the VDD pin. If

this voltage falls below on e of the four select ed levels, the BOD asserts an interrupt signal

to the NVIC. This signal can be enabled for interrupt in the Interr upt Enable Register in th e

NVIC in order to cause a CPU interrupt; if no t, software can monitor the signal by reading

a dedicated status register. Four additional threshold levels can be selected to cause a

forced reset of the chip.

7.16.4 Code security (Code Read Protection - CRP)

This feature of the LPC1111/12/13/14 allows user to enable different levels of security in

the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD)

and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by

programming a specific pattern into a dedicated flash location. IAP commands are not

affected by the CRP.

In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For

details see the LPC111x user manual.

There are three levels of Code Read Protection:

1. CRP1 disables access to the chip via the SWD and allows partial flash update

(excluding flash sector 0) using a limited set of the ISP commands. This mode is

useful when CRP is required and flash field updates are neede d but all sectors can

not be erased.

Product data sheet Rev. 3 — 10 November 2010 30 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

2. CRP2 disables access to the chip via the SWD and only allows full flash erase and

update using a reduced set of the ISP commands.

3. Running an application with level CRP3 selected fully disables any access to the ch ip

via the SWD pins and the ISP. This mode effectively disables ISP override using

PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update

mechanism using IAP calls or call reinvoke ISP command to enable flash update via

the UART.

In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be

disabled. For details see the LPC111x user manual.

7.16.5 APB interface

The APB peripherals are located on one APB bus.

7.16.6 AHBLite

The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main

static RAM, and the Boot ROM.

7.16.7 External interrupt inputs

All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs

serve as exte rn al in te r ru pts (see Section 7.16.1).

7.17 Emulation and debugging

Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four

breakpoints and two watchpoints is supported.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

Product data sheet Rev. 3 — 10 November 2010 31 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

8. Limiting values

[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless

otherwise noted.

[2] Including voltage on outputs in 3-state mode.

[3] The peak current is limited to 25 times the corresponding maximum current.

[4] Dependent on package type.

[5] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

Table 6. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).[1]

Symbol Parameter Conditions Min Max Unit

VDD supply voltage (core and external rail) 1.8 3.6 V

VIinput voltage 5 V tolerant I/O

pins; only valid

when the VDD

supply voltage is

present

[2] −0.5 +5.5 V

IDD supply current per supply pin [3] - 100 mA

ISS ground current per ground pin [3] - 100 mA

Ilatch I/O latch-up current −(0.5VDD) < VI <

(1.5VDD);

Tj < 125 °C

- 100 mA

Tstg storage temperature [4] −65 +150 °C

Tj(max) maximum junction temperature - 150 °C

Ptot(pack) total power dissipation (per package) based on package

heat transfer, not

device power

consumption

-1.5W

VESD electrostatic discharge voltage human body

model; all pins [5] −6500 +6500 V

Product data sheet Rev. 3 — 10 November 2010 32 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

9. Static characteristics

Table 7. Static characteristics

Tamb =−40 °C to +85 °C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

VDD supply voltage (core

and external rail) 1.8 3.3 3.6 V

LPC1100 series (LPC11 1x/101/201/301) power consumption

IDD supply current Active mode; code

while(1){}

executed from flash

system clock = 12 MHz

VDD = 3.3 V

[2][3][4]

[5][6] -3-mA

system clock = 50 MHz

VDD = 3.3 V

[2][3][5]

[6][7] -9-mA

Sleep mode;

system clock = 12 MHz

VDD = 3.3 V

[2][3][4]

[5][6] -2-mA

Deep-sleep mode;

VDD = 3.3 V [2][3][8] -6-μA

Deep power-down mode;

VDD = 3.3 V [2][9] -220-nA

LPC1100L se ries (LPC111x/102/202/302) power consumption in low-c urrent mode[10]

IDD supply current Active mode; code

while(1){}

executed from flash

system clock = 12 MHz

VDD = 3.3 V

[2][3][4]

[5][6] -2-mA

system clock = 50 MHz

VDD = 3.3 V

[2][3][5]

[6][7] -7-mA

Sleep mode;

system clock = 12 MHz

VDD = 3.3 V

[2][3][4]

[5][6] -1-mA

Deep-sleep mode;

VDD = 3.3 V [2][3][8] -2-μA

Deep power-down mode;

VDD = 3.3 V [2][9] -220-nA

Standard port pins, RESET

IIL LOW-level input current VI= 0 V; on-chip pull-up

resistor disabled - 0.5 10 nA

IIH HIGH-level input

current VI=V

DD; on-chip

pull-down resistor

disabled

- 0.5 10 nA

IOZ OFF-state output

current VO=0V; V

O=V

DD;

on-chip pull-up/down

resistors disabled

- 0.5 10 nA

Product data sheet Rev. 3 — 10 November 2010 33 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

VIinput voltage pin configured to provide

a digital function [11][12]

[13] 0- 5.0V

VOoutput voltage output active 0 - VDD V

VIH HIGH-level input

voltage 0.7VDD --V

VIL LOW-level input voltage - - 0.3VDD V

Vhys hysteresis voltage - 0.4 - V

VOH HIGH-level output

voltage 2.0 V ≤ VDD ≤ 3.6 V;

IOH =−4 mA VDD − 0.4--V

1.8 V ≤ VDD < 2.0 V;

IOH =−3 mA VDD − 0.4--V

VOL LOW-level output

voltage 2.0 V ≤ VDD ≤ 3.6 V;

IOL =4 mA --0.4V

1.8 V ≤ VDD < 2.0 V;

IOL =3 mA --0.4V

IOH HIGH-level output

current VOH =V

DD −0.4 V;

2.0 V ≤ VDD ≤ 3.6 V

−4--mA

1.8 V ≤ VDD < 2.0 V −3--mA

IOL LOW-level output

current VOL =0.4V

2.0 V ≤ VDD ≤ 3.6 V 4--mA

1.8 V ≤ VDD < 2.0 V 3--mA

IOHS HIGH-level short-circuit

output current VOH =0V [14] --−45 mA

IOLS LOW-level short-circuit

output current VOL =V

DD [14] --50mA

Ipd pull-down curre nt VI=5V 10 50 150 μA

Ipu pull-up current VI=0V;

2.0 V ≤ VDD ≤ 3.6 V

−15 −50 −85 μA

1.8 V ≤ VDD < 2.0 V −10 −50 −85 μA

VDD <V

I<5V 000μA

High-drive output pin (PIO0_7)

IIL LOW-level input current VI= 0 V; on-chip pull-up

resistor disabled - 0.5 10 nA

IIH HIGH-level input

current VI=V

DD; on-chip

pull-down resistor

disabled

- 0.5 10 nA

IOZ OFF-state output

current VO=0V; V

O=V

DD;

on-chip pull-up/down

resistors disabled

- 0.5 10 nA

VIinput voltage pin configured to provide

a digital function [11][12]

[13] 0- 5.0V

VOoutput voltage output active 0 - VDD V

VIH HIGH-level input

voltage 0.7VDD --V

Table 7. Static characteristics …continued

Tamb =−40 °C to +85 °C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 3 — 10 November 2010 34 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

VIL LOW-level input voltage - - 0.3VDD V

Vhys hysteresis voltage 0.4 - - V

VOH HIGH-level output

voltage 2.5 V ≤ VDD ≤ 3.6 V;

IOH =−20 mA VDD − 0.4--V

1.8 V ≤ VDD < 2.5 V;

IOH =−12 mA VDD − 0.4--V

VOL LOW-level output

voltage 2.0 V ≤ VDD ≤ 3.6 V;

IOL =4 mA --0.4V

1.8 V ≤ VDD < 2.0 V;

IOL =3 mA --0.4V

IOH HIGH-level output

current VOH =V

DD −0.4 V;

2.5 V ≤ VDD ≤ 3.6 V 20--mA

1.8 V ≤ VDD < 2.5 V 12 - - mA

IOL LOW-level output

current VOL =0.4V

2.0 V ≤ VDD ≤ 3.6 V 4--mA

1.8 V ≤ VDD < 2.0 V 3--mA

IOLS LOW-level short-circuit

output current VOL =V

DD [14] --50mA

Ipd pull-down curre nt VI=5V 10 50 150 μA

Ipu pull-up current VI=0V

2.0 V ≤ VDD ≤ 3.6 V

−15 −50 −85 μA

1.8 V ≤ VDD < 2.0 V −10 −50 −85 μA

VDD <V

I<5V 000μA

I2C-bus pins (PIO0_4 and PIO0_5)

VIH HIGH-level input

voltage 0.7VDD --V

VIL LOW-level input voltage - - 0.3VDD V

Vhys hysteresis voltage - 0.5VDD -V

IOL LOW-level output

current VOL =0.4V; I

2C-bus pins

configured as standard

mode pins

2.0 V ≤ VDD ≤ 3.6 V

4--mA

1.8 V ≤ VDD < 2.0 V 3 - -

IOL LOW-level output

current VOL =0.4V; I

2C-bus pins

configure d as Fast -mo de

Plus pins

2.0 V ≤ VDD ≤ 3.6 V

20--mA

1.8 V ≤ VDD < 2.0 V 16 - -

ILI input leakage current VI=V

DD [15] -24μA

VI=5V - 10 22 μA

Oscillator pins

Vi(xtal) crystal input voltage −0.5 1.8 1.95 V

Vo(xtal) crystal output voltage −0.5 1.8 1.95 V

Table 7. Static characteristics …cont inued

Tamb =−40 °C to +85 °C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 3 — 10 November 2010 35 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.

[2] Tamb =25°C.

[3] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.

[4] IRC enabled; system oscillator disabled; system PLL disabled.

[5] BOD disabled.

[6] All peripherals disabled in the SYSAHBCLKCTRL register. Peri pheral clocks to UART and SPI0/1 disabled in system configuration

block.

[7] IRC disabled; system oscillator enabled; system PLL enabled.

[8] All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 18FF.

[9] WAKEUP pin pulled HIGH externally.

[10] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles.

[11] Including voltage on outputs in 3-state mode.

[12] VDD supply voltage must be present.

[13] 3-state outputs go into 3-state mode in Deep power-down mode.

[14] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[15] To VSS.

[1] The ADC is monotonic, there are no missing codes.

[2] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 7.

[3] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 7.

[4] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the

ideal curve. See Figure 7.

[5] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset

error, and the straight line which fits the ideal transfer curve. See Figure 7.

[6] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated

ADC and the ideal transfer curve. See Figure 7.

[7] Tamb = 25 °C; maximum sampling frequency fs = 4.5 MHz and analog input capacitance Cia = 1 pF.

[8] Input resistance Ri depends on the sampling frequency fs: Ri = 1 / (fs × Cia).

Table 8. ADC static characteristics

Tamb =−40 °C to +85 °C unless otherwise specified; ADC frequency 4.5 MHz, VDD = 2.5 V to 3.6 V.

Symbol Parameter Conditions Min Typ Max Unit

VIA analog input voltage 0 - VDD V

Cia analog input capacitance - - 1 pF

EDdifferential linearity error [1][2] --± 1LSB

EL(adj) integral non-linearity [3] --± 1.5 LSB

EOoffset error [4] --± 3.5 LSB

EGgain error [5] --0.6%

ETabsolute er ror [6] --± 4LSB

Rvsi voltage source interface

resistance --40kΩ

Riinput resistance [7][8] --2.5MΩ

Product data sheet Rev. 3 — 10 November 2010 36 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (ED).

(4) Integral non-linearity (EL(adj)).

(5) Center of a step of the actual transfer curve.

Fig 7. ADC characteristics

002aaf426

1023

1022

1021

1020

1019

(2)

(1)

10241018 1019 1020 1021 1022 1023

7123456

1018

(5)

(4)

(3)

1 LSB

(ideal)

code

out

VDD − VSS

1024

offset

error

gain

error

offset error

VIA (LSBideal)

1 LSB =

Product data sheet Rev. 3 — 10 November 2010 37 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

9.1 BOD static characteristics

[1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC111x

user manual.

9.2 Power consumption LPC111x/101/201/301

Power measurement s in Active, Sleep , and Deep-sleep modes wer e performed under the

following conditions (see LPC111x user manual):

•Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block.

•Configure GPIO pins as outputs using the GPIOnDIR registers.

•Write 0 to all GPIOnDATA registers to drive the outputs LOW.

Table 9. BOD static characteristics[1]

Tamb =25°C.

Symbol Parameter Conditions Min Typ Max Unit

Vth threshold voltage i nterrupt level 0

assertion - 1.65 - V

de-assertion - 1.80 - V

interrupt level 1

assertion - 2.22 - V

de-assertion - 2.35 - V

interrupt level 2

assertion - 2.52 - V

de-assertion - 2.66 - V

interrupt level 3

assertion - 2.80 - V

de-assertion - 2.90 - V

reset level 0

assertion - 1.46 - V

de-assertion - 1.63 - V

reset level 1

assertion - 2.06 - V

de-assertion - 2.15 - V

reset level 2

assertion - 2.35 - V

de-assertion - 2.43 - V

reset level 3

assertion - 2.63 - V

de-assertion - 2.71 - V

Product data sheet Rev. 3 — 10 November 2010 38 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

Conditions: Tamb = 25 °C; active mode entered executing code

while(1){}

from flash; all peripherals

disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks

disabled; internal pull-up resistors disabled; BOD disabled.

(1) System oscillator and system PLL disabled; IRC enabled.

(2) System oscillator and system PLL enabled; IRC disabled.

Fig 8. Active mode: Typical supply current IDD versus supply voltage VDD for different

system clock frequencies (for LPC111x/101/201/301)

Conditions: VDD = 3.3 V; active mode entered executing code

while(1){}

from flash; all peripherals

disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks

disabled; internal pull-up resistors disabled; BOD disabled.

(1) System oscillator and system PLL disabled; IRC enabled.

(2) System oscillator and system PLL enabled; IRC disabled.

Fig 9. Active mode: Typical supply current IDD versus temperature for different system

clock frequencies (for LPC111x/101/201/301)

VDD (V)

1.8 3.63.02.4

002aaf390

IDD

(mA)

12 MHz(1)

24 MHz(2)

36 MHz(2)

48 MHz(2)

temperature (°C)

−40 853510 60−15

002aaf391

IDD

(mA)

12 MHz(1)

24 MHz(2)

36 MHz(2)

48 MHz(2)

Product data sheet Rev. 3 — 10 November 2010 39 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the

SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal

pull-up resistors disabled; BOD disabled.

(1) System oscillator and system PLL disabled; IRC enabled.

(2) System oscillator and system PLL enabled; IRC disabled.

Fig 10. Sleep mode: Typical supply current IDDversus temperature for differen t system

clock frequencies (for LPC111x/101/201/301)

Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register

(PDSLEEPCFG = 0x0000 18FF).

Fig 11. Deep-sleep mode: Typical supply current IDD versus temperature for different

supply vo ltages VDD (for LPC111x/101/201/301)

002aaf392

temperature (°C)

−40 853510 60−15

IDD

(mA)

12 MHz(1)

36 MHz(2)

48 MHz(2)

24 MHz(2)

002aaf394

temperature (°C)

−40 853510 60−15

IDD

(μA)

3.6 V

3.3 V

2.0 V

1.8 V

Product data sheet Rev. 3 — 10 November 2010 40 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

9.3 Power consumption LPC111x/102/202/302

Power measurement s in Active, Sleep , and Deep-sleep modes wer e performed under the

following conditions (see LPC111x user manual):

•Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block.

•Configure GPIO pins as outputs using the GPIOnDIR registers.

•Write 0 to all GPIOnDATA registers to drive the outputs LOW.

Fig 12. Deep power-down mode: Typical supply current IDD versus temperature for

different supply voltages VDD (for LPC1 11x/101/201/301)

002aaf457

0.2

0.6

0.4

0.8

IDD

(μA)

temperature (°C)

−40 853510 60−15

VDD = 3.6 V

3.3 V

2.0 V

1.8 V

Product data sheet Rev. 3 — 10 November 2010 41 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

Conditions: Tamb = 25 °C; active mode entered executing code

while(1){}

from flash; all peripherals

disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks

disabled; internal pull-up resistors disabled; BOD disabled.

(1) System oscillator and system PLL disabled; IRC enabled.

(2) System oscillator and system PLL enabled; IRC disabled.

Fig 13. Active mode: Typical supply current IDD versus supply voltage VDD for different

system clock frequencies (for LPC111x/102/202/302)

Conditions: VDD = 3.3 V; active mode entered executing code

while(1){}

from flash; all peripherals

disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks

disabled; internal pull-up resistors disabled; BOD disabled.

(1) System oscillator and system PLL disabled; IRC enabled.

(2) System oscillator and system PLL enabled; IRC disabled.

Fig 14. Active mode: Typical supply current IDD versus temperature for different system

clock frequencies (for LPC111x/102/202/302)

<tbd>

X (X)

XXXXXX

001aab173

(X)

<tbd>

X (X)

XXXXXX

001aab173

(X)

Product data sheet Rev. 3 — 10 November 2010 42 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the

SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal

pull-up resistors disabled; BOD disabled.

(1) System oscillator and system PLL disabled; IRC enabled.

(2) System oscillator and system PLL enabled; IRC disabled.

Fig 15. Sleep mode: Typical supply current IDDversus temperature for differen t system

clock frequencies (for LPC111x/102/202/302)

Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register

(PDSLEEPCFG = 0x0000 18FF).

Fig 16. Deep-slee p mode: Typi cal supply cu rrent IDD versus temperature for different

supply vo ltages VDD (for LPC111x/102/202/302)

<tbd>

X (X)

XXXXXX

001aab173

(X)

<tbd>

X (X)

XXXXXX

001aab173

(X)

Product data sheet Rev. 3 — 10 November 2010 43 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

Fig 17. Deep power-down mode: Typical supply current IDD versus temperature for

different supply voltages VDD (for LPC1 11x/102/202/302)

<tbd>

X (X)

XXXXXX

001aab173

(X)

Product data sheet Rev. 3 — 10 November 2010 44 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

9.4 Peripheral power consumption

The supply current p er peripheral is measured as the differ ence in supply current between

the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG

and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both

registers and no code is executed. Mea sured on a typical sample at Tamb =25 °C. Unless

noted otherwise, the system oscillator and PLL are running in both measurements.

The supply currents are shown for system clock frequencies of 12 MHz and 48 MHz.

Table 10. Power consumpt ion for individu al analog and digi tal blocks

Peripheral Typical supply current in

mA Notes

n/a 12 MHz 48 MHz

IRC 0.27 - - System oscillator running; PLL off; independent

of main clock frequency.

System oscillator

at 12 MHz 0.22 - - IRC running; PLL off; independent of main clock

frequency.

Watchdog

oscillator at

500 kHz/2

0.004 - - System oscillator running; PLL off; independent

of main clock frequency.

BOD 0.051 - - Independent of main clock frequency.

Main PLL - 0.21 -

ADC - 0.08 0.29

CLKOUT - 0.12 0.47 Main clock divided by 4 in the CLKOUTDIV

CT16B0 - 0.02 0.06

CT16B1 - 0.02 0.06

CT32B0 - 0.02 0.07

CT32B1 - 0.02 0.06

GPIO - 0.23 0.88 GPIO pins configured as outputs and set to

LOW. Direction and pin state are maintained if

the GPIO is disabled in the SYSAHBCLKCFG

IOCONFIG - 0.03 0.10

I2C - 0.04 0.13

ROM - 0.04 0.15

SPI0 - 0.12 0.45

SPI1 - 0.12 0.45

UART - 0.22 0.82

WDT - 0.02 0.06 Main clock selected as clock source for the

WDT.

Product data sheet Rev. 3 — 10 November 2010 45 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

9.5 Electrical pin characteristics

Conditions: VDD = 3.3 V; on pin PIO0_7.

Fig 18. High-drive output: Typical HIGH-level outpu t voltage VOH versus HIGH-level

output current IOH.

Conditions: VDD = 3.3 V; on pins PIO0_4 and PIO0_5.

Fig 19. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus

LOW-level output voltage VOL

IOH (mA)

0 60402010 5030

002aae990

2.8

2.4

3.2

3.6

VOH

(V)

T = 85 °C

25 °C

−40 °C

VOL (V)

0 0.60.40.2

002aaf019

IOL

(mA)

T = 85 °C

25 °C

−40 °C

Product data sheet Rev. 3 — 10 November 2010 46 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

Conditions: VDD = 3.3 V; standard port pins and PIO0_7.

Fig 20. Typical LOW-level output current IOL versus LOW-level output voltage VOL

Conditions: VDD = 3.3 V; standard port pins.

Fig 21. Typical HIGH-level output voltage VOH versus HIGH-level output source current

IOH

VOL (V)

0 0.60.40.2

002aae991

IOL

(mA)

T = 85 °C

25 °C

−40 °C

IOH (mA)

0 24168

002aae992

2.8

2.4

3.2

3.6

VOH

(V)

T = 85 °C

25 °C

−40 °C

Product data sheet Rev. 3 — 10 November 2010 47 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

Conditions: VDD = 3.3 V; standard port pins.

Fig 22. Typical pull-up curren t Ipu versus input voltage VI

Conditions: VDD = 3.3 V; standard port pins.

Fig 23. Typical pull-down curren t Ipd versus input voltage VI

VI (V)

0 54231

002aae988

−30

−50

−10

Ipu

(μA)

−70

T = 85 °C

25 °C

−40 °C

VI (V)

0 54231

002aae989

Ipd

(μA)

T = 85 °C

25 °C

−40 °C

Product data sheet Rev. 3 — 10 November 2010 48 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

10. Dynamic characteristics

10.1 Flash memory

[1] Number of program/erase cycles.

[2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash

in blocks of 256 bytes.

10.2 External clock

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply

voltages.

Table 11. Flash characteristics

Tamb =−40 °C to +85 °C, unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Nendu endurance [1] 10000 - - cycles

tret retention time powered 10 - - years

unpowered 20 - - years

ter erase time sector or multiple

consecutive

sectors

95 100 105 ms

tprog programming

time [2] 0.95 1 1.05 ms

Table 12. Dynamic characteristic: external clock

Tamb =−40 °C to +85 °C; VDD over specified ranges.[1]

Symbol Parameter Conditions Min Typ[2] Max Unit

fosc oscillator frequency 1 - 25 MHz

Tcy(clk) clock cycle time 40 - 1000 ns

tCHCX clock HIGH time Tcy(clk) ×0.4 - - ns

tCLCX clock LOW time Tcy(clk) ×0.4 - - ns

tCLCH clock rise time - - 5 ns

tCHCL clock fall time - - 5 ns

Fig 24. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)

CHCL

CLCX

CHCX

cy(clk)

CLCH

002aaa90

Product data sheet Rev. 3 — 10 November 2010 49 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

10.3 Internal oscillators

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply

voltages.

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply

voltages.

[2] The typical frequency spread over processing and temperature (Tamb = −40 °C to +85 °C) is ±40 %.

[3] See the LPC111x user manual.

Table 13. Dynamic characteristic: internal oscillators

Tamb =−40 °C to +85 °C; 2.7 V ≤ VDD ≤ 3.6 V.[1]

Symbol Parameter Conditions Min Typ[2] Max Unit

fosc(RC) internal RC oscillator freq uency - 11.88 12 12.12 MHz

Conditions: Frequency values are typical values. 12 MHz ± 1 % accuracy is guaranteed for

2.7 V ≤ VDD ≤ 3.6 V and Tamb =−40 °C to +85 °C. Variations between parts may cause the IRC to

fall outside the 12 MHz ± 1 % accuracy specification for voltages below 2.7 V.

Fig 25. Internal RC oscillator frequency vs. temperature

Ta ble 14. Dynamic characteristics: Watchdog oscillator

Symbol Parameter Conditions Min Typ[1] Max Unit

fosc(int) internal oscillator

frequency DIVSEL = 0x1F, FREQSEL = 0x1

in the WDTOSCCTRL register; [2][3] -7.8 - kHz

DIVSEL = 0x00, FREQSEL = 0xF

in the WDTOSCCTRL regi st er [2][3] - 1700 - kHz

002aaf403

11.95

12.05

12.15

(MHz)

11.85

temperature (°C)

−40 853510 60−15

VDD = 3.6 V

3.3 V

3.0 V

2.7 V

2.4 V

2.0 V

Product data sheet Rev. 3 — 10 November 2010 50 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

10.4 I/O pins

[1] Applies to standard port pins and RESET pin.

10.5 I2C-bus

[1] See the I2C-bus specification UM10204 fo r details.

[2] Parameters are valid over operating temperature range unless otherwise specified.

[3] tHD;DAT is the data hold time that is measured from the falling edg e of SCL; applies to data in transmission

and the acknowledge.

[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the

VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.

[5] Cb = total capacitance of one bus line in pF.

Table 15. Dynamic ch aracteristic: I/O pins[1]

Tamb =−40 °C to +85 °C; 3.0 V ≤ VDD ≤ 3.6 V.

Symbol Parameter Conditions Min Typ Max Unit

trrise time pin

configured as

output

3.0 - 5.0 ns

tffall time pin

configured as

output

2.5 - 5.0 ns

Table 16. Dynamic characteristic: I2C-bus pins[1]

Tamb =−40 °C to +85 °C.[2]

Symbol Parameter Conditions Min Max Unit

fSCL SCL clock

frequency Standard-mode 0 100 kHz

Fast-mode 0 400 kHz

Fast-mode Plus 0 1 MHz

tffall time [4][5][6][7] of both SDA and

SCL signals

Standard-mode

- 300 ns

Fast-mode 20 + 0.1 × Cb300 ns

Fast-mode Plus - 120 ns

tLOW LOW period of

the SCL clock Standard-mode 4.7 - μs

Fast-mode 1.3 - μs

Fast-mode Plus 0.5 - μs

tHIGH HIGH period of

the SCL clock Standard-mode 4.0 - μs

Fast-mode 0.6 - μs

Fast-mode Plus 0.26 - μs

tHD;DAT data hold time [3][4][8] Standard-mode 0 - μs

Fast-mode 0 - μs

Fast-mode Plus 0 - μs

tSU;DAT data set-up

time

[9][10] Standard-mode 250 - ns

Fast-mode 100 - ns

Fast-mode Plus 50 - ns

Product data sheet Rev. 3 — 10 November 2010 51 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

[6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA

output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the

SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.

[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors

are used, designers should allow for this when considering bus timing.

[8] The maximum tHD;DAT could be 3.45 μs and 0.9 μs for S tandard-mode and Fast-mode but must be less than

the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if

the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the

data must be valid by the set-up time before it releases the clock.

[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to d ata in

transmission and the acknowledge.

[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement

tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the

LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must

output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the

Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must

meet this set-up time.

10.6 SPI interfaces

Fig 26. I2C-bus pins clock timing

002aaf425

70 %

30 %

SDA

70 %

30 %

70 %

30 %

70 %

30 %

tHD;DAT

SCL

1 / fSCL

70 %

30 %

70 %

30 %

tVD;DAT

tHIGH

tLOW

tSU;DAT

Table 17. Dynamic characteristics of SPI pins in SPI mode

Symbol Parameter Conditions Min Typ Max Unit

SPI master (in SPI mode)

Tcy(clk) clock cycle time when only receiving [1] 40 - - ns

when only transmitting [1] 27.8 ns

tDS data set-up time in SPI mode

2.4 V ≤ VDD ≤ 3.6 V

[2] 15 - - ns

2.0 V ≤ VDD < 2.4 V [2] 20 ns

1.8 V ≤ VDD < 2.0 V [2] 24 - - ns

tDH data hold time in SPI mode [2] 0-- ns

tv(Q) data output valid time in SPI mode [2] --10 ns

th(Q) data output hold time in SPI mode [2] 0-- ns

SPI slave (in SPI mode)

Product data sheet Rev. 3 — 10 November 2010 52 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

[1] Tcy(clk) = (SSPCLKDIV × (1 + SCR) × CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the

main clock frequency fmain, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),

and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).

[2] Tamb = −40 °C to 85 °C.

[3] Tcy(clk) = 12 × Tcy(PCLK).

[4] Tamb = 25 °C; for normal voltage supply range: VDD = 3.3 V.

Tcy(PCLK) PCLK cycle time 20 - - ns

tDS data set-up time in SPI mode [3][4] 0-- ns

tDH data hold time in SPI mode [3][4] 3 × Tcy(PCLK) + 4 - - ns

tv(Q) data output valid time in SPI mode [3][4] --3 × Tcy(PCLK) + 11 ns

th(Q) data output hold time in SPI mode [3][4] --2 × Tcy(PCLK) + 5 ns

Table 17. Dynamic characteristics of SPI pins in SPI mode

Symbol Parameter Conditions Min Typ Max Unit

Pin names SCK, MISO, and MOSI r e fer to pins for both SPI peripherals, SPI0 and SPI1.

Fig 27. SPI master timing in SPI mode

SCK (CPOL = 0)

MOSI

MISO

Tcy(clk) tclk(H) tclk(L)

tDS tDH

tv(Q)

DATA VALID DATA VALID

th(Q)

SCK (CPOL = 1)

DATA VALID DATA VALID

MOSI

MISO

tDS tDH

DATA VALID DATA VALID

th(Q)

DATA VALID DATA VALID

tv(Q)

CPHA = 1

CPHA = 0

002aae82

Product data sheet Rev. 3 — 10 November 2010 53 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

Pin names SCK, MISO, and MOSI r e fer to pins for both SPI peripherals, SPI0 and SPI1.

Fig 28. SPI slave timing in SPI mode

SCK (CPOL = 0)

MOSI

MISO

Tcy(clk) tclk(H) tclk(L)

tDS tDH

tv(Q)

DATA VALID DATA VALID

th(Q)

SCK (CPOL = 1)

DATA VALID DATA VALID

MOSI

MISO

tDS tDH

tv(Q)

DATA VALID DATA VALID

th(Q)

DATA VALID DATA VALID

CPHA = 1

CPHA = 0

002aae83

Product data sheet Rev. 3 — 10 November 2010 54 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

11. Application information

11.1 ADC usage notes

The following guidelines show how to increase the performance of the ADC in a noisy

environment beyond the ADC specifications listed in Table 8:

•The ADC input trace mu st be short and as close as possible to the LPC1111/12/13/14

chip.

•The ADC input traces must be shielded from fast switching digital signals and noisy

power supply lin e s.

•Because the ADC and the digital co re share the same power supply, the power supply

line must be adequately filtered.

•To improve the ADC performance in a very noisy environment, put the device in Sleep

mode during the ADC conversion.

11.2 XTAL input

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a

clock in slave mode, it is recommende d that the inpu t be coupled th rough a cap acitor wi th

Ci = 100 pF. To limit the input voltage to the specified range, choose an additional

capacitor to ground Cg which attenuates the input volt age by a facto r Ci/(Ci + Cg). In slave

mode, a minimum of 200 mV(RMS) is needed.

In slave mode the input clock signal should be coup led by means of a cap acitor of 100 pF

(Figure 29), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This

corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.

The XTALOUT pin in this configuration can be left unconnected.

External components and models used in oscillation mode are shown in Figure 30 and in

Table 18 and Table 19. Since the feedback resistance is integrated on chip, only a crystal

and the capacitances CX1 and CX2 need to be connected externally in case of

fundamental mode oscillation (the fundamental frequency is represented by L, CL and

RS). Capacitance CP in Figure 30 represent s the p arallel p ackage cap acitance and should

not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal

manufacturer (see Table 18).

Fig 29. Slave mode operation of the on-chip oscillator

LPC1xxx

XTALIN

100 pF

002aae78

Product data sheet Rev. 3 — 10 November 2010 55 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

11.3 XTAL Printed Circuit Board (PCB) layout guidelines

The crystal should be connected on the PCB as close as possible to the oscillator input

and output pins of the chip. Take care that the load cap acitors Cx1, Cx2, and Cx3 in ca se o f

third overtone crystal usage have a common ground plane. The external components

must also be connected to the ground plain. Loops must be made as small as possible in

Fig 30. Oscillator mod es and models: oscillation mode of operation and external crystal

model used for CX1/CX2 evaluation

Table 18. Recommended values for CX1/CX2 in oscillation mode (crystal and external

components parameters) low frequency mode

Fundamental oscillation

frequency FOSC

Crystal load

capacitance CL

Maximum crystal

series resistance RS

External load

capacitors CX1, CX2

1 MHz - 5 MH z 10 pF < 300 Ω18 pF, 18 pF

20 pF < 300 Ω39 pF, 39 pF

30 pF < 300 Ω57 pF, 57 pF

5 MHz - 10 MHz 10 pF < 300 Ω18 pF, 18 pF

20 pF < 200 Ω39 pF, 39 pF

30 pF < 100 Ω57 pF, 57 pF

10 MHz - 15 MHz 10 pF < 160 Ω18 pF, 18 pF

20 pF < 60 Ω39 pF, 39 pF

15 MHz - 20 MHz 10 pF < 80 Ω18 pF, 18 pF

Table 19. Recommended values for CX1/CX2 in oscillation mode (crystal and external

components parameters) high frequency mode

Fundamental oscillation

frequency FOSC

Crystal load

capacitance CL

Maximum crystal

series resistance RS

External load

capacitors CX1, CX2

15 MHz - 20 MHz 10 pF < 180 Ω18 pF, 18 pF

20 pF < 100 Ω39 pF, 39 pF

20 MHz - 25 MHz 10 pF < 160 Ω18 pF, 18 pF

20 pF < 80 Ω39 pF, 39 pF

002aaf42

LPC1xxx

XTALIN XTALOUT

CX2

CX1

XTAL

CLCP

Product data sheet Rev. 3 — 10 November 2010 56 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

order to keep the noise coup le d in via the PCB as sm all as po ss ible . A lso parasitics

should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller

accordingly to the increase in parasitics of the PCB layout.

11.4 Standard I/O pad configuration

Figure 31 shows the possible pin modes for standard I/O pins with analog input function:

•Digital output driver

•Digital input: Pull-up enabled/disabled

•Digital input: Pull-down enabled/disabled

•Digital input: Repeater mode enab led/disabled

•Analog input

Fig 31. Standard I/O pad configur ation

VDD

ESD

VSS

ESD

VDD

weak

pull-up

weak

pull-down

output enable

repeater mode

enable

output

pull-up enable

pull-down enable

data input

analog input

select analog input

002aaf30

pin configured

as digital output

driver

pin configured

as digital input

pin configured

as analog input

Product data sheet Rev. 3 — 10 November 2010 57 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

11.5 Reset pad configuration

Fig 32. Reset pad configuration

VSS

reset

002aaf27

VDD

Rpu ESD

ESD

20 ns RC

GLITCH FILTER PIN

Product data sheet Rev. 3 — 10 November 2010 58 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

12. Package outline

Fig 33. Package outline SOT313-2 (LQFP48)

UNIT A

max. A1A2A3bpcE

(1) eH

ELL

pZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 1.6 0.20

0.05

1.45

1.35 0.25 0.27

0.17

0.18

0.12

7.1

6.9 0.5 9.15

8.85

0.95

0.55

0.12 0.10.21

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT313-2 MS-026136E05 00-01-19

03-02-25

D(1) (1)(1)

7.1

6.9

9.15

8.85

0.95

0.55

vMB

vMA

36 25

detail X

(A )

0 2.5 5 mm

scale

pin 1 index

QFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313

-2

Product data sheet Rev. 3 — 10 November 2010 59 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

Fig 34. Package outline PLCC44

UNIT A A1

min.

max. bpeywv β

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 4.57

4.19 0.51 3.05 0.53

0.33

0.021

0.013

16.66

16.51 1.27 17.65

17.40 2.16

45o

0.18 0.10.18

DIMENSIONS (mm dimensions are derived from the original inch dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

SOT187-2

D(1) E(1)

16.66

16.51

HDHE

17.65

17.40

ZD(1)

max. ZE(1)

max.

2.16

0.81

0.66

1.22

1.07

0.180

0.165 0.02 0.12

0.25

0.01 0.656

0.650 0.05 0.695

0.685 0.085

0.007 0.0040.007

1.44

1.02

0.057

0.040

0.656

0.650

0.695

0.685

eDeE

16.00

14.99

0.63

0.59

16.00

14.99

0.63

0.59 0.085

0.032

0.026

0.048

0.042

2939

717

detail X

(A )

vMB

vMA

pin 1 index

112E10 MS-018 EDR-7319

0 5 10 mm

scale

99-12-27

01-11-14

inches

PLCC44: plastic leaded chip carrier; 44 leads SOT187-

Product data sheet Rev. 3 — 10 November 2010 60 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

Fig 35. Package outline (HVQFN33)

References

Outline

version

European

projection Issue date

IEC JEDEC JEITA

- - -

hvqfn33_po

09-03-17

09-03-23

Unit

max

nom

min

1.00

0.85

0.80

0.05

0.02

0.00

0.2

7.1

7.0

6.9

4.85

4.70

4.55

7.1

7.0

6.9

0.65 4.55

0.75

0.60

0.45

0.1

A(1)

Dimensions

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

VQFN33: plastic thermal enhanced very thin quad flat package; no leads;

3 terminals; body 7 x 7 x 0.85 mm

A1b

0.35

0.28

0.23

(1) DhE(1) Eh

4.85

4.70

4.55

1e2

4.55

0.1

0.05

0.08

0 2.5 5 mm

scale

terminal 1

index area

detail X

AC B

terminal 1

index area Dh

9 16

Product data sheet Rev. 3 — 10 November 2010 61 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

13. Abbreviations

Ta ble 20. Abbre viations

Acronym Description

ADC Analog-to-Digital Converter

AHB Advanced High-performance Bus

APB Advanced Peripheral Bus

BOD BrownOut Detection

GPIO General Purpose Input/Output

PLL Phase-Locked Loop

RC Resistor-Capacitor

SPI Serial Peripheral Interface

SSI Serial Synchronous Interface

SSP Synchronous Serial Port

UART Universal Asynchronous Receiver/Transmitter

Product data sheet Rev. 3 — 10 November 2010 62 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

14. Revision history

Table 21. Revision history

Document ID Release date Data sheet status Change notice Supersedes

LPC1111_12_13_14 v.3 20101110 Product data sheet - LPC1111_12_13_14 v.2

Modifications: •Parts LPC111x/102/202/302 added (LPC1100L series).

•Power consumption data for parts LPC111x/102/202/302 added in Table 7.

•PLL output frequency limited to 100 MHz in Section 7.15.2.

•Description of RESET and WAKEUP functions updated in Section 6.

•WDT description updated in Section 7.14. The WDT is a 24-bit timer.

•Power profiles added to Section 2 and Section 7 for parts LPC111x/102/202/302.

LPC1111_12_13_14 v.2 20100818 Product data sheet - LPC1111_12_13_14 v.1

Modifications: •VESD limit changed to −6500 V (min) /+6500 V (max) in Table 6.

•tDS updated for SPI in master mode (Table 17).

•Deep-sleep mode functionality changed to allow BOD and watchdog oscillator as the

only analog blocks allowed to rema in running in Deep-sleep mode (Section 7.15.5.3).

•VDD range changed to 3.0 V ≤ VDD ≤ 3.6 V in Table 15.

•Reset state of pins and start logic functionality added in Table 3 to Table 5.

•Section 7.16.1 added.

•Section “Memory mapping control” removed.

•VOH and IOH specifications updated for high-drive pins in Table 7.

•Section 9.4 added.

LPC1111_12_13_14 v.1 20100416 Product data sheet - -

Product data sheet Rev. 3 — 10 November 2010 63 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

15.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict wit h the short data sheet, the

full data sheet shall pre va il.

Product specificat ion — The information and data provided in a Product

data sheet shall define the specification of the product as agr eed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

15.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warrant ies, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggreg ate and cumulative l iability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suit able for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applicati ons or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Custo mers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party custo m er(s). Customer is responsible for doing all necessary

testing for the customer’s applications and pro ducts using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter m s and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or inte llectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from national authorities.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contain s the product specification.

Product data sheet Rev. 3 — 10 November 2010 64 of 65

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for aut omo tive use. It i s neither qua lified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standards, custome r

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such au tomotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y

liability, damages or failed product claims resulting f rom customer design an d

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

15.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

I2C-bus — logo is a trademark of NXP B.V.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 10 Nove mber 2010

Document identifier: LPC1111_12_ 13_14

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3

4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 4

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 6

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9

7 Functional description . . . . . . . . . . . . . . . . . . 20

7.1 ARM Cortex-M0 processor. . . . . . . . . . . . . . . 20

7.2 On-chip flash program memory . . . . . . . . . . . 20

7.3 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 20

7.4 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.5 Nested Vectored Interrupt Controller (NVIC) . 21

7.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.5.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 22

7.6 IOCONFIG block . . . . . . . . . . . . . . . . . . . . . . 22

7.7 Fast general purpose parallel I/O . . . . . . . . . . 22

7.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.8 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.9 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 23

7.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.10 I2C-bus serial I/O controller . . . . . . . . . . . . . . 23

7.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.11 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.12 Gene ral purpose external event

counter/timers. . . . . . . . . . . . . . . . . . . . . . . . . 24

7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.13 System tick timer . . . . . . . . . . . . . . . . . . . . . . 25

7.14 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 25

7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.15 Clocking and power control . . . . . . . . . . . . . . 26

7.15.1 Crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 26

7.15.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 26

7.15.1.2 System oscillator . . . . . . . . . . . . . . . . . . . . . . 27

7.15.1.3 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 27

7.15.2 System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.15.3 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.15.4 Wake-up process . . . . . . . . . . . . . . . . . . . . . . 27

7.15.5 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.15.5.1 Power profiles (LPC1100L series,

LPC111x/102/202/302 only) . . . . . . . . . . . . . . 28

7.15.5.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.15.5.3 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 28

7.15.5.4 Deep power-down mode . . . . . . . . . . . . . . . . 28

7.16 System control. . . . . . . . . . . . . . . . . . . . . . . . 29

7.16.1 Start logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.16.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.16.3 Brownout detection . . . . . . . . . . . . . . . . . . . . 29

7.16.4 Code security (Code Read Protection - CRP) 29

7.16.5 APB interface. . . . . . . . . . . . . . . . . . . . . . . . . 30

7.16.6 AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.16.7 External interrupt inputs. . . . . . . . . . . . . . . . . 30

7.17 Emulation and debugging . . . . . . . . . . . . . . . 30

8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 31

9 Static characteristics . . . . . . . . . . . . . . . . . . . 32

9.1 BOD static characteristics . . . . . . . . . . . . . . . 37

9.2 Power consumption LPC111x/101/201/301. . 37

9.3 Power consumption LPC111x/102/202/302. . 40

9.4 Peripheral power consumption . . . . . . . . . . . 44

9.5 Electrical pin characteristics. . . . . . . . . . . . . . 45

10 Dynamic characteristics. . . . . . . . . . . . . . . . . 48

10.1 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 48

10.2 External clock. . . . . . . . . . . . . . . . . . . . . . . . . 48

10.3 Internal oscillato rs . . . . . . . . . . . . . . . . . . . . . 49

10.4 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.5 I2C-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.6 SPI interfaces. . . . . . . . . . . . . . . . . . . . . . . . . 51

11 Application information . . . . . . . . . . . . . . . . . 54

11.1 ADC usage notes. . . . . . . . . . . . . . . . . . . . . . 54

11.2 XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

11 .3 XTAL Printed Circuit Board (PCB) layout

guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

11.4 Standard I/O pad configuration . . . . . . . . . . . 56

11.5 Reset pad configuration. . . . . . . . . . . . . . . . . 57

12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 58

13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 61

14 Revision history . . . . . . . . . . . . . . . . . . . . . . . 62

15 Legal information . . . . . . . . . . . . . . . . . . . . . . 63

15.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 63

15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 63

15.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 64

16 Contact information . . . . . . . . . . . . . . . . . . . . 64

17 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65