● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
VN2222NC
S
S
S
G4
G3
G2
G1
S
S
S
S
S
NC
D4
D3
D2
D1
NC
S
S
Features
Free from secondary breakdown
Low power drive requirement
Ease of paralleling
Low CISS and fast switching speeds
Excellent thermal stability
Integral source-drain diode
High input impedance and high gain
4 N-channel MOSFETs
Applications
Motor controls
Converters
Amplifiers
Switches
Power supply circuits
Drivers (relays, hammers, solenoids, lamps,
memories, displays, bipolar transistors, etc.)
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General Description
The Supertex VN2222NC is an enhancement-mode (normally-
off) transistor array consisting of four N-channel MOSFETs in a
20-Lead ceramic side-brazed DIP package. These transistors
utilize a vertical DMOS structure and Supertex’s well-
proven silicon-gate manufacturing process. This combination
produces a device with the power handling capabilities of
bipolar transistors, and the high input impedance and positive
temperature coefficient inherent in MOS devices. Characteristic
of all MOS structures, this device is free from thermal runaway
and thermally-induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide
range of switching and amplifying applications where very
low threshold voltage, high breakdown voltage, high input
impedance, low input capacitance, and fast switching speeds
are desired.
Ordering Information
Device
Package Option
BVDSS/BVDGS
(V)
RDS(ON)
(max)
(Ω)
ID(ON)
(min)
(A)
20-Lead Ceramic Side-Braze DIP
.980x.280in. body
.200in. height (max)
.100in. pitch
VN2222NC VN2222NC 220 1.25 5.0
Absolute Maximum Ratings
Parameter Value
Drain-to-source voltage BVDSS
Drain-to-gate voltage BVDGS
Gate-to-source voltage ±20V
Operating and storage temperature -55°C to +150°C
Soldering temperature* +300°C
Absolute Maximum Ratings are those values beyond which damage to
the device may occur. Functional operation under these conditions is not
implied. Continuous operation of the device at the absolute rating level
may affect device reliability. All voltages are referenced to device ground.
* Distance of 1.6mm from case for 10 seconds.
Pin Configuration
N-Channel Enhancement-Mode
Vertical DMOS FETs
Product Marking
20-Lead Ceramic Side-Braze DIP (NC)
(top view)
20-Lead Ceramic Side-Braze DIP (NC)
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
Top Marking
Bottom Marking
YYWW
VN2222NC
LLLLLLL
CCCCCCCCCCC
AAA
Package may or may not include the following marks: Si or