VN2222NC - Supertex, Inc. - Datasheet.Live

● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com

VN2222NC

S

G4

G3

G2

G1

S

NC

D4

D3

D2

D1

NC

S

Features

Free from secondary breakdown

Low power drive requirement

Ease of paralleling

Low CISS and fast switching speeds

Excellent thermal stability

Integral source-drain diode

High input impedance and high gain

4 N-channel MOSFETs

Applications

Motor controls

Converters

Ampliﬁers

Switches

Power supply circuits

Drivers (relays, hammers, solenoids, lamps,

memories, displays, bipolar transistors, etc.)

►

General Description

The Supertex VN2222NC is an enhancement-mode (normally-

off) transistor array consisting of four N-channel MOSFETs in a

20-Lead ceramic side-brazed DIP package. These transistors

utilize a vertical DMOS structure and Supertex’s well-

proven silicon-gate manufacturing process. This combination

produces a device with the power handling capabilities of

bipolar transistors, and the high input impedance and positive

temperature coefﬁcient inherent in MOS devices. Characteristic

of all MOS structures, this device is free from thermal runaway

and thermally-induced secondary breakdown.

Supertex’s vertical DMOS FETs are ideally suited to a wide

range of switching and amplifying applications where very

low threshold voltage, high breakdown voltage, high input

impedance, low input capacitance, and fast switching speeds

are desired.

Ordering Information

Device

Package Option

BVDSS/BVDGS

(V)

RDS(ON)

(max)

(Ω)

ID(ON)

(min)

(A)

20-Lead Ceramic Side-Braze DIP

.980x.280in. body

.200in. height (max)

.100in. pitch

VN2222NC VN2222NC 220 1.25 5.0

Absolute Maximum Ratings

Parameter Value

Drain-to-source voltage BVDSS

Drain-to-gate voltage BVDGS

Gate-to-source voltage ±20V

Operating and storage temperature -55°C to +150°C

Soldering temperature* +300°C

Absolute Maximum Ratings are those values beyond which damage to

the device may occur. Functional operation under these conditions is not

implied. Continuous operation of the device at the absolute rating level

may affect device reliability. All voltages are referenced to device ground.

* Distance of 1.6mm from case for 10 seconds.

Pin Conﬁguration

N-Channel Enhancement-Mode

Vertical DMOS FETs

Product Marking

20-Lead Ceramic Side-Braze DIP (NC)

(top view)

20-Lead Ceramic Side-Braze DIP (NC)

YY = Year Sealed

WW = Week Sealed

L = Lot Number

C = Country of Origin*

A = Assembler ID*

= “Green” Packaging

*May be part of top marking

Top Marking

Bottom Marking

YYWW

VN2222NC

LLLLLLL

CCCCCCCCCCC

AAA

Package may or may not include the following marks: Si or

2

VN2222NC

● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com

Electrical Characteristics (TA = 25°C unless otherwise speciﬁed)

Sym Parameter Min Typ Max Units Conditions

BVDSS Drain-to-source breakdown voltage 220 - - V VGS = 0V, ID = 5.0mA

VGS(th) Gate threshold voltage 1.0 - 3.0 V VGS = VDS, ID = 5.0mA

∆VGS(th) Change in VGS(th) with temperature -4.0 -5.0 mV/°C VGS = VDS, ID = 5.0mA

IGSS Gate body leakage current - 1.0 100 nA VGS = ±20V, VDS = 0V

IDSS Zero gate voltage drain current

- - 50 µA VGS = 0V, VDS = Max Rating

- - 5.0 mA VDS = 0.8 Max Rating,

VGS = 0V, TA = 125OC

ID(ON) On-state drain current 2.0 - - AVGS = 5.0V, VDS = 25V

5.0 10 - VGS = 10V, VDS = 25V

RDS(ON)

Static drain-to-source on-state

resistance

- 1.0 1.5 ΩVGS = 5.0V, ID = 2.0A

- 0.9 1.25 VGS = 10V, ID = 2.0A

∆RDS(ON) Change in RDS(ON) with temperature - 1.0 1.4 %/°C VGS = 10V, ID = 2.0A

GFS Forward transconductance 1000 2200 - mmho VDS = 25V, ID = 2.0A

CISS Input capacitance - 300 350

pF

VGS = 0V,

VDS = 25V,

f = 1.0MHz

COSS Common source output capacitance - 85 150

CRSS Reverse transfer capacitance - 20 35

td(ON) Turn-on delay time - 6.0 15

ns

VDD = 25V,

ID = 2.0A,

RGEN = 10Ω

trRise time 16 25

td(OFF) Turn-off delay time - 65 90

tfFall time - 30 60

VSD Reverse recovery time - 0.8 1.0 ns VGS = 0V, ISD = 100mA

trr Diode forward voltage drop - 500 - V VGS = 0V, ISD = 1.0A

Notes:

All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)

All A.C. parameters sample tested.

1.

2.

Switching Waveforms and Test Circuit

90%

10%

90% 90%

10%

PULSE

GENERATOR

V

DD

RL

OUTPUT

D.U.T.

t(ON)

td(ON)

t(OFF)

td(OFF)

tr

INPUT

OUTPUT

10V

VDD

R

GEN

0V

tf

Thermal Characteristics

Package

ID

(continuous)†

(A)

ID

(pulsed)

(A)

Power Dissipation

@TA = 25OC

(W)

θjc

(OC/W)

θja

(OC/W)

IDR

†

(A)

IDRM

(A)

Ceramic DIP 0.75 (1 FET) 6.0 1.39 41 90 0.75 6.0

0.37 (4 FETs) 2.0 0.37 2.0

Notes:

† ID (continuous) is limited by max rated Tj .

3

VN2222NC

● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com

Typical Performance Curves

Output Characteristics

10

8

6

4

2

0

VDS (volts)

ID)s

e

r

epm

a(

ID)

s

erep

m

a(

Saturation Characteristics

10

8

6

4

2

0

VDS (volts)

0 10 20 30 5040

4V

3V

0 2 4 6 108

V

GS

= 10V

6V

4V

3V

V

GS

= 10V

6V

8V

On-Resistance vs. Drain Current

R)NO(SD )sm

ho(

VB SSD )d

e

zilam

r

on(

T

j

(

O

C) I

D

(amperes)

BV

DSS

Variation with Temperature

-50 0 50 100 150

1.1

1.0

5

2

VGS = 5V

VGS = 10V

0 2 4 6 108

0

3

4

0.9

1

4

VN2222NC

● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com

Typical Performance Curves

Gate Drive Dynamic Characteristics

Q

G

(nanocoulombs)

V

S

G

)

s

t

l

ov(

T

j

(

O

C)

V

)ht

(S

G

)d

e

zil

amr

on

(

R

)N

O

(S

D

)dezilamron(

V

(th)

and R

DS

Variation with Temperature

Capacitance vs. Drain-to-Source Voltage

400

)

s

d

ar

afo

c

ip(

C

V

DS

(volts)

0 10 20 30 40

300

200

0

1.4

1.0

0.4

10

8

6

4

2

0 2 468 10-50 0 50 100 150

300 pF

V

DS

= 40V

V

DS

= 10V

f = 1MHz

C

ISS

COSS

C

RSS

733 pF

0.6

0.8

1.2

2.4

2.0

1.6

1.2

0.8

0.4

Vth @ 5mA

100

0

RDS @ 10V, 2A

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives

an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability

to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and

specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888

www.supertex.com

5

VN2222NC

(The package drawing(s) in this data sheet may not reﬂect the most current speciﬁcations. For the latest package outline

information go to http://www.supertex.com/packaging.html.)

Doc.# DSFP-VN2222NC

B111209

Symbol A A1 b b1 D E E1 eA eB e L

Dimension

(inches)

MIN .085 .025 .015 .045 .980 .300 .280

.300

REF

.300†

.100

BSC

.125

NOM - - - - - - - - -

MAX .200 .070 .022 .065 1.020 .325 .310 .400 .200

JEDEC Registration MS-015, Variation AE, Issue A, July, 1990.

† This dimension differs from the JEDEC drawing.

Drawings not to scale.

Supertex Doc.#: DSPD-20CDIPCNC, Version D041309.

Note:

A Pin 1 identiﬁer must be located in the index area indicated. The Pin 1 identiﬁer can be: a molded mark/identiﬁer; an embedded metal marker; or

a printed indicator.

1.

Note 1

(Index Area)

20

1

D

LA1

ASeating

Plane

e

E1 E

A

Side View

Top View

View A - A

eA

eB

View B

b

b1

20-Lead Ceramic Side-Brazed Package Outline (NC)

.980x.280in. body, .200in. height (max), .100in. pitch