Preliminary 512Kx72 Pipelined NtRAMTM K7N327249M 512Kx72-Bit Pipelined NtRAM TM FEATURES GENERAL DESCRIPTION * 2.5V 5% Power Supply. * Byte Writable Function. * Enable clock and suspend operation. * Single READ/WRITE control pin. * Self-Timed Write Cycle. * Three Chip Enable for simple depth expansion with no data contention . * A interleaved burst or a linear burst mode. * Asynchronous output enable control. * Power Down mode. * TTL-Level Three-State Outputs. * 209BGA(11x19 Ball Grid Array Package). FAST ACCESS TIMES PARAMETER Symbol -25 -22 -20 Unit tCYC 4.0 4.4 5.0 ns Clock Access Time tCD 2.6 2.8 3.2 ns Output Enable Access Time tOE 2.6 2.8 3.2 ns Cycle Time The K7N327249M is 37,748,736-bits Synchronous Static SRAMs. The NtRAM TM , or No Turnaround Random Access Memory utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied "High or Low". Asynchronous inputs include the sleep mode enable(ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. For read cycles, pipelined SRAM output data is temporarily stored by an edge triggered output register and then released to the output buffers at the next rising edge of clock. The K7N327249M are implemented with SAMSUNGs high performance CMOS technology and is available in 209BGA packages. Multiple power and ground pins minimize ground bounce. LOGIC BLOCK DIAGRAM LBO A [0:18] CKE CON TROL LOGIC CLK ADDRESS REGISTER A 2~A 18 ADV WE BW x (x=a ~ h) WRITE ADDRESS REGISTER K CONTROL R EG ISTE R CS 1 CS 2 CS 2 BURST ADDRESS COUNTER A 0~A1 A 0~A 1 512K x 72 MEMORY ARRAY WRITE ADDRESS REGISTER CONTROL LOGIC K DATA-IN REGISTER K DATA-IN REGISTER K OUTPUT REGISTER BUFFER OE ZZ 72 DQa 0 ~ DQh7 DQPa ~ DQPh NtRAMT M and No Turnaround Random Access Memory are trademarks of Samsung. -1- May 2001 Rev 0.0 Preliminary 512Kx72 Pipelined NtRAMTM K7N327249M 209BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW) K7N327249M(512K x 72) 1 2 3 4 5 6 7 8 9 10 11 A DQg DQg A CS2 A ADV A CS 2 A DQb DQb B DQg DQg BWc BWg NC WE A BWb BW f DQb DQb C DQg DQg BWh BWd NC CS 1 NC BWe BWa DQb DQb D DQg DQg VSS NC NC OE NC NC V SS DQb DQb E DQPg DQPc VDDQ V DDQ V DD VDD V DD VDDQ V DDQ DQPf DQPb F DQc DQc VSS V SS VSS NC VSS VSS V SS DQf DQf G DQc DQc VDDQ V DDQ V DD NC V DD VDDQ V DDQ DQf DQf H DQc DQc VSS V SS VSS NC VSS VSS V SS DQf DQf J DQc DQc VDDQ V DDQ V DD NC V DD VDDQ V DDQ DQf DQf K NC NC CLK NC VSS CKE VSS NC NC NC NC L DQh DQh VDDQ V DDQ V DD NC V DD VDDQ V DDQ DQa DQa M DQh DQh VSS V SS VSS NC VSS VSS V SS DQa DQa N DQh DQh VDDQ V DDQ V DD NC V DD VDDQ V DDQ DQa DQa P DQh DQh VSS V SS VSS ZZ VSS VSS V SS DQa DQa R DQPd DQPh VDDQ V DDQ V DD VDD V DD VDDQ V DDQ DQPa DQPe T DQd DQd VSS NC NC LBO NC NC V SS DQe DQe U DQd DQd NC A NC(64M) A A A NC DQe DQe V DQd DQd A A A A 1** A A A DQe DQe W DQd DQd TMS TDI A A 0** A TDO TCK DQe DQe Notes : 1. ** A0 and A 1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. PIN NAME SYMBOL PIN NAME A Address Inputs A0,A1 ADV WE CLK CKE CS1 CS2 CS2 Burst Address Inputs Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs BWx (x=a~h) OE ZZ LBO Output Enable Power Sleep Mode Burst Mode Control TCK TMS TDI TDO JTAG Test Clock JTAG Test Mode Select JTAG Test Data Input JTAG Test Data Output SYMBOL PIN NAME V DD V SS Power Supply Ground N.C. No Connect DQa DQb DQc DQd DQe DQf DQg DQh DQPa~Ph Data Data Data Data Data Data Data Data Data V DDQ Output Power Supply -2- Inputs/Outputs Inputs/Outputs Inputs/Outputs Inputs/Outputs Inputs/Outputs Inputs/Outputs Inputs/Outputs Inputs/Outputs Inputs/Outputs May 2001 Rev 0.0