512Kx72 Pipelined NtRAMTM
- 1 - Rev 0.0
May 2001
K7N327249M Preliminary
512Kx72-Bit Pipelined NtRAMTM
The K7N327249M is 37,748,736-bits Synchronous Static SRAMs.
The NtRAMTM, or No Turnaround Random Access Memory uti-
lizes all the bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output enable
and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-chip
write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily stored
by an edge triggered output register and then released to the out-
put buffers at the next rising edge of clock.
The K7N327249M are implemented with SAMSUNG′s high per-
formance CMOS technology and is available in 209BGA pack-
ages. Multiple power and ground pins minimize ground bounce.
GENERAL DESCRIPTIONFEATURES
• 2.5V ±5% Power Supply.
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no data
contention .
• A interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• TTL-Level Three-State Outputs.
• 209BGA(11x19 Ball Grid Array Package).
NtRAMTM and No Turnaround Random Access Memory are trademarks of Samsung.
LOGIC BLOCK DIAGRAM
WE
BWx
CLK
CKE
CS1
CS2
CS2
ADV
OE
ZZ
DQa0 ~ DQh7
ADDRESS
ADDRESS
REGISTER
CONTROL
LOGIC
A′0~A′1
72
DQPa ~ DQPh
OUTPUT
BUFFER
REGISTER
DATA-IN
REGISTER
DATA-IN
REGISTER
K
K
K
REGISTER
BURST
ADDRESS
COUNTER
WRITE
ADDRESS
REGISTER
WRITE
CONTROL
LOGIC
CONTROL
REGISTER
K
A [0:18]
LBO
A2~A18
A0~A1
(x=a ~ h)
512K x 72
MEMORY
ARRAY
FAST ACCESS TIMES
PARAMETER Symbol -25 -22 -20 Unit
Cycle Time tCYC 4.0 4.4 5.0 ns
Clock Access Time tCD 2.6 2.8 3.2 ns
Output Enable Access Time tOE 2.6 2.8 3.2 ns
512Kx72 Pipelined NtRAMTM
- 2 - Rev 0.0
May 2001
K7N327249M Preliminary
209BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW)
K7N327249M(512K x 72)
Notes : 1. ** A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
1 2 3 4 5 6 7 8 9 10 11
ADQg DQg ACS2AADV ACS2ADQb DQb
BDQg DQg BWcBWgNC WE ABWbBWfDQb DQb
CDQg DQg BWhBWdNC CS1NC BWeBWaDQb DQb
DDQg DQg VSS NC NC OE NC NC VSS DQb DQb
EDQPg DQPc VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPf DQPb
FDQc DQc VSS VSS VSS NC VSS VSS VSS DQf DQf
GDQc DQc VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQf DQf
HDQc DQc VSS VSS VSS NC VSS VSS VSS DQf DQf
JDQc DQc VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQf DQf
KNC NC CLK NC VSS CKE VSS NC NC NC NC
LDQh DQh VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQa DQa
MDQh DQh VSS VSS VSS NC VSS VSS VSS DQa DQa
NDQh DQh VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQa DQa
PDQh DQh VSS VSS VSS ZZ VSS VSS VSS DQa DQa
RDQPd DQPh VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPa DQPe
TDQd DQd VSS NC NC LBO NC NC VSS DQe DQe
UDQd DQd NC ANC(64M) A A A NC DQe DQe
VDQd DQd A A A A1** A A A DQe DQe
WDQd DQd TMS TDI A A0** ATDO TCK DQe DQe
PIN NAME
SYMBOL PIN NAME SYMBOL PIN NAME
A
A0,A1
ADV
WE
CLK
CKE
CS1
CS2
CS2
BWx
(x=a~h)
OE
ZZ
LBO
TCK
TMS
TDI
TDO
Address Inputs
Burst Address Inputs
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
VDD
VSS
N.C.
DQa
DQb
DQc
DQd
DQe
DQf
DQg
DQh
DQPa~Ph
VDDQ
Power Supply
Ground
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Output Power Supply
