128K X 36 Dual I/O Dual Address Synchronous SRAM
CY7C1300A
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05075 Rev. *C Revised January 19, 2003
Features
•Fast clock speed: 100 and 83 MHz
•Fast access times: 5.0/6.0 ns max.
•Single clock operation
•Single 3.3V –5% and +5% power supply VCC
•Separate VCCQ for output buffer
•Two chip enables for simple depth expansion
•Address, data input, CE1X, CE2X, CE1Y, CE2Y, PTX,
PTY, WEX, WEY, and data output registers on-chip
•Concurrent Reads and Wr ite s
•Two bidirectional data buses
•Can be configured as separate I/O
•Pass-through feature
•Asynchronous output enables (OEX, OEY)
•LVTTL-compatible I/O
•Self-timed Write
•Automatic power-down
•176-pin TQFP packa ge
Functional Description
The CY7C1300A SRAM integrates 131,072 × 36 SRAM cells
with advanced synchronous peripheral circuitry. It employs
high-speed, low-power CMOS designs using advanced
triple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high-valued
resistors.
The CY7C1300A allows the user to concurrently perform
Reads, Writes, or pass-through cycles in combination on the
two data ports. The two ad dress po rts (AX, AY) determine the
Read or Write locations for their respec tive data ports (D QX,
DQY).
All i nput pins exce pt output ena ble pins (OEX, OEY) are gated
by registers controlled by a positive-edge-triggered clock
(CLK) input. The synchronous inputs include all addresses,
data inputs, depth-expansion chip enables (CE1X, CE2X,
CE1Y and CE2 Y), pass-t hrough c ontrols (PTX and P TY), and
Read–Wr ite co ntrol (WEX and WEY).
The pass-through feature allows data to be passed from one
port to another, in either direction. The PTX input must be
asserted to pass data from port X to port Y. The PTY will
likewise pass data from port Y to port X. A pass-through
operation takes precedence over a Read operation.
When AX and A Y are the same, certain protocols are followed.
If bot h po rts a re R ea d, th e re ads oc cu r norm al ly. If one port is
writte n and the o ther is rea d, the read f rom the arra y will occ ur
before the data is written. If both ports are written, only the data
on DQY will be written to the array.
The CY7C1300A operates from a +3.3V power supply. All
inputs and outputs are LVTTL-compatible. These dual I/O,
dual address synchronous SRAMs are well suited for ATM,
Ethernet switches, routers, cell/frame buffe rs, SNA switches,
and shared memory applications.
The CY7C1 300A needs one ex tra cycle after pow er for proper
power-on reset. The extra cycle is needed after VCC is stable
on the device.
This device is available in a 176-pin TQFP package.
YY
Logic Block Diagram[1]
Note:
1. For 128K x 36 devices, AX and AY are 17-bit-wide buses.
CY7C1300A
Document #: 38-05075 Rev. *C Page 2 of 12
Selection Gu ide
Pin Configuration
-100 -83 Unit
Maximum access time 5.0 6.0 ns
Maximum operating current 500 430 mA
Maximum CMOS standby current 100 100 mA
Shaded areas con tain adva nce info rm atio n.
132
VSS
45
VSS
46474849505152535455565758596061626364656667686970717273747576777879808182838485868788
44
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167
168
169
170
171
172
173
174
175
176
VSS
VCCQ
DQY35
DQX35
VSS
VSS
AY5
AX5
VSS
VCC
AX14
AY14
VCCQ
VSS
DQX1
DQY1
VSS
DQX0
DQY0
AX13
AY13
AX12
AY12
AX11
AY11
AX10
AY10
AY4
AX4
AY3
AX3
AY2
AX2
AY1
AX1
AY0
AX0
DQY34
DQX34
DQX20
DQY20
VSS
VCCQ
DQX21
DQY21
DQX22
DQY22
VSS
VCCQ
DQX23
DQY23
DQX24
DQY24
VSS
VCCQ
DQX25
DQY25
DQX26
DQY26
VSS
VCC
DQY27
DQX27
DQY28
DQX28
VSS
VCCQ
DQY29
DQX29
DQY30
DQX30
VSS
VCCQ
DQY31
DQX31
DQY32
DQX32
VSS
VCCQ
DQY33
DQX33
VSS
VSS
DQX15
DQY15
VCCQ
VSS
DQX14
DQY14
DQX13
DQY13
VCCQ
VSS
DQX12
DQY12
DQX11
DQY11
VCCQ
VSS
DQX10
DQY10
DQX9
DQY9
VCC
VSS
DQY8
DQX8
DQY7
DQX7
VCCQ
VSS
DQY6
DQX6
DQY5
DQX5
VCCQ
VSS
DQY4
DQX4
DQY3
DQX3
VCCQ
VSS
DQY2
DQX2
VSS
VSS
VSS
VCCQ
DQY18
DQX18
AX6
AY6
AX7
AY7
VCC
VSS
AX8
AY8
AX9
VCC
VSS
DQX16
DQY16
VSS
DQX17
DQY17
AY9
AX17*
AY17*
PTY#
PTX#
WEY#
WEX#
CE2X
CE1X#
OEY#
OEX#
VSS
NC
NC
NC
VSS
NC
NC
CLK
DQY19
DQX19
AX16
AY16
AX15
AY15
CE2Y
CE1Y#
176 -pin TQFP
CY7C1300A
Document #: 38-05075 Rev. *C Page 3 of 12
Pin Definitions
Name I/O Description
AX0–
AX16 Input–
Synchronous Synchronous Address Inputs of Port X: Do not allow address pins to float.
AY0–
AY16 Input–
Synchronous Synchronous Address Inputs of Port Y: Do not allow address pins to float.
WEX Input–
Synchronous Read Write of Port X: WEX signal is a synchronous input that identifies whether the current loaded
cycle is a Read or Write operation.
WEY Input–
Synchronous Read Write of Port Y: WEY signal is a synchronous input that identifies whether the current loaded cycle
is a Read or Write operation.
PTX Input–
Synchronous Pass-Through of Port X: PT X signal is a synchronous input that enables passing Port X input to Port
Y output.
PTY Input–
Synchronous Pass-Through of Port Y: PTY signal is a synchronous input that enables passing Port Y input to Port
X output.
OEX Input Asynchronous Output Enable of Port X: OEX must be LOW to read data. When OEX is HIGH, the
DQXx pins are in high-impedance state.
OEY Input Asynchronous Output Enable of Port Y: OEY must be LOW to read data. When OEY is HIGH, the
DQYx pins are in high-impedance state.
DQX0–
DQX35 Input/
Output Data Inputs/Outputs of Port X: Both the data input path and data output path are registered and
triggered by the rising edge of CLK.
DQY0–
DQY35 Input/
Output Data Inputs/Outputs of Port Y: Both the data input path and data output path are registered and
triggered by the rising edge of CLK.
CLK Input–
Synchronous Clock: This is the clock input to this device. Except for OEX and OEY , all timing references of the address,
data in, and all control signals for the de vice are made with respect to the rising edge of CLK.
CE1X Input–
Synchronous Synchronous Active LOW Chip Enable Port X: CE1X is used with CE2X to enable Port X of this
device. CE1X sampled HIGH at the rising edge of clock initiates a deselect cycle for Port X.
CE2X Input–
Synchronous Synchronous Active HIGH Chip Enable Port X: CE2X is used with CE1X to enable Port X of this
device. CE2X sampled LOW at the rising edge of clock initiates a deselect cycle for Port X.
CE1Y Input–
Synchronous Synchronous Active LOW Chip Enable Port Y: CE1Y is used with CE2Y to enable Port Y of this device.
CE1Y sampled HIGH at the rising edge of clock initiates a deselect cycle for Port Y.
CE2Y Input–
Synchronous Synchronous Active HIGH Chip Enable Port Y: CE2Y is used with CE1Y to enable Port Y of this
device. CE2Y sampled LOW at the rising edge of clock initiates a deselect cycle for Port Y.
VCC Supply Power Supply: +3.3V –5% and +5%.
VSS Ground Ground: GND.
VSS Ground Ground: GN D. No chip current flows through these pins. However, the user needs to connect GND to
these pins.
VCCQ I/O Supply Output Buffe r Supply: +3.3V -5% and +5%.
NC –No Connect: These signals are not internally connected. The user can connect them to VCC, VSS, or
any signal lines, or simply leave them floating.
Cycle Descripti on Truth Table [2, 3, 4, 5, 6, 7, 8, 9]
Operation CE1X CE2X CE1Y CE2Y WEX WEY PTX PTY
Desele ct Cycle H X H X X X X X
Desele ct Cycle X L X L X X X X
Write Port X L HXX0XXX
Notes:
2. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
3. All inputs except OEX and OEY must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
4. OEX and OEY must be asserted to avoid bus contention during Write and Pass-through cycles. For Write and Pass-through operations following a Read
operation, OEX/OEY must be HIGH before the input data required set-up time plus High-Z time for OEX/OEY and staying HIGH throughout the input data
hold time.
5. Operation numbers 3–6 can be used in any combi na tion .
6. Operation numbers 4 and 7, 3 and 8, and 7 and 8 can be combined.
7. Operation numbers 5 can not be combined with operation number 7 or 8 because Pass-through operation has higher priority over a Read operation.
8. Operation number 6 can not be combined with operation number 7 or 8 because Pass-through operation has higher priority over a Read operation.
9. This device contains circuitry that will ensure the outputs will be in High-Z during power-up
CY7C1300A
Document #: 38-05075 Rev. *C Page 4 of 12
Maximum Ratings
(Above w hi ch the useful life m ay be im pai red. For user guide-
lines, not tes ted .)
Storage Temperature .....................................−55°C to +125°C
Ambient Temperature with
Power Applied.................................................... −10°C to +85°C
Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State[10] ...................................−0.5V to VCCQ + 0.5V
DC Input Voltage[10]................................−0.5V to VCCQ + 0.5V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage......................................... > 1601V
(per MIL-STD-883, Method 3015)
Latch-up Current ................................................... > 200 mA
Write Port Y X X L H X 0 X X
Pass-through from X to Y L H L H X X 0 X
Pass-through from Y to X L H L H X X X 0
Read Port X L H X X 1 X 1 1
Read Port Y X X L H X 1 1 1
Cycle Description Truth Table (continued)[2, 3, 4, 5, 6, 7, 8, 9]
Operation CE1X CE2X CE1Y CE2Y WEX WEY PTX PTY
Operating Range
Range Ambient
Temperature[11] VDD/VDDQ(12)
Commercial 0°C to +70°C 3.3V ± 5%
Electrical Characteristics Ov er the Op erating Range
Paramete
rDescription Test Conditions Min. Max. Unit
VDD Power Supp ly V oltage 3.135 3.465 V
VDDQ I/O Supply Voltage 3.135 3.465 V
VOH Output HIGH Voltage VDD = Min., IOH = –4.0 mA 2.4 V
VOL Output LOW Voltage VDD = Min., IOL = 8.0 mA 0.4 V
VIH Input HIGH
Voltage[13] 2.0 VCC + 0.5V V
VIL Input LOW Voltage[14] −0.5 0.8 V
IXInput Load Cur rent GND ≤ VIN ≤ VDDQ −5 5 µA
IOZ Output Leakage
Current GND ≤ VIN ≤ VDDQ, Output Disabled −5 5 µA
ICC VDD Operating Supply VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC 10.0 ns cycle, MHz 500 mA
12.0 ns cycle, 83 MHz 430 mA
ISB Automatic CE
Power-down
Current—CMOS
Inputs
Max. VDD, Device Deselected[15],
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
f = 0
10.0 ns cy cle , 100 MH z 140 mA
12.0 ns cycle, 83 MHz 120 mA
Capacitance[16]
Parameter Description Test Conditions Max. Unit
CIN Input capacitance TA = 25°C, f = 1 MHz,
VCC = 3.3V,
VCCQ = 3.3V
8pF
CCLK Clock input capacitance 9 pF
Notes:
10. Minimum voltage equals –2.0V for pulse duration less than 20 ns.
11. TA is the case temperature.
12. Power supply ramp up should be monotonic.
13. Overshoot: VIH ≤ +6.0V for t ≤ tKC /2.
14. Under shoot: VIL ≤ –2.0V for t ≤ tKC /2.
15. “Device Deselecte d” means the device is in power-down mode as defined in the truth table.
16. Tested initially and after any design or process change that may affect these parameters.
CY7C1300A
Document #: 38-05075 Rev. *C Page 5 of 12
AC Test Loads and Waveforms[1 7, 18]
Thermal Resistance
Parameter Description Test Conditions TQFP Typ. Units Notes
ΘJA Therm al Resistance
(Junction to Ambient) (@200l fm) Sing le-l ay er print ed cir cui t board 40 °C/W 15
ΘJC Thermal R esi st anc e
(Junction to Ambient) (@200lfm) Four-layer printed circuit board 35 °C/W 15
ΘJA Therm al Resistance
(Junction to Board) Bottom 23 °C/W 15
ΘJC Thermal R esi st anc e
(Junction to Case) Top 9 °C/W 15
Notes:
17. AC test conditions assume a signal transition time of 1 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading shown in
part (a) of AC Test Loa ds.
18. Overshoot: VIH(AC) <VDD + 1.5V for t <tTCYC/2; undershoot: VIL(AC) < 0.5V for t <tTCYC/2; power-up: VIH < 2.6V and VDD <2.4V and VDDQ < 1.4V for
t<200 ms.
3.0V
GND
OUTPUT
R = 317Ω
R = 351Ω
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
ALL INP U T PULSES
OUTPUT
RL= 5 0Ω
Z0= 50Ω
VL= 1.5V
3.3V [17]
1V/ns 1V/ns
(c)
CY7C1300A
Document #: 38-05075 Rev. *C Page 6 of 12
Switching Characteristics Over the Op erating Range[17, 19, 20]
-100 -83
Parameter Description Min. Max. Min. Max. Unit
Clock
tKC Clock cycle time 10 12 ns
tKH Clock HIGH time 3.5 4.0 ns
tKL Clock LOW time 3.5 4.0 ns
Output times
tKQ Clock to output valid 5.0 6.0 ns
tKQX Clock to output invalid 1.5 1.5 ns
tKQLZ Clock to output in Low-Z[21] 0 0 ns
tKQHZ Clock to output in High-Z[21] 3.0 3.0 ns
tOEQ OEX/OEY to output valid 5.0 6.0 ns
tOELZ OEX/OEY to output in Low-Z[21] 0 0 ns
tOEHZ OEX/OEY to output in High-Z[21] 3.0 3.0 ns
Set-up times
tSAddresses, controls, and data In 1.8 2.0 ns
Hold times
tHAddresses, controls, and data In 0.5 0.5 ns
Notes:
19. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with AC test conditions, as shown in part (a) of AC T est Loads. T ransition is measured ±200 mV from steady-state
voltage.
20. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but rather reflect parameters guaranteed over worst-case user conditions. Device is
designed to achieve High-Z prior to Low-Z under the same system conditions.
21. This parameter is sampled and not 100% tested.
CY7C1300A
Document #: 38-05075 Rev. *C Page 7 of 12
Switching Waveforms [22]
22. CE LOW means (CE1X and CE1Y) equals LOW and (CE2X and CE2Y) equals HIGH. CE HIGH me ans (CE 1X and CE1Y) equals HIGH or (CE2X and CE2Y)
equals LOW.
CLK
AX
CE#
(See Note)
OEX#
DQX
2
t
KQ
t
OELZ
t
H
t
S
t
KH
t
KL
t
KC
t
OEQ
1 43 65 87 9
Q(1) Q(2) Q(3) Q(5) Q(6) Q(7)
OEY#
DQY
Q(12) Q(13) Q(14) Q(16) Q(6) Q(7)
AY
1312 1514 616 197 20
t
H
t
S
t
KQHZ
t
KQ
t
OEHZ
t
KQLZ
PORT X
PORT Y
Read Cycle Timing from Both Ports (WEX, WEY, PTX, PTY HIGH)[22]
CY7C1300A
Document #: 38-05075 Rev. *C Page 8 of 12
Switching Waveforms (continued)[22]
CLK
AX
CE#
(See Note)
OEX#
DQX
2
t
H
t
S
t
KH
t
KL
t
KC
1 43 65 87 9
D(3)
OEY#
DQY
AY
1312 1514 65 1918 20
t
H
t
S
WEX#
WEY#
PORT X
PORT Y
D(2) D(4) D(8) D(9)
D(14) D(15) D(19)D(5) D(6) D(18)
t
H
t
S
PORT Y TAKES
PRIORITY OVER PORT X
WHEN AX=AY AND
WRITING TO BOTH
Write Cycle Timing to Both Ports (PTX, PTY HIGH)[21]
CY7C1300A
Document #: 38-05075 Rev. *C Page 9 of 12
Switching Waveforms (continued)[22]
CLK
AX
CE#
(See Note)
OEX#
DQX
2
t
H
t
S
t
KH
t
KL
t
KC
1 43 65 87 9
D(3)
OEY#
DQY
AY
1312 1514 1716 1918 20
WEX#
WEY#
PORT X
PORT Y
D(2) D(X)
PTY#
PTY#
D(Y) D(6)
Q(3) D(X) D(Y) Q(17)
t
KQHZ
t
KQ
t
KQX
t
S
t
H
Write to Port X and Pass-through to Port Y[21]
PTX#
CY7C1300A
Document #: 38-05075 Rev. *C Page 10 of 12
Switching Waveforms (continued)[22]
3
CLK
AX
OEX#
DQX
2
t
H
t
S
t
KH
t
KL
t
KC
1 1 2
OEY#
DQY
AY
WEX#
WEY#
PORT X
PORT Y
D(DEF)
PORT Y TAKES
PRIORITY OVER PORT X
WHEN AX=AY AND
WRITING TO BOTH
PORTS.
D(ABC) Q(PQR) Q(XYZ) Q(JKL)
D(XYZ)D(PQR) Q(JKL)D(JKL)Q(PQR)
TRY TO
WRITE TRY TO
WRITE READ READ READ READ READ READ
3
21 1 2
WRITE WRITE READ READ READ READ READ READ
PTX# = PTY# = HIGH
D(Value) = Value is the input of the data port.
Q(Value) = Value is the output of the data port.
Combination Read/Write with Same Address on Each Port
CY7C1300A
Document #: 38-05075 Rev. *C Page 11 of 12
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cypress Semi conductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagram
All product and company names mentioned in this document may be the trademarks of their respective holders.
Ordering Information
Speed
(MHz) Ordering Code Package
Name Package Type Operating
Range
100 CY7C1300A-100AC AC 176-lead TQFP Commercial
83 CY7C1300A-83AC
176-lead Thin Quad Flat Pack (24 × 24 × 1.4 m m) A176
51-85132
CY7C1300A
Document #: 38-05075 Rev. *C Page 12 of 12
Document Title: CY7C1300A 128K x 36 Dual I/O Dual Address Synchronous SRAM
Document Number: 38-05075
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 107304 06/08/01 NSL New Data Sheet
*A 109296 10/31/01 CJM 1. Removed 133 MHz speed bin
2. Changed ESD voltage from >2001V to >1601V
3. Changed tS from 1.5 ns to 1.8 ns (only 100 MHz)
4. Changed ISB from 100 mA to 120 mA (All speeds)
5. Changed CIN from 6 pF to 8 pF (All speeds)
6. Changed CCLK from 6 pF to 9 pF (All speeds)
7. Changed ICC to reflect char data (All speeds)
8. Changed ordering code from CY7C1301A to CY7C1300A (All speeds)
9. Removed Preliminary
*B 113017 04/09/02 KOM Changed ICC values on first page to correct value (500 and 430). Also
updated Logic Block Diagram.
*C 123844 01/19/03 AJH Updated power-up requirements in Operating Range and in AC Test Loads
and Waveforms.
