AD9231BCPZ-20 - Analog Devices, Inc.

12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,

1.8 V Dual Analog-to-Digital Converter

AD9231

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

1.8 V analog supply operation

1.8 V to 3.3 V output supply

SNR

71.3 dBFS at 9.7 MHz input

69.0 dBFS at 200 MHz input

SFDR

93 dBc at 9.7 MHz input

83 dBc at 200 MHz input

Low power

32 mW per channel at 20 MSPS

71 mW per channel at 80 MSPS

Differential input with 700 MHz bandwidth

On-chip voltage reference and sample-and-hold circuit

2 V p-p differential analog input

DNL = ±0.40 LSB

Serial port control options

Offset binary, gray code, or twos complement data format

Optional clock duty cycle stabilizer

Integer 1-to-8 input clock divider

Data output multiplex option

Built-in selectable digital test pattern generation

Energy-saving power-down modes

Data clock out with programmable clock and data alignment

APPLICATIONS

Communications

Diversity radio systems

Multimode digital receivers

GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA

I/Q demodulation systems

Smart antenna systems

Battery-powered instruments

Hand held scope meters

Portable medical imaging

Ultrasound

Radar/LIDAR

FUNCTIONAL BLOCK DIAGRAM

VIN+A

VIN–A

VREF

SENSE

VCM

RBIAS

VIN–B

VIN+B

ORA

D0A

D11A

DCOA

DRVDD

ORB

D11B

D0B

DCOB

SDIOGND

DD SCLK

SPI

PROGRAMMING DATA

MUX OPTION

PDWN DFSCLK+ CLK–

MODE

CONTROLS

DCS

DUTY CYCLE

STABILIZER

SYNC

DIVIDE

1TO 8

OEB

CSB

REF

SELECT

ADC

CMOS

OUTPUT BUFFER

ADC

CMOS

OUTPUT BUFFER

AD9231

08121-001

Figure 1.

PRODUCT HIGHLIGHTS

1. The AD9231 operates from a single 1.8 V analog power

supply and features a separate digital output driver supply

to accommodate 1.8 V to 3.3 V logic families.

2. The patented sample-and-hold circuit maintains excellent

performance for input frequencies up to 200 MHz and is

designed for low cost, low power, and ease of use.

3. A standard serial port interface supports various product

features and functions, such as data output formatting,

internal clock divider, power-down, DCO/DATA timing

and offset adjustments, and voltage reference modes.

4. The AD9231 is packaged in a 64-lead RoHS compliant

LFCSP that is pin compatible with the AD9268 16-bit

ADC, the AD9258 14-bit ADC, the AD9251 14-bit ADC,

and the AD9204 10-bit ADC, enabling a simple migration

path between 10-bit and 16-bit converters sampling from

20 MSPS to 125 MSPS.

AD9231

Rev. A | Page 2 of 36

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

General Description......................................................................... 3

Specifications..................................................................................... 4

DC Specifications ......................................................................... 4

AC Specifications.......................................................................... 5

Digital Specifications ................................................................... 6

Switching Specifications .............................................................. 7

Timing Specifications .................................................................. 8

Absolute Maximum Ratings............................................................ 9

Thermal Characteristics .............................................................. 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 12

AD9231-80 .................................................................................. 12

AD9231-65 .................................................................................. 14

AD9231-40 .................................................................................. 15

AD9231-20 .................................................................................. 16

Equivalent Circuits......................................................................... 17

Theory of Operation ...................................................................... 19

ADC Architecture ...................................................................... 19

Analog Input Considerations.................................................... 19

Voltage Reference ....................................................................... 22

Clock Input Considerations...................................................... 23

Channel/Chip Synchronization................................................ 25

Power Dissipation and Standby Mode .................................... 25

Digital Outputs ........................................................................... 26

Timing ......................................................................................... 26

Built-In Self-Test (BIST) and Output Test .................................. 27

Built-In Self-Test (BIST)............................................................ 27

Output Test Modes..................................................................... 27

Serial Port Interface (SPI).............................................................. 28

Configuration Using the SPI..................................................... 28

Hardware Interface..................................................................... 29

Configuration Without the SPI ................................................ 29

SPI Accessible Features.............................................................. 29

Memory Map .................................................................................. 30

Reading the Memory Map Register Table............................... 30

Open Locations .......................................................................... 30

Default Values............................................................................. 30

Memory Map Register Table..................................................... 31

Memory Map Register Descriptions........................................ 33

Applications Information.............................................................. 34

Design Guidelines ...................................................................... 34

Outline Dimensions ....................................................................... 35

Ordering Guide .......................................................................... 35

REVISION HISTORY

6/10—Rev. 0 to Rev. A

Changes to Features Section............................................................ 1

10/09—Revision 0: Initial Version

AD9231

Rev. A | Page 3 of 36

GENERAL DESCRIPTION

The AD9231 is a monolithic, dual-channel, 1.8 V supply, 12-bit,

20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital conver-

ter (ADC). It features a high performance sample-and-hold

circuit and on-chip voltage reference.

The product uses multistage differential pipeline architecture

with output error correction logic to provide 12-bit accuracy at

80 MSPS data rates and to guarantee no missing codes over the

full operating temperature range.

The ADC contains several features designed to maximize

flexibility and minimize system cost, such as programmable

clock and data alignment and programmable digital test pattern

generation. The available digital test patterns include built-in

deterministic and pseudorandom patterns, along with custom

user-defined test patterns entered via the serial port interface (SPI).

A differential clock input controls all internal conversion cycles.

An optional duty cycle stabilizer (DCS) compensates for wide

variations in the clock duty cycle while maintaining excellent

overall ADC performance.

The digital output data is presented in offset binary, gray code,

or twos complement format. A data output clock (DCO) is

provided for each ADC channel to ensure proper latch timing

with receiving logic. Both 1.8 V and 3.3 V CMOS levels are

supported, and output data can be multiplexed onto a single

output bus.

The AD9231 is available in a 64-lead RoHS compliant LFCSP

and is specified over the industrial temperature range (−40°C

to +85°C).

AD9231

Rev. A | Page 4 of 36

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,

DCS disabled, unless otherwise noted.

Table 1.

AD9231-20/AD9231-40 AD9231-65 AD9231-80

Parameter Temp

Min Typ Max Min Typ Max Min Typ Max Unit

RESOLUTION Full 12 12 12 Bits

ACCURACY

No Missing Codes Full Guaranteed Guaranteed Guaranteed

Offset Error Full 0.05 ±0.5 0.05 ±0.5 0.05 ±0.5 % FSR

Gain Error1 Full −1.5 −1.5 −1.5 % FSR

Differential Nonlinearity (DNL)2 Full ±0.30 ±0.40 ±0.40 LSB

25°C ±0.12 ±0.17 ±0.2 LSB

Integral Nonlinearity (INL)2 Full ±0.45 ±0.50 ±0.65 LSB

25°C ±0.15 ±0.17 ±0.2 LSB

MATCHING CHARACTERISTICS

Offset Error 25°C ±0.0 ±0.70 ±0.0 ±0.60 ±0.0 ±0.60 % FSR

Gain Error1 25°C 0.3 0.3 0.4 % FSR

TEMPERATURE DRIFT

Offset Error Full ±2 ±2 ±2 ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage (1 V Mode) Full 0.981 0.993 1.005 0.981 0.993 1.005 0.981 0.993 1.005 V

Load Regulation Error at 1.0 mA Full 2 2 2 mV

INPUT-REFERRED NOISE

VREF = 1.0 V 25°C 0.25 0.25 0.25 LSB rms

ANALOG INPUT

Input Span, VREF = 1.0 V Full 2 2 2 V p-p

Input Capacitance3 Full 6 6 6 pF

Input Common-Mode Voltage Full 0.9 0.9 0.9 V

Input Common-Mode Range Full 0.5 1.3 0.5 1.3 0.5 1.3 V

REFERENCE INPUT RESISTANCE Full 7.5 7.5 7.5 kΩ

POWER SUPPLIES

Supply Voltage

AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V

DRVDD Full 1.7 3.6 1.7 3.6 1.7 3.6 V

Supply Current

IAVDD2 Full 35.7/49.0 37.7/52.2 69 72.4 80.0 83.4 mA

IDRVDD2 (1.8 V) Full 3.0/5.1 7.4 9.1 mA

IDRVDD2 (3.3 V) Full 5.9/10.1 14.9 18.3 mA

POWER CONSUMPTION

DC Input Full 63.5/87.1 122.9 141.8 mW

Sine Wave Input2 (DRVDD = 1.8 V) Full 69.7/97.3 73.3/103.0 138.0 143.8 160.4 166.5 mW

Sine Wave Input2 (DRVDD = 3.3 V) Full 83.7/121.5 173.4 204 mW

Standby Power4 Full 37/37 37 37 mW

Power-Down Power Full 2.2 2.2 2.2 mW

1 Measured with 1.0 V external reference.

2 Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit.

3 Input capacitance refers to the effective capacitance between one differential input pin and AGND.

4 Standby power is measured with a dc input and the CLK active.

AD9231

Rev. A | Page 5 of 36

AC SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,

DCS disabled, unless otherwise noted.

Table 2.

AD9231-20/AD9231-40 AD9231-65 AD9231-80

Parameter1 Temp

Min Typ Max Min Typ Max Min Typ Max

Unit

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 9.7 MHz 25°C 70.7/71.5 71.4 71.3 dBFS

fIN = 30.5 MHz 25°C 70.6/71.3 71.3 71.2 dBFS

Full 70.1/70.7 70.5 dBFS

fIN = 70 MHz 25°C 70.5/71.0 71.0 70.9 dBFS

Full 70.1 dBFS

fIN = 200 MHz 25°C 69.0 69.0 69.0 dBFS

SIGNAL-TO-NOISE-AND-DISTORTION (SINAD)

fIN = 9.7 MHz 25°C 70.6/71.4 71.3 71.2 dBFS

fIN = 30.5 MHz 25°C 70.6/71.2 71.2 71.1 dBFS

Full 70.1/70.6 70.0 dBFS

fIN = 70 MHz 25°C 70.4/70.9 70.9 70.8 dBFS

Full 70.0 dBFS

fIN = 200 MHz 25°C 68 68 68 dBFS

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 9.7 MHz 25°C 11.4/11.6 11.6 11.5 Bits

fIN = 30.5 MHz 25°C 11.4/11.5 11.5 11.5 Bits

fIN = 70 MHz 25°C 11.4/11.5 11.5 11.5 Bits

fIN = 200 MHz 25°C 11.0 11.0 11.0 Bits

WORST SECOND OR THIRD HARMONIC

fIN = 9.7 MHz 25°C −95 −95 −93 dBc

fIN = 30.5 MHz 25°C −95 −95 −93 dBc

Full −81 −81 dBc

fIN = 70 MHz 25°C −92/−94 −94 −92 dBc

Full −81 dBc

fIN = 200 MHz 25°C −83 −83 −83 dBc

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 9.7 MHz 25°C 95 95 93 dBc

fIN = 30.5 MHz 25°C 95 95 93 dBc

Full 81 81 dBc

fIN = 70 MHz 25°C 92/94 94 92 dBc

Full 81 dBc

fIN = 200 MHz 25°C 83 83 83 dBc

WORST OTHER (HARMONIC OR SPUR)

fIN = 9.7 MHz 25°C −98 −98 −97 dBc

fIN = 30.5 MHz 25°C −97/−98 −98 −97 dBc

Full −90 −90 dBc

fIN = 70 MHz 25°C −97/−98 −98 −95 dBc

Full −89 dBc

fIN = 200 MHz 25°C −92 −92 −92 dBc

TWO-TONE SFDR

fIN = 28.3 MHz (−7 dBFS), 30.6 MHz (−7 dBFS) 25°C 90 90 90 dBc

CROSSTALK2 Full −110 −110 −110 dBc

ANALOG INPUT BANDWIDTH 25°C 700 700 700 MHz

1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

2 Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.

AD9231

Rev. A | Page 6 of 36

DIGITAL SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,

DCS disabled, unless otherwise noted.

Table 3.

AD9231-20/AD9231-40/AD9231-65/AD9231-80

Parameter Temp

Min Typ Max Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL

Internal Common-Mode Bias Full 0.9 V

Differential Input Voltage Full 0.2 3.6 V p-p

Input Voltage Range Full GND − 0.3 AVDD + 0.2 V

High Level Input Current Full −10 +10 μA

Low Level Input Current Full −10 +10 μA

Input Resistance Full 8 10 12 kΩ

Input Capacitance Full 4 pF

LOGIC INPUTS (SCLK/DFS, SYNC, PDWN)1

High Level Input Voltage Full 1.2 DRVDD + 0.3 V

Low Level Input Voltage Full 0 0.8 V

High Level Input Current Full −50 −75 μA

Low Level Input Current Full −10 +10 μA

Input Resistance Full 30 kΩ

Input Capacitance Full 2 pF

LOGIC INPUTS (CSB)2

High Level Input Voltage Full 1.2 DRVDD + 0.3 V

Low Level Input Voltage Full 0 0.8 V

High Level Input Current Full −10 +10 μA

Low Level Input Current Full 40 135 μA

Input Resistance Full 26 kΩ

Input Capacitance Full 2 pF

LOGIC INPUTS (SDIO1/DCS2)

High Level Input Voltage Full 1.2 DRVDD + 0.3 V

Low Level Input Voltage Full 0 0.8 V

High Level Input Current Full −10 +10 μA

Low Level Input Current Full 40 130 μA

Input Resistance Full 26 kΩ

Input Capacitance Full 5 pF

DIGITAL OUTPUTS

DRVDD = 3.3 V

High Level Output Voltage, IOH = 50 μA Full 3.29 V

High Level Output Voltage, IOH = 0.5 mA Full 3.25 V

Low Level Output Voltage, IOL = 1.6 mA Full 0.2 V

Low Level Output Voltage, IOL = 50 μA Full 0.05 V

DRVDD = 1.8 V

High Level Output Voltage, IOH = 50 μA Full 1.79 V

High Level Output Voltage, IOH = 0.5 mA Full 1.75 V

Low Level Output Voltage, IOL = 1.6 mA Full 0.2 V

Low Level Output Voltage, IOL = 50 μA Full 0.05 V

1 Internal 30 kΩ pull-down.

2 Internal 30 kΩ pull-up.

AD9231

Rev. A | Page 7 of 36

SWITCHING SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,

DCS disabled, unless otherwise noted.

Table 4.

AD9231-20/AD9231-40 AD9231-65 AD9231-80

Parameter Temp

Min Typ Max Min Typ Max Min Typ Max

Unit

CLOCK INPUT PARAMETERS

Input Clock Rate Full 625 625 625 MHz

Conversion Rate1 Full 3 20/40 3 65 3 80 MSPS

CLK Period—Divide-by-1 Mode (tCLK) Full 50/25 15.38 12.5 ns

CLK Pulse Width High (tCH) 25.0/12.5 7.69 6.25 ns

Aperture Delay (tA) Full 1.0 1.0 1.0 ns

Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms

DATA OUTPUT PARAMETERS

Data Propagation Delay (tPD) Full 3

3 3 ns

DCO Propagation Delay (tDCO) Full

3 3 ns

DCO to Data Skew (tSKEW) Full

0.1

0.1 0.1 ns

Pipeline Delay (Latency) Full 9 9 9 Cycles

Wake-Up Time2 Full 350 350 350 μs

Standby Full 600/400 300 260 ns

OUT-OF-RANGE RECOVERY TIME Full 2 2 2 Cycles

1 Conversion rate is the clock rate after the CLK divider.

2 Wake-up time is dependent on the value of the decoupling capacitors.

SKEW

DCO

CLK

N – 9

N – 1

N + 1 N + 2

N + 3

N + 5

N + 4

N – 8N – 7N – 6N – 5

VIN

CLK+

CLK–

CH A/CH B DATA

DCOA/DCOB

08121-002

Figure 2. CMOS Output Data Timing

SKEW

DCO

CLK

CH A

N – 9 CH B

N – 9 CH A

N – 8 CH B

N – 8 CH A

N – 7 CH B

N – 7 CH A

N – 6 CH B

N – 6 CH A

N – 5

N – 1

N + 1 N + 2

N + 3

N + 5

N + 4

VIN

CLK+

CLK–

CH A/CH B DATA

DCOA/DCOB

08121-003

Figure 3. CMOS Interleaved Output Timing

AD9231

Rev. A | Page 8 of 36

TIMING SPECIFICATIONS

Table 5.

Parameter Conditions Min Typ Max Unit

SYNC TIMING REQUIREMENTS

tSSYNC SYNC to rising edge of CLK setup time 0.24 ns

tHSYNC SYNC to rising edge of CLK hold time 0.40 ns

SPI TIMING REQUIREMENTS

tDS Setup time between the data and the rising edge of SCLK 2 ns

tDH Hold time between the data and the rising edge of SCLK 2 ns

tCLK Period of the SCLK 40 ns

tS Setup time between CSB and SCLK 2 ns

tH Hold time between CSB and SCLK 2 ns

tHIGH SCLK pulse width high 10 ns

tLOW SCLK pulse width low 10 ns

tEN_SDIO Time required for the SDIO pin to switch from an input to an

output relative to the SCLK falling edge

10 ns

tDIS_SDIO Time required for the SDIO pin to switch from an output to an

input relative to the SCLK rising edge

10 ns

SYNC

CLK+

HSYNC

SSYNC

08121-004

Figure 4. SYNC Input Timing Requirements

AD9231

Rev. A | Page 9 of 36

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

AVDD to AGND −0.3 V to +2.0 V

DRVDD to AGND −0.3 V to +3.9 V

VIN+A, VIN+B, VIN−A, VIN−B to AGND −0.3 V to AVDD + 0.2 V

CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V

SYNC to AGND −0.3 V to DRVDD + 0.3 V

VREF to AGND −0.3 V to AVDD + 0.2 V

SENSE to AGND −0.3 V to AVDD + 0.2 V

VCM to AGND −0.3 V to AVDD + 0.2 V

RBIAS to AGND −0.3 V to AVDD + 0.2 V

CSB to AGND −0.3 V to DRVDD + 0.3 V

SCLK/DFS to AGND −0.3 V to DRVDD + 0.3 V

SDIO/DCS to AGND −0.3 V to DRVDD + 0.3 V

OEB to AGND −0.3 V to DRVDD + 0.3 V

PDWN to AGND −0.3 V to DRVDD + 0.3 V

D0A/D0B through D11A/D11B to AGND

−0.3 V to DRVDD + 0.3 V

DCOA/DCOB to AGND

−0.3 V to DRVDD + 0.3 V

Operating Temperature Range (Ambient) −40°C to +85°C

Maximum Junction Temperature Under Bias 150°C

Storage Temperature Range (Ambient) −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

THERMAL CHARACTERISTICS

The exposed paddle is the only ground connection for the chip.

The exposed paddle must be soldered to the AGND plane of the

user’s circuit board. Soldering the exposed paddle to the user’s

board also increases the reliability of the solder joints and

maximizes the thermal capability of the package.

Table 7. Thermal Resistance

Package Type

Airflow

Velocity

(m/sec) θJA1, 2 θJC1, 3 θJB1, 4 Unit

0 23 2.0 °C/W

1.0 20 12 °C/W

64-Lead LFCSP

9 mm × 9 mm

(CP-64-4) 2.5 18 °C/W

1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.

2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

3 Per MIL-Std 883, Method 1012.1.

4 Per JEDEC JESD51-8 (still air).

Typical θJA is specified for a 4-layer PCB with a solid ground

plane. As shown in Table 7 , airflow improves heat dissipation,

which reduces θJA. In addition, metal in direct contact with the

package leads from metal traces, through holes, ground, and

power planes, reduces the θJA.

ESD CAUTION

AD9231

Rev. A | Page 10 of 36

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

D8B

D9B

DRVDD

D10B

(MSB) D11B

ORB

DCOB

DCOA

DRVDD

(LSB) D0A

D1A

D2A

AVDD

VIN+B

VIN–B

AVDD

RBIAS

VCM

SENSE

VREF

AVDD

VIN–A

VIN+A

AVDD

CLK+

CLK–

SYNC

(LSB) D0B

D1B

DRVDD

D2B

D3B

D4B

D5B

D6B

D7B

NOTES

1. NC = NO CONNECT.

2. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB GROUND TO

ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL

STRENGTH BENEFITS.

PDWN

OEB

CSB

SCLK/DFS

SDIO/DCS

ORA

D11A (MSB)

D10A

D9A

D8A

D7A

DRVDD

D6A

D5A

D4A

D3A

AD9231

TOP VIEW

(Not to Scale)

08121-005

Figure 5. Pin Configuration

Table 8. Pin Function Description

Pin No. Mnemonic Description

0 GND Exposed paddle is the only ground connection for the chip. Must be connected to PCB AGND.

1, 2 CLK+, CLK− Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.

3 SYNC Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down.

4, 5, 6, 7, 25, 26, 27, 29 NC Do Not Connect.

8 to 9, 11 to 18, 20, 21 D0B to D11B Channel B Digital Outputs. D11B = MSB.

10, 19, 28, 37 DRVDD Digital Output Driver Supply (1.8 V to 3.3 V).

22 ORB Channel B Out-of-Range Digital Output.

23 DCOB Channel B Data Clock Digital Output.

24 DCOA Channel A Data Clock Digital Output.

30 to 36, 38 to 42 D0A to D11A Channel A Digital Outputs. D11A = MSB.

43 ORA Channel A Out-of-Range Digital Output.

44 SDIO/DCS

SPI Data Input/Output (SDIO). Bidirectional SPI Data I/O in SPI mode. 30 kΩ internal pull-

down in SPI mode.

Duty Cycle Stabilizer (DCS). Static enable input for duty cycle stabilizer in non-SPI mode.

30 kΩ internal pull-up in non-SPI (DCS) mode.

45 SCLK/DFS

SPI Clock (SCLK) Input in SPI mode. 30 kΩ internal pull-down.

Data Format Select (DFS). Static control of data output format in non-SPI mode. 30 kΩ internal

pull-down.

DFS high = twos complement output.

DFS low = offset binary output.

46 CSB SPI Chip Select. Active low enable; 30 kΩ internal pull-up.

47 OEB

Digital Input. Enable Channel A and Channel B digital outputs if low, tristate outputs if high.

30 kΩ internal pull-down.

48 PDWN

Digital Input. 30 kΩ internal pull-down.

PDWN high = power-down device.

PDWN low = run device, normal operation.

AD9231

Rev. A | Page 11 of 36

Pin No. Mnemonic Description

49, 50, 53, 54, 59, 60, 63, 64 AVDD 1.8 V Analog Supply Pins.

51, 52 VIN+A, VIN−A Channel A Analog Inputs.

55 VREF Voltage Reference Input/Output.

56 SENSE Reference Mode Selection.

57 VCM Analog output voltage at midsupply to set common mode of the analog inputs.

58 RBIAS Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.

61, 62 VIN−B, VIN+B Channel B Analog Inputs.

AD9231

Rev. A | Page 12 of 36

TYPICAL PERFORMANCE CHARACTERISTICS

AD9231-80

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS

disabled, unless otherwise noted.

–15

–30

–45

–60

–75

–90

–105

–120

–135

40 8 12 16 20 24 28 32 36 40

FREQUENCY (MHz)

AMPLITUDE (dBFS)

08121-054

80MSPS

9.7MHz @ –1dBFS

SNR = 70.2dB (71.2dBFS)

SFDR = 93.6dBc

Figure 6. AD9231-80 Single-Tone FFT with fIN = 9.7 MHz

–15

–30

–45

–60

–75

–90

–105

–120

–135

40 8 12 16 20 24 28 32 36 40

FREQUENCY (MHz)

AMPLITUDE (dBFS)

08121-055

80MSPS

30.6MHz @ –1dBFS

SNR = 70.1dB (71.1dBFS)

SFDR = 94.4dBc

Figure 7. AD9231-80 Single-Tone FFT with fIN = 30.6 MHz

–15

–30

–45

–60

–75

–90

–105

–120

–135

40 8 12 16 20 24 28 32 36 40

FREQUENCY (MHz)

AMPLITUDE (dBFS)

08121-056

80MSPS

69MHz @ –1dBFS

SNR = 69.9dB (70.9dBFS)

SFDR = 94.3dBc

Figure 8. AD9231-80 Single-Tone FFT with fIN = 69 MHz

–15

–30

–45

–60

–75

–90

–105

–120

–135

40 8 12 16 20 24 28 32 36 40

FREQUENCY (MHz)

AMPLITUDE (dBFS)

08121-057

80MSPS

100.3MHz @ –1dBFS

SNR = 69.5dB (70.5dBFS)

SFDR = 87.7dBc

Figure 9. AD9231-80 Single-Tone FFT with fIN = 100.3 MHz

–15

–30

–45

–60

–75

–90

–105

–120

–135

40 8 12 16 20 24 28 32 36 40

FREQUENCY (MHz)

AMPLITUDE (dBFS)

08121-058

80MSPS

210.3MHz @ –1dBFS

SNR = 67.9dB (68.9dBFS)

SFDR = 83.2dBc

Figure 10. AD9231-80 Single-Tone FFT with fIN = 210.3 MHz

–15

–30

–45

–60

–75

–90

–105

–120

–135

40 8 12 16 20 24 28 32 36 40

FREQUENCY (MHz)

AMPLITUDE (dBFS)

08121-059

F2 – F1 2F2 – F1

2F1 + F2

F1 + F2 2F2 – F1 2F1 – F2

80MSPS

28.3 @ –7dBFS

30.6 @ –7dBFS

SFDR = 90dBc

Figure 11. AD9231-80 Two-Tone FFT with fIN1 = 28.3 MHz and fIN2 = 30.6 MHz

AD9231

Rev. A | Page 13 of 36

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS

disabled, unless otherwise noted.

–120

–70 –60 –50 –40

INPUT AMPLITUDE (dBFS)

–30 –20 –10

–100

–80

–60

–40

–20

SFDR/IMD3 (dBc/dBFS)

SFDR (dBc)

SFDR (dBFS)

IMD3 (dBc)

IMD3 (dBFS)

08121-060

Figure 12. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with

fIN1 = 28.3 MHz and fIN2 = 30.6 MHz

100

0 50 100 150 200

SNR/SFDR (dBFS/dBc)

INPUT FREQUENCY (MHz)

SNR

SFDR

08121-061

Figure 13. AD9231-80 SNR/SFDR vs. Input Frequency (AIN) with

2 V p-p Full Scale

0.3

0.2

0.1

–0.1

–0.2

–0.3

0 500 1000 1500 2000 2500 3000 3500 4000

OUTPUT CODE

DNL ERROR (LSB)

08121-063

Figure 14. AD9231-80 DNL Error with fIN = 9.7 MHz

100

10 20 30 40 50 60 70 80

SNRFS/SFDR (dBFS/dBc)

SAMPLE RATE (MHz)

SNRFS

SFDR

08121-062

Figure 15. AD9231-80 SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz

100

–70 –60 –50 –40 –30 –20 –10 0

SNR/SFDR (dBc AND dBFS)

INPUT AMPLITUDE (dBc)

SNR

SNRFS

SFDR

SFDRFS

08121-064

Figure 16. AD9231-80 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz

–0.2

0.4

0.2

0.4

0 500 1000 1500 2000 2500 3000 3500 4000

OUTPUT CODE

INL ERROR (LSB)

08121-066

Figure 17. AD9231-80 INL with fIN = 9.7 MHz

AD9231

Rev. A | Page 14 of 36

AD9231-65

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS

disabled, unless otherwise noted.

–15

–30

–45

–60

–75

–90

–105

–120

–135

30 6 9 1215182124 3027 33

FREQUENCY (MHz)

AMPLITUDE (dBFS)

08121-067

543

65MSPS

9.7MHz @ –1dBFS

SNR =70.3 (71.3dBFS)

SFDR = 94.2dBc

Figure 18. AD9231-65 Single-Tone FFT with fIN = 9.7 MHz

–15

–30

–45

–60

–75

–90

–105

–120

–135

30 6 9 1215182124 3027 33

FREQUENCY (MHz)

AMPLITUDE (dBFS)

08121-069

65MSPS

30.6MHz @ –1dBFS

SNR = 70.2dB (71.2dBFS)

SFDR = 94.1dBc

Figure 19. AD9231-65 Single-Tone FFT with fIN = 30.6 MHz

–15

–30

–45

–60

–75

–90

–105

–120

–135

30 6 9 1215182124 3027 33

FREQUENCY (MHz)

AMPLITUDE (dBFS)

08121-068

65MSPS

69MHz @ –1dBFS

SNR = 69.9dB (70.9dBFS)

SFDR = 92.0dBc

Figure 20. AD9231-65 Single-Tone FFT with fIN = 69 MHz

100

120

–70 –60 –50 –40 –30 –20 –10 0

SNR/SFDR (dBc AND dBFS)

INPUT AMPLITUDE (dBc)

SNR

SNRFS

SFDR

SFDRFS

08121-070

Figure 21. AD9231-65 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz

100

0 50 100 150 200

SNR/SFDR (dBFS/dBc)

INPUT FREQUENCY (MHz)

SNR

SFDR

08121-071

Figure 22. AD9231-65 SNR/SFDR vs. Input Frequency (AIN) with

2 V p-p Full Scale

AD9231

Rev. A | Page 15 of 36

AD9231-40

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS

disabled, unless otherwise noted.

–15

–30

–45

–60

–75

–90

–105

–120

–135

20 4 6 8 10 12 14 16 2018

FREQUENCY (MHz)

AMPLITUDE (dBFS)

08121-072

436

40MSPS

9.7MHz @ –1dBFS

SNR = 70.3dB (71.3dBFS)

SFDR = 93.8dBc

Figure 23. AD9231-40 Single-Tone FFT with fIN = 9.7 MHz

–15

–30

–45

–60

–75

–90

–105

–120

–135

20 4 6 8 10 12 14 16 2018

FREQUENCY (MHz)

AMPLITUDE (dBFS)

08121-073

40MSPS

30.6MHz @ –1dBFS

SNR = 70.2dB (71.2dBFS)

SFDR = 95.4dBc

Figure 24. AD9231-40 Single-Tone FFT with fIN = 30.6 MHz

100

120

–70 –60 –50 –40 –30 –20 –10 0

SNR/SFDR (dBc AND dBFS)

INPUT AMPLITUDE (dBc)

SNR

SNRFS

SFDR

SFDRFS

8121-074

Figure 25. AD9231-40 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz

AD9231

Rev. A | Page 16 of 36

AD9231-20

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS

disabled, unless otherwise noted.

–15

–30

–45

–60

–75

–90

–105

–120

–135

0.950 1.902.853.804.755.706.657.608.559.50

FREQUENCY (MHz)

AMPLITUDE (dBFS)

08121-075

20MSPS

9.7MHz @ –1dBFS

SNR = 70.3dB (71.3dBFS)

SFDR = 94.1dBc

Figure 26. AD9231-20 Single-Tone FFT with fIN = 9.7 MHz

–15

–30

–45

–60

–75

–90

–105

–120

–135

AMPLITUDE (dBFS)

08121-076

20MSPS

30.6MHz @ –1dBFS

SNR = 70.2dB (71.2dBFS)

SFDR = 94.6dBc

0.950 1.902.853.804.755.706.657.608.559.50

FREQUENCY (MHz)

Figure 27. AD9231-20 Single-Tone FFT with fIN = 30.6 MHz

100

120

–70 –60 –50 –40 –30 –20 –10 0

SNR/SFDR (dBc AND dBFS)

INPUT AMPLITUDE (dBc)

SNR

SNRFS

SFDR

SFDRFS

08121-077

Figure 28. AD9231-20 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz

AD9231

Rev. A | Page 17 of 36

EQUIVALENT CIRCUITS

VIN±x

08121-039

Figure 29. Equivalent Analog Input Circuit

CLK+

CLK–

0.9V

15kΩ

5Ω

15kΩ

08121-040

Figure 30. Equivalent Clock Input Circuit

30kΩ

DIO/DCS 350Ω

DRVDD

08121-041

Figure 31. Equivalent SDIO/DCS Input Circuit

08121-042

Figure 32. Equivalent Digital Output Circuit

350Ω

30kΩ

SCLK/DFS, SYNC,

OEB, AND PDWN

08121-043

Figure 33. Equivalent SCLK/DFS, SYNC, OEB, and PDWN Input Circuit

RBIAS

ND VCM

375Ω

08121-044

Figure 34. Equivalent RBIAS and VCM Circuit

AD9231

Rev. A | Page 18 of 36

30kΩ

CSB 350Ω

AVDD

08121-045

Figure 35. Equivalent CSB Input Circuit

ENSE 375Ω

08121-046

Figure 36. Equivalent SENSE Circuit

7.5kΩ

VREF 375Ω

08121-047

Figure 37. Equivalent VREF Circuit

AD9231

Rev. A | Page 19 of 36

THEORY OF OPERATION

The AD9231 dual ADC design can be used for diversity recep-

tion of signals, where the ADCs are operating identically on the

same carrier but from two separate antennae. The ADCs can

also be operated with independent analog inputs. The user can

sample any fS/2 frequency segment from dc to 200 MHz, using

appropriate low-pass or band-pass filtering at the ADC inputs

with little loss in ADC performance. Operation to 300 MHz

analog input is permitted but occurs at the expense of increased

ADC noise and distortion.

In nondiversity applications, the AD9231 can be used as a base-

band or direct downconversion receiver, where one ADC is

used for I input data and the other is used for Q input data.

Synchronization capability is provided to allow synchronized

timing between multiple channels or multiple devices.

Programming and control of the AD9231 is accomplished using

a 3-bit SPI-compatible serial interface.

ADC ARCHITECTURE

The AD9231 architecture consists of a multistage, pipelined ADC.

Each stage provides sufficient overlap to correct for flash errors

in the preceding stage. The quantized outputs from each stage are

combined into a final 12-bit result in the digital correction logic.

The pipelined architecture permits the first stage to operate with

a new input sample while the remaining stages operate with

preceding samples. Sampling occurs on the rising edge of

the clock.

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched-capacitor DAC

and an interstage residue amplifier (for example, a multiplying

digital-to-analog converter (MDAC)). The residue amplifier

magnifies the difference between the reconstructed DAC output

and the flash input for the next stage in the pipeline. One bit of

redundancy is used in each stage to facilitate digital correction

of flash errors. The last stage simply consists of a flash ADC.

The output staging block aligns the data, corrects errors, and

passes the data to the CMOS output buffers. The output buffers

are powered from a separate (DRVDD) supply, allowing adjust-

ment of the output voltage swing. During power-down, the

output buffers go into a high impedance state.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9231 is a differential switched-

capacitor circuit designed for processing differential input

signals. This circuit can support a wide common-mode range

while maintaining excellent performance. By using an input

common-mode voltage of midsupply, users can minimize

signal-dependent errors and achieve optimum performance.

PAR

SAMPLE

PAR

VIN–x

IN+x

08121-006

Figure 38. Switched-Capacitor Input Circuit

The clock signal alternately switches the input circuit between

sample-and-hold mode (see Figure 38). When the input circuit

is switched to sample mode, the signal source must be capable

of charging the sample capacitors and settling within one-half

of a clock cycle. A small resistor in series with each input can

help reduce the peak transient current injected from the output

stage of the driving source. In addition, low Q inductors or ferrite

beads can be placed on each leg of the input to reduce high

differential capacitance at the analog inputs and, therefore,

achieve the maximum bandwidth of the ADC. Such use of low

Q inductors or ferrite beads is required when driving the converter

front end at high IF frequencies. Either a shunt capacitor or two

single-ended capacitors can be placed on the inputs to provide a

matching passive network. This ultimately creates a low-pass

filter at the input to limit unwanted broadband noise. See the

AN-742 Application Note, the AN-827 Application Note, and the

Analog Dialogue article “Transformer-Coupled Front-End for

Wideband A/D Converters” (Volume 39, April 2005) for more

information. In general, the precise values depend on the

application.

AD9231

Rev. A | Page 20 of 36

Input Common Mode

The analog inputs of the AD9231 are not internally dc-biased.

Therefore, in ac-coupled applications, the user must provide a

dc bias externally. Setting the device so that VCM = AVDD/2 is

recommended for optimum performance, but the device can

function over a wider range with reasonable performance, as

shown in Figure 39 and Figure 40.

An on-board, common-mode voltage reference is included in

the design and is available from the VCM pin. The VCM pin

must be decoupled to ground by a 0.1 µF capacitor, as described

in the Applications Information section.

100

0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3

INPUT COMMON-MODE VOLTAGE (V)

SNR/SFDR (dBFS/dBc)

08121-149

SFDR (dBc)

SNR (dBFS)

Figure 39. SNR/SFDR vs. Input Common-Mode Voltage,

fIN = 32.1 MHz, fS = 80 MSPS

100

0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3

INPUT COMMON-MODE VOLTAGE (V)

SNR/SFDR (dBFS/dBc)

08121-150

SFDR (dBc)

SNR (dBFS)

Figure 40. SNR/SFDR vs. Input Common-Mode Voltage,

fIN = 10.3 MHz, fS = 20 MSPS

Differential Input Configurations

Optimum performance is achieved while driving the AD9231 in a

differential input configuration. For baseband applications, the

AD8138, ADA4937-2, and ADA4938-2 differential drivers provide

excellent performance and a flexible interface to the ADC.

The output common-mode voltage of the ADA4938-2 is easily

set with the VCM pin of the AD9231 (see Figure 41), and the

driver can be configured in a Sallen-Key filter topology to

provide band limiting of the input signal.

AVDD

VIN 76.8Ω

120Ω

0.1µF

33Ω

10pF

200Ω

90Ω

ADA4938

ADC

VIN–x

VIN+x VCM

08121-007

Figure 41. Differential Input Configuration Using the ADA4938-2

For baseband applications below ~10 MHz where SNR is a key

parameter, differential transformer-coupling is the recommended

input configuration. An example is shown in Figure 42. To bias

the analog input, the VCM voltage can be connected to the

center tap of the secondary winding of the transformer.

2V p-p 49.9Ω

0.1µF

ADC

VCM

VIN+x

VIN–x

08121-008

Figure 42. Differential Transformer-Coupled Configuration

The signal characteristics must be considered when selecting

a transformer. Most RF transformers saturate at frequencies

below a few megahertz (MHz). Excessive signal power can also

cause core saturation, which leads to distortion.

At input frequencies in the second Nyquist zone and above, the

noise performance of most amplifiers is not adequate to achieve

the true SNR performance of the AD9231. For applications above

~10 MHz where SNR is a key parameter, differential double balun

coupling is the recommended input configuration (see Figure 44).

An alternative to using a transformer-coupled input at frequencies

in the second Nyquist zone is to use the AD8352 differential driver.

An example is shown in Figure 45. See the AD8352 data sheet

for more information.

In any configuration, the value of Shunt Capacitor C is dependent

on the input frequency and source impedance and may need to

be reduced or removed. Tabl e 9 displays the suggested values to set

the RC network. However, these values are dependent on the

input signal and should be used only as a starting guide.

Table 9. Example RC Network

Frequency Range (MHz)

R Series

(Ω Each) C Differential (pF)

0 to 70 33 22

70 to 200 125 Open

AD9231

Rev. A | Page 21 of 36

1V p-p

49.9Ω0.1µF

10µF

10µF 0.1µF

AVDD

1kΩ

ADC

VIN+x

VIN–x

08121-009

Single-Ended Input Configuration

A single-ended input can provide adequate performance in

cost-sensitive applications. In this configuration, SFDR and

distortion performance degrade due to the large input common-

mode swing. If the source impedances on each input are matched,

there should be little effect on SNR performance. Figure 43

shows a typical single-ended input configuration.

Figure 43. Single-Ended Input Configuration

ADC

R0.1µ

0.1µF

V p-

VCM

0.1µF

25Ω

VIN+x

VIN–x

08121-010

Figure 44. Differential Double Balun Input Configuration

AD8352

0Ω

CDRDRG

0.1µF

8, 13

200Ω

ANALOG INPUT

ADC

VCM

VIN+x

VIN–x

08121-011

Figure 45. Differential Input Configuration Using the AD8352

AD9231

Rev. A | Page 22 of 36

VOLTAGE REFERENCE

A stable and accurate 1.0 V voltage reference is built into the

AD9231. The VREF can be configured using either the internal

1.0 V reference or an externally applied 1.0 V reference voltage.

The various reference modes are summarized in the sections

that follow. The Reference Decoupling section describes the

best practices PCB layout of the reference.

Internal Reference Connection

A comparator within the AD9231 detects the potential at the

SENSE pin and configures the reference into two possible modes,

which are summarized in Table 10. If SENSE is grounded, the

reference amplifier switch is connected to the internal resistor

divider (see Figure 46), setting VREF to 1.0 V.

VREF

SENSE

0.5V

ADC

SELECT

LOGIC

0.1µF1.0µF

VIN–A/VIN–B

VIN+A/VIN+B

ADC

CORE

08121-012

Figure 46. Internal Reference Configuration

If the internal reference of the AD9231 is used to drive multiple

converters to improve gain matching, the loading of the reference

by the other converters must be considered. Figure 47 shows

how the internal reference voltage is affected by loading.

–3.0

LOAD CURRENT (mA)

REFERENCE VOLTAGE ERROR (%)

–0.5

–1.0

–1.5

–2.0

–2.5

0.2 0.4 0.6 0.8 1.0 1.4 1.6 1.81.2

INTERNAL VREF = 0.993V

08121-014

Figure 47. VREF Accuracy vs. Load Current

Table 10. Reference Configuration Summary

Selected Mode SENSE Voltage (V) Resulting VREF (V) Resulting Differential Span (V p-p)

Fixed Internal Reference AGND to 0.2 1.0 internal 2.0

Fixed External Reference AVDD 1.0 applied to external VREF pin 2.0

AD9231

Rev. A | Page 23 of 36

External Reference Operation

The use of an external reference may be necessary to enhance

the gain accuracy of the ADC or improve thermal drift charac-

teristics. Figure 48 shows the typical drift characteristics of the

internal reference in 1.0 V mode.

–1

–2

–3

–4

–5

–6

–40 –20 0 20 40 60 80

TEMPERATURE (°C)

REF

ERROR (mV)

VREF ERROR (mV)

8121-052

Figure 48. Typical VREF Drift

When the SENSE pin is tied to AVDD, the internal reference is

disabled, allowing the use of an external reference. An internal

reference buffer loads the external reference with an equivalent

7.5 kΩ load (see Figure 37). The internal buffer generates the

positive and negative full-scale references for the ADC core.

Therefore, the external reference must be limited to a maximum

of 1.0 V.

CLOCK INPUT CONSIDERATIONS

For optimum performance, clock the AD9231 sample clock

inputs, CLK+ and CLK−, with a differential signal. The signal

is typically ac-coupled into the CLK+ and CLK− pins via a

transformer or capacitors. These pins are biased internally

(see Figure 49) and require no external bias.

0.9V

AVDD

2pF 2pF

CLK–CLK+

08121-016

Figure 49. Equivalent Clock Input Circuit

Clock Input Options

The AD9231 has a very flexible clock input structure. The clock

input can be a CMOS, LVDS, LVPECL, or sine wave signal.

Regardless of the type of signal being used, clock source jitter

is of the most concern, as described in the Jitter Considerations

section.

Figure 50 and Figure 51 show two preferred methods for clock-

ing the AD9231 (at clock rates up to 625 MHz). A low jitter clock

source is converted from a single-ended signal to a differential

signal using either an RF transformer or an RF balun.

The RF balun configuration is recommended for clock frequencies

between 125 MHz and 625 MHz, and the RF transformer is recom-

mended for clock frequencies from 10 MHz to 200 MHz. The

back-to-back Schottky diodes across the transformer/balun

secondary limit clock excursions into the AD9231 to approx-

imately 0.8 V p-p differential.

This limit helps prevent the large voltage swings of the clock

from feeding through to other portions of the AD9231 while

preserving the fast rise and fall times of the signal that are

critical to a low jitter performance.

0.1µF

0.1µF0.1µF

SCHOTTKY

DIODES:

HSMS2822

CLOCK

INPUT 50Ω100Ω

CLK–

CLK+

ADC

Mini-Circuits

ADT1-1WT, 1:1 Z

XFMR

08121-017

Figure 50. Transformer-Coupled Differential Clock (Up to 200 MHz)

0.1µF

0.1µF1nF

CLOCK

INPUT

1nF

50Ω

CLK–

CLK+

SCHOTTKY

DIODES:

HSMS2822

ADC

08121-018

Figure 51. Balun-Coupled Differential Clock (Up to 625 MHz)

AD9231

Rev. A | Page 24 of 36

If a low jitter clock source is not available, another option is to

ac couple a differential PECL signal to the sample clock input

pins, as shown in Figure 52. The AD9510/AD9511/AD9512/

AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer

excellent jitter performance.

100Ω

0.1µF

240Ω240Ω

50kΩ50kΩ

CLK–

CLK+

CLOCK

INPUT

CLOCK

INPUT

ADC

AD951x

PECL DRIVER

08121-019

Figure 52. Differential PECL Sample Clock (Up to 625 MHz)

A third option is to ac couple a differential LVDS signal to the

sample clock input pins, as shown in Figure 53. The AD9510/

AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517

clock drivers offer excellent jitter performance.

100Ω

0.1µF

50kΩ50kΩ

CLK–

CLK+

ADC

CLOCK

INPUT

CLOCK

INPUT

AD951x

LVDS DRIVER

08121-020

Figure 53. Differential LVDS Sample Clock (Up to 625 MHz)

In some applications, it may be acceptable to drive the sample

clock inputs with a single-ended 1.8 V CMOS signal. In such

applications, drive the CLK+ pin directly from a CMOS gate, and

bypass the CLK− pin to ground with a 0.1 F capacitor (see

Figure 54).

OPTIONAL

100Ω0.1µF

0.1µF

50Ω

50Ω RESISTOR IS OPTIONAL.

CLK–

CLK+

ADC

1kΩ

LOCK

INPUT

AD951x

CMOS DRIVER

08121-021

Figure 54. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)

Input Clock Divider

The AD9231 contains an input clock divider with the ability

to divide the input clock by integer values between 1 and 8.

Optimum performance is obtained by enabling the internal

duty cycle stabilizer (DCS) when using divide ratios other

than 1, 2, or 4.

The AD9231 clock divider can be synchronized using the

external SYNC input. Bit 1 and Bit 2 of Register 0x100 allow

the clock divider to be resynchronized on every SYNC signal

or only on the first SYNC signal after the register is written. A

valid SYNC causes the clock divider to reset to its initial state.

This synchronization feature allows multiple parts to have

their clock dividers aligned to guarantee simultaneous input

sampling.

Clock Duty Cycle

Typical high speed ADCs use both clock edges to generate

a variety of internal timing signals and, as a result, may be

sensitive to clock duty cycle. Commonly, a ±5% tolerance is

required on the clock duty cycle to maintain dynamic

performance characteristics.

The AD9231 contains a duty cycle stabilizer (DCS) that retimes

the nonsampling (falling) edge, providing an internal clock

signal with a nominal 50% duty cycle. This allows the user to

provide a wide range of clock input duty cycles without affecting

the performance of the AD9231. Noise and distortion perform-

ance are nearly flat for a wide range of duty cycles with the DCS

on, as shown in Figure 55.

Jitter in the rising edge of the input is still of concern and is not

easily reduced by the internal stabilization circuit. The duty

cycle control loop does not function for clock rates less than

20 MHz nominally. The loop has a time constant associated

with it that must be considered in applications in which the

clock rate can change dynamically. A wait time of 1.5 µs to 5 µs

is required after a dynamic clock frequency increase or decrease

before the DCS loop is relocked to the input signal.

10 20 30 40 50 60 70 80

SNR (dBFS)

POSITIVE DUTY CYCLE (%)

DCS OFF

DCS ON

08121-078

Figure 55. SNR vs. DCS On/Off

AD9231

Rev. A | Page 25 of 36

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality

of the clock input. The degradation in SNR from the low fre-

quency SNR (SNRLF) at a given input frequency (fINPUT) due to

jitter (tJRMS) can be calculated by

SNRHF = −10 log[(2π × fINPUT × tJRMS)2 + 10 ]

)10/( LF

SNR−

In the previous equation, the rms aperture jitter represents the

clock input jitter specification. IF undersampling applications

are particularly sensitive to jitter, as illustrated in Figure 56.

1 10 100 1k

FREQUENCY (MHz)

SNR (dBFS)

0.5ps

0.2ps

0.05ps

1.0ps

1.5ps

2.0ps

2.5ps

3.0ps

08121-022

Figure 56. SNR vs. Input Frequency and Jitter

The clock input should be treated as an analog signal in cases in

which aperture jitter may affect the dynamic range of the AD9231.

To avoid modulating the clock signal with digital noise, keep

power supplies for clock drivers separate from the ADC output

driver supplies. Low jitter, crystal-controlled oscillators make the

best clock sources. If the clock is generated from another type of

source (by gating, dividing, or another method), it should be

retimed by the original clock at the last step.

For more information, see the AN-501 Application Note and the

AN-756 Application Note available on www.analog.com.

CHANNEL/CHIP SYNCHRONIZATION

The AD9231 has a SYNC input that offers the user flexible

synchronization options for synchronizing sample clocks

across multiple ADCs. The input clock divider can be enabled

to synchronize on a single occurrence of the SYNC signal or on

every occurrence. The SYNC input is internally synchronized

to the sample clock; however, to ensure there is no timing

uncertainty between multiple parts, the SYNC input signal should

be externally synchronized to the input clock signal, meeting the

setup and hold times shown in Table 5. Drive the SYNC input

using a single-ended CMOS-type signal.

POWER DISSIPATION AND STANDBY MODE

As shown in Figure 57, the analog core power dissipated by

the AD9231 is proportional to its sample rate. The digital

power dissipation of the CMOS outputs are determined

primarily by the strength of the digital drivers and the load

on each output bit.

The maximum DRVDD current (IDRVDD) can be calculated as

IDRVDD = VDRVDD × CLOAD × fCLK × N

where N is the number of output bits (26, in the case of the

AD9231).

This maximum current occurs when every output bit switches

on every clock cycle, that is, a full-scale square wave at the Nyquist

frequency of fCLK/2. In practice, the DRVDD current is estab-

lished by the average number of output bits switching, which

is determined by the sample rate and the characteristics of the

analog input signal.

Reducing the capacitive load presented to the output drivers can

minimize digital power consumption. The data in Figure 57 was

taken using the same operating conditions as those used for the

Typical Performance Characteristics, with a 5 pF load on each

output driver.

110

130

150

0 102030405060708

ANALOG CORE POWER (mW)

CLOCK RATE (MSPS)

AD9231-20

AD9231-40

AD9231-65

AD9231-80

08121-079

Figure 57. Analog Core Power vs. Clock Rate

AD9231

Rev. A | Page 26 of 36

The AD9231 is placed in power-down mode either by the SPI

port or by asserting the PDWN pin high. In this state, the ADC

typically dissipates 2.2 mW. During power-down, the output

drivers are placed in a high impedance state. Asserting the

PDWN pin low returns the AD9231 to its normal operating

mode. Note that PDWN is referenced to the digital output

driver supply (DRVDD) and should not exceed that supply

voltage.

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. Internal capacitors are discharged when entering power-

down mode and then must be recharged when returning to normal

operation. As a result, wake-up time is related to the time spent

in power-down mode, and shorter power-down cycles result in

proportionally shorter wake-up times.

When using the SPI port interface, the user can place the ADC

in power-down mode or standby mode. Standby mode allows

the user to keep the internal reference circuitry powered when

faster wake-up times are required. See the Memory Map section

for more details.

DIGITAL OUTPUTS

The AD9231 output drivers can be configured to interface with

1.8 V to 3.3 V CMOS logic families. Output data can also be

multiplexed onto a single output bus to reduce the total number

of traces required.

The CMOS output drivers are sized to provide sufficient output

current to drive a wide variety of logic families. However, large

drive currents tend to cause current glitches on the supplies

and may affect converter performance.

Applications requiring the ADC to drive large capacitive loads

or large fanouts may require external buffers or latches.

The output data format can be selected to be either offset binary

or twos complement by setting the SCLK/DFS pin when operating

in the external pin mode (see Table 11).

As detailed in the AN-877 Application Note, Interfacing to High

Speed ADCs via SPI, the data format can be selected for offset

binary, twos complement, or gray code when using the SPI control.

Table 11. SCLK/DFS Mode Selection (External Pin Mode)

Voltage at Pin SCLK/DFS SDIO/DCS

AGND Offset binary (default) DCS disabled(default)

DRVDD Twos complement DCS enabled

Digital Output Enable Function (OEB)

The AD9231 has a flexible three-state ability for the digital

output pins. The three-state mode is enabled using the OEB pin

or through the SPI interface. If the OEB pin is low, the output

data drivers and DCOs are enabled. If the OEB pin is high, the

output data drivers and DCOs are placed in a high impedance

state. This OEB function is not intended for rapid access to the

data bus. Note that OEB is referenced to the digital output

driver supply (DRVDD) and should not exceed that supply

voltage.

When using the SPI interface, the data outputs and DCO of

each channel can be independently three-stated by using the

output disable (OEB) bit (Bit 4) in Register 0x14.

TIMING

The AD9231 provides latched data with a pipeline delay of

9 clock cycles. Data outputs are available one propagation

delay (tPD) after the rising edge of the clock signal.

Minimize the length of the output data lines and loads placed

on them to reduce transients within the AD9231. These

transients can degrade converter dynamic performance.

The lowest typical conversion rate of the AD9231 is 3 MSPS. At

clock rates below 3 MSPS, dynamic performance can degrade.

Data Clock Output (DCO)

The AD9231 provides two data clock output (DCO) signals

intended for capturing the data in an external register. The CMOS

data outputs are valid on the rising edge of DCO, unless the DCO

clock polarity has been changed via the SPI. See Figure 2 and

Figure 3 for a graphical timing description.

Table 12. Output Data Format

Input (V) Condition (V) Offset Binary Output Mode Twos Complement Mode OR

VIN+ − VIN− < −VREF − 0.5 LSB 0000 0000 0000 1000 0000 0000 1

VIN+ − VIN− = −VREF 0000 0000 0000 1000 0000 0000 0

VIN+ − VIN− = 0 1000 0000 0000 0000 0000 0000 0

VIN+ − VIN− = +VREF − 1.0 LSB 1111 1111 1111 0111 1111 1111 0

VIN+ − VIN− > +VREF − 0.5 LSB 1111 1111 1111 0111 1111 1111 1

AD9231

Rev. A | Page 27 of 36

BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST

The AD9231 includes a built-in self-test feature designed to

enable verification of the integrity of each channel as well as to

facilitate board level debugging. A built-in self-test (BIST) feature

that verifies the integrity of the digital datapath of the AD9231

is included. Various output test options are also provided to place

predictable values on the outputs of the AD9231.

BUILT-IN SELF-TEST (BIST)

The BIST is a thorough test of the digital portion of the selected

AD9231 signal path. Perform the BIST test after a reset to ensure

the part is in a known state. During BIST, data from an internal

pseudorandom noise (PN) source is driven through the digital

datapath of both channels, starting at the ADC block output.

At the datapath output, CRC logic calculates a signature from

the data. The BIST sequence runs for 512 cycles and then stops.

Once completed, the BIST compares the signature results with a

pre-determined value. If the signatures match, the BIST sets Bit 0

of Register 0x24, signifying the test passed. If the BIST test failed,

Bit 0 of Register 0x24 is cleared. The outputs are connected

during this test, so the PN sequence can be observed as it runs.

Writing the value 0x05 to Register 0x0E runs the BIST. This enables

the Bit 0 (BIST enable) of Register 0x0E and resets the PN sequence

generator, Bit 2 (BIST INIT) of Register 0x0E. At the completion of

the BIST, Bit 0 of Register 0x24 is automatically cleared. The PN

sequence can be continued from its last value by writing a 0 in

Bit 2 of Register 0x0E. However, if the PN sequence is not reset,

the signature calculation does not equal the predetermined

value at the end of the test. At that point, the user needs to rely

on verifying the output data.

OUTPUT TEST MODES

The output test options are described in Table 1 6 at Address

0x0D. When an output test mode is enabled, the analog section

of the ADC is disconnected from the digital back-end blocks

and the test pattern is run through the output formatting block.

Some of the test patterns are subject to output formatting, and

some are not. The PN generators from the PN sequence tests

can be reset by setting Bit 4 or Bit 5 of Register 0x0D. These

tests can be performed with or without an analog signal (if

present, the analog signal is ignored), but they do require

an encode clock. For more information, see the AN-877

Application Note, Interfacing to High Speed ADCs via SPI.

AD9231

Rev. A | Page 28 of 36

SERIAL PORT INTERFACE (SPI)

The AD9231 serial port interface (SPI) allows the user to configure

the converter for specific functions or operations through a

structured register space provided inside the ADC. The SPI

gives the user added flexibility and customization, depending

on the application. Addresses are accessed via the serial port

and can be written to or read from via the port. Memory is

organized into bytes that can be further divided into fields,

which are documented in the Memory Map section. For

detailed operational information, see the AN-877 Application

Note, Interfacing to High Speed ADCs via SPI.

CONFIGURATION USING THE SPI

Three pins define the SPI of this ADC: the SCLK, the SDIO,

and the CSB (see Table 13). The SCLK (a serial clock) is used

to synchronize the read and write data presented from and to

the ADC. The SDIO (serial data input/output) is a dual-purpose

pin that allows data to be sent and read from the internal ADC

memory map registers. The CSB (chip select bar) is an active-

low control that enables or disables the read and write cycles.

Table 13. Serial Port Interface Pins

Pin Function

SCLK Serial Clock. The serial shift clock input, which is used to

synchronize serial interface reads and writes.

SDIO Serial Data Input/Output. A dual-purpose pin that

typically serves as an input or an output, depending on

the instruction being sent and the relative position in the

timing frame.

CSB Chip Select Bar. An active-low control that gates the read

and write cycles.

The falling edge of CSB, in conjunction with the rising edge of

SCLK, determines the start of the framing. An example of the

serial timing and its definitions can be found in Figure 58 and

Tabl e 5.

Other modes involving the CSB are available. The CSB can be

held low indefinitely, which permanently enables the device;

this is called streaming. The CSB can stall high between bytes to

allow for additional external timing. When CSB is tied high, SPI

functions are placed in high impedance mode. This mode turns

on any SPI pin secondary functions.

During an instruction phase, a 16-bit instruction is transmitted.

Data follows the instruction phase, and its length is determined

by the W0 and W1 bits as shown in Figure 58.

All data is composed of 8-bit words. The first bit of the first byte

in a multibyte serial data transfer frame indicates whether a read

command or a write command is issued. This allows the serial

data input/output (SDIO) pin to change direction from an input

to an output at the appropriate point in the serial frame.

In addition to word length, the instruction phase determines

whether the serial frame is a read or write operation, allowing

the serial port to be used both to program the chip and to read

the contents of the on-chip memory. If the instruction is a readback

operation, performing a readback causes the serial data input/

output (SDIO) pin to change direction from an input to an output

at the appropriate point in the serial frame.

Data can be sent in MSB-first mode or in LSB-first mode. MSB

first is the default on power-up and can be changed via the SPI

port configuration register. For more information about this

and other features, see the AN-877 Application Note, Interfacing

to High Speed ADCs via SPI.

DON’T CARE

DON’T CAREDON’T CARE

DON’T CARE

SDIO

SCLK

CSB

CLK

R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0

LOW

HIGH

08121-023

Figure 58. Serial Port Interface Timing Diagram

AD9231

Rev. A | Page 29 of 36

HARDWARE INTERFACE

The pins described in Table 13 constitute the physical interface

between the programming device of the user and the serial port

of the AD9231. The SCLK pin and the CSB pin function as inputs

when using the SPI interface. The SDIO pin is bidirectional,

functioning as an input during write phases and as an output

during readback.

The SPI interface is flexible enough to be controlled by

either FPGAs or microcontrollers. One method for SPI

configuration is described in detail in the AN-812 Appli-

cation Note, Microcontroller-Based Serial Port Interface

(SPI) Boot Circuit.

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Because the

SCLK signal, the CSB signal, and the SDIO signal are typically

asynchronous to the ADC clock, noise from these signals can

degrade converter performance. If the on-board SPI bus is used

for other devices, it may be necessary to provide buffers between

this bus and the AD9231 to prevent these signals from transi-

tioning at the converter inputs during critical sampling periods.

SDIO/DCS and SCLK/DFS serve a dual function when the

SPI interface is not being used. When the pins are strapped to

DRVDD or ground during device power-on, they are associated

with a specific function. The Digital Outputs section describes

the strappable functions supported on the AD9231.

CONFIGURATION WITHOUT THE SPI

In applications that do not interface to the SPI control registers,

the SDIO/DCS pin, the SCLK/DFS pin, the OEB pin, and the

PDWN pin serve as standalone CMOS-compatible control

pins. When the device is powered up, it is assumed that the

user intends to use the pins as static control lines for the duty

cycle stabilizer, output data format, output enable, and power-

down feature control. In this mode, connect the CSB chip select

to DRVDD, which disables the serial port interface.

Table 14. Mode Selection

External

Voltage Configuration

DRVDD Duty cycle stabilizer enabled SDIO/DCS

AGND(default) Duty cycle stabilizer disabled

DRVDD Twos complement enabled SCLK/DFS

AGND (default) Offset binary enabled

DRVDD Outputs in high impedance OEB

AGND (default) Outputs enabled

DRVDD Chip in power-down or standby PDWN

AGND (default) Normal operation

SPI ACCESSIBLE FEATURES

Tabl e 15 provides a brief description of the general features that

are accessible via the SPI. These features are described in detail

in the AN-877 Application Note, Interfacing to High Speed ADCs

via SPI. The AD9231 part-specific features are described in

detail in Table 16.

Table 15. Features Accessible Using the SPI

Feature Description

Mode Allows the user to set either power-down mode

or standby mode

Clock Allows the user to access the DCS via the SPI

Offset Allows the user to digitally adjust the

converter offset

Test I/O Allows the user to set test modes to have known

data on output bits

Output Mode Allows the user to set up outputs

Output Phase Allows the user to set the output clock polarity

Output Delay Allows the user to vary the DCO delay

AD9231

Rev. A | Page 30 of 36

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

Each row in the memory map register table (see Table 16) has

eight bit locations. The memory map is roughly divided into

four sections: the chip configuration registers (Address 0x00

to Address 0x02); the device index and transfer registers

(Address 0x05 and Address 0xFF); the program registers,

including setup, control, and test (Address 0x08 to Address

0x2E); and the digital feature control registers (Address 0x100

and Address 0x101).

Tabl e 16 documents the default hexadecimal value for each

hexadecimal address shown. The column with the heading Bit 7

(MSB) is the start of the default hexadecimal value given. For

example, Address 0x05, the channel index register, has a hexade-

cimal default value of 0x03. This means that in Address 0x05

Bit[7:2] = 0, and the remaining Bits[1:0] = 1. This setting is the

default channel index setting. The default value results in both

ADC channels receiving the next write command. For more

information on this function and others, see the AN-877

Application Note, Interfacing to High Speed ADCs via SPI. This

application note details the functions controlled by Register 0x00

to Register 0xFF. The remaining registers, Register 0x100 and

Descriptions section following Table 16.

OPEN LOCATIONS

All address and bit locations that are not included in the SPI

map are not currently supported for this device. Unused bits of

a valid address location should be written with 0s. Writing to these

locations is required only when part of an address location is

open (for example, Address 0x05). If the entire address location

is open, it is omitted from the SPI map (for example, Address 0x13)

and should not be written.

DEFAULT VALUES

After the AD9231 is reset, critical registers are loaded with

default values. The default values for the registers are given

in the memory map register table (see Tabl e 16).

Logic Levels

An explanation of logic level terminology follows:

• “Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

• “Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

Transfer Register Map

Address 0x08 to Address 0x18 are shadowed. Writes to these

addresses do not affect part operation until a transfer command

is issued by writing 0x01 to Address 0xFF, setting the transfer bit.

This allows these registers to be updated internally and simulta-

neously when the transfer bit is set. The internal update takes

place when the transfer bit is set, and then the bit autoclears.

Channel-Specific Registers

Some channel setup functions can be programmed differently

for each channel. In these cases, channel address locations are

internally duplicated for each channel. These registers and bits

are designated in the memory map register table as local. These

local registers and bits can be accessed by setting the appropriate

Channel A (Bit 0) or Channel B (Bit 1) bits in Register 0x05.

If both bits are set, the subsequent write affects the registers of

both channels. In a read cycle, set only Channel A or Channel B

to read one of the two registers. If both bits are set during an

SPI read cycle, the part returns the value for Channel A.

Registers and bits designated as global in the memory map

which independent settings are not allowed between channels.

The settings in Register 0x05 do not affect the global registers

and bits.

AD9231

Rev. A | Page 31 of 36

MEMORY MAP REGISTER TABLE

All address and bit locations that are not included in Table 16 are not currently supported for this device.

Table 16.

Addr

(Hex)

Name

Bit 7

(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Bit 0

(LSB)

Default

Value

(Hex) Comments

Chip Configuration Registers

0x00 SPI port

configuration

(global)

0 LSB

first

Soft reset 1 1 Soft

reset

LSB

first

0 0x18 The nibbles are

mirrored so that

LSB- or MSB-first

mode registers

correctly, regardless

of shift mode

0x01 Chip ID (global) 8-bit chip ID bits [7:0]

AD9231 = 0x24

Unique chip ID used

to differentiate

devices; read only

0x02 Chip grade

(global)

Open Speed grade ID [6:4]

20 MSPS = 000

40 MSPS = 001

65 MSPS = 010

80 MSPS = 011

Open Unique speed

grade ID used to

differentiate

devices; read only

Device Index and Transfer Registers

0x05 Channel index Open Open Open Open Open Open ADC B

default

ADC A

default

0x03 Bits are set to

determine which

device on chip

receives the next

write command;

the default is all

devices on chip

0xFF Transfer Open Open Open Open Open Open Open Transfer 0x00 Synchronously

transfers data from

the master shift

Program Registers (May or May Not Be Indexed by Device Index)

0x08 Modes External

power-

down

enable

(local)

External pin function

0x00 full power-down

0x01 standby

(local)

Open Open 00 = chip run

01 = full power-

down

10 = standby

11 = chip wide

digital reset (local)

0x80 Determines various

generic modes of

chip operation

0x09 Clock (global) Open Open Open Open Open Duty

cycle

stabilize

0x00

0x0B Clock divide

(global)

Open Clock divider [2:0]

Clock divide ratio

000 = divide by 1

001 = divide by 2

010 = divide by 3

011 = divide by 4

100 = divide by 5

101 = divide by 6

110 = divide by 7

111 = divide by 8

0x00 The divide ratio is

the value plus 1

0x0D Test mode (local) User test mode

(local)

00 = single

01 = alternate

10 = single once

11 = alternate

once

Reset PN

long gen

Reset

short

gen

Output test mode [3:0] (local)

0000 = off (default)

0001 = midscale short

0010 = positive FS

0011 = negative FS

0100 = alternating checkerboard

0101 = PN 23 sequence

0110 = PN 9 sequence

0111 = one/zero word toggle

1000 = user input

1001 = 1-/0-bit toggle

1010 = 1x sync

1011 = one bit high

1100 = mixed bit frequency

0x00 When set, the test

data is placed on

the output pins in

place of normal

data

AD9231

Rev. A | Page 32 of 36

Addr

(Hex)

Name

Bit 7

(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Bit 0

(LSB)

Default

Value

(Hex) Comments

0x0E BIST enable Open Open Open Open Open BIST

INIT

Open BIST

enable

0x00 When Bit 0 is set,

the BIST function is

initiated

0x10 Offset adjust

(local)

8-bit device offset adjustment [7:0] (local)

Offset adjust in LSBs from +127 to −128 (twos complement format)

0x00 Device offset trim

0x14 Output mode 00 = 3.3 V CMOS

10 = 1.8 V CMOS

Output mux

enable

(interleaved)

Output

disable

(local)

Open Output

invert

(local)

00 = offset binary

01 = twos

complement

10 = gray code

11 = offset binary

(local)

0x00 Configures the

outputs and the

format of the data

0x15 OUTPUT_ADJUST 3.3 V DCO

drive strength

00 = 1 stripe

(default)

01 = 2 stripes

10 = 3 stripes

11 = 4 stripes

1.8 V DCO

drive strength

00 = 1 stripe

01 = 2 stripes

10 = 3 stripes (default)

11 = 4 stripes

3.3 V data

drive strength

00 = 1 stripe

(default)

01 = 2 stripes

10 = 3 stripes

11 = 4 stripes

1.8 V data

drive strength

00 = 1 stripe

01 = 2 stripes

10 = 3 stripes

(default)

11 = 4 stripes

0x22 Determines

CMOS output drive

strength properties

0x16 OUTPUT_PHASE DCO

output

polarity

0 =

normal

1 =

inverted

(local)

Open Open Open Open Input clock phase adjust [2:0]

(Value is number of input clock

cycles of phase delay)

000 = no delay

001 = 1 input clock cycle

010 = 2 input clock cycles

011 = 3 input clock cycles

100 = 4 input clock cycles

101 = 5 input clock cycles

110 = 6 input clock cycles

111 = 7 input clock cycles

0x00 On devices that

utilize global clock

divide, this register

determines which

phase of the divider

output is used to

supply the output

clock; internal

latching is

unaffected

0x17 OUTPUT_DELAY Enable

DCO

delay

Open Enable

data

delay

Open Open

DCO/Data delay[2:0]

000 = 0.56 ns

001 = 1.12 ns

010 = 1.68 ns

011 = 2.24 ns

100 = 2.80 ns

101 = 3.36 ns

110 = 3.92 ns

111 = 4.48 ns

0x00 This sets the fine

output delay of the

output clock but

does not change

internal timing

0x19 USER_PATT1_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined

pattern, 1 LSB

0x1A USER_PATT1_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined

pattern, 1 MSB

0x1B USER_PATT2_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined

pattern, 2 LSB

0x1C USER_PATT2_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined

pattern, 2 MSB

0x24 BIST signature LSB BIST signature [7:0] 0x00 Least significant

byte of BIST

signature, read only

0x2A Features Open Open Open Open Open Open Open OR OE

(local)

0x01 Disable the OR pin

for the indexed

channel

0x2E Output assign Open Open Open Open Open Open Open 0 =

ADC A

1 =

ADC B

(local)

Ch A =

0x00

Ch B =

0x01

Assign an ADC to an

output channel

AD9231

Rev. A | Page 33 of 36

Addr

(Hex)

Name

Bit 7

(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Bit 0

(LSB)

Default

Value

(Hex) Comments

Digital Feature Control

0x100 Sync control

(global)

Open Open Open Open Open Clock

divider

sync

only

Clock

divider

sync

enable

Master

sync

enable

0x01

0x101 USR2 Enable

OEB

Pin 47

(local)

Open Open Open Enable

GCLK

detect

Run

GCLK

Open Disable

SDIO

pull-

down

0x88 Enables internal

oscillator for clock

rates < 5 MHz

MEMORY MAP REGISTER DESCRIPTIONS

For additional information about functions controlled in

Note, Interfacing to High Speed ADCs via SPI.

Sync Control (Register 0x100)

Bits[7:3]—Reserved

Bit 2—Clock Divider Next Sync Only

If the master sync enable bit (Address 0x100, Bit 0) and the

clock divider sync enable bit (Address 0x100, Bit 1) are high,

Bit 2 allows the clock divider to sync to the first sync pulse it

receives and to ignore the rest. The clock divider sync enable

bit (Address 0x100, Bit 1) resets after it syncs.

Bit 1—Clock Divider Sync Enable

Bit 1 gates the sync pulse to the clock divider. The sync signal

is enabled when Bit 1 and Bit 0 are high and the device is

operating in continuous sync mode as long as Bit 2 of the

sync control is low.

Bit 0—Master Sync Enable

Bit 0 must be high to enable any of the sync functions.

USR2 (Register 0x101)

Bit 7—Enable OEB Pin 47

Normally set high, this bit allows Pin 47 to function as the

output enable. If it is set low, it disables Pin 47.

Bit 3—Enable GCLK Detect

Normally set high, this bit enables a circuit that detects encode

rates below about 5 MSPS. When a low encode rate is detected

an internal oscillator, GCLK, is enabled ensuring the proper

operation of several circuits. If set low the detector is disabled.

Bit 2—Run GCLK

This bit enables the GCLK oscillator. For some applications

with encode rates below 10 MSPS, it may be preferable to set

this bit high to supersede the GCLK detector.

Bit 0—Disable SDIO Pull-Down

This bit can be set high to disable the internal 30 k pull-down

on the SDIO pin, which can be used to limit the loading when

many devices are connected to the SPI bus.

AD9231

Rev. A | Page 34 of 36

APPLICATIONS INFORMATION

DESIGN GUIDELINES

Before starting design and layout of the AD9231 as a system,

it is recommended that the designer become familiar with these

guidelines, which discuss the special circuit connections and

layout requirements needed for certain pins.

Power and Ground Recommendations

When connecting power to the AD9231, it is strongly

recommended that two separate supplies be used. Use one 1.8 V

supply for analog (AVDD); use a separate 1.8 V to 3.3 V supply for

the digital output supply (DRVDD). If a common 1.8 V AVDD

and DRVDD supply must be used, the AVDD and DRVDD

domains must be isolated with a ferrite bead or filter choke and

separate decoupling capacitors. Several different decoupling

capacitors can be used to cover both high and low frequencies.

Locate these capacitors close to the point of entry at the PCB

level and close to the pins of the part, with minimal trace length.

A single PCB ground plane should be sufficient when using the

AD9231. With proper decoupling and smart partitioning of the

PCB analog, digital, and clock sections, optimum performance

is easily achieved.

Exposed Paddle Thermal Heat Sink Recommendations

The exposed paddle (Pin 0) is the only ground connection for

the AD9231; therefore, it must be connected to analog ground

(AGND) on the customer’s PCB. To achieve the best electrical

and thermal performance, mate an exposed (no solder mask)

continuous copper plane on the PCB to the AD9231 exposed

paddle, Pin 0.

The copper plane should have several vias to achieve the

lowest possible resistive thermal path for heat dissipation to

flow through the bottom of the PCB. Fill or plug these vias

with nonconductive epoxy.

To maximize the coverage and adhesion between the ADC and

the PCB, a silkscreen should be overlaid to partition the continuous

plane on the PCB into several uniform sections. This provides

several tie points between the ADC and the PCB during the reflow

process. Using one continuous plane with no partitions guarantees

only one tie point between the ADC and the PCB. For detailed

information about packaging and PCB layout of chip scale

packages, see the AN-772 Application Note, A Design and

Manufacturing Guide for the Lead Frame Chip Scale Package

(LFCSP), at www.analog.com.

VCM

The VCM pin should be decoupled to ground with a 0.1 F

capacitor, as shown in Figure 42.

RBIAS

The AD9231 requires that a 10 kΩ resistor be placed between

the RBIAS pin and ground. This resistor sets the master current

reference of the ADC core and should have at least a 1% tolerance.

Reference Decoupling

Externally decoupled the VREF pin to ground with a low ESR,

1.0 F capacitor in parallel with a low ESR, 0.1 F ceramic

capacitor.

SPI Port

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Because the

SCLK, CSB, and SDIO signals are typically asynchronous to the

ADC clock, noise from these signals can degrade converter

performance. If the on-board SPI bus is used for other devices,

it may be necessary to provide buffers between this bus and the

AD9231 to keep these signals from transitioning at the converter

inputs during critical sampling periods.

AD9231

Rev. A | Page 35 of 36

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4

091707-C

6.35

6.20 SQ

6.05

0.25 MIN

TOP VIEW 8.75

BSC SQ

9.00

BSC SQ

0.50

0.40

0.30

0.50

BSC

0.20 REF

12° MAX 0.80 MAX

0.65 TYP

1.00

0.85

0.80

7.50

REF

0.05 MAX

0.02 NOM

0.60 MAX

0.60

MAX

EXPOSED PAD

(BOTTOM VIEW)

SEATING

PLANE

PIN 1

INDICATOR

PIN 1

INDICATOR

0.30

0.23

0.18

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

Figure 59. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm × 9 mm Body, Very Thin Quad (CP-64-4)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Notes Temperature Range Package Description Package Option

AD9231BCPZ-80 2 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4

AD9231BCPZRL7-80 2 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4

AD9231BCPZ-65 2 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4

AD9231BCPZRL7-65 2 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4

AD9231BCPZ-40 2 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4

AD9231BCPZRL7-40 2 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4

AD9231BCPZ-20 2 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4

AD9231BCPZRL7-20 2 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4

AD9231-80EBZ Evaluation Board

AD9231-65EBZ Evaluation Board

AD9231-40EBZ Evaluation Board

AD9231-20EBZ Evaluation Board

1 Z = RoHS Compliant Part.

2 The exposed paddle (Pin 0) is the only GND connection on the chip and must be connected to the PCB AGND.

AD9231

Rev. A | Page 36 of 36

NOTES

registered trademarks are the property of their respective owners.

D08121-0-6/10(A)