This document is a general product description and is subject t o change without notice. Hynix Semiconductor do es not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1 / May. 2008 1
240pin Registered DDR2 SDRAM DIMMs based on 512 Mb F ver.
This Hynix registered Dual In-Line Memory Module (DIMM) series consists of 512Mb F ver. DDR2 SDRAMs in Fine Ball
Grid Arra y(FBGA) pa ck age s on a 2 40pin glass-epoxy substrate. This Hynix 512Mb F ver. based Registered DDR2 DI MM
series prov ide a high perfo rmance 8 byte inte rface in 133.35mm width form factor of industry standard. It is suitable
for easy interchange and addition.
ORDERING INFORMATION
Note:
1. “P” of part number[7th digit] stands for Parity Registered DIMM.
2. “P” of part number[11th digit] stands for Lead free products.
SPEED GRADE & KEY PARAMETERS
Part Name Density Org. Component Con f iguration Ranks Parity
Support
HMP564P7FFP8C-Y5 512MB 64Mx72 64Mx8(H5PS5182FFP)*9 1 O
HMP512R7FFP4C-E3 1GB 128Mx72 128Mx4(H5PS5142FFP)*18 1 X
HMP512P7FFP4C-Y5 1GB 128Mx72 128Mx4(H5PS5142FFP)*18 1 O
HMP525R7FFP4C-E3 2GB 256Mx72 128Mx4(H5PS5142FFP)*36 2 X
HMP525P7FFP4C-Y5 2GB 256Mx72 128Mx4(H5PS5142FFP)*36 2 O
E3 (DDR2-400) C4 (DDR2-533) Y5 (DDR2-667) S6 (DDR2-800) S5 (DDR2-800)
Speed@CL3 400 400 400 400 400
Speed@CL4 400 533 533 533 533
Speed@CL5 - - 667 - 800
Speed@CL6 - - - 800 -
CL-tRCD-tRP 3-3-3 4-4-4 5-5-5 6-6-6 5-5-5
Rev. 0.1 / May. 2008 2
1
240pin Registered DDR2 SDRAM DIMMs
FEATURES
ADDRESS TABLE
Density Organization Ranks SDRAMs # of
DRAMs # of row/bank/column Address Refresh
Method
512MB 64M x 72 1 64Mb x 8 9 14(A0~A13)/2(BA0~BA1)/10(A0~A9) 8K / 64ms
1GB 128M x 72 1 128Mb x 4 18 14(A0~A13)/2(BA0~BA1)/11(A0~A9,A11) 8K / 64ms
2GB 256M x 72 2 128Mb x 4 36 14(A0~A13)/2(BA0~BA1)/11(A0~A9,A11) 8K / 64ms
• JEDEC standard 1.8V +/- 0.1V Power Supply
•V
DDQ : 1.8V +/- 0.1V
• All inputs and outputs are compatible with SSTL_1.8 interface
•4 Bank architecture
•Posted CAS
• Programmable CAS Latency 3 , 4 , 5
• OCD (Off-Chip Driver Impedance Adjustment)
• ODT (On-Die Termination)
• Fully differential clock operations (CK & CK)
• Programmable Burst Length 4 / 8 with both sequential and interleave mode
• Average Auto Refresh Period 7.8us under TCASE 85℃, 3.9us at 85℃ < TCASE ≤ 95 ℃
• High Temperature Self-Refresh Entry enable features
• PASR(Partial Array Self- Refresh)
• 8192 refresh cycles / 64ms
• Serial presence detect with EEPROM
• DDR2 SDRAM Package: 60ball FBGA
• 133.35 x 30.00 mm form factor
• Lead-free Products are RoHS compliant
Rev. 0.1 / May. 2008 3
1
240pin Registered DDR2 SDRAM DIMMs
Input/Output Functional Description
Symbol Type Polarity Pin Description
CK0 IN Positive
Edge Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
CK0IN Negative
Edge Negative li ne of the dif ferenti al pair of sy stem clock i nputs that dr ives i nput to the on- DIMM PLL.
CKE[1:0] IN Active
High Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low.
By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode.
S[1:0] IN Active
Low
Enables the associated DDR2 SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored but
previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1
ODT[1:0] IN Active
High On-Die Termination signals.
RAS, CAS, WE IN Active
Low When sampled at the positive rising edge of the clock. RAS,CAS and WE(ALO NG WITH S) define
the command being entered.
Vref Supply Reference voltage for SSTL18 inputs
VDDQ Supply Power supplies for the DDR2 SDRAM output buffers to provide improved noise immunity. For all
current DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins.
BA[1:0] IN -Selects which DDR2 SDRAM internal bank of four is activated.
A[9:0],
A10/AP
A[13:11] IN -
During a Bank Activate command cycle, Address input difines the row address(RA0~RA13)
During a Read or Write command cycle, Address input defines the column address when sam-
pled at the cross poin t of the rising edge of CK and f alling edg e of CK. In addition to th e column
address, AP is used to invoke autoprecharge operation at the end of the burst read or write
cycle. If AP is high., autoprecharge is select ed and BA0-BAn defines the bank to be pr echarged.
If AP is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in con-
junction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be pre-
charged r egardless of t he state of BA0-BAn inputs. If AP is low , then BA0-BAn ar e used to defi ne
which bank to precharge.
DQ[63:0],
CB[7:0] IN -Data and Check B it Input/Outp ut pins.
DM[8:0] IN Active
High
DM is an input mask signal for write data. Input data is masked when DM is samp led High coin-
cident with that input data durin g a write access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ and DQS loading.
VDD,VSS Supply Power and ground for the DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins ar e
tied to VDD/VDDQ planes on these modules.
DQS[17:0] I/O Positive
Edge Positive line of the differential data strobe for input and output data
DQS[17:0] I/O Negative
Edge Negative line of the differential data strobe for input and output data
SA[2:0] IN -These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD
EEPROM address range.
SDA I/O -This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister may
be connected from the SDA bus line to VDDSPD on the system planar to act as a pull up.
SCL IN -This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
from SCL to VDDSPD to act as a pull up on the system board.
VDDSPD Supply Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane.
EEPROM supply is operable from 1.7V to 3.6V.
RESET IN The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When
low, all register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will
be set to low level (the PLL will remain synchronized with the input clock)
Par_In IN Parity bit for the Address and Control bus(“1”. Odd, “0”.Even)
Err_Out OUT Parity error found in the Address and Control bus
TEST Used by memory bus analysis tools(unused on memory DIMMs)
Rev. 0.1 / May. 2008 4
1
240pin Registered DDR2 SDRAM DIMMs
PIN DESCRIPTION
PIN LOCATION
Pin Pin Description Pin Pin Description
CK0 Clock Input,positive line ODT[1:0] On Die Termination Inputs
CK0Clock input,negative line VDDQ DQs Power Supply
CKE0~CKE1 Clock Enable Input DQ0~DQ63 Data Input/Output
RAS Row Address Strobe CB0~CB7 Data check bits Input/Output
CAS Column Address Strobe DQS(0~8) Data strobes
WE Write Enable DQS(0~8) Data strobes,negative line
S0,S1 Chip Select Input DM(0~8),
DQS(9~17) Data Maskes/Data strobes
A0~A9,
A11~A13 Address input DQS(9~17) D ata strobe s,negative line
A10/AP Address input/Autoprecharge RFU Reserved for Future Use
BA0,BA1 SDRAM Bank Address NC No Connect
SCL Serial Presence Detect(SPD) Clock Input TEST Memory bus test tool
(Not Connected and Not Usable on DIMMs)
SDA SPD Data Input/Output VDD Core Power
SA0~SA2 E2PROM Address Inputs VDDQ I/O Power
Par_In Parity bit for the Address and Control bus VSS Ground
Err_Out Parity error found on the Address VREF Input/Output Reference
RESET Reset Enable VDDSPD SPD Power
CB0~CB7 Data Check bit Inputs/Outputs
1 pin
Front Side
64 pin 65 pin 1 20 pin
121 pin
Back Side
184 pin 185 pin 240 pin
Rev. 0.1 / May. 2008 5
1
240pin Registered DDR2 SDRAM DIMMs
PIN ASSIGNMENT
NC= No Connect, RFU= Reserved for Future Use.
Note:
1. RESET(Pin 18) is connected to both OE of PLL and Reset of register.
2. NC/Err_out (Pin 55) and NC/Par_In(Pin68) are for optional function to check address and command parity.
3. The Test pin(Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules(DIMMs)
Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name
1VREF 41 VSS 81 DQ33 121 VSS 161 CB4 201 VSS
2VSS 42 CB0 82 VSS 122 DQ4 162 CB5 202 DM4/DQS13
3DQ0 43 CB1 83 DQS4123 DQ5 163 VSS 203 DQS13
4DQ1 44 VSS 84 DQS4 124 VSS 164 DM8,DQS17 204 VSS
5VSS 45 DQS885 VSS 125 DM0/DQS9 165 DQS17 205 DQ38
6DQS046 DQS8 86 DQ34 126 DQS9166 VSS 206 DQ39
7DQS0 47 VSS 87 DQ35 127 VSS 167 CB6 207 VSS
8VSS 48 CB2 88 VSS 128 DQ6 168 CB7 208 DQ44
9DQ2 49 CB3 89 DQ40 129 DQ7 169 VSS 209 DQ45
10 DQ3 50 VSS 90 DQ41 130 VSS 170 VDDQ 210 VSS
11 VSS 51 VDDQ 91 VSS 131 DQ12 171 NC,CKE1 211 DM5/DQS14
12 DQ8 52 CKE0 92 DQS5132 DQ13 172 VDD 212 DQS14
13 DQ9 53 VDD 93 DQS5 133 VSS 173 A15,NC 213 VSS
14 VSS 54 BA2,NC 94 VSS 134 DM1/DQS10 174 A14,NC 214 DQ46
15 DQS155 NC,Err_Out 95 DQ42 135 DQS10 175 VDDQ 215 DQ47
16 DQS1 56 VDDQ 96 DQ43 136 VSS 176 A12 216 VSS
17 VSS 57 A11 97 VSS 137 RFU 177 A9 217 DQ52
18 RESET 58 A7 98 DQ48 138 RFU 178 VDD 218 DQ53
19 NC 59 VDD 99 DQ49 139 VSS 179 A8 219 VSS
20 VSS 60 A5 100 VSS 140 DQ14 180 A6 220 RFU
21 DQ10 61 A4 101 SA2 141 DQ15 181 VDDQ 221 RFU
22 DQ11 62 VDDQ 102 NC(TEST) 142 VSS 182 A3 222 VSS
23 VSS 63 A2 103 VSS 143 DQ20 183 A1 223 DM6/DQS15
24 DQ16 64 VDD 104 DQS6144 DQ21 184 VDD 224 NC,DQS15
25 DQ17 Key 105 DQS6 145 VSS Key 225 VSS
26 VSS 65 VSS 106 VSS 146 DM2/DQS11 185 CK0 226 DQ54
27 DQS266 VSS 107 DQ50 147 DQS11 186 CK0227 DQ55
28 DQS2 67 VDD 108 DQ51 148 VSS 187 VDD 228 VSS
29 VSS 68 NC,Err_Out 109 VSS 149 DQ22 188 A0 229 DQ60
30 DQ18 69 VDD 110 DQ56 150 DQ23 189 VDD 230 DQ61
31 DQ19 70 A10/AP 111 DQ57 151 VSS 190 BA1 231 VSS
32 VSS 71 BA0 112 VSS 152 DQ28 191 VDDQ 232 DM7/DQS16
33 DQ24 72 VDDQ 113 DQS7153 DQ29 192 RAS 233 NC,DQS16
34 DQ25 73 WE 114 DQS7 154 VSS 193 S0 234 VSS
35 VSS 74 CAS 115 VSS 155 DM3/DQS12 194 VDDQ 235 DQ62
36 DQS375 VDDQ 116 DQ58 156 DQS12 195 ODT0 236 DQ63
37 DQS3 76 NC, S1 117 DQ59 157 VSS 196 A13,NC 237 VSS
38 VSS 77 NC, ODT1 118 VSS 158 DQ30 197 VDD 238 VDDSPD
39 DQ26 78 VDDQ 119 SDA 159 DQ31 198 VSS 239 SA0
40 DQ27 79 VSS 120 SCL 160 VSS 199 DQ36 240 SA1
80 DQ32 200 DQ37
Rev. 0.1 / May. 2008 6
1
240pin Registered DDR2 SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
512MB(64Mbx72) : HMP564P7FFP8C
P
L
L
OE
PCK0 to PCK6, PCK8,PCK9 ==> CK: SDRAMs D0 toD8
/PCK0 to /PCK6, /PCK8, /PCK9 ==> /CK: SDRAMs D0 toD8
PCK7 ==> CK: Register
/PCK7 ==> /C K: R egister
CK0
/CK0
/RESET
/RS0
D0
DQ0 I/O 0
DQ1 I/O 1
DQ2 I/O 2
DQ3 I/O 3
DQ4 I/O 4
DQ5 I/O 5
DQ6 I/O 6
I/O 7
DQ7
/DQS0
DM0,DQS9
DQS0
/CS D QS /DQS
DM
RDQS NU
/RDQS
/DQS9
D1
DQ8 I/O 0
DQ9 I/O 1
DQ10 I/O 2
DQ11 I/O 3
DQ12 I/O 4
DQ13 I/O 5
DQ14 I/O 6
I/O 7
DQ15
/DQS1
DM1,DQS10
DQS1
/CS D QS /DQS
DM
RDQS NU
/RDQS
/DQS10
D2
DQ16 I/O 0
DQ17 I/O 1
DQ18 I/O 2
DQ19 I/O 3
DQ20 I/O 4
DQ21 I/O 5
DQ22 I/O 6
I/O 7
DQ23
/DQS2
DM2,DQS11
DQS2
/CS D QS /DQS
DM
RDQS NU
/RDQS
/DQS11
D3
DQ24 I/O 0
DQ25 I/O 1
DQ26 I/O 2
DQ27 I/O 3
DQ28 I/O 4
DQ29 I/O 5
DQ30 I/O 6
I/O 7
DQ31
/DQS3
DM3,DQS12
DQS3
/CS D QS /DQS
DM
RDQS NU
/RDQS
/DQS12
D8
CB0 I/O 0
CB1 I/O 1
CB2 I/O 2
CB3 I/O 3
CB4 I/O 4
CB5 I/O 5
CB6 I/O 6
I/O 7
CB7
/DQS8
DM8DQS17
DQS8
/CS D QS /DQS
DM
RDQS NU
/RDQS
/DQS17
D4
DQ32 I/O 0
DQ33 I/O 1
DQ34 I/O 2
DQ35 I/O 3
DQ36 I/O 4
DQ37 I/O 5
DQ38 I/O 6
I/O 7
DQ39
/DQS4
DM4,DQS13
DQS4
/CS D QS /DQS
DM
RDQS NU
/RDQS
/DQS13
D5
DQ40 I/O 0
DQ41 I/O 1
DQ42 I/O 2
DQ43 I/O 3
DQ44 I/O 4
DQ45 I/O 5
DQ46 I/O 6
I/O 7
DQ47
/DQS5
DM5,DQS14
DQS5
/CS D QS /DQS
DM
RDQS NU
/RDQS
/DQS14
D6
DQ48 I/O 0
DQ49 I/O 1
DQ50 I/O 2
DQ51 I/O 3
DQ52 I/O 4
DQ53 I/O 5
DQ54 I/O 6
I/O 7
DQ55
/DQS6
DM6,DQS15
DQS6
/CS D QS /DQS
DM
RDQS NU
/RDQS
/DQS15
D7
DQ56 I/O 0
DQ57 I/O 1
DQ58 I/O 2
DQ59 I/O 3
DQ60 I/O 4
DQ61 I/O 5
DQ62 I/O 6
I/O 7
DQ63
/DQS7
DM7,DQS16
DQS7
/CS D QS /DQS
DM
RDQS NU
/RDQS
/DQS16
VDD SPD
VDD /
VDDQ
VREF
VSS
Serial PD
DO-D8
DO-D8
DO-D8
SA0 SA1 SA2
WP
SCL SDA
A0 A1 A2
Serial PD
SCL U0 SDA
* : /S0 connects to D/CS and VDD connects to /CSR on register.
ODT0
CKE0
/PCK7
/WE
R
E
G
I
S
T
E
R
PCK7
/RESET
/CAS
/RAS
BA0 to BA1
A0 to A13
/CS0*
RODT0 ==> ODT0: SDRAMs D0 to D8
/RWE = => /W E : S DRA Ms D 0 to D8
RCKE0 ==> CKE: SDRAMs D0 to D8
/RCAS ==>/CAS: SDRAMs D0 to D8
/RRAS ==>/RAS: SDRAMs D0 to D8
/RA0 to RA 13 ==> A0 to A1 3: SDRAM s D0 to D8
RBA0 to RBA1 ==> BA0 to BA1: SDRAMs D0 to D8
/RS0 to /CS == > /CS : S DRA Ms D0 to D8
/RST
1. Register values are 22 Ohms.
Notes :
Register
C0
C1
PAR_IN PPO
/QERR
VSS
PAR_IN
100K ohms /Err-Out
Signals for Address and Command Parity Function
The resistors on Par_In, A13, A14, A15, BA2 and
the sign a l line of E rr_ O u t re fe r to th e s e c tion:
“Register Options for Unused Address inputs”
VSS
Rev. 0.1 / May. 2008 7
1
240pin Registered DDR2 SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
1GB(64Mbx72) : HMP512R(P)7FFP4C
/RS0
VSS
D0
DQS /CS DM
I/O0
I/O1
I/O2
I/O3
DQ0
DQ1
DQ2
DQ3
/DQS0
/DQS
DQS0
D1
DQS /CS DM
I/O0
I/O1
I/O2
I/O3
/DQS1
/DQS
DQS1
D2
DQS /CS DM
I/O0
I/O1
I/O2
I/O3
DQ16
DQ17
DQ18
DQ19
/DQS2
/DQS
DQS2
D3
DQS /CS DM
I/O0
I/O1
I/O2
I/O3
/DQS3
/DQS
DQS3
D4
DQS /CS DM
I/O0
I/O1
I/O2
I/O3
/DQS4
/DQS
DQS4
D5
DQS /CS DM
I/O0
I/O1
I/O2
I/O3
/DQS5
/DQS
DQS5
D6
DQS /CS DM
I/O0
I/O1
I/O2
I/O3
/DQS6
/DQS
DQS6
D7
DQS /CS DM
I/O0
I/O1
I/O2
I/O3
/DQS7
/DQS
DQS7
D8
DQS /CS DM
I/O0
I/O1
I/O2
I/O3
CB0
CB1
CB2
CB3
/DQS8
/DQS
DQS8
D9
DQS /CS DM
I/O0
I/O1
I/O2
I/O3
DQ4
DQ5
DQ6
DQ7
/DQS9
/DQS
DQS9
D10
DQS /CS DM
I/O0
I/O1
I/O2
I/O3
/DQS10
/DQS
DQS10
D11
DQS /CS DM
I/O0
I/O1
I/O2
I/O3
/DQS11
/DQS
DQS11
D12
DQS /CS DM
I/O0
I/O1
I/O2
I/O3
/DQS12
/DQS
DQS12
D13
DQS /CS DM
I/O0
I/O1
I/O2
I/O3
/DQS13
/DQS
DQS13
D14
DQS /CS DM
I/O0
I/O1
I/O2
I/O3
/DQS14
/DQS
DQS14
D15
DQS /CS DM
I/O0
I/O1
I/O2
I/O3
/DQS15
/DQS
DQS15
D16
DQS /CS DM
I/O0
I/O1
I/O2
I/O3
/DQS16
/DQS
DQS16
D17
DQS /CS DM
I/O0
I/O1
I/O2
I/O3
CB4
CB5
CB6
CB7
/DQS17
/DQS
DQS17
DQ60
DQ61
DQ62
DQ63
DQ52
DQ53
DQ54
DQ55
DQ44
DQ45
DQ46
DQ47
DQ36
DQ37
DQ38
DQ39
DQ28
DQ29
DQ30
DQ31
DQ20
DQ21
DQ22
DQ23
DQ12
DQ13
DQ14
DQ15
DQ8
DQ9
DQ10
DQ11
DQ24
DQ25
DQ26
DQ27
DQ32
DQ33
DQ34
DQ35
DQ40
DQ41
DQ42
DQ43
DQ48
DQ49
DQ50
DQ51
DQ56
DQ57
DQ58
DQ59
* /S0 connects to D/CS of Register1 and /CSR of Register2. /CSR of register and D/CS of register2 connects to VDD.
** /RESET,PCK7 connect to both Registers. Other signals connect to one of two Registers. /S1,CKE1 and ODT1 are NC.
P
L
L
OE
CK0
/CK0
/RESET
PCK0 to PCK6, PCK8,PCK9 = > CK : SDRAMx D0-D17
/PCK0 to /PCK6, /PCK8,/PCK9 = > /CK : SDRAMx D0-D17
PCK7 = > CK: Register
/PCK7 = > /CK: Register
SA0 SA1 SA2
W
P
SCL SDA
A0 A1 A2
Serial PD
SCL U0 SDA
VDD SPD
VREF
VDD/VDDQ
VSS
Serial
PD
DO-D17
DO-D17
DO-D17
1. Resistor values are 2 2 Ohms +/- 5%.
Notes:
ODT0
CKE0
/PCK7
/WE
R
E
G
I
S
T
E
R
PCK7
/RESET
/CAS
/RAS
BA0 to BA1
A0 to A13
/CS0*
RODT0 ==> ODT0: SDRAMs D0 to D17
/RWE ==> /WE: SDRAMs D0 to D17
RCKE0 ==> CKE: SD RAMs D0 to D17
/RCAS ==>/CAS: SDRAMs D0 to D17
/RRAS ==>/RAS: SDRAMs D0 to D17
/RA0 to RA13 ==> A0 to A13: SDRAMs D0 to D17
RBA0 to R BA1 ==> BA0 to BA1: S DRAMs D0 to D17
/RS0 to /CS ==> /CS: SDRAMs D0 to D17
/RST
Register
C0 A
C1
PAR_IN PPO
/QERR
VSS
VDD
PAR_IN
100K ohms /Err-Out
Signals for Address and Command Parity Function
The resistors on Par_In, A13, A14, A15, BA2 and
the signal line of Err_Out refer to the section:
“Register Opt ions for Unused Address inp uts”
Register
C0 B
C1
PAR_IN PPO
/QERR
VDD
VDD
Rev. 0.1 / May. 2008 8
1
240pin Registered DDR2 SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
2GB(256Mbx72) : HMP525P[R]7FFP4C
VSS
RS0
RS1
DQS0
DQ0
DQ1
DQ2
I/O 0
I/O 1
I/O 2
I/O 3
CS
D18
RS0 -> CS: SDRAMs D0-D17S0*
S1*
BA0-BA2***
A0-A15***
RAS
CAS
WE
CKE0
CKE1
ODT1
ODT0
RESET** PCK7**
PCK7**
RS1 -> CS: SDRAMs D18-D35
RBA0-RBA2 -> BA0- BA 2: SD R AM s D0- D 35
RA0-RA15 -> A0-A15: SDRAMs D0-D35
RRAS -> RAS: SDRAMs D0-D35
RCAS -> CAS: SDRAMs D0-D35
RWE -> WE: SDRAMs D0-D35
RCKE0 -> CKE0-1: SDRAMs D0-D17
RCKE1 -> CKE0-1: SDRAMs D18-D35
RODT0 -> ODT1: SDRAMs D0-D17
RODT1 -> ODT1: SDRAMs D18-D35
*S0 connects to DCS and S1 command to CRS on a pair of Register, S2 connects to DCS and S0 connect t o CRS on another pair of Registe r.
** RESET, PCK7 and PCK7 connect to all Registers. Other signals connect to one pair of four Registers.
*** A14-15, BA2 have the optional pull down resistors (100K ohms), which is not indicated here.
1:2
R
E
G
I
S
T
E
R
PCK7 -> CK: Register
PCK7 -> CK: Register
PCK0-PCK6, PCK8, PCK9 -> CK : SDRAMs D0-D35
PCK0-PCK6, PCK8, PCK9 -> CK: SDRAMs D0-D35
P
L
L
RST
CK0
CK0
RESET OE
Register
Register
PARIN PTYERR
PARIN PTYERR
Par_In
Err_Out
Serial PD
WP A0 A1 A2
SA0 SA1SA2
SCL SDA
100KΩ
0Ω
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D0
DM DQS DQS
DQS0
I/O 0
I/O 1
I/O 2
I/O 3
CS
D27
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D9
DM DQS DQS
DQ3
DQS9
DQS9
DQ4
DQ5
DQ6
DQ7
DQS1
DQ8
DQ9
DQ10
I/O 0
I/O 1
I/O 2
I/O 3
CS
D19
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D1
DM DQS DQS
DQS1
I/O 0
I/O 1
I/O 2
I/O 3
CS
D28
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D10
DM DQS DQS
DQ11
DQS10
DQS10
DQ12
DQ13
DQ14
DQ15
DQS2
DQ16
DQ17
DQ18
I/O 0
I/O 1
I/O 2
I/O 3
CS
D20
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D2
DM DQS DQS
DQS2
I/O 0
I/O 1
I/O 2
I/O 3
CS
D29
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D11
DM DQS DQS
DQ19
DQS11
DQS11
DQ20
DQ21
DQ22
DQ23
DQS3
DQ24
DQ25
DQ26
I/O 0
I/O 1
I/O 2
I/O 3
CS
D21
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D3
DM DQS DQS
DQS3
I/O 0
I/O 1
I/O 2
I/O 3
CS
D30
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D12
DM DQS DQS
DQ27
DQS12
DQS12
DQ28
DQ29
DQ30
DQ30
DQS8 DQS17
RS0
RS1
DQS4
DQ32
DQ33
DQ34
I/O 0
I/O 1
I/O 2
I/O 3
CS
D22
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D4
DM DQS DQS
DQS4
I/O 0
I/O 1
I/O 2
I/O 3
CS
D31
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D13
DM DQS DQS
DQ35
DQS13
DQS13
DQ36
DQ37
DQ38
DQ39
DQS5
DQ40
DQ41
DQ42
I/O 0
I/O 1
I/O 2
I/O 3
CS
D23
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D5
DM DQS DQS
DQS5
I/O 0
I/O 1
I/O 2
I/O 3
CS
D32
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D14
DM DQS DQS
DQ43
DQS14
DQS14
DQ44
DQ45
DQ46
DQ47
DQS6
DQ48
DQ49
DQ50
I/O 0
I/O 1
I/O 2
I/O 3
CS
D24
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D6
DM DQS DQS
DQS6
I/O 0
I/O 1
I/O 2
I/O 3
CS
D33
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D15
DM DQS DQS
DQ51
DQS15
DQS15
DQ52
DQ53
DQ54
DQ55
DQS7
DQ56
DQ57
DQ58
I/O 0
I/O 1
I/O 2
I/O 3
CS
D25
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D7
DM DQS DQS
DQS7
I/O 0
I/O 1
I/O 2
I/O 3
CS
D34
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D16
DM DQS DQS
DQ59
DQS16
DQS16
DQ60
DQ61
DQ62
DQ63
Note:
1. DQ-to-I/O wiring may be ch anged within a nibble.
2. Unless otherwise noted, resistor values are 22 Ohms ±5%.
3. RS0 and RS1 alternate between the bottom and surface sides of the DIMM.
CB0
CB1
CB2
I/O 0
I/O 1
I/O 2
I/O 3
CS
D26
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D8
DM DQS DQS
DQS8
I/O 0
I/O 1
I/O 2
I/O 3
CS
D35
DM DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D17
DM DQS DQS
CB3
DQS17
CB4
CB5
CB6
CB7
Signals for Address and Command
Parity Fun ction
o ohm resis tor on E rr_Out is not popul ated
for non-parity card.
The resistors on Par_In,A13,A14,A15,BA2
and the signal lin e of Err_Out refer to the
section:
“Register Options for Unused Address
input”
D0–D35
D0–D35
VREF
SPD
VDD/VDDQ
V
SS
D0–D35
VDDSPD
Rev. 0.1 / May. 2008 9
1
240pin Registered DDR2 SDRAM DIMMs
ABSOLUTE MAXIMUM RATINGS
Note :
1. Stress greater than those listed may cause permanent dama ge to the device. This is a stress r ating only, and device
functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating con
ditions for extended periods may affect reliablility.
OPERATING CONDITIONS
Note :
1. Up to 9850 ft.
2. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to
tREFI=3.9us. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2.
DC OPERATING CONDITIONS (SSTL_1.8)
Note :
1. VDDQ must be less than or equal to VDD.
2. Peak to peak ac noise on VREF may not exeed +/-2% VREF(dc)
3. VTT of transmitting device must track VREF of receiving device.
Parameter Symbol Value Unit Note
Voltage on VDD pin relative to Vss VDD - 1.0 V ~ 2.3 V V 1
Voltage on VDDL pin relative to Vss VDDL -0.5V ~ 2.3 V V 1
Voltage on VDDQ pin relative to Vss VDDQ - 0.5 V ~ 2.3 V V 1
Voltage on any pin relative to Vss VIN, VOUT - 0.5 V ~ 2.3 V V 1
Storage Temperature TSTG -50 ~ +100 oC1
Storage Humidity(without condensation) HSTG 5 to 95 %1
Parameter Symbol Rating Units Notes
DIMM Operating temperature(ambient) TOPR 0 ~ +55 oC
DIMM Barometric Pressure(ope rating & storage) PBAR 105 to 69 K Pascal 1
DRAM Component Case Temperature Range TCASE 0 ~+95 oC2
Parameter Symbol Min Max Unit Note
Power Supply Voltage VDD 1.7 1.9 V
VDDL 1.7 1.9 V
VDDQ 1.7 1.9 V 1
Input Reference Voltage VREF 0.49 x VDDQ 0.51 x VDDQ V2
EEPROM Supply Voltage VDDSPD 1.7 3.6 V
Termination Voltage VTT VREF-0.04 VREF+0.04 V3
Input leakage current; any input 0V VIN VDD;
all other balls not under test = 0V) II-2 2 uA
Output leakage current; 0V VOUT VDDQ;
DQ and ODT disabled IOZ -5 5 uA
Rev. 0.1 / May. 2008 10
1
240pin Registered DDR2 SDRAM DIMMs
INPUT DC LOGIC LEVEL
INPUT AC LOGIC LEVEL
AC INPUT TEST CONDITIONS
Notes:
1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device
under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges
and the range from VREF to VIL(ac) max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions
and VIH(ac) to VIL(ac) on the negative transitions.
Parameter Symbol Min Max Unit Notes
Input High Voltage VIH(DC) VREF + 0.125 VDDQ + 0.3 V
Input Low Voltage VIL(DC) -0.30 VREF - 0.125 V
Parameter Symbol DDR2 400/533 DDR2 667/800 Unit Notes
Min Max Min Max
AC Input logic High VIH(AC) VREF + 0.250 - VREF + 0.200 - V
AC Input logic Low VIL(AC) -V
REF - 0.250 - VREF - 0.200 V
Symbol Condition Value Units Notes
VREF Input reference voltage 0.5 * VDDQ V1
VSWING(MAX) Input signal maximum peak to peak swing 1.0 V 1
SLEW Input signal minimum slew rate 1.0 V/ns 2, 3
VDDQ
VIH(ac) min
VIH(dc) min
VREF
VIL(dc) max
VIL(ac) max
VSS
V
SWING(MAX)
delta TRdelta TF
VREF
-
VIL
(ac)
max
delta TF
Falling Slew = Rising Slew =
VIH
(ac)
min
- V
REF
delta TR
< Figure : AC Input Test Signal Waveform>
Rev. 0.1 / May. 2008 11
1
240pin Registered DDR2 SDRAM DIMMs
Differential Input AC logic Level
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS,
LDQS, UDQS and UDQS.
2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as
CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The mini-
mum value is equal to VIH(DC) - VIL(DC).
Notes:
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal
(such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS).
The minimum value is equal to V IH(AC) - VIL(AC).
2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to
track variations in VDDQ . VIX(AC) indicates the voltage at whitch differential input signals must cross.
DIFFERENTIAL AC OUTPUT PARAMETERS
Note:
1. The typical v a lue of VOX(AC) is expected to be abou t 0.5 * V DDQ of the transmitting device and V OX(AC) is expected to
track variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross.
Symbol Parameter Min. Max. Units Note
VID (ac) ac differential input voltage 0.5 VDDQ + 0.6 V 1
VIX (ac) ac differential cross point voltage 0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175 V 2
Symbol Parameter Min. Max. Units Note
VOX (ac) ac differential cross point voltage 0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125 V 1
VDDQ
Crossing point
VSSQ
VTR
VCP
VID VIX or VOX
< Differential signal levels >
Rev. 0.1 / May. 2008 12
1
240pin Registered DDR2 SDRAM DIMMs
OUTPUT BUFFER LEVELS
OUTPUT AC TEST CONDITIONS
Notes:
1. The VDDQ of the device under test is referenced.
OUTPUT DC CURRENT DRIVE
Notes:
1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and
VDDQ - 280 mV.
2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV.
3. The dc value of VREF applied to the receiving device is set to VTT
4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device
drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an
SSTL_18 receiver.
The actual current values are deriv ed by shifting the desir ed driv er operating poin t along a 21 ohm load line to define
a convenient driver current for measurement.
Symbol Parameter SSTL_18 Units Notes
VOTR Output Timing Measurement Reference Level 0.5 * VDDQ V1
Symbol Parameter SSTl_18 Units Notes
IOH(dc) Output Minimum Source DC Current - 13.4 mA 1, 3, 4
IOL(dc) Output Minimum Sink DC Current 13.4 mA 2, 3, 4
Rev. 0.1 / May. 2008 13
1
240pin Registered DDR2 SDRAM DIMMs
PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25℃. f=1MHz )
512MB : HMP564P7FFP8C
1GB : HMP512R7FFP4C / HMP512P7FFP4C
2GB : HMP525R7FFP4C / HMP525P7FFP4C
Note :
1. Pins not under test are tied to GND.
2. These values are guaranteed by design and tested on a sample basis only.
Pin Symbol Min Max Unit
CK0, CK0CCK 711 pF
CKE, ODT CI1 812 pF
CS CI2 812 pF
Address, RAS, CAS, WE CI3 812 pF
DQ, DM, DQS, DQS CIO 6 9 pF
Pin Symbol Min Max Unit
CK0, CK0CCK 711 pF
CKE, ODT CI1 812 pF
CS CI2 10 15 pF
Address, RAS, CAS, WE CI3 812 pF
DQ, DM, DQS, DQS CIO 6 9 pF
Pin Symbol Min Max Unit
CK0, CK0CCK 711 pF
CKE, ODT CI1 10 15 pF
CS CI2 10 15 pF
Address, RAS, CAS, WE CI3 10 15 pF
DQ, DM, DQS, DQS CIO 915 pF
Rev. 0.1 / May. 2008 14
1
240pin Registered DDR2 SDRAM DIMMs
IDD SPECIFICATIONS (TCASE : 0 to 95oC)
512MB, 64M x 72 Registered DIMM : HMP564P7FFP8C
1GB, 128M x 72 Registered DIMM : HMP512R[P]7FFP4C
Notes :
1. IDD6 current values are guaranteed up to Tcase of 85oC max.
Symbol E3 (400@CL3) C4 (533@CL4) Y5 (667@CL5) S5 (800@CL5) Unit Notes
IDD0 1280 1325 1325 1370 mA
IDD1 1415 1415 1415 1460 mA
IDD2P 722 722 722 722 mA
IDD2Q 920 920 965 965 mA
IDD2N 965 965 1010 1010 mA
IDD3P-F 920 920 920 920 mA
IDD3P-S 758 758 758 758 mA
IDD3N 1100 1100 1145 1145 mA
IDD4W 1325 1325 1550 1685 mA
IDD4R 1415 1415 1640 1775 mA
IDD5 1595 1595 1640 1685 mA 1
IDD6 522 522 522 522 mA
IDD7 1955 2045 2135 2225 mA
Symbol E3 (400@CL3) C4 (533@CL4) Y5 (667@CL5) S5 (800@CL5) Unit Notes
IDD0 1910 2000 2000 2090 mA
IDD1 2180 2180 2180 2270 mA
IDD2P 794 794 794 794 mA
IDD2Q 1190 1190 1280 1280 mA
IDD2N 1280 1280 1370 1370 mA
IDD3P-F 1190 1190 1190 1190 mA
IDD3P-S 866 866 866 866 mA
IDD3N 1550 1550 1640 1640 mA
IDD4W 2000 2000 2450 2720 mA
IDD4R 2180 2180 2630 2900 mA
IDD5 2340 2340 2430 2520 mA 1
IDD6 594 594 594 594 mA
IDD7 3260 3440 3620 3800 mA
Rev. 0.1 / May. 2008 15
1
240pin Registered DDR2 SDRAM DIMMs
2GB, 256M x 72 Registered DIMM : HMP525R[P]7FFP4C
Symbol E3 (400@CL3) C4 (533@CL4) Y5 (667@CL5) S5 (800@CL5) Unit Notes
IDD0 2540 2630 2720 2810 mA
IDD1 2810 2810 2900 2990 mA
IDD2P 938 938 938 938 mA
IDD2Q 1730 1730 1910 1910 mA
IDD2N 1910 1910 2090 2090 mA
IDD3P-F 1730 1730 1730 1730 mA
IDD3P-S 1082 1082 1082 1082 mA
IDD3N 2450 2450 2630 2630 mA
IDD4W 2630 2630 3170 3440 mA
IDD4R 2810 2810 3350 3620 mA
IDD5 2970 2970 3150 3240 mA 1
IDD6 738 738 738 738 mA
IDD7 3890 4070 4340 4520 mA
Rev. 0.1 / May. 2008 16
1
240pin Registered DDR2 SDRAM DIMMs
IDD Measurement Conditions
Notes:
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LD Q S, LDQS, UDQS, and UDQS. IDD values must be met with
all combinations of EMRS bits 10 and 11.
5. Definiti ons for IDD
LOW is defined as Vin ≤ VILAC(max)
HIGH is defined as V in ≥ VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VRE F = VDDQ/2
SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks ) for address and
control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock)
for DQ signals not including masks or strobes.
Symbol Conditions Units
IDD0 Operating one bank active-precharge current ; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS-
min(IDD);CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus
inputs are SWITCHIN G mA
IDD1 Operating one bank active-read-precharge current ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0; tCK =
tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD) ; CKE is HIGH, CS is HIGH between valid
commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W mA
IDD2P Precharge power-down current ; All banks idle ; tCK = tCK(IDD) ; CKE is LOW ; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING mA
IDD2Q Precharge quiet standby current ; All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH; Other control
and address bus inputs are STABLE; Data bus inputs are FLOATING mA
IDD2N Precharge standby current ; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA
IDD3P Active power-down current ; All banks open; tCK = tCK(IDD); CKE is
LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
Fast PDN Exit MRS(12) = 0 mA
Slow PDN Exit MRS(12) = 1 mA
IDD3N Active standby current ; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =tRP(IDD); CKE is
HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHIN G mA
IDD4W Operating burst write current ; All banks open, Continuou s burst writes; BL = 4 , CL = CL(IDD), AL = 0; tCK
= tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA
IDD4R Operating burst read current ; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD),
AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid com-
mands; Address bus input s are SWITCHING;; Data pattern is same as IDD4W mA
IDD5B Burst refresh current ; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is
HIGH between valid comma nds; Other control an d a ddress bus inputs are SWITCHING; Da ta bus inputs are
SWITCHING mA
IDD6 Self refresh current ; CK and CK at 0V; CKE ≤ 0.2V; Other contr ol and address bus inputs are F LOA TING; Data
bus inputs are FLOA TING. IDD6 current values are guaranted up to Tcase of 85℃ max. mA
IDD7
Operating bank interleave read current ; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD),
AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is
HIGH, CS is HIGH between v al id commands; Addr ess bus input s are STABLE during DESELECTs; Data patter n is
same as IDD4R; - Refer to the following page for detailed timing conditions
mA
Rev. 0.1 / May. 2008 17
1
240pin Registered DDR2 SDRAM DIMMs
Electrical Characteristics & AC Timings
Speed Bins and CL,tRCD,tRP,tRC and tRAS for Corresponding Bin
AC Timing Parameters by Speed Grade
Speed DDR2-800 DDR2-667 DDR2-533 DDR2-400 Unit
Bin(CL-tRCD-tRP) 5-5-5 5-5-5 4-4-4 3-3-3
Parameter min min min min
CAS Latency 55 4 5
ns
tRCD 12.5 15 15 15 ns
tRP 12.5 15 15 15 ns
tRAS 45 45 45 40 ns
tRC 57.25 60 60 55 ns
Parameter Symbol DDR2-400 DDR2-533 Unit Note
Min Max Min Max
Data-Out edge to Cl ock edge Skew tAC -600 +600 -500 500 ps
DQS-Out edge to Clock edge Skew tDQSCK -500 +500 -500 450 ns
Clock High Level Width tCH 0.45 0.55 0.45 0.55 CK
Clock Low Level Width tCL 0.45 0.55 0.45 0.55 CK
Clock Half Period tHP min(tCL,tCH) -min
(tCL,tCH) -ns
System Clock Cycle Time tCK 5000 8000 3750 8000 ps
DQ and DM input setup time(differential strobe) tDS 150 - 100 -ps 1
DQ and DM input hold time(differe ntial strobe) tDH 275 - 225 -ps 1
DQ and DM input setup time(single ended strobe) tDS1 25 --25-ps 1
DQ and DM input hold time(single ended strobe) tDH1 25 --25-ps 1
Control & Address input Pulse Width for each input tIPW 0.6 -0.6 - tCK
DQ and DM input pulse witdth for each input tDIPW 0.35 -0.35 - tCK
Data-out high-impedance window from CK, /CK tHZ - tAC max- tAC max
ps
DQS low-impedance time from CK/CK tLZ(DQS) tAC min tAC max tAC min tAC max ps
DQ low-impedance time from CK/CK tLZ(DQ) 2*tAC min tAC max 2*tAC min tAC max ps
DQS-DQ skew for DQS and associated DQ signals tDQSQ - 350 - 300 ps
DQ hold skew factor tQHS - 450 - 400 ps
DQ/DQS output hold time from DQS tQH tHP - tQHS -tHP - tQHS -ps
First DQS latching transition to associated clock edge tDQSS -0.25 + 0.25 -0.25 + 0.25 tCK
DQS input high pulse width tDQSH 0.35 -0.35 -tCK
DQS input low pulse width tDQSL 0.35 -0.35 -tCK
DQS falling edge to CK setup time tDSS 0.2 -0.2 -tCK
DQS falling edge hold time from CK tDSH 0.2 -0.2 -tCK
Mode register set command cycle time tMRD 2 - 2 - tCK
Write postamble tWPST 0.4 0.6 0.4 0.6 tCK
Rev. 0.1 / May. 2008 18
1
240pin Registered DDR2 SDRAM DIMMs
- continued -
Note :
1. For details and notes, please refer to the relevant HYNIX component datasheet (HY5PS12[4, 8]21CFP).
2. 0°C ≤ TCASE ≤ 85°C
3. 85°C ＜ TCASE ≤ 95°C
Parameter Symbol DDR2-400 DDR2-533 Unit Note
Min Max Min Max
Write preamble tWPRE 0.3 5 - 0.35 -tCK
Address and control input setup time tIS 350 -250-ps
Address and control input hold time tIH 475 -375-ps
Read pre a m bl e tRPRE 0.9 1.1 0.9 1.1 tCK
Read postamb le tRPST 0.4 0.6 0.4 0.6 tCK
Auto-Refresh to Active/Aut o-Refresh command
period tRFC 105 -105 -ns
Row Active to Row Active Delay for 1KB page size tRRD 7.5 -7.5 - ns
Four Activate Window for 1KB page size tFAW 37.5 -37.5 - ns
CAS to CAS command delay tCCD 2 2 tCK
Write recovery time tWR 15 - 15-ns
Auto Precharge Write Recovery + Precharge Time tDAL WR+tRP -tWR+tRP - tCK
Write to Read Command Delay tWTR 10 -7.5-ns
Internal read to precharge command delay tRTP 7.5 7.5 ns
Exit self refresh to a non-read command tXSNR tRFC + 10 tRFC + 10 ns
Exit self refresh to a read command tXSRD 200 -200 -tCK
Exit precharge power down to any non-read
command tXP 2 -2 -tCK
Exit active power down to read command tXARD 2 2 tCK
Exit active power down to read command
(Slow exit, Lower power) tXARDS 6 - AL 6 - AL tCK
CKE minimum pulse width
(high and low pulse width) tCKE 3 3 tCK
ODT turn-on delay tAOND 2222
tCK
ODT turn-on tAON tAC(min) tAC(max)+1 tAC(min) tAC(max)+1 ns
ODT turn-on(Power-Down mode) tAONPD tAC(min)+2 2tCK+
tAC(max)+1 tAC(min)+2 2tCK+tAC(m
ax)+1 ns
ODT turn-off delay tAOFD 2.5 2.5 2.5 2.5 tCK
ODT turn-off tAOF tAC(min) tAC(max)+0
.6 tAC(min) tAC(max)+
0.6 ns
ODT turn-off (Power-Down mode) tAOFPD tAC(min)+2 2.5tCK+tAC(
max)+1 tAC(min)+2 2.5tCK+tAC(
max)+1 ns
ODT to power down entry latency tANPD 33
tCK
ODT power down exit latency tAXPD 88
tCK
OCD drive mode output delay tOIT 012012
ns
Minimum time clocks remains ON after CKE
asynchronously drops LOW tDelay tIS+tCK+tIH tIS+tCK+tIH ns
Average periodic Refresh Interval tREFI -7.8-7.8us 2
tREFI -3.9 -3.9 us 3
Rev. 0.1 / May. 2008 19
1
240pin Registered DDR2 SDRAM DIMMs
Parameter Symbol DDR2-667 DDR2-800 Unit Note
min max min max
DQ output access time from CK/CK tAC -450 +450 -400 +400 ps
DQS output access time from CK/CK tDQSCK -400 +400 -350 +350 ps
CK high-level width tCH 0.45 0.55 0.45 0.55 tCK
CK low-level width tCL 0.45 0.55 0.45 0.55 tCK
CK half period tHP min(tCL,
tCH) -min(tCL,
tCH) -ps
Clock cycle time, CL=x tCK 3000 8000 2500 ps
DQ and DM input setup time
(differen t ial strobe) tDS 100 - 50 -ps 1
DQ and DM input hold time
(differen t ial strobe) tDH 175 - 125 -ps 1
Control & Addres s input puls e width f or each
input tIPW 0.6 - 0.6 -tCK
DQ and DM input pulse width for each input tDIPW 0.35 - 0.35 -tCK
Data-out high-impe dan ce time from CK/CK tHZ - tAC max - tAC max ps
DQS low-impedance time from CK/CK tLZ(DQS) tAC min tAC max tAC min tAC max ps
DQ low-impedance time from CK/CK tLZ(DQ) 2*tAC min tAC max 2*tAC min tAC max ps
DQS-DQ skew for DQS and associated DQ
signals tDQSQ - 240 -200ps
DQ hold skew factor tQHS - 340 -300ps
DQ/DQS output hold time from DQS tQH t H P - t QHS -tHP - tQHS -ps
First DQS latching transition to associated
clock edge tDQSS - 0.25 + 0.25 - 0.25 + 0.25 tCK
DQS input high pulse width tDQSH 0.35 -0.35 -tCK
DQS input low pulse width tDQSL 0.35 -0.35 -tCK
DQS falling edge to CK setup time tDSS 0.2 -0.2 -tCK
DQS falling edge hold time from CK tDSH 0.2 -0.2 -tCK
Mode register set com m a nd cycle time tMRD 2 - 2 - tCK
Write postamble tWPST 0.4 0.6 0.4 0.6 tCK
Write preamble tWPRE 0.35 - 0.35 -tCK
Address and co nt rol input setup time tIS 200 - 175 -ps
Address and co nt rol input hold tim e tIH 275 - 250 -ps
Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK
Read postamble tRPST 0.4 0.6 0.4 0.6 tCK
Activate to precharge command tRAS 45 70000 45 70000 ns
Active to active command period for 1KB
page size products tRRD 7.5 -7.5-ns
Four Active Window for 1KB page size
products tFAW 37.5 -35 -ns
Rev. 0.1 / May. 2008 20
1
240pin Registered DDR2 SDRAM DIMMs
- continued -
Note :
1. For details and notes, please refer to the relevant HYNIX component datasheet (HY5PS12[4, 8]21CFP).
2. 0°C ≤ TCASE ≤ 85°C
3. 85°C ＜ TCASE ≤ 95°C
Parameter Symbol DDR2-667 DDR2-800 Unit Note
min max min max
CAS to CAS command delay tCCD 2 2 tCK
Write reco v ery time tWR 15 - 15-ns
Auto precharge write recovery + precharge
time tDAL WR+tRP -WR+tRP -tCK
Internal write to read command delay tWTR 7.5 -7.5-ns
Internal read to precharge command delay tRTP 7.5 7.5 ns
Exit self refresh to a non-read command tXSNR tRFC + 10 tRFC + 10 ns
Exit self refresh to a read command tXSRD 200 -200 -tCK
Exit precharge power down to any non-read
command tXP 2 -2 -tCK
Exit active power down to read command tXARD 2 2 tCK
Exit active power down to read command
(Slow exit, Lower power) tXARDS 7 - AL 8 - AL tCK
CKE minimum pulse width
(high and low pulse width) tCKE 33tCK
ODT turn-on delay tAOND 2222tCK
ODT turn-on tAON tAC(min) tAC(max)
+0.7 tAC(min) tAC(max)
+0.7 ns
ODT turn-on(Power-Down mode) tAONPD tAC(min)+2 2tCK+
tAC(max)+1 tAC(min)
+2 2tCK+
tAC(max)+1 ns
ODT turn-off delay tAOFD 2.5 2.5 2.5 2.5 tCK
ODT turn-off tAOF tAC(min) tAC(max)+
0.6 tAC(min) tAC(max)
+0.6 ns
ODT turn-off (Power-Down mode) tAOFPD tAC(min)
+2 2.5tCK+
tAC(max)+1 tAC(min)
+2 2.5tCK+
tAC(max)+1 ns
ODT to power down entry latency tANPD 3 3 tCK
ODT power down exit latency tAXPD 8 8 tCK
OCD drive mode output delay tOIT 0 12 0 12 ns
Minimum time clocks remains ON after CKE
asynchronously drops LOW tDelay tIS+tCK+tIH tIS+tCK
+tIH ns
Average periodic Refresh Interval tREFI - 7.8 - 7.8 us 2
tREFI -3.9 -3.9 us 3
Rev. 0.1 / May. 2008 21
1
240pin Registered DDR2 SDRAM DIMMs
PACKAGE OUTLINE
64Mx72 (1 rank) - HMP564R[P]7FFP8C
Note) All dimensions are typical millimeter scale unless otherwise stated.
Front
30.0
4.0±0.1
133.35
63.0
5.175
5.175
55.0
5.0
Back
0.8
± 0.05
1.0
0.20
Detail of Contacts A
2.50 ± 0.20
Detail of Contacts B
2.50
1.50 ± 0.10
3.80
5.00
Detail-A Detail-B
3.0 3.0
10.0
17.80
PLL
Side
2.7 max.
(Front)
1.27±0.10
Register
Rev. 0.1 / May. 2008 22
1
240pin Registered DDR2 SDRAM DIMMs
PACKAGE OUTLINE
128Mx72 (1 rank) - HMP512R[P]7FFP4
Note) All dimensions are typical millimeter scale unless otherwise stated.
Front
30.0
4.0±0.1
133.35
63.0
5.175
5.175
55.0
5.0
Back
0.8
± 0.05
1.0
0.20
Detail of Contacts A
2.50 ± 0.20
Detail of Contacts B
2.50
1.50 ± 0.10
3.80
5.00
Detail-A Detail-B
Side
4.0 max
1.27 ± 0.10
3.0 3.0
10.0
17.80
PLL
Register Register
Rev. 0.1 / May. 2008 23
1
240pin Registered DDR2 SDRAM DIMMs
PACKAGE OUTLINE
512Mx72 (2 ranks) - HYMP151P7EFR4C
PACKAGE OUTLINE
512Mx72 (2 ranks) - HYMP151P7EFR4C
PACKAGE OUTLINE
256Mx72 (2 rank) - HMP525P7FFP4C
55.063.0 5.0
2X 3.00MIN
Front
1.27 ±0.10
4.00max
Side
1.0
0.35
0.8 ±0.05
2.50 ±0.20
Detail of Contacts A
Note) All dimensions are typical unless otherwise stated. Inches
Millimeters
4X FULL R
DETAIL-A DETAIL-B
128.95
133.35
2X
Ø2.50±
0.10
4X 4.0 ±0.1
2X 2.3 ±0.1
5.175
2X R1.00
10.00
17.80
30.00
0.05
Back
Register
PLL
Register
5.00
1.50 ±0.10
3.80
2.50
Detail of Contacts B
3.0 ±0.15
0.3 ±0.7
Rev. 0.1 / May. 2008 24
1
240pin Registered DDR2 SDRAM DIMMs
REVISION HISTORY
Revision History Date Remark
0.1 First Version Release May. 2008
