A5974D Up to 2.5 A step down switching regulator for automotive applications Features Qualified following the AEC-Q100 requirements (see PPAP for more details) 2.5 A DC output current Operating input voltage from 4 V to 36 V 3.3 V / (2%) reference voltage Output voltage adjustable from 1.235 V to 35 V Low dropout operation: 100% duty cycle 250 kHz internally fixed frequency Voltage feedforward Zero load current operation Internal current limiting Inhibit for zero current consumption Synchronization Protection against feedback disconnection Thermal shutdown HSOP8 - exposed pad Description The A5974D is a step down monolithic power switching regulator with a minimum switch current limit of 3.1 A so it is able to deliver up to 2.5 A DC current to the load depending on the application conditions. The output voltage can be set from 1.235 V to 35 V. The high current level is also achieved thanks to an HSOP8 package with exposed frame, that allows to reduce the Rth(JA) down to approximately 40 C/W. The device uses an internal p-channel DMOS transistor (with a typical RDS(on) of 250 m) as switching element to minimize the size of the external components. An internal oscillator fixes the switching frequency at 250 kHz. Having a minimum input voltage of 4 V only it fits the automotive applications requiring the device operation even in cold crank conditions. Pulse by pulse current limit with the internal frequency modulation offers an effective constant current short circuit protection. Application Dedicated to automotive applications Figure 1. Application schematic U1 VIN =4V TO 36V L1 C1 10uF 50V C2 68nF 50V VCC 6 VREF 2 SYNC 4 COMP INH R3 10K VOUT 1 FB GND 5 15uH TP2 VOUT A5974D R1 3 EX-PAD 9 5.6K 7 D1 STPS3L40U TP1 8 C3 100p C4 33nF C9 R2 3.3K 330uF small signal TP3 GND TP4 GND power plane May 2011 Doc ID 018774 Rev 1 1/46 www.st.com 46 Contents A5974D Contents 1 2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Datasheet parameters over the temperature range . . . . . . . . . . . . . . . . 8 5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 7 8 2/46 5.1 Power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 Voltages monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.3 Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.4 Current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.5 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.6 PWM comparator and power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.7 Inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.8 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Additional features and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 Feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.2 Output overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3 Zero load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Closing the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.1 Error amplifier and compensation network . . . . . . . . . . . . . . . . . . . . . . . . 16 7.2 LC filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.3 PWM comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Doc ID 018774 Rev 1 A5974D Contents 8.1 Component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.2 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.3 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.3.1 Thermal resistance RthJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.3.2 Thermal impedance ZTHJ-A(t) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.4 R.M.S. current of the embedded power MOSFET . . . . . . . . . . . . . . . . . . 29 8.5 Short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.6 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.7 Positive buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.8 Negative buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.9 Floating boost current generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.10 Synchronization example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.11 Compensation network with MLCC at the output . . . . . . . . . . . . . . . . . . . 38 8.12 External SOFT_START network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Doc ID 018774 Rev 1 3/46 Pin settings A5974D 1 Pin settings 1.1 Pin connection Figure 2. 1.2 /54 6## 39.# '.$ ).( 62%& #/-0 &" Pin description Table 1. 4/46 Pin connection (top view) Pin description N Pin Description 1 OUT 2 SYNCH 3 INH 4 COMP 5 FB 6 VREF 3.3 V VREF. No cap is requested for stability. 7 GND Ground. 8 VCC Unregulated DC input voltage. Regulator output. Master/slave synchronization. A logical signal (active high) disables the device. If INH not used the pin must be grounded. When it is open an internal pull-up disable the device. E/A output for frequency compensation. Feedback input. Connecting directly to this pin results in an output voltage of 1.23 V. An external resistive divider is required for higher output voltages. Doc ID 018774 Rev 1 A5974D Electrical data 2 Electrical data 2.1 Maximum ratings Table 2. Absolute maximum ratings Symbol Value Unit 40 V V V V8 Input voltage V1 OUT pin DC voltage OUT pin peak voltage at t = 0.1 s -1 to 40 -5 to 40 I1 Maximum output current int. limit. V4, V5 Analog pins 4 V -0.3 to VCC V -0.3 to 4 V 2.25 W Operating junction temperature range -40 to 150 C Storage temperature range -55 to 150 C Value Unit (1) C/W V3 INH V2 SYNCH PTOT TJ TSTG 2.2 Parameter Power dissipation at TA 60 C Thermal data Table 3. Symbol RthJA Thermal data Parameter Maximum thermal resistance junction-ambient 40 1. Package mounted on evaluation board Doc ID 018774 Rev 1 5/46 Electrical characteristics 3 A5974D Electrical characteristics TJ = -40 C to 125 C, VCC = 12 V, unless otherwise specified. Table 4. Electrical characteristics Symbol VCC RDS(on) IL fSW Parameter Test condition Operating input voltage range V0 = 1.235 V; I0 = 2 A Min Max Unit 36 V 0.250 0.5 3.1 3.6 4.1 A 212 250 280 kHz 100 % 1.235 1.272 V 3 5 mA 2.5 mA 4 MOSFET on resistance Maximum limiting current VCC = 5 V Switching frequency Duty cycle Typ 0 Dynamic characteristics (see test circuit) V5 4.4 V < VCC < 36 V, 20 mA < I0 < 2 A Voltage feedback 1.198 DC characteristics Iqop Total operating quiescent current Iq Quiescent current Iqst-by Total stand-by quiescent current Duty cycle = 0; VFB = 1.5 V Vinh > 2.2 V 50 100 A VC C = 36 V; Vinh > 2.2 V 50 100 A 0.8 V Inhibit Device ON INH threshold voltage Device OFF 2.2 V 3.5 V Error amplifier VOH High level output voltage VFB = 1 V VOL Low level output voltage VFB = 1.5 V Source output current VCOMP = 1.9 V; VFB = 1 V Io sink Sink output current VCOMP = 1.9 V; VFB = 1.5 V Ib Source bias current Io source gm 6/46 0.4 190 300 A 1 1.5 mA 2.5 DC open loop gain RL = Transconductance ICOMP = -0.1 mA to 0.1 mA; VCOMP = 1.9 V Doc ID 018774 Rev 1 V 50 4 A 65 dB 2.3 mS A5974D Electrical characteristics Table 4. Electrical characteristics (continued) Symbol Parameter Test condition Min Typ Max Unit VREF V 0.74 V 0.25 0.45 mA Synch function High input voltage VCC = 4.4 to 36 V; 2.5 Low input voltage VCC = 4.4 to 36 V; Slave synch current(1) Vsynch = 0.74 V Vsynch = 2.33 V 0.11 0.21 Master output amplitude Isource = 3 mA 2.75 3 V Output pulse width no load, Vsynch = 1.65 V 0.20 0.35 s Reference voltage IREF = 0 to 5 mA VCC = 4.4 V to 36 V 3.2 3.3 3.399 V Line regulation IREF = 0 mA VCC = 4.4 V to 36 V 5 10 mV Load regulation IREF = 0 mA 8 15 mV 18 35 mA Reference section Short circuit current 5 1. Guaranteed by design Doc ID 018774 Rev 1 7/46 Datasheet parameters over the temperature range 4 A5974D Datasheet parameters over the temperature range The 100% of the population in the production flow is tested at three different ambient temperatures (-40 C; +25 C, +125 C) to guarantee the datasheet parameters inside the junction temperature range (-40 C; +125 C). The device operation is so guaranteed when the junction temperature is inside the (-40 C; +150 C) temperature range. The designer can estimate the silicon temperature increase respect to the ambient temperature evaluating the internal power losses generated during the device operation (please refer to the Chapter 2.2). However the embedded thermal protection disables the switching activity to protect the device in case the junction temperature reaches the TSHTDWN (+150 C10 C) temperature. All the datasheet parameters can be guaranteed to a maximum junction temperature of +125 C to avoid triggering the thermal shutdown protection during the testing phase because of self heating. 8/46 Doc ID 018774 Rev 1 A5974D 5 Functional description Functional description The main internal blocks are shown in the device block diagram in Figure 3. They are: A voltage regulator supplying the internal circuitry. From this regulator, a 3.3 V reference voltage is externally available. A voltage monitor circuit which checks the input and the internal voltages. A fully integrated sawtooth oscillator with a frequency of 250 kHz 15%, including also the voltage feed forward function and an input/output synchronization pin. Two embedded current limitation circuits which control the current that flows through the power switch. The pulse-by-pulse current limit forces the power switch OFF cycle by cycle if the current reaches an internal threshold, while the frequency shifter reduces the switching frequency in order to significantly reduce the duty cycle. A transconductance error amplifier. A pulse width modulator (PWM) comparator and the relative logic circuitry necessary to drive the internal power. A high side driver for the internal P-MOS switch. An inhibit block for stand-by operation. A circuit to implement the thermal protection function. Figure 3. Block diagram 6## 42)--).' 6/,4!'%3 -/.)4/2 62%& "5&&%2 3500,9 4(%2-!, 3(54$/7. 6 6 ).()")4 ).( 0%!+ 4/ 0%!+ #522%.4 ,)-)4 #/-0 %! &" 07- $ 1 $2)6%2 #K 6 39.# &2%15%.#9 3()&4%2 /3#),,!4/2 '.$ 5.1 62%& ,0$-/3 0/7%2 /54 !-V Power supply and voltage reference The internal regulator circuit (shown in Figure 4) consists of a start-up circuit, an internal voltage pre-regulator, the Bandgap voltage reference and the Bias block that provides current to all the blocks. The Starter supplies the start-up currents to the entire device when the input voltage goes high and the device is enabled (inhibit pin connected to ground). The pre-regulator block supplies the Bandgap cell with a pre-regulated voltage VREG that has a very low supply voltage noise sensitivity. Doc ID 018774 Rev 1 9/46 Functional description 5.2 A5974D Voltages monitor An internal block continuously senses the Vcc, Vref and Vbg. If the voltages go higher than their thresholds, the regulator begins operating. There is also a hysteresis on the VCC (UVLO). Figure 4. Internal circuit 6## 34!24%2 02%2%'5,!4/2 62%' "!.$'!0 )# ")!3 62%& 5.3 Oscillator and synchronization Figure 5 shows the block diagram of the oscillator circuit. The clock generator provides the switching frequency of the device, which is internally fixed at 250 kHz. The frequency shifter block acts to reduce the switching frequency in case of strong overcurrent or short circuit. The clock signal is then used in the internal logic circuitry and is the input of the ramp generator and synchronizer blocks. The ramp generator circuit provides the sawtooth signal, used for PWM control and the internal voltage feed-forward, while the synchronizer circuit generates the synchronization signal. The device also has a synchronization pin which can work both as master and slave. Beating frequency noise is an issue when more than one voltage rail is on the same board. A simple way to avoid this issue is to operate all the regulators at the same switching frequency. The synchronization feature of a set of the A5974D is simply get connecting together their SYNCH pin. The device with highest switching frequency will be the MASTER and it provides the synchronization signal to the others. Therefore the SYNCH is a I/O pin to deliver or recognize a frequency signal. The synchronization circuitry is powered by the internal reference (VREF) so a small filtering capacitor ( 100 nF) connected between VREF pin and the signal ground of the Master device is suggested for its proper operation. However when a set of synchronized devices populates a board it is not possible to know in advance the one working as Master, so the filtering capacitor have to be designed for whole set of devices. When one or more devices are synchronized to an external signal, its amplitude have to be in comply with specifications given in the Table 4. The frequency of the synchronization signal must be, at a minimum, higher than the maximum guaranteed natural switching frequency of the device (275 kHz, see Table 4) while the duty cycle of the synchronization signal can vary from approximately 10% to 90%. The small capacitor under VREF pin is required for this operation. 10/46 Doc ID 018774 Rev 1 A5974D Functional description Figure 5. Oscillator circuit block diagram &2%15%.#9 &2%15%.#9 3()&4%2 3()&4%2 #,/#+ T )BIAS?OSC #,/#+ #,/#+ '%.%2!4/2 '%.%2!4/2 2!-0 2!-0 '%.%2!4/2 '%.%2!4/2 2!-0 39.#(2/.):!4/2 39.#(2/.):%2 39.# Figure 6. Synchronization example SYNCH OUT SYNCH OUT A5973D A5974D FB A5973D A5974D FB COMP COMP SS/INH SS/INH GND OUT SYNCH A5973D A5974D GND OUT SYNCH A5973D A5974D FB FB COMP SS/INH 5.4 COMP SS/INH GND GND Current protection The A5974D features two types of current limit protection: pulse-by-pulse and frequency foldback. The schematic of the current limitation circuitry for the pulse-by-pulse protection is shown in Figure 7. The output power PDMOS transistor is split into two parallel PDMOS transistors. The smallest one includes a resistor in series, RSENSE. The current is sensed through RSENSE and if it reaches the threshold, the mirror becomes unbalanced and the PDMOS is switched off until the next falling edge of the internal clock pulse. Due to this reduction of the ON time, the output voltage decreases. Since the minimum switch ON time necessary to sense the current in order to avoid a false overcurrent signal is too short to obtain a sufficiently low duty cycle at 250 kHz (see Chapter 8.5), the output current in strong overcurrent or short circuit conditions could be not properly limited. For this reason the switching frequency is also reduced, thus keeping the inductor current under its maximum Doc ID 018774 Rev 1 11/46 Functional description A5974D threshold. The frequency shifter (Figure 5) functions based on the feedback voltage. As the feedback voltage decreases (due to the reduced duty cycle), the switching frequency decreases also. Figure 7. Current limitation circuitry VCC RSENSE IOFF RTH DRIVER A1 IL A2 OUT A1/A2=95 I I NOT PWM AM00008v1 5.5 Error amplifier The voltage error amplifier is the core of the loop regulation. It is a transconductance operational amplifier whose non inverting input is connected to the internal voltage reference (1.235 V), while the inverting input (FB) is connected to the external divider or directly to the output voltage. The output (COMP) is connected to the external compensation network. The uncompensated error amplifier has the following characteristics: Table 5. Uncompensated error amplifier characteristics Description Values Transconductance 2300 S Low frequency gain 65 dB Minimum sink/source voltage 1500 A/300 A Output voltage swing 0.4 V/3.65 V Input bias current 2.5 A The error amplifier output is compared to the oscillator sawtooth to perform PWM control. 5.6 PWM comparator and power stage This block compares the oscillator sawtooth and the error amplifier output signals to generate the PWM signal for the driving stage. The power stage is a highly critical block, as it functions to guarantee a correct turn ON and turn OFF of the PDMOS. The turn ON of the power element, or more accurately, the rise time of the current at turn ON, is a very critical parameter. At a first approach, it appears that the faster the rise time, the lower the turn ON losses. However, there is a limit introduced by the recovery time of the recirculation diode. 12/46 Doc ID 018774 Rev 1 A5974D Functional description In fact, when the current of the power element is equal to the inductor current, the diode turns OFF and the drain of the power is able to go high. But during its recovery time, the diode can be considered a high value capacitor and this produces a very high peak current, responsible for numerous problems: Spikes on the device supply voltage that cause oscillations (and thus noise) due to the board parasites. Turn ON overcurrent leads to a decrease in the efficiency and system reliability. Major EMI problems. Shorter freewheeling diode life. The fall time of the current during turn OFF is also critical, as it produces voltage spikes (due to the parasites elements of the board) that increase the voltage drop across the PDMOS. In order to minimize these problems, a new driving circuit topology has been used and the block diagram is shown in Figure 8. The basic idea is to change the current levels used to turn the power switch ON and OFF, based on the PDMOS and the gate clamp status. This circuitry allows the power switch to be turned OFF and ON quickly and addresses the freewheeling diode recovery time problem. The gate clamp is necessary to ensure that VGS of the internal switch does not go higher than VGSmax. The ON/OFF Control block protects against any cross conduction between the supply line and ground. Figure 8. Driving circuitry VCC Vgsmax IOFF CLAMP GATE PDMOS DRAIN STOP DRIVE DRAIN ON/OFF CONTROL VOUT L OFF ESR ILOAD ON C ION AM00009v1 5.7 Inhibit function The inhibit feature is used to put the device in standby mode. With the INH pin higher than 2.2 V the device is disabled and the power consumption is reduced to less than 100 A. With the INH pin lower than 0.8 V, the device is enabled. If the INH pin is left floating, an internal pull up ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. The pin is also Vcc compatible. Doc ID 018774 Rev 1 13/46 Functional description 5.8 A5974D Thermal shutdown The shutdown block generates a signal that turns OFF the power stage if the temperature of the chip goes higher than a fixed internal threshold (15010 C). The sensing element of the chip is very close to the PDMOS area, ensuring fast and accurate temperature detection. A hysteresis of approximately 20 C keeps the device from turning ON and OFF continuously. 14/46 Doc ID 018774 Rev 1 A5974D Additional features and protection 6 Additional features and protection 6.1 Feedback disconnection If the feedback is disconnected, the duty cycle increases towards the maximum allowed value, bringing the output voltage close to the input supply. This condition could destroy the load. To avoid this hazardous condition, the device is turned OFF if the feedback pin is left floating. 6.2 Output overvoltage protection Overvoltage protection, or OVP, is achieved by using an internal comparator connected to the feedback, which turns OFF the power stage when the OVP threshold is reached. This threshold is typically 30% higher than the feedback voltage. When a voltage divider is required to adjust the output voltage (Figure 19), the OVP intervention will be set at: Equation 1 R1 + R2 V OVP = 1.3 * -------------------- * V FB R2 Where R1 is the resistor connected between the output voltage and the feedback pin, and R2 is between the feedback pin and ground. 6.3 Zero load Due to the fact that the internal power is a PDMOS, no boostrap capacitor is required and so the device works properly even with no load at the output. In this case it works in burst mode, with a random burst repetition rate. Doc ID 018774 Rev 1 15/46 Closing the loop 7 A5974D Closing the loop Figure 9. Block diagram of the loop 9&& LQWHUQDOVZLWFK /&ILOWHU / H[WHUQDOUHVLVWRUGLYLGHU 56(16( &287 5 3:0FRPSDUDWRU FRPSHQVDWLRQQHWZRUN )% &3 5& && 7.1 95() 5 HUURU DPSOLILHU Error amplifier and compensation network The output L-C filter of a step-down converter contributes with 180 degrees phase shift in the control loop. For this reason a compensation network between the COMP pin and GROUND is added. The simplest compensation network together with the equivalent circuit of the error amplifier are shown in Figure 10. RC and CC introduce a pole and a zero in the open loop gain. CP does not significantly affect system stability but it is useful to reduce the noise of the COMP pin. The transfer function of the error amplifier and its compensation network is: Equation 2 A V0 * ( 1 + s * R c * C c ) A 0 ( s ) = --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------2 s * R0 * ( C0 + Cp ) * Rc * Cc + s * ( R0 * Cc + R0 * ( C0 + Cp ) + Rc * Cc ) + 1 Where Avo = Gm * Ro 16/46 Doc ID 018774 Rev 1 A5974D Closing the loop Figure 10. Error amplifier equivalent circuit and compensation network + E/A COMP - FB RC CP CC V+ V R0 C0 0.8M 10pF Gm V RC CP CC The poles of this transfer function are (if Cc >> C0+CP): Equation 3 1 F P1 = ------------------------------------2 * * R0 * Cc Equation 4 1 F P2 = -------------------------------------------------------2 * * Rc * ( C0 + Cp ) whereas the zero is defined as: Equation 5 1 F Z1 = -----------------------------------2 * * Rc * Cc FP1 is the low frequency which sets the bandwidth, while the zero FZ1 is usually put near to the frequency of the double pole of the L-C filter (see below). FP2 is usually at a very high frequency. Doc ID 018774 Rev 1 17/46 Closing the loop 7.2 A5974D LC filter The transfer function of the L-C filter is given by: Equation 6 R LOAD * ( 1 + ESR * C OUT * s ) A LC ( s ) = ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------2 s * L * C OUT * ( ESR + R LOAD ) + s * ( ESR * C OUT * R LOAD + L ) + R LOAD where RLOAD is defined as the ratio between VOUT and IOUT. If RLOAD>>ESR, the previous expression of ALC can be simplified and becomes: Equation 7 1 + ESR * C OUT * s A LC ( s ) = --------------------------------------------------------------------------------------------2 L * C OUT * s + ESR * C OUT * s + 1 The zero of this transfer function is given by: Equation 8 1 F O = ---------------------------------------------------2 * * ESR * C OUT F0 is the zero introduced by the ESR of the output capacitor and it is very important to increase the phase margin of the loop. The poles of the transfer function can be calculated through the following expression: Equation 9 2 - ESR * C ( ESR * C ) -4*L*C OUT OUT OUT F PLC1, 2 = -----------------------------------------------------------------------------------------------------------------------------------------2 * L * C OUT In the denominator of ALC the typical second order system equation can be recognized: Equation 10 2 s + 2 * * n * s + 2 n If the damping coefficient is very close to zero, the roots of the equation become a double root whose value is n. Similarly for ALC the poles can usually be defined as a double pole whose value is: Equation 11 1 F PLC = ---------------------------------------------2 * * L * C OUT 7.3 PWM comparator The PWM gain is given by the following formula: 18/46 Doc ID 018774 Rev 1 A5974D Closing the loop Equation 12 V cc G PWM ( s ) = ------------------------------------------------------------( V OSCMAX - V OSCMIN ) where VOSCMAX is the maximum value of a sawtooth waveform and VOSCMIN is the minimum value. A voltage feed forward is implemented to ensure a constant GPWM. This is obtained by generating a sawtooth waveform directly proportional to the input voltage VCC. Equation 13 V OSCMAX - V OSCMIN = K * V CC Where K is equal to 0.076. Therefore the PWM gain is also equal to: Equation 14 1- = const G PWM ( s ) = --K This means that even if the input voltage changes, the error amplifier does not change its value to keep the loop in regulation, thus ensuring a better line regulation and line transient response. In summary, the open loop gain can be expressed as: Equation 15 R2 G ( s ) = G PWM ( s ) * -------------------- * A O ( s ) * A LC ( s ) R1 + R2 Example: Considering RC = 10 k, CC = 33 nF and CP = 100 pF, the poles and zeroes of A0 are: FP1 = 6 Hz FP2 = 150 kHz FZ1 = 480 Hz If L = 15 H, DCR =56 m, COUT = 330 F and ESR = 25 m, the poles and zeroes of ALC become: FPLC = 2.2 kHz FZ ESR= 20 kHz Finally R1 = 5.6 k and R2 = 3.3 k. The gain and phase bode diagrams are plotted respectively in Figure 11 and Figure 12. Doc ID 018774 Rev 1 19/46 Closing the loop A5974D Figure 11. Module plot Figure 12. Phase plot The cut-off frequency and the phase margin are: Equation 16 F C = 33KHz 20/46 Phase margin = 49 Doc ID 018774 Rev 1 A5974D Application information 8 Application information 8.1 Component selection Input capacitor The input capacitor must be able to support the maximum input operating voltage and the maximum RMS input current. Since step-down converters draw current from the input in pulses, the input current is squared and the height of each pulse is equal to the output current. The input capacitor has to absorb all this switching current, which can be up to the load current divided by two (worst case, with duty cycle of 50%). For this reason, the quality of these capacitors has to be very high to minimize the power dissipation generated by the internal ESR, thereby improving system reliability and efficiency. The critical parameter is usually the RMS current rating, which must be higher than the RMS input current. The maximum RMS input current (flowing through the input capacitor) is: Equation 17 2 2 * D- + D I RMS = I O * D - 2 --------------------2 Where is the expected system efficiency, D is the duty cycle and IO is the output DC current. This function reaches its maximum value at D = 0.5 and the equivalent RMS current is equal to IO divided by 2 (considering = 1). The maximum and minimum duty cycles are: Equation 18 V OUT + V F D MAX = -----------------------------------V INMIN - V SW and Equation 19 V OUT + V F D MIN = ------------------------------------V INMAX - V SW Doc ID 018774 Rev 1 21/46 Application information A5974D Where VF is the freewheeling diode forward voltage and VSW the voltage drop across the internal PDMOS. Considering the range DMIN to DMAX, it is possible to determine the max IRMS going through the input capacitor. Capacitors that can be considered are: Electrolytic capacitors: These are widely used due to their low price and their availability in a wide range of RMS current ratings. The only drawback is that, considering ripple current rating requirements, they are physically larger than other capacitors. Ceramic capacitors: If available for the required value and voltage rating, these capacitors usually have a higher RMS current rating for a given physical dimension (due to very low ESR). The drawback is the considerably high cost. Tantalum capacitors: Very good, small tantalum capacitors with very low ESR are becoming more available. However, they can occasionally burn if subjected to very high current during charge. Therefore, it is better to avoid this type of capacitor for the input filter of the device. They can, however, be subjected to high surge current when connected to the power supply. Table 6. List of ceramic capacitors for the A5974D Manufacturer Series Capacitor value () Rated voltage (V) TAIYO YUDEN UMK325BJ106MM-T 10 50 MURATA GRM42-2 X7R 475K 50 4.7 50 Output capacitor The output capacitor is very important to meet the output voltage ripple requirement. Using a small inductor value is useful to reduce the size of the choke but it increases the current ripple. So, to reduce the output voltage ripple, a low ESR capacitor is required. Nevertheless, the ESR of the output capacitor introduces a zero in the open loop gain, which helps to increase the phase margin of the system. If the zero goes to a very high frequency, its effect is negligible. For this reason, ceramic capacitors and very low ESR capacitors in general should be avoided. Tantalum and electrolytic capacitors are usually a good choice for this purpose. A list of some tantalum capacitor manufacturers is provided in Table 7.: Output capacitor selection. Table 7. Output capacitor selection Manufacturer Series Cap value (F) Rated voltage (V) ESR (m) Sanyo POSCAP(1) TAE 47 to 680 2.5 to 10 25 to 35 TV 68 to 330 4 to 6.3 25 to 40 TPS 100 to 470 4 to 35 50 to 200 KEMET T494/5 100 to 470 4 to 20 30 to 200 Sprague 595D 220 to 390 4 to 20 160 to 650 AVX 1. POSCAP capacitors have some characteristics which are very similar to tantalum. 22/46 Inductor Doc ID 018774 Rev 1 A5974D Application information The inductor value is very important as it fixes the ripple current flowing through the output capacitor. The ripple current is usually fixed at 20 - 40% of Iomax, which is 0.6 - 1.2 A with IOmax = 3 A. The approximate inductor value is obtained using the following formula: Equation 20 ( V IN - V OUT ) L = ---------------------------------- * T ON I where TON is the ON time of the internal switch, given by D * T. For example, with VOUT = 3.3 V, VIN = 12 V and IO = 0.9 A, the inductor value is about 12 H. The peak current through the inductor is given by: Equation 21 I I PK = I O + ----2 and it can be observed that if the inductor value decreases, the peak current (which must be lower than the current limit of the device) increases. So, when the peak current is fixed, a higher inductor value allows a higher value for the output current. In the Table 8.: Inductor selection, some inductor manufacturers are listed. Table 8. Inductor selection Manufacturer Series Inductor value (H) Saturation current (A) Coilcraft DO3316T 5.6 to 12 3.5 to 4.7 Coilcraft MSS1260T 5.6 to 15 3.5 to 8 WE-PD L 4.7 to 27 3.55 to 6 Wurth Elektronik 8.2 Layout considerations The layout of switching DC-DC converters is very important to minimize noise and interference. Power-generating portions of the layout are the main cause of noise and so high switching current loop areas should be kept as small as possible and lead lengths as short as possible. High impedance paths (in particular the feedback connections) are susceptible to interference, so they should be as far as possible from the high current paths. An layout example is provided in Figure 13 below. The input and output loops are minimized to avoid radiation and high frequency resonance problems. The feedback pin connections to the external divider are very close to the device to avoid pick-up noise. Another important issue is the ground plane of the board. Since the package has an exposed pad, it is very important to connect it to an extended ground plane in order to reduce the thermal resistance junction-to-ambient. Doc ID 018774 Rev 1 23/46 Application information A5974D Figure 13. Layout example &203(16$7,211(7:25.)$5 )520+,*+&855(173$7+6 (;7(1'('*5281'3/$1( 217+(%277206,'( WRRXWSXWYROWDJH 0,1,0816,=(2))(('%$&. 3,1&211(&7,21672$92,' 3,&.83 ,QKLELWVLJQDO 5 5 / $' 9LQ 9RXW &LQ ' &RXW *QG 9(5<60$//+,*+&855(17 &,5&8/$7,1*3$7+720,1,0,=( 5$',$7,21$1'+,*+)5(48(1&< 5(621$1&(352%/(06 287387&$3$&,725 ',5(&7/< &211(&7('72 +($9<*5281' &211(&7,2172 *5281'3/$1( 7+528*+9,$6 8.3 Thermal considerations 8.3.1 Thermal resistance RthJA RthJ-A is the equivalent static thermal resistance junction to ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient. For this device the path through the exposed pad is the one conducting the largest amount of heat. The static RthJA measured on the application is about 40 C/W. The junction temperature of device will be: Equation 22 T J = T A + Rth J -A * P TOT The dissipated power of the device is tied to three different sources: Conduction losses due to the not insignificant RDSON, which are equal to: Equation 23 2 P ON = R DSON * ( I OUT ) * D Where D is the duty cycle of the application. Note that the duty cycle is theoretically given by the ratio between VOUT and VIN, but in practice it is substantially higher than this value to 24/46 Doc ID 018774 Rev 1 A5974D Application information compensate for the losses in the overall application. For this reason, the switching losses related to the RDSON increases compared to an ideal case. Switching losses due to turning ON and OFF. These are derived using the following equation: Equation 24 ( T ON + T OFF ) P SW = V IN * I OUT * ------------------------------------ * F SW = V IN * I OUT * T SW * F SW 2 Where TRISE and TFALL represent the switching times of the power element that cause the switching losses when driving an inductive load (see Figure 14). TSW is the equivalent switching time. Figure 14. Switching losses Quiescent current losses. Equation 25 P Q = V IN * I Q Where IQ is the quiescent current. Example: - VIN = 12 V - VOUT = 3.3 V - IOUT = 2.5 A RDS(on) has a typical value of 0.25 @ 25 C and increases up to a maximum value of 0.5. @ 150 C. We can consider a value of 0.4 . TSW is approximately 70 ns. IQ has a typical value of 2.5 mA @ VIN = 12 V. The overall losses are: Doc ID 018774 Rev 1 25/46 Application information A5974D Equation 26 2 P TOT = R DSON * ( I OUT ) * D + V IN * I OUT * T SW * F SW + V IN * I Q = 2 = 0.4 * 2.5 * 0.3 + 12 * 2.5 * 70 * 10 -9 3 * 250 * 10 + 12 * 2.5 * 10 -3 1.3W The junction temperature of device will be: Equation 27 T J = T A + Rth J -A * P TOT Equation 28 T J = 60 + 1.3 * 42 115C 8.3.2 Thermal impedance ZTHJ-A(t) The thermal impedance of the system, considered as the device in HSO8 package soldered on the application board, takes on an important rule when the maximum output power is limited by the static thermal performance and not by the electrical performance of the device. Therefore the embedded power elements could manage an higher current but the system is already taking away the maximum power generated by the internal losses. In case the output power increases the thermal shutdown will be triggered because the junction temperature triggers the designed thermal shutdown threshold. The RTH is a static parameter of the package: it sets the maximum power loss which can be generated from the system given the operation conditions. If we suppose, as an example, TA = 60 C, 140 C is the maximum operating temperature before triggering the thermal shutdown and RTH = 40 C/W so the maximum power loss achievable with the thermal performance of the system will be: T- = T J MAX - T AMB P MAX DC = ---------------------------------------------- = 80 ------ = 2W R TH R TH 40 Figure 15. represents the estimation of Power losses for different output voltages at VIN=5V and TAMB=60C. The calculations are performed considering the RDS(on) of the power element equal to 0.4A 26/46 Doc ID 018774 Rev 1 A5974D Application information Figure 15. Power losses estimation (VIN = 5 V, fSW = 250 kHz) The red trace represents the maximum power which can be taken away as calculated above, whilst the rest of the traces are the total internal losses for different output voltage. The embedded conduction losses are proportional to the duty cycle required for the conversion. Assuming the input voltage constant, the switching losses are proportional to the output current while the quiescent losses can be considered as constant. As a consequence in Figure 15. the maximum power losses is for VOUT=3.3V where the system can manage a continuos output current up to 2.35 A. The device could deliver a continuos output current up to 2.5 A to the load, however the maximum power loss of 2 W is reached with an output current of 2.35 A, so the maximum output power is derated. Figure 16. plots the power losses for VIN=12V and main output rails. Figure 16. Power losses estimation (VIN = 12V, fSW = 250 kHz) Doc ID 018774 Rev 1 27/46 Application information A5974D At VIN=12V and VOUT=5V can deliver 2.5A continuously (see Figure 17.) because the total power loss is now lower than 2W (( switching loss + quiescent loss) < conduction loss). As a consequence, the calculation of the internal power losses must be done for each specific operating condition given by the final application. In applications where the current to the output is pulsed, the thermal impedance should be considered instead of the thermal resistance. The thermal impedance of the system could be much lower than the thermal resistance, which is a static parameter. As a consequence the maximum power losses can be higher than 2 W if a pulsed output power is requested from the load: T J MAX - T AMB T - = ------------------------------------P MAX ( t ) = ---------------Z TH ( t ) Z TH ( t ) So, depending on the pulse duration and its frequency, the maximum output current can be delivered to the load. The characterization of the thermal impedance is strictly dependent on the layout of the board. In Figure 17. the measurement of the thermal impedance of the evaluation board of the A5974D is provided. Figure 17. Measurement of the thermal impedance of the evaluation board 1RUPDOL]HGWHPSHUDWXUHULVH>&@ H H 7LPH>V@ As it can be see, for example, for load pulses with duration of 1 second, the actual thermal impedance is lower than 20 C/W. This means that, for short pulses, the device can deliver an higher output current value. 28/46 Doc ID 018774 Rev 1 A5974D 8.4 Application information R.M.S. current of the embedded power MOSFET As the A5974D embeds the high side switch and so the internal power dissipation is sometimes the bottleneck for the output current capability (refer to Chapter 8.3 for the estimation of the operating temperature). Nevertheless, as mentioned in the general description on page 1 the device can manage a continuos output current of 2.5 A in most of the application conditions. However the rated maximum RMS current of the power elements is 2 A, where: I RMS HS = I LOAD D and the real duty cycle D: V OUT + ( R DS ON LS + DCR ) I LOAD D = --------------------------------------------------------------------------------------------------V IN + ( R DS ON LS - R DS ON HS ) I LOAD Fixing the limit of 2 A for IRMS HS the maximum output current can be derived, as illustrated in Figure 18.. Figure 18. Maximum continuos output current vs. duty cycle 8.5 Short-circuit protection In overcurrent protection mode, when the peak current reaches the current limit, the device reduces the TON down to its minimum value (approximately 250 nsec) and the switching frequency to approximately one third of its nominal value even when synchronized to an external signal (see Section 5.4: Current protection). In these conditions, the duty cycle is strongly reduced and, in most applications, this is enough to limit the current to ILIM. In any event, in case of heavy short-circuit at the output (VO = 0 V) and depending on the Doc ID 018774 Rev 1 29/46 Application information A5974D application conditions (Vcc value and parasitic effect of external components) the current peak could reach values higher than ILIM. This can be understood considering the inductor current ripple during the ON and OFF phases: ON phase Equation 29 V IN - V out - ( DCR L + R DSON ) I I L TON = ------------------------------------------------------------------------------------ ( T ON ) L OFF phase Equation 30 - ( V D + V out + DCR L * I ) I L TOFF = --------------------------------------------------------------- ( T OFF ) L where VD is the voltage drop across the diode, DCRL is the series resistance of the inductor. In short-circuit conditions VOUT is negligible so during TOFF the voltage across the inductor is very small as equal to the voltage drop across parasitic components (typically the DCR of the inductor and the VFW of the free wheeling diode) while during TON the voltage applied the inductor is instead maximized as approximately equal to VIN. So the Equation 29 and the Equation 30 in overcurrent conditions can be simplified to: Equation 31 V IN - ( DCR L + R DSON ) I V IN I L TON = ---------------------------------------------------------------- ( T ON MIN ) --------- ( 250ns ) L L considering TON that has been already reduced to its minimum. Equation 32 - ( V D + V out + DCR L * I ) - ( V D + V out + DCR L * I ) I L TOFF = --------------------------------------------------------------- ( 3 T SW ) --------------------------------------------------------------- ( 12s ) L L considering that fSW has been already reduced to one third of the nominal. In case a short circuit at the output is applied and VIN = 12 V the inductor current is controlled in most of the applications (see Figure 19). When the application must sustain the short-circuit condition for an extended period, the external components (mainly the inductor and diode) must be selected based on this value. In case the VIN is very high, it could occur that the ripple current during TOFF (Equation 32) does not compensate the current increase during TON(Equation 31). The Figure 21 shows an example of a power up phase with VIN = VIN MAX = 36 V where IL TON > IL TOFF so the current escalates and the balance between Equation 31 and Equation 32 occurs at a current slightly higher than the current limit. This must be taken into account in particular to avoid the risk of an abrupt inductor saturation. 30/46 Doc ID 018774 Rev 1 A5974D Application information Figure 19. Short-circuit current VIN = 12 V Figure 20. Short-circuit current VIN = 24 V Figure 21. Short-circuit current VIN = 36 V Doc ID 018774 Rev 1 31/46 Application information 8.6 A5974D Application circuit Figure 22 shows the evaluation board application circuit, where the input supply voltage, VCC, can range from 4 V to 36 V and the output voltage is adjustable from 1.235 V to 6.3 V due to the voltage rating of the output capacitor,. Figure 22. Evaluation board application circuit 6<1& 73 9 73 5 10 / 9729 73 95() 9&& 6<1& & X) 9 & Q) 9 & S P& 5 . + & 10 9287 5 10 ' & Q) 9 5 . )% (;3$' *1' & N& Q 4 U( X+ 73 &203 ,1+ 5 10 10 *1' 9287 6736/8 9,1 -3 & 10 5 . & & 10 X 5 10 *1' VPDOOVLJQDO SRZHUSODQH 73 & 10 73 5 10 & 10 Table 9. Component list Reference C1 UMK325BJ106MM-T Description 10 F, 50 V C2 68 nF, 5%, 0603 C3 100 pF, 5%, 0603 C4 33 nF, 5%, 0603 C10 32/46 Part number POSCAP 6TVB330ML 330 H, 25 m R1 5.6 k, 1%, 0.1 W 0603 R2 3.3 k, 1%, 0.1 W 0603 R3 10 k, 1%, 0.1 W 0603 D1 STPS3L40U 3 A, 40 V L1 MSS1246T-153 15 H, IRMS 20C 2.85A Doc ID 018774 Rev 1 Manufacturer Taiyo Yuden Sanyo STMicroelectronics Coilcraft A5974D Application information Figure 23. PCB layout (component side) Figure 24. PCB layout (bottom side) Figure 25. PCB layout (front side) Doc ID 018774 Rev 1 33/46 Application information 8.7 A5974D Positive buck-boost regulator The device can be used to implement a step-up/down converter with a positive output voltage. The output voltage is given by: Equation 33 D V OUT = V IN ------------1-D where the ideal duty cycle D for the buck boost converter is: Equation 34 V OUT D = ----------------------------V IN + V OUT However, due to power losses in the passive elements, the real duty cycle is always higher than this. The real value (that can be measured in the application) should be used in the following formulas. The peak current flowing in the embedded switch is: Equation 35 I LOAD V IN D I LOAD I RIPPLE I SW = -------------- + -------------------- = -------------- + ----------- --------1-D 2 1 - D 2 L f SW while its average current is equal to: Equation 36 I LOAD I SW = -------------1-D This is due to the fact that the current flowing through the internal power switch is delivered to the output only during the OFF phase. The switch peak current must be lower than the minimum current limit of the overcurrent protection (see Table 4 for details) while the average current must be lower than the rated DC current of the device. As a consequence, the maximum output current is: Equation 37 I OUT MAX I SW MAX ( 1 - D ) where ISW MAX represents the rated current of the device. The current capability is reduced by the term (1-D) and so, for example, with a duty cycle of 0.5, and considering an average current through the switch of 3 A, the maximum output current deliverable to the load is 1.5 A. The figure below shows the schematic circuit of this topology for a 12 V output voltage and 5 V input. 34/46 Doc ID 018774 Rev 1 A5974D Application information Figure 26. Positive buck-boost regulator 6).6 6## /54 # N& 2 K $ 3403,5 !$ # P& 39.# 62%& '.$ $ 3403,5 6/546! 5 #/-0 # U& 6 #ERAMIC , U( K &" ).( # U& 6 - 34..%, K 6 6IN6 6OUT6 )OUT! %FFICIENCY 8.8 Negative buck-boost regulator In Figure 27, the schematic circuit for a standard buck-boost topology is shown. The output voltage is: Equation 38 D V OUT = - V IN ------------1-D where the ideal duty cycle D for the buck boost converter is: Equation 39 - V OUT D = ----------------------------V IN - V OUT The considerations given in Section 8.8 for the real duty cycle are still valid here. Also the Equation 35 till Equation 37 can be used to calculate the maximum output current. So, as an example, considering the conversion VIN = 12 V to VOUT = -5 V, ILOAD = 0.5 A: Equation 40 5 - = 0.706 D = --------------5 + 12 Equation 41 I LOAD 0.5 - = 1.7A I SW = -------------- = ----------------------1-D 1 - 0.706 An important thing to take into account is that the ground pin of the device is connected to the negative output voltage. Therefore, the device is subjected to a voltage equal to VIN-VO, which must be lower than 36 V (the maximum operating input voltage). Doc ID 018774 Rev 1 35/46 Application information A5974D Figure 27. Negative buck-boost regulator 6).6 6## , U( /54 $ #/-0 # U& 6 #ERAMIC 8.9 # U& # 6 #ERAMIC P& ! # N& 2 K 39.# 62%& '.$ &" ).( 6/54 6! K # U& 6 %32 3/4 K 6 Floating boost current generator The A5974D doesn't support a nominal boost conversion as this topology requires a low side switch, however a floating boost can be useful in applications where the load can be floating. A typical example is a current generator for LEDs driving as the LED does not require a connection to the ground. Figure 28. Floating boost topology 6). 6/54 3/4 Figure 29. 350mA LED boost current source TP6 VAC TP4 C9 4.7u 50V U1 D1 D4 VDC STPS3L40U TP1 L1 STPS3L40U VCC 2 SYNC 6 VREF 4 VAC TP3 330u D5 D6 36/46 STPS3L40U STPS3L40U KZM 330uF 25V (8x11,5) VIN = 12VAC C5 C6 10uF 220n R1 220K C2 KZM 330uF 25V (8x11,5) C1 330u L5973D 22uH 8 VOUT COMP INH 3 FB EX-PADGND 9 R4 1.8 1 D3 BZX84-C33 VLED+ NM C10 NM STPS3L40U ILED = 350mA C11 Rsense TP2 D2 VLED- R5 2K 5 7 C4 C7 NM R2 6.8k C8 470n BC327 C3 Q1 470n 1u R3 15 GND small signal GND TP5 Doc ID 018774 Rev 1 GND power A5974D Application information The device is powered from the output voltage so the maximum voltage drop across the LEDs and resistor sense is 36 V. The output voltage is given by: Equation 42 V IN V OUT = -----------1-D where the ideal duty cycle D for the boost converter is: Equation 43 V OUT - V IN D = ----------------------------V OUT As for positive and inverting buck boost (see Chapter 8.7 and Chapter 8.8.) the measured real duty cycle has to be used to calculate the switch current level. The peak current flowing in the embedded switch is: Equation 44 I LOAD I RIPPLE I LOAD V IN D - + -------------------- = -------------- + ----------- --------I SW = -------------1-D 2 1 - D 2 L f SW while its average current is equal to: Equation 45 I LOAD I SW = -------------1-D This is due to the fact that the current flowing through the internal power switch is delivered to the output only during the OFF phase. The switch peak current must be lower than the minimum current limit of the overcurrent protection (see Table 4 for details) while the average current must be lower than the rated DC current of the device. As a consequence, the maximum output current is: Equation 46 I OUT MAX I SW MAX ( 1 - D ) where ISW MAX represents the rated current of the device. Figure 29 shows a tested circuit to implement a boost current source for high current LED driving (350mA). To implement a boost conversion the LEDs string must be composed of a minimum device number having a total voltage drop larger than maximum input voltage. The input voltage can be either a DC or AC thanks to the input bridge rectifier. In case of a DC voltage source D1, D2, D3, D4, C1, C2 can be removed from the circuit and 1F capacitor value can be used for C5. Doc ID 018774 Rev 1 37/46 Application information 8.10 A5974D Synchronization example See Chapter 5.3 for details. Figure 30. Synchronization example 6). /54 6## #/-0 !$ 39.# 62%& 8.11 '.$ /54 6## &" #/-0 ).( !$ 39.# 62%& '.$ &" ).( Compensation network with MLCC at the output The A5974D standard compensation network (please refer to Figure 1. and Chapter 7) introduces a single zero and a low frequency pole in the system bandwidth, so an high ESR output capacitor must be selected to compensate the 180 degree phase shift given by the LC double pole. The selection of the output capacitor has to guarantee that the zero introduced by this component is inside the designed system bandwidth and close to the frequency of the double pole introduced by the LC filter. A general rule for the selection of this compound for the system stability is provided in Equation 47. Equation 47 1 - < bandwidth f Z ESR = ----------------------------------------------2 ESR C OUT f LC < f Z ESR < 10 f LC MLCCs (multiple layer ceramic capacitor) with values in the range of 10 F-22 F and rated voltages in the range of 10 V-25 V are available today at relatively low cost from many manufacturers. These capacitors have very low ESR values (a few m) and thus are occasionally used for the output filter in order to reduce the voltage ripple and the overall size of the application. However the zero given by the output capacitor falls outside the designed bandwidth and so the system becomes unstable with the standard compensation network. The Figure 31 shows the type III compensation network stabilizing the system with ceramic capacitors at the output (the optimum components value depends on the application). This configuration introduces two zeros and a low frequency pole in the designed bandwidth so guarantee a proper phase margin. An excel worksheet supporting the compensation network design with ceramic output capacitor is available at www.st.com in the A5974D product page. The tool, once selected the power components, properly places the singularities and calculates the value of the external components. 38/46 Doc ID 018774 Rev 1 A5974D Application information Figure 31. MLCC compensation network circuit R8 NM L1 VIN = 4V TO 36V 6 VREF 8 VCC 2 SYNC 4 C2 68nF 50V R1 COMP INH R6 220K 5 FB EX-PADGND 3 9 C5 R4 7 COUT D1 Q1 BC327 STPS3L40U C1 10uF 50V VOUT 1 VOUT C3 C11 68nF C8 470nF R2 GND GND small signal power plane C7 R5 C6 8.12 External SOFT_START network At start-up the device can quickly increase the current up to the current limit in order to charge the output capacitor. If soft ramp-up of the output voltage is required, an external soft-start network can be implemented as shown in Figure 32. The capacitor C is charged up to an external reference through R and the BJT clamps the COMP pin. This clamps the duty cycle, limiting the slew rate of the output voltage. Figure 32. Soft-start network example U1 VIN =4V TO 36V TP1 R2 220K R3 C1 BC327 50V Q1 TP3 C4 470nF L597xD L1 6 VREF 8 VCC 2 SYNC 4 COMP INH 3 VOUT 1 FB EX-PADGND 5 TP2 VOUT R1 9 C3 C2 7 D1 R4 C5 small signal GND TP4 GND power plane Doc ID 018774 Rev 1 39/46 Typical characteristics 9 A5974D Typical characteristics Figure 33. Line regulator Figure 34. Shutdown current vs junction temperature ,VKG P$ 9R 9 9FF 9 9R 9 7M & 9FF 9 7M & 9FF 9 Figure 35. Output voltage vs junction temperature 7M & Figure 36. Switching frequency vs junction temperature 9R 9 )VZ .+] 9FF 9 9FF 9 7M & Figure 37. Quiescent current vs junction temperature ,T P$ 9FF 9 '& 40/46 9FF 9 9R 9 7M & Doc ID 018774 Rev 1 7M & A5974D Typical characteristics Figure 38. Junction temperature vs output current VIN = 5 V Figure 39. Junction temperature vs output current VIN = 12 V Figure 40. Efficiency vs output current VIN = 12 V Figure 41. Efficiency vs output current VIN = 5 V Doc ID 018774 Rev 1 41/46 Package mechanical data 10 A5974D Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Table 10. HSOP8 mechanical data mm inch Dim. Min. Typ. A Min. Typ. 1.70 Max. 0.0669 A1 0.00 A2 1.25 b 0.31 0.51 0.0122 0.0201 c 0.17 0.25 0.0067 0.0098 D 4.80 4.90 5.00 0.1890 0.1929 0.1969 D1 3 3.1 3.2 0.118 0.122 0.126 E 5.80 6.00 6.20 0.2283 0.2441 E1 3.80 3.90 4.00 0.1496 0.1575 E2 2.31 2.41 2.51 0.091 e 0.10 0.00 0.0039 0.0492 0.095 0.099 1.27 h 0.25 0.50 0.0098 0.0197 L 0.40 1.27 0.0157 0.0500 k ccc 42/46 Max. 0 (min), 8 (max) 0.10 Doc ID 018774 Rev 1 0.0039 A5974D Package mechanical data Figure 42. Package dimensions $ Doc ID 018774 Rev 1 43/46 Ordering information 11 A5974D Ordering information Table 11. Ordering information Order codes Package A5974D Packaging Tube HSOP8 A5974DTR 44/46 Tape and reel Doc ID 018774 Rev 1 A5974D 12 Revision history Revision history Table 12. Document revision history Date Revision 17-May-2011 1 Changes Initial release Doc ID 018774 Rev 1 45/46 A5974D Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. 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