54F413DMQB. - NATIONAL SEMICONDUCTOR

54F413,74F413

54F413 74F413 64 x 4 First-In First-Out Buffer Memory with Parallel I/O

Literature Number: SNOS198A

TL/F/9541

54F/74F413 64 x 4 First-In First-Out Buffer Memory with Parallel I/O

January 1995

54F/74F413

64 x 4 First-In First-Out Buffer Memory with Parallel I/O

General Description

The ’F413 is an expandable fall-through type high-speed

First-In First-Out (FIFO) buffer memory organized as 64

words by four bits. The 4-bit input and output registers rec-

ord and transmit, respectively, asynchronous data in parallel

form. Control pins on the input and output allow for hand-

shaking and expansion. The 4-bit wide, 62-bit deep fall-

through stack has self-contained control logic.

Features

YSeparate input and output clocks

YParallel input and output

YExpandable without external logic

Y15 MHz data rate

YSupply current 160 mA max

YAvailable in SOIC, (300 mil only)

Commercial Military Package Package Description

Number

74F413PC N16E 16-Lead (0.300×Wide) Molded Dual-In-Line

54F413DM (Note 1) J16A 16-Lead Ceramic Dual-In-Line

Note 1: Military grade device with environmental and burn-in processing. Use suffix eDMQB.

Logic Symbol

TL/F/9541–1

Connection Diagram

Pin Assignment

for DIP

TL/F/9541–2

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Obsolete

Unit Loading/Fan Out

54F/74F

Pin Names Description U.L. Input IIH/IIL

HIGH/LOW Output IOH/IOL

D0–D3Data Inputs 1.0/0.667 20 mA/b0.4 mA

O0–O3Data Outputs 50/13.3 b1 mA/8 mA

IR Input Ready 1.0/0.667 20 mA/b0.4 mA

SI Shift In 1.0/0.667 20 mA/b0.4 mA

SO Shift Out 1.0/0.667 20 mA/b0.4 mA

OR Output Ready 1.0/0.667 20 mA/b0.4 mA

MR Master Reset 1.0/0.667 20 mA/b0.4 mA

Functional Description

Data InputÐData is entered into the FIFO on D0–D3in-

puts. To enter data the Input Ready (IR) should be HIGH,

indicating that the first location is ready to accept data. Data

then present at the four data inputs is entered into the first

location when the Shift In (SI) is brought HIGH. An SI HIGH

signal causes the IR to go LOW. Data remains at the first

location until SI is brought LOW. When SI is brought LOW

and the FIFO is not full, IR will go HIGH, indicating that more

room is available. Simultaneously, data will propagate to the

second location and continue shifting until it reaches the

output stage or a full location. If the memory is full, IR will

remain LOW.

Data TransferÐOnce data is entered into the second cell,

the transfer of any full cell to the adjacent (downstream)

empty cell is automatic, activated by an on-chip control.

Thus data will stack up at the end of the device while empty

locations will ‘‘bubble’’ to the front. The tPT parameter de-

fines the time required for the first data to travel from input

to the output of a previously empty device.

Data OutputÐData is read from the O0–O3outputs. When

data is shifted to the output stage, Output Ready (OR) goes

HIGH, indicating the presence of valid data. When the OR is

HIGH, data may be shifted out by bringing the Shift Out (SO)

HIGH. A HIGH signal at SO causes the OR to go LOW. Valid

data is maintained while the SO is HIGH. When SO is

brought LOW, the upstream data, provided that stage has

valid data, is shifted to the output stage. When new valid

data is shifted to the output stage, OR goes HIGH. If the

FIFO is emptied, OR stays LOW, and O0–O3remains as

before, i.e., data does not change if FIFO is empty.

Input Ready and Output Ready may also be used as

status signals indicating that the FIFO is completely full (In-

put Ready stays LOW for at least tPT) or completely empty

(Output Ready stays LOW for at least tPT).

Block Diagram

TL/F/9541–4

Obsolete

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Storage Temperature b65§Ctoa

150§C

Ambient Temperature under Bias b55§Ctoa

125§C

Junction Temperature under Bias b55§Ctoa

175§C

Plastic b55§Ctoa

150§C

VCC Pin Potential to

Ground Pin b0.5V to a7.0V

Input Voltage (Note 2) b0.5V to a7.0V

Input Current (Note 2) b30 mA to a5.0 mA

Voltage Applied to Output

in HIGH State (with VCC e0V)

Standard Output b0.5V to VCC

TRI-STATEÉOutput b0.5V to a5.5V

Current Applied to Output

in LOW State (Max) twice the rated IOL (mA)

Note 1: Absolute maximum ratings are values beyond which the device may

be damaged or have its useful life impaired. Functional operation under

these conditions is not implied.

Note 2: Either voltage limit or current limit is sufficient to protect inputs.

Recommended Operating

Conditions

Free Air Ambient Temperature

Military b55§Ctoa

125§C

Commercial 0§Ctoa

70§C

Supply Voltage

Military a4.5V to a5.5V

Commercial a4.5V to a5.5V

DC Electrical Characteristics

Symbol Parameter 54F/74F Units VCC Conditions

Min Typ Max

VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal

VCD Input Clamp Diode Voltage b1.5 V Min IIN eb

18 mA

VOH Output HIGH 54F 10% VCC 2.4 IOH eb

1mA

Voltage 74F 10% VCC 2.4 V Min IOH eb

1mA

74F 5% VCC 2.7 IOH eb

1mA

OL Output LOW 54F 10% VCC 0.5 V Min IOL e8mA

Voltage 74F 10% VCC 0.5 IOL e8mA

IH Input HIGH 54F 20.0

mA Max VIN e2.7V

Current 74F 5.0

IBVI Input HIGH Current 54F 100

mA Max VIN e7.0V

Breakdown Test 74F 7.0

ICEX Output HIGH 54F 250

mA Max VOUT eVCC

Leakage Current 74F 50

VID Input Leakage 74F 4.75 V 0.0 IID e1.9 mA

Test All Other Pins Grounded

IOD Output Leakage 74F 3.75 mA 0.0 VIOD e150 mV

Circuit Current All Other Pins Grounded

IIL Input LOW Current b0.4 mA Max VIN e0.5V

IOS Output Short-Circuit Current b20 b130 mA Max VOUT e0V

ICCH Power Supply Current 115 160 mA Max VOeHIGH

Obsolete

AC Electrical Characteristics

74F 54F 74F

TAea

25§CTA,V

CC eMil TA,V

CC eCom

Symbol Parameter VCC ea

5.0V CLe50 pF CLe50 pF Units

CLe50 pF

Min Typ Max Min Max Min Max

fmax Shift In Rate 10 8.0 10 MHz

fmax Shift Out Rate 10 8.0 10 MHz

tPLH Propagation Delay 1.5 44.0 1.5 50.0 1.5 48.0 ns

tPHL Shift In to IR 1.5 31.0 1.5 37.0 1.5 35.0

tPLH Propagation Delay 1.5 52.0 1.5 57.0 1.5 55.0 ns

tPHL Shift Out to OR 1.5 31.0 1.5 37.0 1.5 35.0

tPLH Propagation Delay 1.5 46.0 1.5 52.0 1.5 50.0 ns

tPHL Output Data Delay 1.5 34.0 1.5 39.0 1.5 37.0

tPLH Propagation Delay 1.5 27.0 1.5 33.0 1.5 31.0 ns

Master Reset to IR

tPLH Propagation Delay 1.5 30.0 1.5 34.0 1.5 32.0 ns

Master Reset to OR

AC Operating Requirements

74F 54F 74F

Symbol Parameter TAea

25§CTA,V

CC eMil TA,V

CC eCom Units

VCC ea

5.0V

Min Max Min Max Min Max

ts(H) Setup Time, HIGH or LOW 1.0 1.0 1.0

ts(L) Dnto SI 1.0 1.0 1.0 ns

th(H) Hold Time, HIGH or LOW 10.0 10.0 10.0

th(L) Dnto SI 10.0 10.0 10.0

tw(H) Shift In Pulse Width 5.0 5.0 5.0

tw(L) HIGH or LOW 10.0 10.0 10.0 ns

tw(H) Shift Out Pulse Width 7.5 8.5 7.5

tw(L) HIGH or LOW 10.0 10.0 10.0

tw(H) Input Ready Pulse Width, 7.5 8.5 7.5 ns

HIGH

tw(L) Output Ready Pulse Width, 5.0 5.0 5.0 ns

LOW

tw(L) Master Reset Pulse Width, 10.0 10.0 10.0 ns

LOW

trec Recovery Time, MR to SI 32.0 35.0 35.0 ns

tPT Data Throughput Time 0.9 1.0 1.0 ms

Obsolete

Ordering Information

The device number is used to form part of a simplified purchasing code where the package type and temperature range are

defined as follows:

74F 413 P C X

Temperature Range Family Special Variations

74F eCommercial QB eMilitary grade device with

54F eMilitary environmental and burn-in

processing

Device Type

Temperature Range

Package Code CeCommercial (0§Ctoa

70§C)

PePlastic DIP MeMilitary (b55§Ctoa

125§C)

DeCeramic DIP

Physical Dimensions inches (millimeters)

16-Lead Ceramic Dual-In-Line Package (D)

NS Package Number J16A

Obsolete

54F/74F413 64 x 4 First-In First-Out Buffer Memory with Parallel I/O

Physical Dimensions inches (millimeters) (Continued)

16-Lead (0.300×Wide) Molded Dual-In-Line Package (P)

NS Package Number N16E

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Obsolete

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