Features
•Provides Analog Transmission Line
Interface for T1 and E1 Applications
•Drop-in Replacement for CS61574 with
the Following Enhancements:
-Lower Power Consumption
-Transmitter Short-Circuit
Current Limiting
-Greater Transmitter Immunity
to Line Reflections
-Software Selection Between 75Ω and
120Ω E1 Output Options
-Internally Controlled E1 Pulse Width
-B8ZS/HDB3/AMI Encoder/Decoder
General Description
The CS61577 is a drop-in replacement for the
CS61574, and combines the complete analog transmit
and receive line interface for T1 or E1 applications in a
low power, 28-pin device operating from a +5V supply.
The CS61577 supports processor-based or stand-
alone operation and interfaces with industry standard
T1 and E1 framers.
The receiver uses a digital Delay-Locked-Loop which is
continuously calibrated from a crystal reference to pro-
vide excellent stability and jitter tolerance. The receiver
includes a jitter attenuator optimized for minimum delay
in switching and transmission applications. The trans-
mitter provides internal pulse shaping to insure
compliance with T1 and E1 pulse template specifica-
tions.
Applications
•Interfacing Network Equipment such as DACS and
Channel Banks to a DSX-1 Cross Connect
•Building Channel Service Un its
ORDERING INFORMATION
CS61577-IP1 28 Pin Plastic DIP
CS61577-IL1 28 Pin Plastic PLCC
MAY ’96
DS155PP2
1
Crystal Semiconductor Corporation
P. O. Box 17847, Austin, Texas, 78760
(512) 445-7222 FAX:(512) 445-7581
T1/E1 Line Interface
TTIP
TCLK
7RRING
RTIP
TRING
TGND
14
CONTROL
LINE RECEIVER
LINE DRIVER 15
3
2
6
4
RCLK 8
27
LLOOP
(SCLK)
2524
(INT)
LEN0 (SDI)
LEN1 (SDO)
LEN2
28 23
(CLKE)
TAOS
5
MODE
TPOS
[TDATA]
RPOS
[RDATA]
RNEG
[BPV]
TNEG
[TCODE]
MTIP
[RCODE]
DPM
[AIS]
LOS
12 21
RV+
22
RGND
13
19
20
17
11
18
16
MRING
[PCS]
XTALIN
9
XTALOUT
10
ACLKI
1
( ) = Pin Function in
Host Mode
[ ] = Pin Function in
Extended Hardware Mode
26
RLOOP
(CS)
R
E
M
O
T
E
L
O
O
P
B
A
C
K
AMI,
B8ZS,
HDB3,
CODER JITTER
ATTENUATOR
PULSE
SHAPER
CLOCK &
DATA
RECOVERY
SIGNAL
QUALITY
MONITOR DRIVER
MONITOR
TV+
L
O
C
A
L
L
O
O
P
B
A
C
K
Copyright
Crystal Semiconductor Corporation 1996
(All Rights Reserved)
CS61577
This document contains information for a new product. Crystal
Semic onductor re ser ves the rig ht to modify this pro duct without n otice.
Preliminary Product Information
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Min Max Units
DC Supply (referen ced to RGND=TGND=0V) RV+
TV+ -
-6.0
(RV+) + 0.3 V
V
Input Voltage, Any Pin (Note 1) Vin RGND-0.3 (RV+) + 0.3 V
Input Current, Any Pin (Note 2) Iin -10 10 mA
Ambient Operating Temperature TA-40 85 °C
Storage Temperature Tstg -65 150 °C
WARNING:Opera tions at or beyo nd thes e limits may result in permanent damage t o the device.
Normal operation is not guaranteed at these extremes.
Notes: 1. Excluding RTIP, RRI NG, which must stay within - 6V to (RV+ ) + 0.3V .
2. Transient curre nts of up to 1 00 mA will not cause SCR la tch-up. Also TTIP, TRING, TV+ and TGND
can withst and a continuous cur rent of 100 mA.
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Typ Max Units
DC Supply (Note 3) RV+, TV+ 4.75 5.0 5.25 V
Ambient Operating Temperature TA-40 25 85 °C
Power Consumption (Notes 4,5) PC-400500mW
Power Consumption (Notes 4,6) PC-230-mW
Notes: 3. TV+ must not exceed RV+ by more than 0.3V.
4. Power consumption while driving line load over operating temper ature range. Includes IC and load.
Digital input levels are within 10% of t he supply rails and digital outputs are driving a 50 pF
capacitive load.
5. Assumes 100% ones density and maximum line length at 5.25V.
6. Assumes 50% ones density and 300ft. line lengt h at 5.0V.
DIGITAL CHARACTERISTICS (TA = -40°C to 8 5°C; TV+, RV + = 5.0V ±5%; GND = 0V)
Parameter Symbol Min Typ Max Units
High-Level Input Voltage (Notes 7, 8)
PINS 1-4, 17, 18, 23-2 8 VIH 2.0 - - V
Low-Level Input Voltage (Notes 7, 8)
PINS 1-4, 17, 18, 23-2 8 VIL --0.8V
High-Level Output Voltage (Notes 7, 8, 9)
IOUT = -40 µA PINS 6-8, 11, 12, 25 VOH 4.0 - - V
Low-Level Output Voltage (Notes 7, 8, 9)
IOUT = 1.6 mA PINS 6-8, 11, 12, 23, 25 VOL --0.4V
Input Leakage Current (Except Pin 5) - - ±10 µA
Low-Level Input Voltage, PIN 5 VIL --0.2V
High-Level Input Voltage, PIN 5 VIH (RV+) - 0.2 - - V
Mid-Level I nput Voltage, PIN 5 (Note 10) VIM 2.3 - 2.7 V
Notes: 7. In Extended Hardware Mode, pins 17 and 18 are digital inputs. In Host Mode, pin 23 is
an open drain output and pin 25 is a tristate output.
8. This specification guarantees TTL compatibility (VOH = 2.4V @ IOUT = -40µA).
9. Output drive rs will drive CMOS logic levels int o a CMOS lo ad.
10. A s a n al ter nat ive t o su ppl yin g a 2.3- to -2.7 V in put, th is p in may b e le ft flo ati ng.
CS61577
2DS155PP2
ANALOG SPECIFICATIONS (TA = -40°C to 85°C; TV+, RV+ = 5.0 V ±5%; GND = 0 V)
Parameter Min Typ Max Units
Transmitter
AMI Output Pulse Amplitudes (Note 11)
E1, 75 Ω(Note 12)
E1, 120 Ω(Note 13)
T1, (FCC Part 68) (Note 14)
T1, DSX-1 (Note 15)
2.14
2.7
2.7
2.4
2.37
3.0
3.0
3.0
2.6
3.3
3.3
3.6
V
V
V
V
Load Presented To Transmitter Output (Note 11) - 25 - Ω
Jitter Added During Remote Loopback (Note 16)
10H z - 8kHz
8kH z - 40k Hz
10H z - 40k Hz
Broad Band
-
-
-
-
0.005
0.008
0.010
0.015
-
-
-
-
UI
UI
UI
UI
Power in 2kHz band about 772kHz (Notes 11, 17) 12.6 15 17.9 dBm
Power in 2kHz band about 1.544MHz (Notes 11, 17)
(referenced to power in 2kHz band at 772kHz) -29 -38 - dB
Positive to Negative Pulse Imbalance (Notes 11, 17) - 0.2 0.5 dB
Transmitter Output Impedance (Notes 17, 18) - - 10 Ω
Transmitter Short Circuit Current (Notes 11, 19) - - 50 mA RMS
Notes: 11. Using a 0.47 µF capacitor in series with the primary of a transformer recommended
in the Applications Section.
12. Pulse amplitude measured at the output of the transformer across a 75 Ω load for line length
settings LEN2/1/0 = 0/0/1 and 0/0/0. For LEN2/1/0 = 0/0/0 only, a 4.4 Ω resistor is required
in series with the transformer primary.
13. Pulse amplitude measured at the output of the transformer across a 120 Ω load for line length
setting LEN2/1/0 = 0/0/0.
14. Pulse amplitude measured at the output of the transformer across a 100 Ω load for line length
setting LEN2/1/0 = 0/1/0.
15. Pulse amplitude measured at the DSX-1 Cross-Connect for all line length settings from
LEN2/1/0 = 0/1/1 to LEN2/1/0 = 1/1/1.
16. Input signal to RTIP/RRING is jitter free. Values will reduce slightly if jitter free clock is input to TCLK.
17. Not production tested. Parameters guaranteed by design and characterization.
18. Measured between the TTI P and TRING pins at 772 kHz during marks and spaces.
19. Measured broadband through a 0.5 Ω resistor across the secondary of the transmitter transformer
during the transmission of an all ones data pattern with LEN2/1/0 = 0/0/0 or 0/0/1.
CS61577
DS155PP2 3
ANALOG SPECIFICATIONS (TA = -40°C to 85°C; TV+, RV+ = 5.0 V ±5%; GND = 0 V)
Parameter Min Typ Max Units
Receiver
RTIP/RRING Input Impedance - 50k - Ω
Sensitivity Below DSX (0dB = 2.4V) -13.6
500 -
--
-dB
mV
Loss of Signal Threshold - 0.30 - V
Data Decision Thr esholdT1, DSX-1 (Note 20)
T1, DSX-1 (Note 21)
T1, (FCC Part 68) and E1 (Note 22)
60
53
45
65
65
50
70
77
55
% of peak
% of peak
% of peak
Allowable Consecutive Zeros before LOS 160 175 190 bits
Receiver Input Jitter Tolerance (Note 23)
10kHz - 100kHz
2kHz
10Hz and below
0.4
6.0
300
-
-
-
-
-
-
UI
UI
UI
Jitter Attenuator
Jitter Attenuation Curve Corner Frequency (Notes 17, 24) - 6 - Hz
Attenuation at 10kHz Jitter Frequency (Notes 17, 24) - 50 - dB
Attenuator Input Jitter Tolerance (Before Onset
of FIFO Overflow or Underflow Protection) (Notes 17, 24) 12 23 - UI
Notes: 20. For input amplitude of 1.2 Vpk to 4. 14 Vpk.
21. For input amplitude of 0.5 Vpk to 1.2 Vpk and from 4.14 Vpk to RV+.
22. For input amplitude of 1.05 Vpk to 3.3 Vpk.
23. Jitter tolerance increases at lower frequencies. See Figure 11.
24. Attenuation measured with input jitter equal to 3/4 of measured jitter toler ance. Circuit attenuates
jitter at 20 dB/decade above the corner frequency. See Figure 12. Output jitter can increase
significantly when more than 12 UI’s are input to the attenuator. See discussion in the text section.
CS61577
4DS155PP2
E1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0 V ±5%;
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Parameter Symbol Min Typ Max Units
Crystal Frequency (Note 25) fc- 8.192000 - MHz
TCLK Frequency ftclk -2.048-MHz
TCLK Duty Cycle for LEN2/1/0 = 0/0/0 (Note 32) tpwh2/tpw2 40 50 60 %
ACLKI Frequency (Note 26) faclki -2.048-MHz
RCLK Duty Cy cle (Note 27) tpwh1/tpw1 45 50 55 %
Rise Time, All Dig ital Outputs (Note 28) tr- - 85 ns
Fall Time, All Digital Ou tputs (Note 28) tf- - 85 ns
TPOS/TNEG (TDATA) to TCLK Falling Setup Time tsu2 25 - - ns
TCLK Falling to TPOS/TNEG ( TDATA) Hold Time th2 25 - - ns
RPOS/RNEG Valid Before RCLK Falling (Note 29) tsu1 100 194 - ns
RDATA Valid Before RCLK Falling (Note 30) tsu1 100 194 - ns
RPOS/RNEG Valid Before RCLK Rising (Note 31) tsu1 100 194 - ns
RPOS/RNEG Valid After RCLK Falling (Note 29) th1 100 194 - ns
RDATA Valid Aft er RCLK Falling (Note 30) th1 100 194 - ns
RPOS/RNEG Valid After RCLK Rising (Note 31) th1 100 194 - ns
T1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%;
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Parameter Symbol Min Typ Max Units
Crystal Frequency (Note 25) fc- 6.176000 - MHz
TCLK Frequency ftclk -1.544-MHz
ACLKI Frequency (Note 26) faclki -1.544-MHz
RCLK Duty Cy cle (Note 27) tpwh1/tpw1 45 50 55 %
Rise Time, All Dig ital Outputs (Note 28) tr- - 85 ns
Fall Time, All Digital Ou tputs (Note 28) tf- - 85 ns
TPOS/TNEG (TDATA) to TCLK Falling Setup Time tsu2 25 - - ns
TCLK Falling to TPOS/TNEG ( TDATA) Hold Time th2 25 - - ns
RPOS/RNEG Valid Before RCLK Falling (Note 29) tsu1 150 274 - ns
RDATA Valid Before RCLK Falling (Note 30) tsu1 150 274 - ns
RPOS/RNEG Valid Before RCLK Rising (Note 31) tsu1 150 274 - ns
RPOS/RNEG Valid After RCLK Falling (Note 29) th1 150 274 - ns
RDATA Valid Aft er RCLK Falling (Note 30) th1 150 274 - ns
RPOS/RNEG Valid After RCLK Rising (Note 31) th1 150 274 - ns
Notes: 25. Crystal must meet specifications described in CXT6176/CXT8192 data sheet .
26. ACLKI provided by an external source or TCLK.
27. RCLK d uty cycle will b e 62.5% or 37.5 % when jitter atte nuator limit s are reached.
28. At max load of 1.6 mA and 50 pF.
29. Host Mode (CLKE = 1).
30. Extended Hardware Mode.
31. Hardware Mode, or Host Mode (CLKE = 0)
32. The transmitted pulse width does not depend on the TCLK duty cycle.
CS61577
DS155PP2 5
SWITCHING CHARACTERISTICS (TA = -4 0° to 85°C; TV+, RV+ = ±5%;
Inputs: Logic 0 = 0V, Logic 1 = RV+)
Parameter Symbol Min Typ Max Units
SDI to SCLK Setup Time tdc 50 - - ns
SCLK to SDI Hold Time tcdh 50 - - ns
SCLK Low Time tcl 240 - - ns
SCLK High Time tch 240 - - ns
SCLK Rise and Fall Time tr, tf- - 50 ns
CS to SCLK Setup Time tcc 50 - - ns
SCLK to CS Hold Time tcch 50 - - ns
CS Inactive Time tcwh 250 - - ns
SCLK to SDO Valid (Note 33) tcdv - - 200 ns
CS to SDO Hig h Z tcdz - 100 - ns
Input Valid To PCS Falling Setup Time tsu4 50 - - ns
PCS Rising to Input Invalid Hold Time th4 50 - - ns
PCS Active Low Time tpcsl 250 - - ns
Notes: 33. Output load capacitance = 50pF
Any Digital Output
t
r
t
f
10% 10%
90% 90%
Figure 1. Signal Rise and Fall Characteristics
RCLK
t
pw1
t
pwl1
t
pwh1
HOST MODE
(CLKE = 1)
EXTENDED
HARDWARE
MODE OR
HARDWARE
HOST MODE
(CLKE = 0)
MODE OR
RCLK
RPOS
RNEG
su1
h1
tt
RDATA
BPV
Figure 2. Recovered Clock and Data Switching Characteristics
CS61577
6DS155PP2
TCLK
TPOS/TNEG
t
su2
t
h2
t
pwh2
t
pw2
Figure 3. Transmit Clock and Data Switching Characteristics
tdc
t
cc
LSB LSB
MSB
CONTROL BYTE DATA BYTE
CS
SCLK
SDI
t
ch
t
cwh
t
cch
t
cdh
t
cl
t
cdh
Figure 4. Serial Port Write Timing Diagram
HIGH Z
CS
SCLK
SDO
CLKE = 1
t
cdz
cdv
t
Figu re 5 . Se rial Port Read Timi ng Di ag ram
PCS
VALID INPUT DATA
LEN 0 /1/2, TAOS,
RLOOP, LLOOP,
RCODE, TCODE
RLOO P, LL OOP,
th4
t
su4
t
pcsl
Fig ure 6. Exte nded Hardwa re Mo de Par allel Chip Sele ct Timin g Dia gra m
CS61577
DS155PP2 7
THEORY OF OPERATION
CS6157 7 Enhancements Relative to CS61574
Existing designs using the CS61574 can be con-
verted to the higher performance, pin-compatible
CS61577 with no changes to the PCB, external
comp onent or system software.
The CS61577 provides higher performance and
more feature s than the CS61574 includi ng:
•Selection of 75 Ω or 120 Ω E1 outpu t op-
tions under software or hardware control,
•50 mARMS transmitter sho rt-circuit cu rrent
limiting for E1 (per OFTEL OTR-001),
• intern ally controlled pu lse width for E1
output option s,
•35% lower power consumption,
•Increased tran smitter immun ity to signal re-
flections for improved signa l quality,
•Option al AMI, B8 ZS, HDB3 enc oder/de-
coder or external line codin g support,
•Receiver AIS (u nframed all on es) detect ion,
•Improved receiver Loss of Signal handling
(LOS set at power-up, reset upon receipt of
3 ones in 32 bit period s with no more than
15 consec utive zero s),
•Tra nsmitter TT IP and TRING outpu ts are
forced low when TCLK is static,
•The Driver Performan ce Monitor operates
over a wider range of input signal levels.
Introduc tion to Operati ng Modes
The CS61577 supports three operating modes
which are selected by the level of the MODE pin
as shown in Tables 1 and 2, Figure 7, and Figures
A1-A3 of the Applications section.
The modes are Hardware Mode, Extended Hard-
ware Mode, and Host Mode. In Hardware and
Exte nded Hardware Mode s, discrete pins are used
to configure and monitor the device. The Ex-
tended Hardware Mode provides a parallel chip
select input which latches the control inputs al-
lowing individual ICs to be configured using a
common set of control lines. In the Host Mode,
an external proc essor monito rs and configures the
device through a serial interface. There are thir-
teen multi-function pins whose functionality is
determined by the operating mode. (see Table 2).
Hardware
Mode Extended
Hardware
Mode
Host
Mod e
Control
Method Control
Pins Control Pins
with Parallel
Chip Select
Serial
Interface
MODE
Pin
Level
<0.2 V Floating or
2.5 V >(RV+)-0.2 V
Line
Coding External Internal-
AMI, B8ZS,
or HDB3
External
AIS
Detection No Yes No
Driver
Performance
Monitor
Yes No Yes
Table 1. Diff erences B etween Operati ng Modes
MODE
FUNCTION PIN HARDWARE EXTENDED
HARDWARE HOST
TRANSMITTER 3TPOS TDATA TPOS
4TNEG TCODE TNEG
RECEIVER/DPM
6 RNEG BPV RNEG
7RPOS RDATA RPOS
11 DPM AIS DPM
17 MTIP RCODE MTIP
18 MRING - MRING
CONTROL
18 - PCS -
23 LEN0 LEN0 INT
24 LEN1 LEN1 SDI
25 LEN2 LEN2 SDO
26 RLOOP RLOOP CS
27 LLOOP LLOOP SCLK
28 TAOS TAOS CLKE
Table 2. Pin Definitions
CS61577
8DS155PP2
TPOS
TNEG
RNEG
RPOS
TRANSMIT
TRANSFORMER
RRING RECEIVE
TRANSFORMER
CONTROL
CS62180B
FRAMER
CIRCUIT
TTIP
TDATA
RDATA
TRING
LINE DRIVER
AMI
B8ZS,
HDB3,
CODER
TRANSMIT
TRANSFORMER
RLOOP PCS LEN0/1/2LLOOPTAOS
CONTROL
HARDWARE MODE
EXTENDED HARDWARE MODE
HOST MODE
CONTROL
5
µ
P SER IAL POR T
RCODETCODE
CLKE
BPV AIS
JITTER
ATTENUATOR
DRIV ER MONITOR
LINE DRIVER
LINE RECEIVER
MTIP
MRING
DPM
RTIP
TTIP
TRING
T1 or E1
REPEATER
OR
MUX
CS61577
CS61577
TTIPTPOS
TNEG
RNEG
TRING
RPOS
RRING
RTIP
RLOOP LEN0/1/2LLOOPTAOS
CONTROL
DPM
DRIVER MONITOR
LINE DRIVER
LINE RECEIVER
MTIP
MRING
CS61577
CS62180B
FRAMER
CIRCUIT
JITTER
ATTENUATOR
TRANSMIT
TRANSFORMER
RECEIVE
TRANSFORMER
RECEIVE
TRANSFORMER
RRING
RTIP
AIS
DETECT JITTER
ATTENUATOR LINE
RECEIVER
Figur e 7. Ov erview o f Operat ing Mo des
CS61577
DS155PP2 9
Transmitter
The transmitter takes digital T1 or E1 input data
and drives appropriately shaped bipolar pulses
onto a transmission line through a 1:2 trans-
former. The transmit data (TPOS & TNEG or
TDATA) is supplied synchronously and sampled
on the falling edge of the input clock, TCLK.
Either T1 (DSX-1 or Network Interface) or E1
CCITT G.703 pulse shapes may be selected.
Pulse shaping and signal level are controlled by
"line length select" inp uts as shown in Table 3.
For T1 DSX-1 ap plicat ions, li ne lengths from 0 to
655 feet (as measured from the transmitter to the
DSX-1 cross connect) may be selected. The five
partition arrangement in Table 3 meets ANSI
T1.102 and AT&T CB-119 requirements when
usin g #22 ABAM cable. A typica l output pu lse is
shown in Figure 8. These pulse settings can also
be used t o meet CCITT pulse shape require ments
for 1.544 MHz operati on.
For T1 Network Interface applications, two addi-
tional opti ons are provided. Note that the o ptimal
pulse width for Part 68 (324 ns) is narrower than
the optimal pulse width for DSX-1 (350 ns). The
CS61577 automatically adjusts the pulse width
based upon the "line length" selection made.
The E1 G.703 pulse shape is supported with line
length selections LEN2/1/0=0/0/0 or
LEN2/1/0=0/0/1. As with the CS61574,
LEN2/1/0=0/0/0 supports the 120 Ω, 3 V output
option without external series resistors, but will
also support the 75 Ω, 2.37 V output option with
an external 4.4 Ω resistor in series with TTIP or
TRING. The new LEN2/1/0=0/0/1 code supports
the 75 Ω, 2.37 V output option without external
series resistors allowing for software selection be-
tween the two E1 out put o ptions. The puls e width
will meet the G.703 pulse shape template shown
in Figure 9, and sp ecified in Table 4.
The CS61577 will detect a static TCLK, and will
force TTIP and TRING low to prevent transmis-
sion when data is not present. When any transmit
control pin (TAOS, LEN0-2 or LLOOP) is tog-
gled, the transmitter outputs will require
approximately 22 bit periods to stabilize. The
transmitter will take longer to stabilize when
RLOOP is selected because the timing circuitry
must adjust to the new frequency.
500
1.0
0.5
0
-0.5
0
250 750 1000
NORMALIZED
AMPLITUDE
AT&T CB 119
SPECIFICATIONS
PULSE SHAPE
OUTPUT
TIME (nanoseconds)
ANSI T1.102,
Figure 8. Typi cal Pulse Shape at DSX-1 Cross Connect
LEN2 LEN1 LEN0 Option Selected Application
0 1 1 0-133 FEET DSX-1
ABAM
(AT&T 600B
or 600C )
100 133-266 FEET
101 266-399 FEET
110 399-533 FEET
111 533-655 FEET
000 75 Ω (with 4.4 Ω
resistor) & 120 ΩE1
CCITT G.703
001 75 Ω (without
4.4 Ω resistor)
0 1 0 FCC PART 68, OPT. A NETWORK
INTERFACE
011 ANSI T1.403
Table 3. Line Length Selection
CS61577
10 DS155PP2
Transmit All Ones Select
The transmitter provides for all ones insertion at
the frequency of TCLK. Transmit all ones is se-
lected when TAOS goes high, and causes
continuous ones to be transmitted on the line
(TTIP and TRING). In this mode, the TPOS and
TNEG (or T DATA) inpu ts are ignored. If Remote
Loopback is in effect, any TAOS request will be
ignored.
Receiver
The rece iver extrac ts data an d cl ock fro m an AMI
(Alternate Mark Inversion) coded signal and out-
puts clock and synchronized data. The receiver is
sensitive to signals over the entire range of
ABAM cab le len gth s and require s no equaliz ation
or ALBO (Automatic Line Build Out) circuits.
The signal is received on both ends of a center-
tapped, center-grounded transformer. The
transformer is center tapped on the IC side. The
clock and data recovery circuit exceeds the jitter
tolerance specifications of Publications 43802,
43801, AT&T 62411, TR-TSY-000170, and
CCIT T REC. G.823.
A block diagram of the receiver is shown in Fig-
ure 10. The two leads of the transformer (RTIP
and RRING) have opposite polarity allowing the
receiver to t r eat RTIP and RRING as unipolar sig-
nals. Comparators are used to detect pulses on
RTIP and R RING. The co mparat or threshol ds are
dynamically established at a percent of the peak
level (50% of peak for E1, 65% of peak for T1;
with the slicing level selected by LEN2/1/0 in-
puts).
The leading edge of an incoming data pulse trig-
gers the clock phase selector. The phase selector
chooses one of the 13 available phases which the
delay line produces for each bit period. The out-
269 ns
244 ns
194 ns
219 ns
488 ns
Nominal Pulse
0
10
50
80
90
100
110
120
-10
-20
Percent of
nominal
peak
voltage
Figure 9. Mask of the Pulse at the 2048 kbps Interface
For coaxial cable,
75Ω load and
transformer specified
in Application Section.
For shielded twisted
pair, 120Ω load and
transformer specified
in Application Section.
Nominal peak voltage of a m ark (pul s e) 2.37 V 3 V
Peak v oltage of a space (no pulse) 0 ±0.237 V 0 ±0.30 V
Nominal pulse widt h 244 ns
Ratio of the amplitudes of positive and negative
pulses at the cent er of the pulse interv al 0. 95 to 1.05*
Ratio of the widths of positive and negative
pulses at the nom i nal ha l f amplitude 0. 95 to 1.05*
* When configured with a 0.47 µF nonpolarized capacitor in series with the TX transformer
primary as shown in Figures A1, A2 and A3.
Table 4. CCITT G.703 Specificati ons
CS61577
DS155PP2 11
put from the phase selector feeds the clock and
data recovery circuits which generate the recov-
ered clock and sample the incoming signal at
appropriate intervals to recov er the data.
Data sampling will continue at the periods se-
lected by the phase selector until an incoming
pulse deviates enou gh to cause a new p hase to be
selected for data sampling. The phases of the de-
lay line are selected an d updat ed to allow as much
as 0.4 UI of jitter from 10 kHz to 100 kHz, with-
out error. The jitter tolerance of the receiver
exceeds that shown in Figure 11. Additionally,
this method o f clock and d ata recovery is tolerant
of long strings of consecutive zeros. The data
sampler will continuously sample data based on
its last input until a new pulse arrives to update
the clock phase selector.
The delay line is continuously calibrated using
the crystal oscillator reference clock. The delay
line produces 13 phases for each cycle of th e ref-
erence clock. In effect, the 13 phases are
analogous to a 20 MHz clock when the reference
cloc k is 1.544 MHz. Th is i mp lementat ion utilizes
the b ene fits of a 2 0 MHz clo ck for cl ock recovery
without actually having the clock present to im-
pede analog circuit performance.
In the Hardware Mode, data at RPOS and R NEG
should be sampled on the rising edge of RCLK,
the recovered clock. In the Extended Hardware
Mode, data at RDATA should be sampled on the
falling edge of RCLK. In the Host Mode, CLKE
determines the clock polarity for which output
data should be sam pled as show n i n Table 5.
10 1k 10k
1
100 100k700
.1
1
10
100
.4
28
300
300
PEAK-TO-PEAK
JITTER
(unit intervals)
JITTER FREQUENCY (Hz)
AT&T 62411
138
Minimum
Performance
Figure 11. Minimum Input Jitter Tolerance of Receiver
(Clock Reco very Circu it an d Jitt er A ttenua tor)
1 : 2 RTIP
RRING
RPOS
RNEG
RCLK
Data
Level
Slicer
Data
Sampling
& Cloc k
Extraction
Jitter
Attenuator
Edge
Detector
Clock
Phase
Selector
Continuously
Calibrated
Delay Line
Figu re 1 0. Re cei ver B loc k D iagr am
CS61577
12 DS155PP2
Loss of Signal
The receiver will indicate loss of signal after
power-up, reset or upon receiving 175 consecu-
tive zeros. A digital counter counts received
zeros, based on RCLK cycles. A zero is received
when the RTIP and RRING inputs are below the
input comparator slicing threshold level estab-
lished by the peak detector. After the signal is
removed for a period of time the data slicing
threshold level decays to approximately
300 mVpeak.
The receiver reports loss of signal by setting the
Loss of Signal pin, LOS, high. If the serial inter-
face is used, the LOS bit will be set and an
interrupt will be issued on INT (unless disabled).
LOS will return low (asserting the INT pin again
in Host Mode) upon receipt of 3 ones in 32 bit
periods with no more than 15 consecutive zeros.
Note that in the Host Mode, LOS is simultane-
ously available from both the register and pin 12.
RPOS/RNEG or RDATA are forced low during
LOS unless the jitter attenuator is disabled. (See
"Jitter Attenuator" section)
If ACLKI is present during the LOS st ate, ACLKI
is switched into the input of the jitter attenuator,
resulting in RCLK matching the frequency of
ACLKI. The jit ter atte nuator buffers any in stanta-
neous changes in phase between the last
recovered clock and the ACLKI reference clock.
This means that RCLK will smoothly transition
to the new frequency. If ACLKI is not present,
then the crysta l osci llator o f the jit ter atte nua tor is
forced to its center frequency. Table 6 shows the
status of RCLK upon LOS.
Jitter Attenuator
The jitter attenuator reduces wander and jitter in
the recovered clock signal. It consists of a 32-bit
FIFO, a crystal oscillator, a set o f load capacitors
for the crysta l, and control logic. The jitter attenu-
ator exce eds the jitter atten uation requi rements of
Publications 43802 and REC. G.742.
The jitter attenuator works in the following man-
ner. T he recovered cloc k and data a re input to the
FIFO with the recovered clock controlling the
FIFO’s write pointer. The crystal oscillator con-
trols the FIFO’s read po inter which reads data out
of the FIFO and presents it at RPOS and RNEG
(or RDATA). The update rate of the read pointer
is analogous to RCLK. By changing the load ca-
pacitance that the IC presents to the crystal, the
oscillation frequency is adjusted to the average
frequency of the recovered signal. Logic deter-
mines the phase relationship between the read and
write pointers and decides how to adjust the load
capacitance of the crystal. Thus the jitter attenu-
ator behaves as a first-order phase loc k loop. Jit ter
is absorbed in the FIFO according to the jitter
tr ansfer charac ter istic shown in Figure 12.
Crystal
present? ACLKI
present? Source of RCLK
No Yes ACLKI
Yes No Centered Crystal
Yes Yes ACLKI via the
Jitter Atte nua to r
Ta ble 6. R CLK St atus at LOS
MODE
(pi n 5) CLKE
(pin 28) DATA CLOCK Clock Edge fo r
Valid Data
LOW
(<0.2V) XRPOS
RNEG RCLK
RCLK Rising
Rising
HIGH
(>(V+) - 0.2V) LOW RPOS
RNEG
SDO
RCLK
RCLK
SCLK
Rising
Rising
Falling
HIGH
(>(V+) - 0.2V) HIGH RPOS
RNEG
SDO
RCLK
RCLK
SCLK
Falling
Falling
Rising
MIDDLE
(2.5V) X RDATA RCLK Falling
X = Don’t Care
Table 5 . Data Output/Clo ck Rela tionship
CS61577
DS155PP2 13
The FIFO in the jitter attenuator is designed to
prevent overflow and underflow. If the jitter am-
plitude becomes very large, the read and write
point ers may get very close together. Shoul d they
attempt to cross, the oscillator’s divide by four
circuit adjusts by performing a divid e by 3 1/ 2 or
divide by 4 1/2 to prevent the overflow or under-
flow. During thi s ac tivity, data will never be lost.
The 32-bit FIFO in the CS61577 attenuator al-
lows it to absorb jitter with minimum data delay
in T1 and E1 switching or transmission applica-
tions. Like the CS61574, the CS61577 will
tolerate large amplitude jitter (>23 UIpp) by
tracki ng ra ther t han a ttenuating it, preventing data
errors so that the jitter may be absorbed in exter-
nal frame buffers.
The jitter attenuator may be bypassed by pulling
XTALIN to RV+ th roug h a 1 kΩ res istor an d pro-
viding a 1.544 MHz (or 2.048 MHz) clock on
ACLKI. RCLK may exhibit quantization jitter of
approximately 1/13 UIpp and a duty cycle of ap-
proximately 30% (70%) when the attenuator is
disabled.
Local Loopback
Local loopback is selected by tak ing LLOOP, pin
27, high or by setting the LLOOP register bit via
the seria l interface.
The local loopback mode takes clock and data
presented on TCLK, TPOS, and TNEG (or
TDATA), sends it thro ugh th e j itter a tte nuator a nd
outputs it at RCLK, RPOS and RNEG (or
RDATA). If the jitter attenuator is disabled, it is
bypassed. Inputs to the transmitter are still trans-
mitted on TTIP and TRING, unless TAOS has
been selected in which case, AMI-cod ed continu-
ous ones are transmitted at the TCLK frequency.
The re ceiver RTIP and R RING inp uts are i gnored
when local loopback is in effect.
Remote Loopback
Remote loopback is selected by taking RLOOP,
pin 26, hi gh or by settin g the RLOOP register bit
via the serial interface.
In remot e loop back, the re covered clock an d data
input on RTIP and RRING are sent through the
jitt er attenuato r and back ou t on the lin e via TTIP
and TRING. Selecting remote loopback ove rrides
any TAOS request (see Table 6). The recovered
incoming signals are also sent to RCLK, RPOS
and RNEG (or RDATA). A remote loopback oc-
curs in response to RLOOP going high.
Attenuat ion in dB
Frequency in Hz
0
10
20
30
40
50
60
110
100
1 k 10 k
b) Maxi m um
Attenuati on
Limit
62411 Requirements
a) Mini mu m Attenuation Limit
Measured Perf ormance
Figu re 1 2. Ty pical Ji tter Tr ansf er Fun ction
RLOOP
Input
Signal
TAOS
Input
Signal
Source of
Data for
TTIP & TRING
Source of
Clock for
TTIP & TRING
00 TDATA TCLK
0 1 all 1s TCLK
1 X RTIP & RRING RTI P & RRING (RCLK)
Notes: 1. X = Don’t Care. The identified All Ones Select
input is ignored when the indicated loopback is
in effect.
2. Logic 1 indicates that Loopback or All Ones
opt ion is sele ct ed.
Table 7. Interactio n of RLOOP wi th TAOS
CS61577
14 DS155PP2
Simultaneous selection of local and remote loop-
back mode s is not valid (see Reset).
In the Extended Hardware Mode the transmitted
data is looped before the AMI/B8ZS/HDB3 en-
coder/ decoder du ring remot e loopbac k so that th e
transmitted signal matches the received signal,
even in the presence of received bipolar viola-
tions. Data output on RDATA is decoded,
however, if RCODE is low.
Alarm Indi cation Signal
In the Extended Hardware Mode, the receiver sets
the output pin AIS high when less than 3 zeros
are detected out of 2048 bit periods.
Line Code Encoder/Decod er
In th e Extend ed Hardware Mode , three line co des
are available: AMI, B8ZS and HDB3. The input
to the encoder is TDATA. The outputs from the
decoder are RDATA and BPV (Bipolar Violation
Strobe). The encoder and decoder are selected
using the LEN2, LEN1, LEN0, TCODE and
RCODE pins as shown in Table 8.
Parallel Chip Sele ct
In the Extended Hardware Mode, PCS can be
used to gate the digital control inputs: TCODE,
RCODE, LEN0, LEN1, LEN2, RLOOP, LLOOP
and TAOS. I nputs are accep ted on th ese p ins only
when PCS is low and will immediately change
the o pera ting stat e of th e device . The refore, wh en
cycling PCS to update the operating state, the
digital control inputs should be stable for the en-
tire PCS low period. The digital control inputs are
ignored when PCS is high
Driver Performance Monitor
To aid in early detection and easy isolation of
non-functioning links, the IC is able to monitor
transmit drive performance and report when the
driver is no longer operational. This feature can
be used to monitor either the device’s perform-
ance or the performance of a neighboring driver.
The driver performance monitor indicator is nor-
mally low, and goes high upon detecting a driver
failure.
The driver performance monitor consists of an ac-
tivity det ect or th at mon ito rs t he t ransm itted s ign al
when MTIP is connected to TTIP and MRING is
connected to TRING. DPM will go high if the
absolute difference between MTIP and MRING
does not transition above or below a threshold
level within a time-out period. In the Host Mode,
DPM is ava ilable from th e regist er and pin 11 .
When ever more t han on e line in terface IC reside s
on t he sa me ci rcuit bo ard, th e effectiveness of the
driver perfor mance monitor can be m aximized by
having each IC monitor performance of a neigh-
boring IC, rather than having it monitor its own
performance. Note that a CS61577 can not be
used to monitor a CS61574 due to output stage
differences.
LEN 2/1/0
000 010-111
TCODE
(Transmit
Encoder
Selection)
LOW HDB3
Encoder B8ZS
Encoder
HIGH AMI Encoder
RCODE
(Receiver
Decoder
Selection)
LOW HDB3
Decoder B8ZS
Decoder
HIGH AMI Decoder
Table 8. Encoder/Decoder Selection
CS61577
DS155PP2 15
Serial Interface
In the Host Mode, pins 23 through 28 serve as a
microprocessor/microcontroller interface. One
on-board register can be written to via the SDI
pin or re ad fro m v ia the SDO p in a t th e clock rat e
determined by SCLK. Through this register, a
host controller can be used to control operational
characteristics and monitor device status. The se-
rial port read/write timing is independent of the
system transmit and receive timing.
Data transfers are initiated by taking the chip se-
lect input, CS, low (CS must initially be high).
Address and input data bits are clocked in on the
rising edge of SCLK. The clock edge on which
output data is stable and valid is determined by
CLK E as sh own in Ta b le 5. D at a tr an sf er s are t er-
minated by setting CS high. CS may go high no
sooner than 50 ns after the rising edge of the
SCLK cycle corresponding to the last write bit.
For a serial data read, CS may go high any time
to terminate the output.
Figure 13 shows the timing relationships for data
transfers when CLKE = 1. When CLKE = 1, dat a
bit D7 is held until the falling edge of the 16th
clock cycle . When CLKE = 0, dat a b it D7 i s held
until t he risin g edg e of t he 17t h c lock cycl e. SDO
goes High-Z after CS goes high or at the end of
the hold period of data bit D7.
An addre ss/command by te, shown in Table 9, pre-
cedes a data register. The first bit of the
addre ss/c ommand byt e d eter mines wheth er a r ead
or a write is requested. The next six bits contain
the address. The line interface responds to address
16 (001000 0). The last bit is igno red.
The data register, shown in Table 10, ca n be writ-
ten to the serial port. Data is input on the eight
clock cycles immediately following the ad-
dress/command byte. Bits 0 and 1 are used to
clear an interrupt issued from the INT pin, which
occurs in response to a loss of signal or a proble m
with the output dri ver.
CS
SCLK
SDO
SDI
D6D5D4D3D2D1D0 D7
0
0
D7D6D5D4D3D2D1D0
Address/Command Byte
Data Inpu t/ Ou tput
00 01 0
R/W
Figure 13. Input/Output Timing
LSB, first bit 0 R/W Read/Write Select; 0 = write, 1 = read
1 ADD0 LSB of address, Must be 0
2 ADD1 Must be 0
3 ADD2 Must be 0
4 ADD3 Must be 0
5 ADD4 Must be 1
6 - Reserved - Mus t be 0
Table 9. Address/Command Byte
LSB: firs t bit i n 0 c lr LOS Cle ar Loss of Signal
1 c lr DPM Clear Driver Performance Monitor
2 LEN 0 Bit 0 - Li n e Le ngt h Se le c t
3 LEN 1 Bit 1 - Li n e Le ngt h Se le c t
4 LEN2 Bit 2 - Line Lenght Select
5 RLOOP Remote Loopback
6 LLOO P Local Loopbac k
MSB: last bit in 7 TAOS Transmit All Ones Select
NOTE: Setting 5, 6, & 7 to 101 or 111 puts the CS61577 into a
factory test mode.
Table 10. Input Data Register
CS61577
16 DS155PP2
Writing a "1" to either "Clear LOS" or "Clear
DPM" ov er the serial interface has three effects:
1) The current i nterrupt on the serial i nterface
will be cleared. (Note t hat simp ly reading
the register b its will not clear the i nter-
rupt).
2) Output data bits 5, 6 and 7 will be reset as
appropriate.
3) Future interrupts for the correspondin g LOS
or DPM will be prevented from occurring.
Writing a "0" to either "Clear LOS" or "Clear
DPM" enables the corresponding interrupt for
LOS or DPM.
Input bits 5/6/7=111 and 5/6/7=101 are the same
request, and cause the line interface to enter into
the factory test mode. In other words, when
RLOOP=1 (Bit 5) and TAOS=1 (Bit 7), LOOP
(Bit 6) is a don’t care. For normal operation,
RLOOP and TAOS should not be simultaneously
selected via the serial interface.
Output data from the serial interface is presented
as shown in Ta bles 11 and 12. Bits 2, 3 and 4 can
be read to verify line length selection. Bits 5, 6
and 7 must be decoded. Codes 101, 110 and 111
(Bits 5, 6 and 7) indicate intermittent losses of
signal and/or driver problems.
SDO goes to a high impedance state when not in
use. SDO and SDI may be tied together in appli-
cations where the host processor has a
bi-dire ctional I/O port.
Power On Reset / Reset
Upon power-up, the IC is held in a static state
until the supply crosses a threshold of approxi-
mately 3 Volts. When this threshold is crossed,
the d ev ice will delay for ab out 10 ms to al low the
power supply to reach operating voltage. After
this delay, calibration of the delay lines used in
th e transmit and re ceive sections commences. The
delay lines can be calibrated only if a reference
clock is present. The reference clock for the re-
ceiver is provided by the crystal oscillator, or
ACLKI if the oscillator i s disabled. The reference
clock for the transmitter is provided by TCLK.
The initial calibration should take less than
20 ms.
In operation, th e delay lines are continuously cali-
brated, making the performance of the device
inde penden t of power suppl y or tempe rature vari-
ations. The continuous calibration function
forgoes any req uirement t o reset the lin e interface
when in operation. However, a reset function is
available whi ch will cle ar all registe r s.
In the Hardware and Extended Hardware Modes,
a reset request is made by simultaneously setting
both the RLOOP and LLOOP pins high for at
leas t 200 ns. Reset will initiate on th e falling edge
of the reset request (falling edge of RLOOP and
LLOOP). In t he Host Mo de, a reset is ini tia ted by
simultaneously writing RLOOP and LLOOP to
LSB: fi rst bi t in 0 LOS Loss of Sig nal
1 DPM Driver Performance Monitor
2 LEN0 Bit 0 - Lin e Length Selec t
3 LEN1 Bit 1 - Lin e Length Selec t
4 LEN2 Bit 2 - Lin e Lenght Selec t
Table 11. Output Data Bits 0 - 4
Bits Status
567
0 0 0 Reset has occurred or no program input.
001TAOS in effect.
0 1 0 LLOOP in effect.
0 1 1 TAOS/LLOOP in effect.
1 0 0 RLOOP in effect
1 0 1 DPM ch ang ed st at e si n ce l as t "c l ear DP M "
occured.
1 1 0 LOS changed state since last "clear LOS"
occured.
1 1 1 LOS and D PM have chang ed st ate si nce
last "clear LOS" and "clear DPM".
Table 12. Coding for Serial Output bits 5,6,7
CS61577
DS155PP2 17
the r egister. In either mode, a r eset will set all reg-
isters to 0 and force the oscillator to its center
frequency before initiating calibration. A reset
will also set LOS h igh.
Power Supply
The d ev ice operate s from a single +5 Vol t supply.
Separate pins for transmit and receive supplies
provide internal isolation. These pins should be
connected externally near the device and decou-
pled to their respective grounds. TV+ must not
exceed RV+ by more than 0.3V.
Decoupling and filtering of the power supplies is
crucial for the proper operation of the analog cir-
cuits in both th e transmit and rece ive path s. A 1.0
µF capacitor should be connected between TV+
and TGND, and a 0.1 µF capacitor sh ould be co n-
nected between RV+ and RGND. Use mylar or
ceramic capacitors and place them as closely as
possible to their respective power supply pins. A
68 µF tantalum capacitor should be added close
to the RV+/RGND supply. Wire-wrap bread-
boarding of the line interface is not recommende d
because lead resistance and inductance serve to
defeat the function of the decoupling capacitors.
Schematic & Layout Review Service
Confirm Optimum
Schematic & Layout
Before Building Your Board.
For Our Free Review Service
Call Applications Engineering.
Call:(512)445-7222
CS61577
18 DS155PP2
PIN DESCRIPTIONS
Hardware Mode
Extended Hardware Mode
top
view
22
20
24
19
21
23
25
327242628
1
12 14 16 18
13 15
17
8
6
10
5
7
9
11
ACLKI
TCLK TAOS
TPOS LLOOP
TNEG RLOOP
MODE LEN2
RNEG LEN1
RPOS LEN0
RCLK RGND
XTALIN RV+
XTALOUT RRING
DPM RTIP
LOS MRING
TTIP MTIP
TGND TRING
TV+
1
2
3
4
5
6
7
8
9
10
11
12
14
13
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ACLKI TAOS
TCLK LLOOP
TPOS RLOOP
TNEG LEN2
MODE LEN1
RNEG LEN0
RPOS RGND
RCLK RV+
XTALIN RRING
XTALOUT RTIP
DPM MRING
LOS MTIP
TTIP TRING
TGND TV+
CS61577
DS155PP2 19
Host Mode
1
2
3
4
5
6
7
8
9
10
11
12
14
13
28
27
26
25
24
23
22
21
20
19
18
17
16
15
top
view
22
20
24
19
21
23
25
327242628
1
12 14 16 18
13 15
17
8
6
10
5
7
9
11
ACLKI CLKE
TCLK SCLK
TPOS CS
TNEG SDO
MODE SDI
RNEG INT
RPOS RGND
RCLK RV+
XTALIN RRING
XTALOUT RTIP
DPM MRING
LOS MTIP
TTIP TRING
TGND TV+
ACLKI
TCLK CLKE
TPOS SCLK
TNEG CS
MODE SDO
RNEG SDI
RPOS INT
RCLK RGND
XTALIN RV+
XTALOUT RRING
DPM RTIP
LOS MRING
TTIP MTIP
TGND TRING
TV+
CS61577
20 DS155PP2
Power Supplies
RGND - Gro und, Pin 22.
Power supply ground for all subcircuits except the transmit driv er; typically 0 Volts.
RV+ - Power Supply, Pin 21.
Power supply for all subcircuits except the transmit dri ver; typically +5 Volts.
TGND - Ground, Transmit Driver, Pin 14.
Power supply ground for the transmit dri ver; typically 0 Volts.
TV+ - Power Supply, Transmit Driver, Pin 15.
Power supply fo r the tran smit driver; typ ically +5 Vol ts. T V+ mus t not exce ed RV+ by more than
0.3 V.
Oscillator
XTALIN, XTALOUT - Crystal Connecti ons, Pins 9 and 10.
A 6.1 76 MHz (or 8. 19 2 MHz) cryst al sh ould b e c onn ected acro ss t hese pin s. If a 1.5 44 MHz (or
2.048 MHz) clock is provided on ACLKI (pin 1), the jitter attenuator may be disabled by tying
XTALIN, Pin 9 to RV+ through a 1 kΩ resistor, and floating XTALOUT, Pin 10.
Overdriving the oscillator with an external clock is not supported.
Control
ACLKI - Alternate External Clock Input, Pin 1.
A 1.544 MHz (or 2.0 48 MHz) clock may be in put to ACLKI, or this pin must be tied to ground.
During LOS, the A C LKI input signal, if present, is output on RCLK through the jitter attenuator.
CLKE - Clock Edge, Pin 28. (Host Mode)
Settin g CLKE to logi c 1 causes RPOS and RNEG to be valid on the falling edge of RCLK, and
SDO to be valid on the rising ed ge of SCLK. Conversely, setti ng CLKE to logic 0 causes RPOS
and RNEG to be valid on the rising edge of RCLK, and SDO to be valid on the falling edge of
SCLK.
CS - Chip Select, Pin 26. (Host Mode)
This pin must transition from high to low to read or write the serial port .
INT - Receive Alarm Interrupt, Pin 23. (Host Mode)
Goes low when LOS or DPM change state to flag the host processor. INT is cleared by writing
"clear LOS" or "c lea r DPM" t o t he regist er. INT is an o pen dra in out put an d shou ld b e tied t o th e
power supply th rough a resis tor.
CS61577
DS155PP2 21
LEN0, LEN1, LEN2 - Line Length Selection, Pins 23, 24 and 25. (Hardware and Extended
Hardware Modes)
Determine s the shape and amplitu de of the tran smitted puls e to acco mmodate several cab le types
and lengths. See Table 3 for information on line length selection. Also controls the receiver
slicing level and the line code in Extended Hardware Mode.
LLOOP - Local Loopback, Pin 27. (Hardware and Extended Hardware Modes)
Settin g LL OOP to a logic 1 rou tes the transmit clock and d ata throug h the jitter attenu ator to the
receive clock and data pins. TCLK and TPOS/TNEG (or TDATA) are still transmitted unless
overridden by a TAOS request. Inputs on RTIP and RRING are ignored.
MODE - Mode Select, Pin 5.
Driving the MODE pin high puts the line interface in the Host Mode. In the host mode, a serial
control port is used to control the line interface and determine its status. Grounding the MODE
pin puts the line interface in the Hardware Mode, where configuration and status are controlled
by discrete pins. Floating the MODE pin or driving it to +2.5 Vselects the Extended Hardware
Mode, where configuration and status are controlled by discrete pins. When floating MODE,
there s hould be no externa l load on th e pin. MODE defines the st atus of 13 pins (see Table 2).
PCS - Parallel Chip Select, Pin 18. (Extended Hardware Mode)
Settin g PCS high ca uses th e line interface to ignore the T CODE, RCODE, L EN0, L EN1, LEN2,
RLOOP, LLOOP and TAOS inputs.
RCODE - Receiver Decoder Select, Pin 17. (Extended Hardware Mode)
Settin g RCODE low enables B8ZS or HDB3 zero substitution in the receiver decoder. Setting
RCODE high enables the AMI receiver decoder (see Table 8).
RLOOP - Remote Loopback, Pin 26. (Hardware and Extended Hardware Modes)
Setting RLOOP to a logic 1 causes the recovered clock and data to be sent through the jitter
attenuator (if active) and through the driver back to the line. The recovered signal is also sent to
RCLK and RPOS/RNEG (or RDATA). Any TAOS request is ignored. In the Host Mode,
simultaneous selection of RLOOP & TAOS enables a factory test mode.
Simultaneously taking RLOOP and LLOOP high for at least 200 ns initiates a device reset.
SCLK - Serial Clock, Pin 27. (Host Mode)
Clock used to read or write the serial port registers. SCLK can be either high or low when the line
interface is selected using the CS pin.
SDI - Serial Data Input, Pin 24. (Host Mode)
Data for the on-chip register. Sampled on the rising edge of SCLK.
SDO - Serial Data Output, Pin 25. (Host Mode)
Status and control information from the on-chip register. If CLKE is high SDO is valid on the
risin g edge of SCL K. If CLKE is low SDO is valid on the fallin g edge of SCLK. Th is pin goes to
a high-impedance state when the serial po rt is being written to or after bit D7 is output.
CS61577
22 DS155PP2
TAOS - Transmit All Ones Select, Pin 28. (Hardware and Extended Hardware Modes)
Setting TAOS to a logic 1 causes continuous ones to be transmitted at the frequency determined
by TCLK. In the Host Mode, simultaneous selection of RLOOP & TAOS enables a factory test
mode.
TCODE - Transmitter Encoder Select, Pin 4. (Extended Hardware Mode)
Settin g TCODE low enables B8ZS or HDB3 z ero substitution i n the transmitter encoder. Setting
TCODE high enables the AMI transmitter encoder .
Data
RDATA - Receive Data - Pin 7. (Extended Hardware Mode)
Data rec overed fro m the RTIP an d RRING inp uts is ou tpu t at thi s pin, afte r being dec oded by th e
line code decoder. RD ATA is NRZ. RDATA is stable and v alid on the falling edge of RCLK.
RCLK - Recovered Clock, Pin 8.
The receiver recovered clock generated by the jitter attenuator is output on this pin.When in the
loss of signal state ACLKI (if present) is output on RCLK via the jitter attenuator. If ACLKI is
not present dur ing LO S , RCLK is fo r ced to th e center fr equency of the crystal oscillator..
RPOS, RNEG - Receive Positive Data , Receive Negative Data, Pins 6 and 7. (Hardware and Host
Modes)The receiver recovered NRZ digital data is output on these pins. In the Hardware Mode, RPOS
and RNEG ar e stable and valid on the rising edge of RCLK. In the Host Mode, CLKE d etermines
the clock edge for which RPOS and RNEG are stable and valid. See Table 5. A positive pulse
(with respect to ground) received on the RTIP pin generates a logic 1 on RPOS, and a positive
pulse recei ved on the RRING pin generates a logic 1 on RNEG.
RTIP, RRING - Receive Tip, Receive Ring, Pins 19 and 20.
The AMI receive signal is input to these pins. A center-tapped, center-grounded, 2:1, step-up
transformer is required on these inputs, as shown in Figure A1 in the Applications section. Data
and clock are recovered and ou tput on RC LK and RPOS/RNEG or RDTA.
TCLK - Transmit Clock, Pin 2.
The1.544 MHz (or 2.048 MHz) transmit clock is input on this pin. TPOS/TNEG or TDATA are
sampled on the falling edge of TCLK.
TDATA - Tr ansmit Data, Pin 3. (Extended Hardware Mode)
Tra nsmitter NRZ inpu t data whi ch passes through th e line c ode encode r, and i s then driven on to
the line through TTIP and TRING. TD ATA is sampled on the falling edge of TCLK.
TPOS, TNEG - Transmit Positive Data, Transmit Negative Data, Pins 3 and 4 . (Hardware and
Host Modes)
Inputs for clock an d data to be transmitted. The signa l is driven on to the line through TTIP and
TRING. TPOS and TNEG are sampled on the falling edge of TCLK. A TPOS input causes a
positiv e pulse to be transmitted, while a TNEG input causes a negati ve pulse to be transmitted.
CS61577
DS155PP2 23
TTIP, TRING - Transmit Tip, Transmit Ring, Pins 13 and 16.
The AMI signal is driven to the line through these pins. The transmitter output is designed to
dr ive a 25 Ω load between TTIP and TRING. A transformer is required as shown in Table A1.
Status
AIS - Alarm Indication Signal, Pin 11. (Extended Hardware Mode)
AIS goes high when unframed all-ones condition (blue alarm) is detected, using the detection
criteria of less than three zeros out of 2048 bit periods.
BPV- Bipolar Violation Strobe, Pin 6. (Extended Hardware Mode)
BPV strobes high when a bipolar violation is detected in the received signal. B8ZS (or HDB3)
zero substitutions are not flagged as bipolar violations if the B8ZS (or HDB3) decoder has been
enabled.
DPM - Driver Performance Monitor, Pin 11. (Hardware and Host Modes)
DPM goes high if no activity is det ected on MTIP and MRING.
LOS - Loss of Signal , Pin 12.
LOS goes high when 175 consecutive zeros have been received. LOS returns low when 3 ones
are received within 32 bit periods with no more than 15 consecutive zeros. When in the loss of
signal state RPOS/RNEG or RDATA are forced low, and ACLKI (if present) is out put on RCLK
via the jitter attenuator. If ACLKI is not present during LOS, RCLK is forced to the center
freq uency of the crystal oscillator.
MTIP, MRING - Monitor Tip, Monitor Ring, Pins 17 and 18. (Hardware and Host Modes)
These pins a r e normally conne cted to TT I P and T RING and moni tor the output of a line interface
IC. If the INT pin in t he host mode is used, and th e monitor is not used, writing "clear DPM" to
the serial interface will prevent an interrupt from the driver performance monitor.
CS61577
24 DS155PP2
28 pin
Plastic DIP
1
28 15
14
MILLIMETERS INCHES
DIM MINMAXMINMAX
D
B
A
L
∝
C
13.72 14.22 0.540 0.560
36.45
1.02
0.36
0.51
3.94
3.18
0.20
0°
15.24
37.21
1.65
0.56
1.02
5.08
3.81
0.38
15°
1.435
0.040
0.014
0.020
0.155
0.125
0.600
0.008
0°
1.465
0.065
0.022
0.040
0.200
0.150
0.015
15°
15.87 0.625
2.41 2.67 0.095 0.105
C
eA
E1
D
B
SEATING
PLANE
A
B1 e1
A1 L
∝
NOTES:
1. POSITION AL TOLERAN CE OF LEADS SHALL BE WITHIN
0.25mm (0.010") AT MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND EACH OTHER.
2. DI M ENS I O N e A TO CE N T ER O F LEADS WHEN F OR ME D PA RALLEL.
3. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.
NOM
13.97
36.83
1.27
0.46
0.76
4.32
-
0.25
-
-
2.54
NOM
0.550
1.450
0.050
0.018
0.030
0.170
-
-
0.010
-
0.100
A1
B1
E1
e1
eA
E
E1
D1
D
D2/E2
28-pin PLCC
28
D2/E2
MAXMIN MAX
MIN
MILLIMETERS INCHES
DIM
A
4.574.20 0.1800.165
D/E
12.32 12.57 0.485 0.495
B
0.530.33 0.0210.013
e
A
A1
Be
2.29 0.090
11.43 11.58 0.450 0.456
9.91 10.92 0.390 0.430
1.19 1.35 0.047 0.053
NOM
4.45
12.45
0.41
2.79
11.51
10.41
1.27
NOM
0.175
0.490
0.016
0.110
0.453
0.410
0.050
3.04 0.120
D1/E1
A1
CS61577
DS155PP2 25
APPLICATIONS
Line Interface
Figures A1-A3 sh ow typi cal T1 and E 1 line int er-
face application circuits. Table A1 shows the
external components which are specific to each
appli cat ion . Fig ur e A1 illus tra tes a T1 inte rfac e in
the Host Mode. Figure A2 illustrates a 120 Ω E1
interface in the Hardware Mode. Figure A3 illus-
trates a 75 Ω E1 interface in the Extended
Hardware Mode.
The 1: 2 receiver transformer h as a ground ed cen-
ter tap on the IC side. Resistors R1 and R2
between the RTIP and RRING pins to ground
provide the termination for the receive line. The
trans mitter als o uses a 1:2 trans former. A 0.47 µF
capacitor is required in series with the transmit
transformer primary. This capacitor is needed to
prevent any output stage imbalance from resulting
in a DC current through the transformer primary.
This current might saturate the transformer pro-
ducing an o utput offset level shi f t.
Control
&
Monitor
Frame
Format
Encoder/
Decoder
CS61577
IN
HOST
MODE
RECEIVE
LINE
TRANSMIT
LINE
28
1
12
11
5
7
6
8
3
4
2
9
10
XTL
RV+
+
68
µ
F
RGND
0.1
µ
F
+5V
21 15
+
1.0
µ
F
TGND
RV+ TV+
CLKE
ACLKI
LOS
DPM
MODE
RPOS
RNEG
RCLK
TPOS
TNEG
TCLK
XTALIN
XTALOUT RGND TGND
22 14
SCLK
CS
INT
SDI
SDO
RTIP
RRING
MTIP
MRING
TRING
TTIP
19
20
17
18
16
13
R1
R2
1
3
5
2
6
0.47
µ
F2
6
1
5
1:2CT
PE-65351
2CT:1
PE-65351
µ
P
Serial
Port
27
26
23
24
25
+5V
100 k
Ω
Fi gure A1. T1 Hos t Mo de C onf igur at ion
Frequency
MHz Crystal
XTL Cable
ΩLEN2/1/0 R3
ΩR1 and R2
Ω
1.544 (T1) CXT6176 100 0/1/1 - 1/1/1 not used 200
2.048 (E1) CXT8192 120 0/0/0 not used 240
75 0/0/0 4.4 150
0/0/1 not used
Table A1. External Component Values
CS61577
26 DS155PP2
Control
&
Monitor
Frame
Format
Encoder/
Decoder
CS61577
IN
HARDWARE
MODE
Line
Length
Setting
RECEIVE
LINE
TRANSMIT
LINE
28
1
26
27
5
7
6
8
3
4
2
9
10
XTL
+68
µ
F
RGND
0.1
µ
F
+5V
21 15
+1.0
µ
F
TGND
RV+ TV+
TAOS
ACLKI
RLOOP
LLOOP
MODE
RPOS
RNEG
RCLK
TPOS
TNEG
TCLK
XTALIN
XTALOUT RGND TGND
22 14
LEN0
LEN1
LEN2
RTIP
RRING
MTIP
MRING
TRING
TTIP
23
24
25
19
20
17
18
16
13
R1
R2
1
3
5
2
6
0.47
µ
F2
6
1
5
1:2CT
PE-65351
2CT:1
PE-65351
12
11 LOS
DPM
Fi gure A2. 120 Ω, E1 Hardware Mode Configuration
Control
&
Monitor
Frame
Format
Encoder/
Decoder
CS61577
IN
EXTENDED
HARDWARE
MODE
Line
Length
Setting
RECEIVE
LINE
TRANSMIT
LINE
17
18
6
28
5
7
8
3
2
9
10
XTL
+68
µ
F
RGND
0.1
µ
F
+5V
21 15
+1.0
µ
F
TGND
RV+ TV+
RCODE
PCS
BPV
TAOS
MODE
RDATA
RCLK
TDATA
TCLK
XTALIN
XTALOUT RGND TGND
22 14
LEN0
LEN1
LEN2
RTIP
RRING
TRING
TTIP
23
24
25
19
20
16
13
R1
R2
1
3
5
2
6
0.47
µ
F2
6
1
5
1:2CT
PE-65351
2CT:1
PE-65351
1
26 ACLKI
RLOOP
27
12 LLOOP
LOS
11 AIS
4TCODE
R3
Note:
R3 is used for LEN2/1/0 = 0/0/0, but
not required with LEN2/1/0 = 0/0/1.
Fi gure A3. 75 Ω, E 1 Ex tended Hard ware Mode Conf igur atio n
CS61577
DS155PP2 27
Transformers
Recommended transmitter and receiver trans-
former specificati ons are shown in Table A2. The
transformers in Table A3 have been tested and
recommende d for us e with th e C S61577. R efer to
the "Telecom Transformer Selection Guide" for
detailed schematics which show how to connect
the line interface IC with a particu lar transformer.
Selecting an Oscillator Crystal
Specific crystal parameters are required for
proper operation of the jitter attenuator. It is rec-
ommended that the Crystal Semiconductor
CXT6176 crystal be used for T1 applications and
the CXT 8 192 cry st al be used for E1 applications.
Transmit Side Jitte r Attenuati on
In some applications it is desirable to attenuate
jitter from the signal to be transmitted. A
CS61577 i n local loopba ck mode can be us ed as a
jitter attenuator. The in puts to the jitter attenua tor
are TPOS, TNEG, TCLK. The outputs from the
jitter attenuator are RPOS, RNEG and RCLK.
Line Prot ec t ion
Secondary protection components can be added
to provide lightning surge and AC power-cross
immunity. Refer to the "Telecom Line Protection
Appli cation Note" fo r detailed information on the
different electrical safety standards and specific
application circuit recommendations.
Turns Ratio 1:2 CT ± 5%
Primary
Inductance 600 µH min. @ 772 kHz
Primary Leakage
Inductance 1.3 µH max. @ 772 kHz
Secondary L eakage
Inductance 0.4 µH max. @ 772 kHz
Interwinding
Capacitance 23 pF max.
ET-constant 16 V-µs min. for T1
12 V-µs min. for E1
Table A2. Transformer Specifications
Turns
Ratio(s) Manufa cturer Part Number Package Type
1:2CT Pulse Engineering PE-65351 1.5 kV through-hole, single
Schott 67129300
Bel Fuse 0553-0013-HC
dual
1:2CT Pulse Engineering PE-64951 1.5 kV through-hole, dual
Bel Fuse 0553-0013-1J
dual
1:2CT Pulse Engineering PE-65761 1.5 kVsurface-mount, dual
Bel Fuse S553-0 01 3 - 03
1:2CT Pulse Engineering PE-65835 3 kV through-hole, single
EN609 50, EN41003 approved
Ta ble A3 . R ecomme nded T ransf or mers
CS61577
28 DS155PP2
Interfacing The CS61577 Wi th the CS62180B
T1 Transceiver
To interface with the CS62180B, connect the de-
vices as shown in Figur e A5. In this case, th e line
interface and CS62180B are in host mode con-
trolled by a microprocesso r serial interface. If the
line in terface is used in Hardware Mod e, then th e
line interface RCLK output must be inverted be-
fore being input to the CS62180B. If the
CS61577 is used in Extended Hardware Mode,
the RC LK o utp ut d oes no t have to be i nverted be-
fore being input to the CS62180B.
ACLK
TCLK
RCLK
RPOS
RNEG
TPOS
TNEG
CS62180B
CLKE
SCLK
INT
SDO
SDI
TCLK
TPOS
TNEG
RNEG
RPOS
RCLK
SCLK
SDO
SDI
TO HOST CONTROLLER
V+
100k
1.544 MHz
CLOCK
SIGNAL
CS61577
CS
CS V+22k
MODE
Figure A4. Interfacing the CS61577 with a CS62180B
(Host Mode)
CS61577
DS155PP2 29
• Notes •
Features
••Socketed Line Interface Device
••All Required Components for Complete
Line Interface Evaluation
••Configuration by DIP Switch or Serial
Interface
••LED Status Indicators for Alarm
Conditions
••Support for Host, Hardware, and
Extended Hardware Modes
General Description
The evaluation board includes a socketed line interface
device and all support components necessary for
evaluation. The board is powered by an external 5 Volt
supply.
The board may be configured for 100 Ω twisted-pair
T1, 75 Ω coax E1, or 120 Ω twisted-pair E1 operation.
Binding posts are provided for line connections. Sev-
eral BNC connectors are available to provide system
clocks and data I/O. Two LED indicators monitor de-
vice alarm conditions. The board supports all line
interface operating modes.
ORDERING INFORMATION:
CDB61534, CDB61535. CDB61535A,
CDB6158, CDB6158A, CDB61574,
CDB61574A, CDB61575, CDB61577,
CDB61304A, CDB61305A
SEP ’95
DS40DB3
31
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
Line Interface Evaluation Board
CDB61534, CDB61535, CDB61535A, CDB6158,
CDB6158A, CDB61574, CDB61574A, CDB61575,
CDB61577, CDB615304A, & CDB61305A
ACLKI
TCLK
TPOS
(TDATA)
TNEG
RNEG
(BPV)
RPOS
(RDATA)
RCLK
CS61534,
CS61535,
CS61535A,
CS6158,
CS6158A,
CS61574,
CS61574A,
CS61575,
CS61577,
CS61304A
or
CS61305A
Reset
Circuit
Mode Select
Circuit
(TCODE)
+5V 0V
LED Status
Indicators
Hardware
Control Circuit
Serial Interface
Control Circuit
TTIP
TRING
RTIP
RRING
XTL
POWER SUPPLY
As shown on the evaluation board schematic in
Figure 1, power is supplied to the evaluation
board from an external +5 Volt supply connected
to the two binding posts labeled +5V and GND.
Transient suppressor D10 protects the compo-
nents on the board from over-voltage damage and
reversed supply connections. The recommended
power supply decoupling is provided by C1, C2
and C3. Ceram ic capacit or C 1 and elect rolytic ca-
pacitor C2 are used to decouple RV+ to RGND.
Capacitor C3 decouples TV+ to TGND. The TV+
and RV+ power supply traces are connected at the
device socket U1. A ground plane on the compo-
nent side of the evaluation board insures optimum
performance.
BOARD CONFIGURATION
Pins on line interface device U1 with more than
one pin name have different functions depending
on the operating mode selected. Pin names not
enclosed in parenthesis or square brackets de-
scribe the Hardware mode pin function. Pin
names enclosed in parenthesis describe the Ex-
tended Hardware mode pin function. Pin names
enclosed in square brackets describe the Host
mode pin function.
Table 1 explains how to configure the evaluation
board jumpers depending on the device installed
and the desired operating mode. Mode selection
is accomplished wi th slide swi tch SW1 and jump-
ers JP2, JP6, and JP7. The CS61535A,
CS61574A, CS61575, CS61577, CS61304A, and
CS61305A support the Hardware, Extended
Hardware, and Host operating modes. The
CS61534, CS61535, and CS61574 support the
Hardware and Host operating modes. The
CS6158 and CS6158A only support the Hardware
operating mode.
Hardware Mode
In the Hardware operating mode, the line inter-
face is configured using DIP switch S2. The digi-
tal control inputs to the device selected by S2 in-
clude: transmit all ones (TAOS), local loopback
(LLOOP), remote loopback (RLOOP), and trans-
mit line length selection (LEN2,LEN1,LEN0).
Closing a DIP switch on S2 towards the label sets
the device control pin of the same name to logic 1
(+5 Volts). Note that S2 switch positions TCODE
and RCODE have no function in Hardware mode.
In addition, the host processor interface connector
JP1 should not be used in the Hardware mode.
Two LED status indicators are provided in Hard-
ware mode. The LED labeled DPM (AIS) illumi-
nates when the line interface asserts the Driver
JUMPER POSITION FUNCTION SELECTED
JP1 - Connector for external processor in Host operating mode.
JP2, JP6, JP7 A-A Extended Hardware operating mode.
B-B Hardware or Host operating modes.
JP3 IN Hardware or Extended Hardware operating modes.
OUT Host operating mode.
JP4 C-C Connects the ACLKI BNC input to pin 1 of device.
D-D Grounds the ACLKI BNC input through 51Ω resistor R1.
JP5 E-E Transmit line connection for all applications except those listed for "F-F" on the next line.
F-F 75Ω coax E1 applications using the Schott 12932/12532 or PE-65389/65566 at transformer T1.
JP8 IN Shorts resistor R2 for all applications except those listed for "OUT" on the next line.
OUT Inserts resistor R2 for 75Ω coax E1 applications using the CS61534, 35, 58, 74, or 77.
Table 1. Eva luation Board Jumper Settings
LINE INTERFACE EVALUATION BOARD
32 DS40DB3
R16
1k
Ω
8
RCLK
2
TCLK
3
TPOS
(TDATA)
6
RNEG
(BPV)
Pin 3
TCLK
RCLK
Pin 6
4
TNEG
7
RPOS
(RDATA)
1
ACLKI
Pin 7
ACLKI
R1 51.1
Ω
Pin 4
S2
R15
100
Ω
RV+
JP3
RV+
Q1
2N2222
R6
470
Ω
LED
D3
RV+
Q2
2N2222
R5
470
Ω
LED
D2
JP1 D9
1N914 D8 R14
4.7kW
SIP
RV+
LOS
DPM
(AIS)
MODE
R18
10k W R17
10k W
511 12
23
24
25
26
27
28
LEN1/SDI
LEN2/SD0
LLOOP/SCLK
TAOS/CLKE
TCODE
RLOOP/CS
SDI
SDO
SCLK
INT
CS
LEN0/INT
S1
RESET
MODE
SW1
R4
221kW
AA
BB
DD
CC
JP4
JP2
RCODE
C4 0.047m
F3
6
875124
HOST:3-1,6-8
EXT HW: 3-2, 6-7
HW: 3-4, 6-5
18
TRING
TTIP
0.47 m
F
C5
TRING
TTIP
+5V
221415 RV+TV+ TGND RGND
D10
P6KE
21
T1
(see Table 2)
17
C2
0.1mFC1
68mF
19 RTIP
RRING
RRING
RTIP
20
JP8
R2
4.4W
C3
1 m
F
RV+
RCLK
TCLK
RNEG (BPV)
ACLKI
LEN1 [SDI]
LEN2 [SD0]
LLOOP [SCLK]
TAOS [CKLE]
XTALIN
{CS6158/58A: RT}
XTALOUT
{CS6158/58A: NC}
LOSDPM (AIS)MODE
13
16
AA
AA
BB
BB
RTIP
RRING
TRING
Pin 17
Pin 18
9
10
TTIP
RV+
R13 (only included for CS6158/58A)
1kW
(Used only for E1 75W
applications with the CS61534,
CS61535, CS6158, CS61574,
OR CS61577)
CS61534, CS61535,
CS61535A, CS6158,
CS6158A, CS61574,
CS61574A, CS61575,
CS61577, CS61304A,
OR CS61305A
U1:
FF
EE
Prototyping
Area
RV+
LEN0 [INT]
RLOOP [CS]
MRING (PCS)
RPOS (R DA TA)
TPOS (TDATA)
MTIP (RCO DE)
JP6
JP7
JP5
E1: CXT8192
T1: CXT6176
(not included for CS6158/58A)
+
TNEG (TCODE)
U1 R9
200W
R10
200W
T2
(see Table 2)
2:1
GND
(0V)
Change R9 and R10 f or E1 operation
Figure 1. Ev aluation Board Schematic
LINE INTERFACE EVALUATION BOARD
DS40DB3 33
Performance Monitor alarm. The LED labeled
LOS illuminates when the line interface receiver
has detected a loss of signal.
Extended Hardware Mode
In the Extended Hardware operating mode, the
line interface is configured using DIP switch S2.
The digital control inputs to the device selected
by S2 include: transmit all ones (TAOS), local
loopback (LLOOP), remote loopback (RLOOP),
transmit line length selection (LEN2, LEN1,
LEN0), transmit line code (TCODE), and receive
line code (RCODE). Closing a DIP switch (mov-
ing it towards the S2 label) sets the device control
pin of the same name to logic 1 (+5 Volts). Note
that the TCODE and RCODE options are active
low and are enabled when the switch is moved
away from the S2 label. The parallel chip select
input PCS is tied to ground in Extended Hard-
ware mode to enable the device to be reconfig-
ured when S2 is changed. In addition, the host
processor interface connector JP1 should not be
used in Extended Hardware mode.
Two LED status indicators are provided in Ex-
tended Hardware mode. The LED labeled DPM
(AIS) illuminates when the line interface detects
the receive blue alarm (AIS). The LED labeled
LOS illuminates when the line interface receiver
has detected a loss of signal.
Host Mode
In the Host operating mode, the line interface is
configured using a host processor connected to
the serial interface port JP1. The S2 switch posi-
tion labeled CLKE selects the active edge of
SCLK and RCLK. Closing the CLKE switch se-
lects RPOS and RNEG to be valid on the falling
edge of RCLK and SDO to be valid on the rising
edge of SCLK as required by the CS2180B T1
framer.
All other DIP switch positions on S2 should be
open (logic 0) to prevent shorting of the serial in-
terface signals. Resistor R15 is a current limiting
resistor that prevents the serial interface signals
from being shorted directly to the +5 Volt supply
if any S2 switch, other than CLKE, is closed.
Jumper JP3 should be out so the INT pin may be
externally pulled-up at the host processor inter-
rupt pin.
Two LED status indicators are provided in Host
mode. The LED labeled DPM (AIS) illuminates
when the line interface asserts the Driver Per-
formance Monitor alarm. The LED labeled LOS
illuminates when the line interface receiver has
detected a loss of signal.
Manual Reset
A manual reset circuit is provided that can be
used in Hardware and Extended Hardware
modes. The reset circuit consists of S1, R4, R16,
C4, D8, and D9. Pressing switch S1 forces both
LLOOP and RLOOP to a logic 1 and causes a
reset. A reset is only necessary for the CS61534
device to calibrate the center frequency of the re-
ceiver clock recovery circuit. All other line inter-
face units use a continuously calibrated clock re-
covery circuit that eliminates the reset require-
ment.
TRANSMIT CIRCUIT
The transmit clock and data signals are supplied
on BNC inputs labeled TCLK, TPOS(TDATA),
and TNEG. In the Hardware and Host operating
modes, data is supplied on the TPOS(TDATA)
and TNEG connectors in dual NRZ format. In the
Extended Hardware operating mode, data is sup-
plied in NRZ format on the TPOS(TDATA) con-
nector and TNEG is not used.
The transmitter output is transformer coupled to
the line through a transformer denoted as T1 in
Figure 1. The signal is available at the TTIP and
TRING binding posts. Capacitor C5 is the recom-
mended 0.47 µF DC blocking capacitor.
LINE INTERFACE EVALUATION BOARD
34 DS40DB3
The evaluation board supports 100Ω twisted-pair
T1, 75Ω coax E1, and 120Ω twisted-pair E1 op-
eration. The CDB61534, CDB61535, CDB6158,
CDB61574, and CDB61577 are supplied from
the factory with a 1:2 transmit transformer that
may be used for all T1 and E1 applications. The
CDB61535A, CDB6158A, CDB61574A,
CDB61575, CDB61304A, and CDB61305A are
supplied with a 1:1.15 transmit transformer in-
stalled for T1 applications. An additional 1:1:1.26
transformer for E1 applications is provided with
the board. This transformer requires JP5 to be
jumpered across F-F for 75Ω coax E1 applica-
tions.
The CDB61534, CDB61535, CDB6158,
CDB61574, and CDB61577 require the JP8
jumper to be out for 75Ω coax E1 applications.
This inserts resistor R2 to reduce the transmit
pulse amplitude and meet the 2.37 V nominal
pulse amplitude requirement in CCITT G.703. In
addition, R2 increases the equivalent load imped-
ance across TTIP and TRING.
RECEIVE CIRCUIT
The receive line interface signal is input at the
RTIP and RRING binding posts. The receive sig-
nal is transformer coupled to the line interface de-
vice through a center-tapped 1:2 transformer. The
transformer produces ground referenced pulses of
equal amplitude and opposite polarity on RTIP
and RRING.
The receive line interface is terminated by resis-
tors R9 and R10. The evaluation boards are sup-
plied from the factory with 200Ω resistors for ter-
minating 100Ω T1 twisted-pair lines. Resistors
R9 and R10 should be replaced with 240Ω resis-
tors for terminating 120Ω E1 twisted-pair lines or
150Ω resistors for terminating 75Ω E1 coaxial
lines. Two 243Ω resistors and two 150Ω resist ors
are included with the evaluation board for this
purpose.
The recovered clock and data signals are avail-
able on BNC outputs labeled RCLK,
RPOS(RDATA), and RNEG(BPV). In the Hard-
ware and Host operating modes, data is output on
the RPOS(RDATA) and RNEG(BPV) connectors
in dual NRZ format. In the Extended Hardware
operating mode, data is output in NRZ format on
the RPOS(RDATA) connector and bipolar viola-
tions are reported on the RNEG(BPV) connector.
QUARTZ CRYSTAL
A quartz crystal must be installed in socket Y1 for
all devices except the CS6158 and CS6158A. A
Crystal Semiconductor CXT6176 crystal is rec-
ommended for T1 operation and a CXT8192 is
recommended for E1 operation. The evaluation
board has a CXT6176 installed at the factory and
a CXT8192 is also provided with the board.
The CDB6158 and CDB6158A have resistor R13
installed instead of a crystal. This connects the RT
pin of the device to the +5 Volt supply.
ALTERNATE CLOCK INPUT
The ACLKI BNC input provides the alternate
clock reference for the line interface device
(ACLK for the CS61534) when JP4 is jumpered
across C-C. This clock is required for the
CS61534, CS61535, CS6158, and CS6158A op-
eration but is optional for all other line interface
devices. If ACLKI is provided, it may be desir-
able to connect both C-C and D-D positions on
JP4 to terminate the external clock source provid-
ing ACLKI with the 51Ω resistor R1. If ACLKI is
optional and not used, connector JP4 should be
jumpered across D-D to ground pin 1 of the de-
vice through resistor R1.
TRANSFORMER SELECTION
To permit the evaluation of other transformers,
Table 2 lists the transformer and line interface de-
vice combinations that can be used in T1 and E1
LINE INTERFACE EVALUATION BOARD
DS40DB3 35
applications. A letter at the intersection of a row
and column in Table 2 indicates that the selected
transformer is supported for use with the device.
The transformer is installed in the evaluation
board with pin 1 positioned to match the letter
illustrated on the drawing in Table 2. For exam-
ple, the Pulse Engineering PE-65388 transformer
may be used with the transmitter of the CS61575
device for 100Ω T1 applications only (as indi-
cated by note 3) when installed in transformer
socket T1 with pin 1 at position D (upper right).
PROTOTYPING AREA
A prototyping area with power supply and ground
connections is provided on the evaluation board.
This area can be used to develop and test a vari-
ety of additional circuits like a data pattern gener-
ator, CS2180B framer, system synchronizer PLL,
or specialized interface logic.
EVALUATION HINTS
1. Properly terminate TTIP/TRING when evaluat-
ing the transmit output signal. For more informa-
tion concerning pulse shape evaluation, refer to
the Crystal application note entitled "Measure-
ment and Evaluation of Pulse Shapes in T1/E1
Transmission Systems."
2. Change the receiver terminating resistors R9
and R10 when evaluating E1 applications. Resis-
tors R9 and R10 should be replaced with 240Ω
resistors for terminating 120Ω E1 twisted-pair
lines or 150Ω resistors for terminating 75Ω E1
coaxial lines. Two 243Ω resistors and two 150Ω
resistors are included with the evaluation board
for this purpose.
3. Closing a DIP switch on S2 towards the label
sets the device control pin of the same name to
logic 1 (+5 Volts).
4. To avoid damage to the external host controller
connected to JP1, all S2 switch positions (except
CLKE) should be open. In the Host operating
mode, the CLKE switch sel ects the active edge of
SCLK and RCLK.
LINE INTERFACE EVALUATION BOARD
36 DS40DB3
NOTES:
1. A letter at the inter section of a row and column in Table 2 indicates
that the selected transformer is supported for use with the device.
The transformer is installed in the evaluation board with pin 1 po-
sitioned to match the letter illustrated in the drawing to the left.
2. The receive transformer (RX) is soldered at location T2 on the
evaluation board and is used for all applications. The transmit
transformer (TX) is socketed at location T1 on the evaluation
board and may be changed according to the application.
3. For use in 100Ω T1 twisted-pair applications only.
4. For use in 75Ω and 120Ω E1 applications only. Place jumper JP5
in position F-F for 75Ω E1 applications requiring a 1:1 turns ratio.
5. Transmitter return loss improves when using a 1:2 turns ratio trans-
form er with t he appropr iate tran smit res istors.
Table 2. Transformer Applications
TRANSFORMER
(Turns Ratio)1,2
LINE INTERFACE UNIT
’34 ’35 ’35A ’58 ’58A ’74,’77 ’74A ’75 ’304A,
’305A
RX TX RX TX RX TX RX TX RX TX RX TX RX TX RX TX RX TX
PE-65351 (1:2CT) A D A D A A D A A D A A A
Schott 12930 (1:2CT) B C B C B B C B B C B B B
PE-65388 (1:1.15) D3D3D3D3D3,5
Schott 12931 (1:1.15) C3C3C3C3C3,5
PE-65389 (1:1:1.26) D4D4D4D4D4,5
Schott 12932 (1:1:1.26) C4C4C4C4C4,5
PE-64951 (dual 1:2CT) E E E E
Schott 11509 (dual 1:2CT) E E E E
PE-65565 (dual 1:1.15 & 1:2CT) E3E3E3E3E3,5
Schott 12531 (dual 1:1.15 & 1:2CT) E3E3E3E3E3,5
PE-65566 (dual 1:1:1.26 & 1:2CT) E4E4E4E4E4,5
Schott 12532 (dual 1:1:1.26 & 1:2CT) E4E4E4E4E4,5
E
T2
T1
D
A
C
B
T2
T1
LINE INTERFACE EVALUATION BOARD
DS40DB3 37
Figure 2. Silk Screen Layer (NOT TO SCALE)
LINE INTERFACE EVALUATION BOARD
38 DS40DB3
Figure 3. Top Ground Plane Layer (NOT TO SCALE)
LINE INTERFACE EVALUATION BOARD
DS40DB3 39
Figure 4. Bottom Trace Layer (NOT TO SCALE)
LINE INTERFACE EVALUATION BOARD
40 DS40DB3
• Notes •
• Notes •
• Notes •
Smart
Analog
TM is a Trademark of Crystal Semiconductor Corporation
