November 2017
DocID030880 Rev 1
1/9
This is information on a product in full production.
www.st.com
ESDZV18-1BF4
Low clamping, low capacitance bidirectional single line ESD
protection
Datasheet - production data
Features
Low clamping voltage
Bidirectional device
Low leakage current < 100 nA
0201 package
ECOPACK®2 compliant component
Exceeds IEC 61000-4-2 level 4 standard:
±30 kV (air discharge)
±30 kV (contact discharge)
Applications
Where transient over voltage protection in ESD
sensitive equipment is required, such as:
Smartphones, mobile phones and
accessories
Tablets and notebooks
Portable multimedia devices and
accessories
Wearable, home automation, healthcare
Highly integrated systems
Description
The ESDZV18-1BF4 is a bidirectional single line
TVS diode designed to protect the data line or
other I/O ports against ESD transients.
The device is ideal for applications where both
reduced line capacitance and board space saving
are required.
Figure 1: Functional diagram
0201 package
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DocID030880 Rev 1
1 Characteristics
Table 1: Absolute ratings (Tamb = 25 °C)
Symbol
Parameter
Value
Unit
VPP
Peak pulse voltage
IEC 61000-4-2 contact discharge
IEC 61000-4-2 air discharge
30
30
kV
PPP
Peak pulse power dissipation (8/20 μs)
140
W
IPP
Peak pulse current (8/20 μs)
6
A
Tj
Operating junction temperature range
-55 to +150
°C
Tstg
Storage temperature range
-65 to +150
°C
TL
Maximum lead temperature for soldering during 10 s
260
°C
Figure 2: Electrical characteristics (definitions)
Table 2: Electrical characteristics (Tamb = 25 °C)
Symbol
Test condition
Min.
Typ.
Max.
Unit
VTrig
Higher voltage than VTrig guarantees the protection turn-on
18
24
V
VH
Lower voltage than VH guarantees the protection turn-off
16
17.3
V
IRM
VRM(1) = 16 V
100
nA
VCL
8 kV contact discharge after 30 ns, IEC 61000-4-2
21.5
V
VCL
8/20 µs waveform, IPP = 1 A
18
V
CLINE
F = 1 MHz, VLINE = 0 V, VOSC = 30 mV
3
4
pF
RD
Pulse duration 100 ns
0.2
Ω
Notes:
(1)Application note: when used to protect a line connected to a DC source, the DC voltage must be lower than the
minimum VH to enable the diode to return to its non-conducting state after the transient.
Symbol Parameter
V=Trigger voltage
I=Leakage current @ V
V=Stand-off voltage
I=Peak pulse current
R
Trig
RM RM
RM
PP
V=Clamping voltage
CL
D=Dynamic resistance
VH=Holding voltage
CLINE =Input capacitance per line
VCL VBR VRM
IR
IPP
V
I
VTrig
IRM
RD
V
I
ESDZV18-1BF4
Characteristics
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1.1 Characteristics (curves)
Figure 3: Leakage current versus junction
temperature (typical values)
Figure 4: Junction capacitance versus reverse
voltage applied (typical values)
Figure 5: ESD response to IEC 61000-4-2
(+8 kV contact discharge)
Figure 6: ESD response to IEC 61000-4-2
(-8 kV contact discharge)
Figure 7: TLP characteristic
Figure 8: S21 attenuation measurement result
0
5
10
0 25 50 75 100 125 150
Ir(nA)
Tj(°C)
C(pF)
VR(V)
0
0.5
1
1.5
2
2.5
3
3.5
0 2 4 6 8 10 12 14 16
Peak clamping voltage
Clamping voltage at 30 ns
Clamping voltage at 60 ns
Clamping voltage at 100 ns
1
2
3
4
20 ns/div
20V/div
1
71 V
2
22 V 3
18 V
4
15 V
20 ns/div
20V/div
1
234
Peak clamping voltage
Clamping voltage at 30 ns
Clamping voltage at 60 ns
Clamping voltage at 100 ns
1
2
3
4
-72 V
-20 V -18 V -17 V
0
10
20
0 10 20
I(A)
VCL(V)
10M
30M
300M
1G
3G
-12
-9
-6
-3
0
100M
S21(dB)
f (Hz)
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DocID030880 Rev 1
2 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
2.1 0201 package information
Figure 9: 0201 package outline
The marking codes can be rotated by 90 ° or 180° to differentiate assembly
location. In no case should this product marking be used to orient the component
for its placement on a PCB. Only pin 1 mark is to be used for this purpose.
ESDZV18-1BF4
Package information
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Dot indicates Pin 1
User direction of unreeling
All dimensions in mm
4.0 ±0.1
2.0 ±0.05
8.0 +0.03 -0.01
2.0 ±0.05
1.75 ±0.1
3.5 ±0.
05
Ø 1.5 ±0.1
0.27 ±0.03 0.34 ±0.03
0.2 ±0.02
0.67 ±0.03
Table 3: 0201 package mechanical data
Ref.
Dimensions
Millimeters
Min.
Typ.
Max.
A
0.270
0.300
0.330
b
0.1675
0.1875
0.2075
D
0.560
0.580
0.600
D1
0.3375
E
0.260
0.280
0.300
E1
0.205
0.225
0.245
fD
0.0175
0.0275
0.0375
fE
0.0175
0.0275
0.0375
Figure 10: Tape and reel specification (in mm)
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DocID030880 Rev 1
3 Recommendation on PCB assembly
3.1 Footprint
1. Footprint in mm
a. SMD footprint design is recommended.
Figure 11: Footprint in mm
3.2 Stencil opening design
1. Reference design
a. Stencil opening thickness: 75 μm / 3 mils
Figure 12: Recommended stencil window position in mm
3.3 Solder paste
1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004.
2. “No clean” solder paste is recommended.
3. Offers a high tack force to resist component movement during high speed.
4. Use solder paste with fine particles: powder particle size 20-38 µm.
ESDZV18-1BF4
Recommendation on PCB assembly
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3.4 Placement
1. Manual positioning is not recommended.
2. It is recommended to use the lead recognition capabilities of the placement system,
not the outline centering
3. Standard tolerance of ±0.05 mm is recommended.
4. 1.0 N placement force is recommended. Too much placement force can lead to
squeezed out solder paste and cause solder joints to short. Too low placement force
can lead to insufficient contact between package and solder paste that could cause
open solder joints or badly centered packages.
5. To improve the package placement accuracy, a bottom side optical control should be
performed with a high resolution tool.
6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is
recommended during solder paste printing, pick and place and reflow soldering by
using optimized tools.
3.5 PCB design preference
1. To control the solder paste amount, the closed via is recommended instead of open
vias.
2. The position of tracks and open vias in the solder area should be well balanced. A
symmetrical layout is recommended, to avoid any tilt phenomena caused by
asymmetrical solder paste due to solder flow away.
3.6 Reflow profile
Figure 13: ST ECOPACK® recommended soldering reflow profile for PCB mounting
Minimize air convection currents in the reflow oven to avoid component
movement. Maximum soldering profile corresponds to the latest IPC/JEDEC J-
STD-020.
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DocID030880 Rev 1
4 Ordering information
Figure 14: Ordering information scheme
Table 4: Ordering information
Order code
Marking
Package
Weight
Base qty.
Delivery mode
ESDZV18-1BF4
1(1)
0201
0.116 mg
15000
Tape and reel
Notes:
(1)The marking can be rotated by multiples of 90° to differentiate assembly location
5 Revision history
Table 5: Document revision history
Date
Revision
Changes
15-Nov-2017
1
First issue.
Z : Ultra low Clamping
snapback effect
ESD protection
V : Very Low Capacitance
Package
F4 = 0201
Number of lines
18 : Minimum trigger voltage
B = Bi-directional
ESD Z V 18 - 1 B F4
ESDZV18-1BF4
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