3D7523-0.5 - Data Delay Devices, Inc.

3D7523

delay

devices, inc.

“

MONOLITHIC MANCHESTER

ENCODER/DECODER

(SERIES 3D7523)

FEATURES PACKAGES

x All-silicon, low-power CMOS technology

x Encoder and decoder function independently

x Encoder has buffered clock output

x TTL/CMOS compatible inputs and outputs

x Vapor phase, IR and wave solderable

x Auto-insertable (DIP pkg.)

x Low ground bounce noise

x Maximum data rate: 50 MBaud

x Data rate range: r15%

x Lock-in time: 1 bit

For mechanical dimensions, click here.

For package marking details, click here.

CEN

COUT

DIN

RESB

VDD

CBUF

LOOP

TXENB

DOUTB

TXB

3D7523-xxx DIP (.300)

3D7523G-xxx Gull Wing (.300)

3D7523D-xxx SOIC (.150)

GND TX

FUNCTIONAL DESCRIPTION PIN DESCRIPTIONS

Encoder:

CIN Clock Input

DIN Data Input

RESB Reset

CEN Clock buffer enable

TXENB Transmit enable

CBUF Buffered clock

TX,TXB Transmitted signal

Decoder:

RX Received Signal

COUT Recovered Clock

DOUTB Recovered Data

Common:

LOOP Loop enable

VDD +5 Volts

GND Ground

The 3D7523 is a monolithic CMOS Manchester Encoder/Decoder combo

chip. The device uses bi-phase-level encoding to embed a clock signal

into a data stream for transmission across a communications link. In this

encoding mode, a logic one is represented by a high-to-low transition in

the center of the bit cell, while a logic zero is represented by a low-to-high

transition.

The Manchester encoder combines the clock (CIN) and data (DIN) into a

single bi-phase-level signal (TX). An inverted version of this signal (TXB) is

also available. The data baud rate (in MBaud) is equal to the input clock

frequency (in MHz). A replica of the clock input is also available (CBUF).

The encoder may be reset by setting the RESB input low; otherwise, it

should be left high. The TX and TXB signals may be disabled (high-Z) by

setting TXENB high. Similarly, CBUF may be disabled by setting CEN low.

Under most operating conditions, TX and TXB are always enabled, and

CBUF is not used. With this in mind, the 3D7523 provides internal pull-

down resistors on CEN and TXENB, so that most users can leave these

inputs uncommitted.

The Manchester decoder accepts the embedded-clock signal at the RX input. The recovered clock and

data signals are presented on COUT and DOUTB, respectively, with the data signal inverted. The

operating baud rate (in MBaud) is specified by the dash number of the device. The input baud rate may

vary by as much as r15% from the nominal device baud rate without compromising the integrity of the

information received.

Because the decoder is not PLL-based, it does not require a long preamble in order to lock onto the

received signal. Rather, the device requires at most one bit cell before the data presented at the output is

valid. This is extremely useful in cases where the information arrives in bursts and the input is otherwise

turned off.

Normally, the encoder and decoder function independently. However, if the LOOP input is set high, the

encoded TX signal is fed back internally into the decoder and the RX input is ignored. This feature is

useful for diagnostics. The LOOP input has an internal pull-down resistor and may be left uncommitted if

this feature is not needed. ”2006 Data Delay Devices

Doc #06003 DATA DELAY DEVICES, INC. 1

5/8/2006 3 Mt. Prospect Ave. Clifton, NJ 07013

3D7523

TABLE 1: PART NUMBER SPECIFICATIONS

PART DECODER BAUD RATE (MBaud)

NUMBER Nominal Minimum Maximum

3D7523-0.5 0.50 0.43 0.57

3D7523-1 1.00 0.85 1.15

3D7523-5 5.00 4.25 5.75

3D7523-10 10.00 8.50 11.50

3D7523-20 20.00 17.00 23.00

3D7523-25 25.00 21.25 28.75

3D7523-50 50.00 42.50 57.50

NOTE: Any baud rate between 0.5 and 50 MBaud not shown is also available at no extra cost.

APPLICATION NOTES

ENCODER

The encoder presents at its outputs the true and

the complimented encoded data. The High-to-

Low time skew of the selected data output should

be budgeted by the user, as it relates to his

application, to satisfactorily estimate the

distortion of the transmitted data stream. Such an

estimate is very useful in determining the

The Manchester encoder subsystem samples the

data input at the rising edge of the input clock.

The sampled data is used in conjunction with the

clock rising and falling edges to generate the by-

phase level Manchester code.

The encoder employs the timing of the clock

rising and falling edges (duty cycle) to implement

the required coding scheme, as shown in Figure

1. To reduce the difference between the output

data high time and low time, it is essential that

the deviation of the input clock duty cycle from

50/50 be minimized.

functionality and margins of the data link, if a

Manchester decoder is used to decode the

received data.

RESET

(RESB)

CLOCK

(CIN)

DATA

(DIN)

TRANSMIT

(TX)

TRANSMIT

(TXB)

tDS tDH

Figure 1: Timing Diagram (Encoder)

1/fC

10110010

(Left high for normal operation)

T2H T2L

T1H T1L

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3D7523

APPLICATION NOTES (CONT’D)

DECODER

to one over twice the baud rate. Otherwise, the

input is presented at the clock output unchanged,

shifted in time. Therefore, the clock duty cycle is

strongly dependent on the baud rate, as this will

affect the clock-high duration.

The Manchester decoder subsystem samples the

input at precise pre-selected intervals to retrieve

the data and to recover the clock from the

received data stream. Its architecture comprises

finely tuned delay elements and proprietary

circuitry which, in conjunction with other circuits,

implement the data decoding and clock recovery

function.

The clock output falling edge is not operated on

by the clock recovery circuitry. It, therefore,

preserves more accurately the clock frequency

information embedded in the transmitted data. It

can therefore be used, if desired, to retrieve clock

frequency information.

Typically, the encoded data transmitted from a

source arrives at the decoder corrupted. Such

corruption of the received data manifests itself as

jitter and/or pulse width distortion at the decoder

input. The instantaneous deviations from

nominal Baud Rate and/or Pulse Width (high or

low) adversely impact the data extraction and

clock recovery function if their published limits

are exceeded. See Table 4, Allowed Baud

Rate/Duty Cycle. The decoder, being a self-

timed device, is tolerant of frequency modulation

(jitter) present in the input data stream, provided

that the input data pulse width variations remain

within the allowable ranges.

INPUT SIGNAL CHARACTERISTICS

The 3D7523 inputs are TTL compatible. The

user should assure him/herself that the 1.5

volt TTL threshold is used when referring to all

timing, especially to the input clock duty cycle

(encoder) and the received data (decoder).

POWER SUPPLY AND

TEMPERATURE CONSIDERATIONS

CMOS integrated circuitry is strongly dependent

on power supply and temperature. The

monolithic 3D7523 Manchester encoder/decoder

utilizes novel and innovative compensation

circuitry to minimize timing variations induced by

fluctuations in power supply and/or temperature.

Nevertheless, optimum performance is achieved

by providing a stable power supply and a clean

ground plane, and by placing a bypass capacitor

(0.1uf typically) as close to the device as

possible.

The decoder presents at its outputs the decoded

data (inverted) and the recovered clock. The

decoded data is valid at the rising edge of the

clock.

The clock recovery function operates in two

modes dictated by the input data stream bit

sequence. When a data bit is succeeded by its

inverse, the clock recovery circuit is engaged and

forces the clock output low for a time equal

CLOCK

(CLK)

RECEIVED

(RX)

Figure 2: Timing Diagram (Decoder)

DECODED 1011001

ENCODED 10110010

DATA

(DATB)

tCL tCWL tCD

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3D7523

DEVICE SPECIFICATIONS

TABLE 2: ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL MIN MAX UNITS NOTES

DC Supply Voltage VDD -0.3 7.0 V

Input Pin Voltage VIN -0.3 VDD+0.3 V

Input Pin Current IIN -10 10 mA 25C

Storage Temperature TSTRG -55 150 C

Lead Temperature TLEAD 300 C 10 sec

TABLE 3: DC ELECTRICAL CHARACTERISTICS

(-40C to 85C, 4.75V to 5.25V)

PARAMETER SYMBOL MIN MAX UNITS NOTES

Static Supply Current* IDD 5 mA

High Level Input Voltage VIH 2.0 V

Low Level Input Voltage VIL 0.8 V

High Level Input Current IIH 1.0

PA VIH = VDD

Low Level Input Current IIL 1.0

PA VIL = 0V

High Level Output Current IOH -4.0 mA VDD = 4.75V

VOH = 2.4V

Low Level Output Current IOL 4.0 mA VDD = 4.75V

VOL = 0.4V

Output Rise & Fall Time TR & TF 2 ns CLD = 5 pf

*IDD(Dynamic) = 2 * CLD * VDD * F Input Capacitance = 10 pf typical

where: CLD = Average capacitance load/pin (pf) Output Load Capacitance (CLD) = 25 pf max

F = Input frequency (GHz)

TABLE 4: AC ELECTRICAL CHARACTERISTICS

(-40C to 85C, 4.75V to 5.25V, except as noted)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Baud Rate (Encoder) fBN 50 MBaud

Clock Frequency fC 50 MHz

Data set-up to clock rising tDS 3.5 ns

Data hold from clock rising tDH 0 ns

TX High-Low time skew t1H - t1L -3.5 3.5 ns 1

TXB High-Low time skew t2H - t2L -2.0 2.0 ns 1

TX - TXB High/Low time skew t1H - t2L -3.0 3.0 ns 1

Nominal Input Baud Rate (Decoder) fBN 5 50 MBaud

Allowed Input Baud Rate Deviation fB -0.15 fBN 0.15 fBN MBaud 0C to 70C

25C, 5.00V

Allowed Input Baud Rate Deviation fB -0.05 fBN 0.05 fBN MBaud 4.75V to 5.25V

Allowed Input Baud Rate Deviation fB -0.03 fBN 0.03 fBN MBaud -55C to 125C

4.75V to 5.25V

Allowed Input Duty Cycle 42.5 50.0 57.5 %

Bit Cell Time tc 1000/fB ns

Input Data Edge to Clock Falling Edge tCL 0.75 tc ns

Clock Width Low tCWL 500/fBN ns r2ns or 5%

Clock Falling Edge to Data Transition tCD 3.0 4.0 5.0 ns

Notes: 1: Assumes a 50% duty cycle clock input

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3D7523

AUTOMATED TESTING - MONOLITHIC PRODUCTS

TEST CONDITIONS

INPUT: OUTPUT:

Ambient Temperature: 25oC r 3oC Rload: 10K: r 10%

Supply Voltage (Vcc): 5.0V r 0.1V Cload: 5pf r 10%

Input Pulse: High = 3.0V r 0.1V Threshold: 1.5V (Rising & Falling)

Low = 0.0V r 0.1V

Source Impedance: 50: Max.

10K:

470:5pf

Device

Under

Test

Digital

Scope

Rise/Fall Time: 3.0 ns Max. (measured

between 0.6V and 2.4V )

Pulse Width: PWIN = 1/(2*BAUD)

Period: PERIN = 1/BAUD

NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.

OUT

TRIG

Figure 3: Test Setup

DEVICE UNDER

TEST (DUT) DIGITAL SCOPE

WAVEFORM

GENERATOR

OUTIN

COMPUTER

SYSTEM

PRINTER

Figure 4: Timing Diagram

tPLH tPHL

PERIN

PWIN

tRISE tFALL

0.6V0.6V 1.5V1.5V

2.4V 2.4V

1.5V1.5V

VIH

VIL

VOH

VOL

INPUT

SIGNAL

OUTPUT

SIGNAL

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5/8/2006 3 Mt. Prospect Ave. Clifton, NJ 07013