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Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY7C1041G Automotive 4-Mbit (256K words x 16-bit) Static RAM with Error-Correcting Code (ECC) 4-Mbit (256K words x 16-bit) Static RAM with Error-Correcting Code (ECC) Features Functional Description CY7C1041G is a high-performance CMOS fast static RAM automotive part with embedded ECC. This device has a single Chip Enable (CE) input and is accessed by asserting it LOW. AEC-Q100 qualified High speed tAA = 10 ns Temperature range Automotive-E: -40 C to 125 C Automotive-A: -40 C to 85 C Data writes are performed by asserting the Write Enable (WE) input LOW, while providing the data on I/O0 through I/O15 and the address on A0 through A17 pins. The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs control write operations to the upper and lower bytes of the specified memory location. BHE controls I/O8 through I/O15 and BLE controls I/O0 through I/O7. Embedded ECC for single-bit error correction[1, 2] Data reads are performed by asserting the Output Enable (OE) input and providing the required address on the address lines. Read data is accessible on the I/O lines (I/O0 through I/O15). Byte accesses can be performed by asserting the required byte enable signal (BHE or BLE) to read either the upper byte or the lower byte of data from the specified address location. Low active and standby currents Active current ICC = 40 mA typical Standby current ISB2 = 6 mA typical Operating voltage range: 2.2 V to 3.6 V 1.0 V data retention TTL- compatible inputs and outputs Pb-free 48-ball VFBGA and 44-pin TSOP II packages All I/Os (I/O0 through I/O15) are placed in a HI-Z state when the device is deselected (CE LOW), or when the control signals are deasserted (OE, BLE, BHE). Refer to the following logic block diagram. Logic Block Diagram - CY7C1041G MEMORY ARRAY ECCDECODER INPUTBUFFER SENSE AMPLIFIERS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROWDECODER ECCENCODER I/O0I/O7 I/O8I/O15 A10 A11 A12 A13 A14 A15 A16 A17 COLUMNDECODER BHE WE OE CE2 CE1 BLE Note 1. This device does not support automatic write-back on error detection. 2. SER FIT Rate <0.1 FIT/Mb. Refer AN88889 for details. Cypress Semiconductor Corporation Document Number: 001-91255 Rev. *J * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised July 16, 2018 CY7C1041G Automotive Contents Pin Configurations ........................................................... 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 DC Electrical Characteristics .......................................... 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 AC Switching Characteristics ......................................... 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Document Number: 001-91255 Rev. *J Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Package Diagrams .......................................................... 13 Acronyms ........................................................................ 14 Document Conventions ................................................. 14 Units of Measure ....................................................... 14 Document History Page ................................................. 15 Sales, Solutions, and Legal Information ...................... 16 Worldwide Sales and Design Support ....................... 16 Products .................................................................... 16 PSoC(R) Solutions ...................................................... 16 Cypress Developer Community ................................. 16 Technical Support ..................................................... 16 Page 2 of 16 CY7C1041G Automotive Pin Configurations Figure 1. 48-ball VFBGA Pinout [3] 1 2 BLE OE I/O8 3 4 5 6 A0 A1 A2 NC A BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 VCC D VCC I/O12 NC A16 I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G NC A8 A9 A10 A11 NC H Figure 2. 44-pin TSOP II Pinout [3] A0 A1 A2 A3 A4 /CE I/O 0 I/O 1 I/O2 I/O3 VCC VSS I/O 4 I/O 5 I/O 6 I/O 7 /WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44-pin TSOP 44 43 42 41 40 39 38 37 II 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A 17 A16 A 15 /OE /BHE /BLE I/O 15 I/O 14 I/O 13 I/O 12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A14 A13 A12 A11 A10 Product Portfolio Power Dissipation Product CY7C1041G Range Automotive-E VCC Range (V) 2.2 V-3.6 V Speed (ns) Operating ICC, (mA), f = fmax 10 Automotive-A Standby, ISB2 (mA) Typ[4] Max Typ[4] Max 40 50 6 14 38 45 6 8 Notes 3. NC pins are not connected internally to the die. 4. Typical values are included for reference only and are not guaranteed or tested. Document Number: 001-91255 Rev. *J Page 3 of 16 CY7C1041G Automotive DC input voltage[5] .............................. -0.3 V to VCC + 0.3 V Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ -65 C to +150 C Ambient temperature with power applied ................................... -55 C to +125 C Current into outputs (in low state) ............................... 20 mA Static discharge voltage (MIL-STD-883, Method 3015) ................................. > 2001 V Latch-up current .................................................... > 140 mA Operating Range Supply voltage on VCC relative to GND[5] .....................-0.5 V to Vcc +0.3 V DC voltage applied to outputs in HI-Z State[5] ......................................-0.3 V to Vcc +0.3 V Grade Ambient Temperature VCC Automotive-E -40 C to +125 C 2.2 V to 3.6 V Automotive-A -40 C to +85 C 2.2 V to 3.6 V DC Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH Description Output HIGH voltage Output LOW voltage Test Conditions 10 ns (Automotive-E) 10 ns (Automotive-A) Min Typ Max Min Typ Max 2.2 V to 2.7 V VCC = Min, IOH = -1.0 mA 2 - - 2 - - 2.7 V to 3.0 V VCC = Min, IOH = -4.0 mA 2.2 - - 2.2 - - 3.0 V to 3.6 V VCC = Min, IOH = -4.0 mA 2.4 - - 2.4 - - 2.2 V to 2.7 V VCC = Min, IOL = 2 mA - - 0.4 - - 0.4 2.7 V to 3.6 V VCC = Min, IOL = 8 mA - - 0.4 - - 0.4 - 2 - VCC + 0.3[5] 2 - VCC + 0.3[5] - + 0.3[5] 2 - + 0.3[5] 0.6 -0.3[5] - 0.6 Input HIGH 2.2 V to 2.7 V voltage 2.7 V to 3.6 V - 2 VCC VCC Unit V V V Input LOW 2.2 V to 2.7 V voltage 2.7 V to 3.6 V - -0.3[5] - [5] -0.3 - 0.8 -0.3[5] - 0.8 IIX Input leakage current GND < VIN < VCC -5 - +5 -1 - +1 A IOZ Output leakage current GND < VOUT < VCC, Output disabled -5 - +5 -1 - +1 A ICC Operating supply current VCC = 3.6 V, f = fMAX = 1/tRC IOUT = 0 mA, CMOS levels - 40 50 - 38 45 mA ISB1 Automatic CE power down current - TTL inputs VCC = 3.6 V, CE > VIH, - - 24 - - 15 mA - 6 14 - 6 8 mA VIL - V VIN > VIH or VIN < VIL, f = fMAX ISB2 Automatic CE power down current - CMOS inputs VCC = 3.6 V, CE > VCC - 0.2 V, VIN > VCC - 0.2 V or VIN < 0.2 V, f=0 Note 5. VIL(min) = -2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns. Document Number: 001-91255 Rev. *J Page 4 of 16 CY7C1041G Automotive Capacitance Parameter[6] Description CIN Input capacitance COUT I/O capacitance Test Conditions All Packages Unit 10 pF 10 pF TA = 25 C, f = 1 MHz, VCC = VCC(typ) Thermal Resistance Parameter[6] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions 48-ball VFBGA 44-pin TSOPII Unit Still air, soldered on a 3 x 4.5 inch, four-layer printed circuit board 30.68 66.82 C/W 14.83 15.97 C/W AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms [7] High-Z Characteristics: VCC 50 Output VTH Z0 = 50 Output 30 pF* * Including jig and scope (b) All Input Pulses VHIGH GND R2 5 pF* (a) * Capacitive load consists of all components of the test environment R1 90% 90% 10% 10% Rise Time: > 1 V/ns (c) Parameters 3.0 V Unit R1 317 R2 351 VTH 1.5 V VHIGH 3 V Fall Time: > 1 V/ns Notes 6. Tested initially and after any design or process change that may affect these parameters. 7. Full-device AC operation assumes a 100 s ramp time from 0 to VCC(min) and a 100 s wait time after VCC stabilization. Document Number: 001-91255 Rev. *J Page 5 of 16 CY7C1041G Automotive Data Retention Characteristics Over the Operating Range Parameter Description Conditions Automotive-E Automotive-A Min Max Min Max Unit VDR VCC for data retention - 1 - 1 - V ICCDR Data retention current VCC = 1.2 V, - 14 - 8 mA CE > VCC - 0.2 V, VIN > VCC - 0.2 V or VIN < 0.2 V tCDR[8] Chip deselect to data retention time - 0 - 0 - ns tR[8, 9] Operation recovery time VCC > 2.2 V 10 - 10 - ns Data Retention Waveform Figure 4. Data Retention Waveform [9] VCC VCC(min) DATA RETENTION MODE VDR = 1 V tCDR VCC(min) tR CE Notes 8. These parameters are guaranteed by design. 9. Full-device operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s. Document Number: 001-91255 Rev. *J Page 6 of 16 CY7C1041G Automotive AC Switching Characteristics Over the Operating Range Parameter[10] Description 10 ns (Automotive-A/Automotive-E) Min Max Unit Read Cycle tRC Read cycle time 10 - ns tAA Address to data - 10 ns tOHA Data 3 - ns - 10 ns - 4.5 ns 0 - ns - 5 ns 3 - ns - 5 ns CE LOW to power up[11, 13] 0 - ns tPD CE HIGH to power down[11, 13] - 10 ns tDBE Byte enable to data valid - 4.5 ns tLZBE Byte enable to low impedance[13] 0 - ns - 6 ns [11] tACE CE LOW to data tDOE OE LOW to data tLZOE tHZOE OE LOW to low impedance OE HIGH to HI-Z[12, 13] impedance[11, 12, 13] tLZCE CE LOW to low tHZCE CE HIGH to HI-Z[11, 12, 13] tPU tHZBE Write [12, 13] Byte disable to HI-Z[13] Cycle[14, 15] tWC Write cycle time 10 - ns tSCE CE LOW to write end[10] 7 - ns tAW Address setup to write end 7 - ns tHA Address hold from write end 0 - ns tSA Address setup to write start 0 - ns tPWE WE pulse width 7 - ns tSD Data setup to write end 5 - ns tHD Data hold from write end 0 - ns [12, 13] tLZWE WE HIGH to low impedance 3 - ns tHZWE WE LOW to HI-Z[12, 13] - 5 ns tBW Byte Enable to write end 7 - ns Notes 10. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3 V). Test conditions for the read cycle use output loading shown in part (a) of Figure 3 on page 5, unless specified otherwise. 11. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 12. tHZOE, tHZCE, tHZWE, tHZBE, tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF as in (b) of Figure 3 on page 5. Transition is measured 200 mV from steady state voltage. 13. These parameters are guaranteed by design and are not tested. 14. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 15. The minimum write cycle pulse width for Write Cycle No. 2 (WE Controlled, OE LOW) should be equal to sum of tSD and tHZWE. Document Number: 001-91255 Rev. *J Page 7 of 16 CY7C1041G Automotive Switching Waveforms Figure 5. Read Cycle No. 1 of CY7C1041G (Address Transition Controlled) [16, 17] tRC ADDRESS tAA tOHA DATA I/O PREVIOUS DATAOUT VALID DATAOUT VALID Figure 6. Read Cycle No. 2 (OE Controlled) [17] ADDRESS tRC CE tPD tHZCE tACE OE tHZOE tDOE tLZOE BHE/ BLE tDBE tLZBE DATA I/O HIGH IMPEDANCE tHZBE DATA OUT VALID HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU ISB Notes 16. The device is continuously selected, OE = VIL, CE = VIL, BHE or BLE or both = VIL. 17. WE is HIGH for read cycle. Document Number: 001-91255 Rev. *J Page 8 of 16 CY7C1041G Automotive Switching Waveforms (continued) Figure 7. Write Cycle No. 1 (CE Controlled) [18, 19, 20] tWC ADDRESS tSA tSCE CE tAW tHA tPWE WE tBW BHE/ BLE OE tHZOE tHD tSD DATA I/O DATAIN VALID Figure 8. Write Cycle No. 2 (WE Controlled, OE LOW) [18, 19, 20, 21] tWC ADDRESS tSCE CE tBW BHE/ BLE tSA tAW tHA tPWE WE t LZWE t HZWE DATA I/O tSD tHD DATAIN VALID Notes 18. Address valid prior to or coincident with CE LOW transition. 19. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 20. Data I/O is in HI-Z state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH. 21. The minimum write cycle pulse width should be equal to sum of tSD and tHZWE. Document Number: 001-91255 Rev. *J Page 9 of 16 CY7C1041G Automotive Switching Waveforms (continued) Figure 9. Write Cycle No. 3 (BLE or BHE Controlled) [22, 23] tWC ADDRESS tSCE CE tAW tSA tHA tBW BHE/ BLE tPWE WE t HZWE tHD tSD DATA I/O t LZWE DATA IN VALID Figure 10. Write Cycle No. 4 (WE Controlled) [22, 23, 24] tWC ADDRESS tSCE CE tBW BHE/ BLE tSA tAW tHA tPWE WE t LZWE t HZWE DATA I/O tSD tHD DATAIN VALID Notes 22. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 23. Data I/O is in HI-Z state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH. 24. Data I/O is high impedance if OE = VIH. 25. During this period the I/Os are in output state. Do not apply input signals. Document Number: 001-91255 Rev. *J Page 10 of 16 CY7C1041G Automotive Truth Table CE OE WE BLE BHE I/O0-I/O7 H X X X X HI-Z HI-Z Power down Standby (ISB) L L H L L Data out Data out Read all bits Active (ICC) L L H L H Data out HI-Z Read lower bits only Active (ICC) L L H H L HI-Z Data out Read upper bits only Active (ICC) L X L L L Data in Data in Write all bits Active (ICC) L X L L H Data in HI-Z Write lower bits only Active (ICC) L X L H L HI-Z Data in Write upper bits only Active (ICC) L H H X X HI-Z HI-Z Selected, outputs disabled Active (ICC) Document Number: 001-91255 Rev. *J I/O8-I/O15 Mode Power Page 11 of 16 CY7C1041G Automotive Ordering Information Speed (ns) 10 Voltage Range 2.2 V-3.6 V Package Diagram Ordering Code Package Type (all Pb-free) CY7C1041G30-10BAJXE 001-85259 48-ball VFBGA CY7C1041G30-10BAJXET 001-85259 48-ball VFBGA, Tape and Reel CY7C1041G30-10ZSXE 51-85087 44-pin TSOP II CY7C1041G30-10ZSXET 51-85087 44-pin TSOP II, Tape and Reel CY7C1041G30-10ZSXA 51-85087 44-pin TSOP II CY7C1041G30-10ZSXAT 51-85087 44-pin TSOP II, Tape and Reel Operating Range Automotive-E Automotive-A Ordering Code Definitions CY 7 C 1 04 1 G 30 - 10 XX J X X X X = blank or T blank = Bulk; T = Tape and Reel Temperature Range: X = E or A E = Automotive-E; A= Automotive-A Pb-free J = JEDEC Compliant Package Type: XX = BA or ZS BA = 48-ball VFBGA; ZS = 44-pin TSOP II Speed: 10 ns Voltage Range: 30 = 2.2 V-3.6 V Process Technology: Revision Code "G" = 65 nm Data Width: 1 = x 16-bits Density: 04 = 4-Mbit Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-91255 Rev. *J Page 12 of 16 CY7C1041G Automotive Package Diagrams Figure 11. 48-ball VFBGA (6 x 8 x 1.2 mm) BA48M/BK48M (0.35 mm Ball Diameter) Package Outline, 001-85259 001-85259 *A Figure 12. 44-pin TSOP Z44-II Package Outline, 51-85087 001-85259 *A 51-85087 *E Document Number: 001-91255 Rev. *J Page 13 of 16 CY7C1041G Automotive Acronyms Document Conventions Table 1. Acronyms Used in this Document Units of Measure Acronym Description Table 2. Units of Measure BHE Byte High Enable BLE Byte Low Enable C degree Celsius CE Chip Enable MHz megahertz CMOS Complementary Metal Oxide Semiconductor A microampere I/O Input/Output s microsecond OE Output Enable mA milliampere SRAM Static Random Access Memory mm millimeter TSOP Thin Small Outline Package ns nanosecond TTL Transistor-Transistor Logic ohm VFBGA Very Fine-Pitch Ball Grid Array % percent WE Write Enable pF picofarad V volt W watt Document Number: 001-91255 Rev. *J Symbol Unit of Measure Page 14 of 16 CY7C1041G Automotive Document History Page Document Title: CY7C1041G Automotive, 4-Mbit (256K words x 16-bit) Static RAM with Error-Correcting Code (ECC) Document Number: 001-91255 Rev. ECN No. Orig. of Change Submission Date *F 4996293 NILE 10/30/2015 Changed status from Preliminary to Final. *G 5026902 NILE 11/25/2015 Added Automotive-A Temperature Range related information in all instances across the document. Updated Ordering Information: Updated part numbers. *H 5427560 NILE 09/07/2016 Updated Maximum Ratings: Updated Note 5 (Replaced "2 ns" with "20 ns"). Updated DC Electrical Characteristics: Removed details of VOH parameter corresponding to Test Condition "2.7 V to 3.6 V". Added details of VOH parameter corresponding to Test Conditions "2.7 V to 3.0 V" and "3.0 V to 3.6 V". Updated Ordering Information: Updated part numbers. Updated to new template. *I 5787756 NILE 06/27/2017 Updated to new template. Completing Sunset Review. *J 6249178 NILE 07/16/2018 Updated Features: Added "AEC-Q100 qualified". Added Note 2 and referred the same note in "Embedded ECC for single-bit error correction". Updated to new template. Completing Sunset Review. Document Number: 001-91255 Rev. *J Description of Change Page 15 of 16 CY7C1041G Automotive Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC(R) Solutions Products Arm(R) Cortex(R) Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface cypress.com/clocks cypress.com/interface Internet of Things Memory cypress.com/iot cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs Touch Sensing USB Controllers Wireless Connectivity PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU Cypress Developer Community Community | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/pmic cypress.com/touch cypress.com/usb cypress.com/wireless (c) Cypress Semiconductor Corporation, 2014-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). 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Document Number: 001-91255 Rev. *J Revised July 16, 2018 Page 16 of 16