NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no respon-
sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
Recommended Substitutions:
8-Bit Addressable, DMOS Power Driver
A6A259
Date of status change: October 29, 2007
These parts are no longer in production The device should not be
purchased for new design applications. Samples are no longer available.
Discontinued Product
Data Sheet
26186.121
8-BIT ADDRESSABLE
DMOS POWER DRIVER
The A6A259KA and A6A259KLB combine a 3-to-8 line CMOS
decoder and accompanying data latches, control circuitry, and DMOS
outputs in a multi-functional power driver capable of storing single-line
data in the addressable latches or use as a decoder or demuliplexer.
Driver applications include relays, solenoids, and other medium-current
or high-voltage peripheral power loads.
The CMOS inputs and latches allow direct interfacing with micro-
processor-based systems. Use with TTL may require appropriate pull-
up resistors to ensure an input logic high. Four modes of operation are
selectable with the CLEAR and ENABLE inputs.
The addressed DMOS output inverts the DATA input with all
unaddressed outputs remaining in their previous states. All of the output
drivers are disabled (the DMOS sink drivers turned off) with the
CLEAR input low and the ENABLE input high. The A6A259KA/KLB
DMOS open-drain outputs are capable of sinking up to 500 mA.
The A6A259KA is furnished in a 20-pin dual in-line plastic pack-
age. The A6A259KLB is furnished in a 24-lead wide-body, small-
outline plastic batwing package (SOIC) with gull-wing leads for surface-
mount applications. Copper lead frames, reduced supply current re-
quirements, and low on-state resistance allow both devices to sink 150
mA from all outputs continuously, to ambient temperatures over 85°C.
FEATURES
■50 V Minimum Output Clamp Voltage
■350 mA Output Current (all outputs simultaneously)
■1 Ω Typical rDS(on)
■Internal Short-Circuit Protection
■Low Power Consumption
■Replacements for TPIC6A259N and TPIC6A259DW
6A259
PRELIMINARY INFORMATION
(Subject to change without notice)
March 24, 2003
LOGIC
GROUND
S
1
OUT
3
V
DD
POWER
GROUND
CLEAR
Dwg. PP-050-4
OUT
2
POWER
GROUND
ENABLE EN
POWER
GROUND
S
2
(MSB)
OUT
5
OUT
4
POWER
GROUND
OUT
0
OUT
1
S
0
(LSB)
LOGIC
SUPPLY
OUT
6
OUT
7
DATA
DECODER
LATCHES
13
14
15
16
17
19
12
18
20
11
1
2
3
8
9
4
5
6
7
10
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Output Voltage, VO............................ 50 V
Output Drain Current,
Continuous, IO...................... 350 mA*
Peak, IOM ........................... 1100 mA*†
Peak, IOM .................................... 2.0 A†
Single-Pulse Avalanche Energy,
EAS ............................................. 75 mJ
Logic Supply Voltage, VDD .............. 7.0 V
Input Voltage Range,
VI............................... -0.3 V to +7.0 V
Package Power Dissipation,
PD....................................... See Graph
Operating Temperature Range,
TA............................. -40°C to +125°C
Storage Temperature Range,
TS............................. -55°C to +150°C
*Each output, all outputs on.
† Pulse duration ≤ 100 µs, duty cycle ≤ 2%.
Caution: These CMOS devices have input static
protection (Class 3) but are still susceptible to dam-
age if exposed to extremely high static electrical
charges.
Always order by complete part number:
Part Number Package Rθθ
θθ
θJA Rθθ
θθ
θJC Rθθ
θθ
θJT
A6A259KA 20-pin DIP 55°C/W 25°C/W —
A6A259KLB 24-lead SOIC 55°C/W — 6°C/W
A6A259KA (DIP)
6A259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
2
Copyright © 2003 Allegro MicroSystems, Inc.
FUNCTION TABLE
Inputs Addressed Other
CLEAR ENABLE DATA OUTPUT OUTPUTs Function
HLH L R Addressable
HLL H R Latch
H H X R R Memory
LLH L H 8-Line
LLL H H Demultiplexer
L H X H H Clear
L = Low Logic Level H = High Logic Level X = Irrelevant R = Previous State
LATCH SELECTION TABLE
Select Inputs Addressed
S2 (MSB)S
1S0 (LSB) OUTPUT
LLL 0
LLH 1
LHL 2
LHH 3
HLL 4
HLH 5
HHL 6
HHH 7
DMOS POWER DRIVER OUTPUTLOGIC INPUTS
Dw
g
. EP-063-5
OUT
IN
Dwg. EP-010-15
VDD
A6A259KLB (SOIC)
POWER
GROUND
CLEAR
POWER
GROUND
ENABLE EN
POWER
GROUND
S
2
(MSB)
OUT
5
OUT
4
POWER
GROUND
OUT
6
OUT
7
DATA
LOGIC
GROUND
S
1
OUT
3
V
DD
POWER
GROUND
OUT
2
POWER
GROUND
POWER
GROUND POWER
GROUND
OUT
0
OUT
1
S
0
(LSB)
LOGIC
SUPPLY
DECODER
LATCHES
Dwg. PP-050-3A
1
2
3
817
18
19
20
21
23
4
5
6
7
22
24
12
9
10
11
13
14
15
16
50 75 100 125 150
5
1
0
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
TEMPERATURE IN °°
°°C
4
3
2
25
Dwg. GP-049-5
SUFFIX 'LB', R = 6.0°C/W
θJT
R = 55°C/W
θJA
SUFFIX 'A', R = 25°C/W
θJC
6A259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
www.allegromicro.com
3
Power grounds must be connected externally to a single point.
V
DD
LOGIC
SUPPLY
DATA
CLEAR
(ACTIVE LOW)
ENABLE
(ACTIVE LOW)
2
S
(MSB)
1
S
0
S
(LSB)
LOGIC
GROUND
POWER
GROUND
Dwg. FP-047-2
OUT
0
D
C1
CLR
OUT
1
D
C1
CLR
OUT
2
D
C1
CLR
OUT
3
D
C1
CLR
OUT
4
D
C1
CLR
OUT
5
D
C1
CLR
OUT
6
D
C1
CLR
OUT
7
D
C1
CLR
CURRENT LIMIT AND CHARGE PUMP
FUNCTIONAL BLOCK DIAGRAM
6A259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
4
Limits
Characteristic Symbol Test Conditions Min. Typ. Max. Units
Logic Supply Voltage VDD Operating 4.5 5.0 5.5 V
Output Breakdown V(BR)DSX IO = 1 mA 50 — — V
Voltage
Off-State Output IDSX VO = 40 V — 0.1 1.0 µA
Current VO = 40 V, TA = 125°C — 0.2 5.0 µA
Static Drain-Source rDS(on) IO = 350 mA — 1.0 1.5 Ω
On-State Resistance IO = 350 mA, TA = 125°C — 1.7 2.5 Ω
Source-to-Drain VSD IF = 350 mA — 1.0 — V
Diode Voltage
Nominal Output IO(nom) VDS(on) = 0.5 V, TA = 85°C — 350 — mA
Current
Output Current IO(chop) IO at which chopping starts, TC = 25°C 0.6 0.8 1.1 A
Logic Input Current IIH VI = VDD = 5.5 V — — 1.0 µA
IIL VI = 0, VDD = 5.5 V — — -1.0 µA
Prop. Delay Time tPLH IO = 350 mA, CL = 30 pF — 100 — ns
tPHL IO = 350 mA, CL = 30 pF — 60 — ns
Output Rise Time trIO = 350 mA, CL = 30 pF — 55 — ns
Output Fall Time tfIO = 350 mA, CL = 30 pF — 40 — ns
Supply Current IDD(off) VDD = 5.5 V, Outputs OFF — 0.75 1.0 mA
IDD(on) VDD = 5.5 V, Outputs ON — 2.0 3.0 mA
Typical Data is at VDD = 5 V and is for design information only.
NOTE — Pulse test, duration ≤ 100 µs, duty cycle ≤ 2%.
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V, tir = tif ≤ 10 ns (unless otherwise
specified).
RECOMMENDED OPERATING CONDITIONS
over operating temperature range
Logic Supply Voltage Range, VDD ............... 4.5 V to 5.5 V
High-Level Input Voltage, VIH ............................ ≥ 0.85VDD
Low-level input voltage, VIL ................................. ≤0.15VDD
6A259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
www.allegromicro.com
5
FUNCTIONAL DESCRIPTION and INPUT REQUIREMENTS
Four modes of operation are selectable by controlling the
CLEAR and ENABLE inputs as shown above.
In the addressable-latch mode, data at the DATA input is
written into the addressed transparent latch. The addressed
output inverts the data input with all other outputs remaining
in their previous states.
In the memory mode, all outputs remain in their previous
states and are unaffected by the DATA or address (Sn) inputs.
To prevent entering erroneus data in the latches, ENABLE
should be held HIGH while the address lines are changing.
In the demultiplexing/decoding mode, the addressed
output inverts the data input and all other outputs are OFF.
In the clear mode, all outputs are OFF and are unaffected
by the DATA or address (SN) inputs.
Given the appropriate inputs, when DATA is LOW for a
given address, the output is OFF; when DATA is HIGH, the
output is ON and can sink current.
DATA INPUT REQUIREMENTS
Data Active Time Before Enable
(Data Set-Up Time), tsu(D) .............................................. 20 ns
Data Active Time After Enable
(Data Hold Time), th(D) ................................................... 20 ns
Data Pulse Width, tw(D) ....................................................... 40 ns
Input Logic High, VIH ................................................ ≥ 0.85VDD
Input Logic Low, VIL ................................................. ≤ 0.15VDD
50%
Dwg. WP-037
ENABLE
DATA
50%
w(D)
t
su(D)
t
h(D)
t
PHL
t
PLH
t
50%
ADDRESSED
OUTPUT
Dwg. WP-036
10%
90%
f
t
r
t
ENABLE
DATA
OUTPUT SWITCHING TIME
LOGIC SYMBOL
G8
Z9
9,0D
10,0R OUT
0
OUT
1
OUT
2
OUT
3
OUT
4
OUT
5
OUT
6
OUT
7
S
1
S
2
DATA
ENABLE
Dw
g
. FP-046-2
0
2
S
0
CLEAR Z10
8M 0/7
9,1D
10,1R
9,2D
10,2R
9,3D
10,3R
9,4D
10,4R
9,5D
10,5R
9,6D
10,6R
9,7D
10,7R
6A259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6
TEST CIRCUITS
Dwg. EP-066-2
OUT
INPUT
I
O
V
O
t
av
I
AS
= 600 mA
V
(BR)DSX
V
O(ON)
1 Ω
210 mH
+15 V
DUT
Single-Pulse Avalanche Energy Test Circuit
and Waveforms
EAS = IAS x V(BR)DSX x tAV/2
6A259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
www.allegromicro.com
7
TERMINAL DESCRIPTIONS
A6A259KA A6A259KLB
(DIP) (SOIC)
Terminal No. Terminal No. Terminal Name Function
1 1 OUT2Current-sinking, open-drain DMOS output, address 010.
2 2 OUT3Current-sinking, open-drain DMOS output, address 011.
33 S
1Binary-coded output-select input.
4 4 LOGIC GROUND Reference terminal for input voltage measurements.
5 5, 6 POWER GROUND Reference terminal for output voltage measurements
(OUT0-3).
6 7, 8 POWER GROUND Reference terminal for output voltage measurements
(OUT4-7).
79 S
2Binary-coded output-select input, most-significant bit.
8 10 ENABLE Mode control input; see Function Table.
9 11 OUT4Current-sinking, open-drain DMOS output, address 100.
10 12 OUT5Current-sinking, open-drain DMOS output, address 101.
11 13 OUT6Current-sinking, open-drain DMOS output, address 110.
12 14 OUT7Current-sinking, open-drain DMOS output, address 111.
13 15 DATA CMOS data input to the addressed output latch. When
enabled, the addressed output inverts the data input
(DATA = HIGH, OUTPUT = LOW).
14 16 CLEAR Mode control input; see Function Table.
15 17, 18 POWER GROUND Reference terminal for output voltage measurements
(OUT4-7).
16 19, 20 POWER GROUND Reference terminal for output voltage measurements
(OUT0-3).
17 21 LOGIC SUPPLY (VDD) The logic supply voltage (typically 5 V).
18 22 S0Binary-coded output-select input, least-significant bit.
19 23 OUT0Current-sinking, open-drain DMOS output, address 000.
20 24 OUT1Current-sinking, open-drain DMOS output, address 001.
NOTE —Power grounds must be connected together externally.
6A259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
8
A6A259KA (DIP)
Dimensions in Inches
(controlling dimensions)
Dimensions in Millimeters
(for reference only)
NOTES:1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Lead thickness is measured at seating plane or below.
4. Supplied in standard sticks/tubes of 18 devices.
0.014
0.008
0.300
BSC
Dwg. MA-001-20 in
0.430
MAX
20
110
0.280
0.240
0.210
MAX
0.070
0.045
0.015
MIN
0.022
0.014
0.100
BSC
0.005
MIN
0.150
0.115
11
1.060
0.980
0.355
0.204
7.62
BSC
Dwg. MA-001-20 mm
10.92
MAX
20
110
7.11
6.10
5.33
MAX
1.77
1.15
0.39
MIN
0.558
0.356
2.54
BSC
0.13
MIN
3.81
2.93
11
26.92
24.89
6A259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
www.allegromicro.com
9
A6A259KLB (SOIC)
Dimensions in Inches
(for reference only)
Dimensions in Millimeters
(controlling dimensions)
0° TO 8°
1
24 13
23
0.2992
0.2914
0.6141
0.5985
0.419
0.394
0.020
0.013
0.0926
0.1043
0.0040
MIN.
0.0125
0.0091
Dwg. MA-008-25A in
0.050
BSC
NOTE 1
NOTE 3
0.050
0.016
0°
TO
8°
1
24
23
7.60
7.40
15.60
15.20
10.65
10.00
0.51
0.33
2.65
2.35
0.10
MIN.
0.32
0.23
1.27
BSC
NOTE 1
NOTE 3
1.27
0.40
Dwg. MA-008-25A mm
NOTES:1. Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece.
2. Lead spacing tolerance is non-cumulative.
3. Exact body and lead configuration at vendor’s option within limits shown.
4. Supplied in standard sticks/tubes of 31 devices, or add “TR” to part number for tape and reel.
6A259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
10
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi-
bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
